1 /*!
2 \file gd32a50x_adc.c
3 \brief ADC driver
4
5 \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7
8 /*
9 Copyright (c) 2022, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32a50x_adc.h"
36
37 /*!
38 \brief reset ADC
39 \param[in] adc_periph: ADCx, x=0,1
40 \param[out] none
41 \retval none
42 */
adc_deinit(uint32_t adc_periph)43 void adc_deinit(uint32_t adc_periph)
44 {
45 switch(adc_periph){
46 case ADC0:
47 rcu_periph_reset_enable(RCU_ADC0RST);
48 rcu_periph_reset_disable(RCU_ADC0RST);
49 break;
50 case ADC1:
51 rcu_periph_reset_enable(RCU_ADC1RST);
52 rcu_periph_reset_disable(RCU_ADC1RST);
53 break;
54 default:
55 break;
56 }
57 }
58
59 /*!
60 \brief enable ADC interface
61 \param[in] adc_periph: ADCx, x=0,1
62 \param[out] none
63 \retval none
64 */
adc_enable(uint32_t adc_periph)65 void adc_enable(uint32_t adc_periph)
66 {
67 if(0U == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
68 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
69 }
70 }
71
72 /*!
73 \brief disable ADC interface
74 \param[in] adc_periph: ADCx, x=0,1
75 \param[out] none
76 \retval none
77 */
adc_disable(uint32_t adc_periph)78 void adc_disable(uint32_t adc_periph)
79 {
80 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
81 }
82
83 /*!
84 \brief ADC calibration and reset calibration
85 \param[in] adc_periph: ADCx, x=0,1
86 \param[out] none
87 \retval none
88 */
adc_calibration_enable(uint32_t adc_periph)89 void adc_calibration_enable(uint32_t adc_periph)
90 {
91 /* reset the selected ADC calibration registers */
92 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
93 /* check the RSTCLB bit state */
94 while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
95 }
96 /* enable ADC calibration process */
97 ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
98 /* check the CLB bit state */
99 while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
100 }
101 }
102
103 /*!
104 \brief enable DMA request
105 \param[in] adc_periph: ADCx, x=0
106 \param[out] none
107 \retval none
108 */
adc_dma_mode_enable(uint32_t adc_periph)109 void adc_dma_mode_enable(uint32_t adc_periph)
110 {
111 ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
112 }
113
114 /*!
115 \brief disable DMA request
116 \param[in] adc_periph: ADCx,x=0
117 \param[out] none
118 \retval none
119 */
adc_dma_mode_disable(uint32_t adc_periph)120 void adc_dma_mode_disable(uint32_t adc_periph)
121 {
122 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
123 }
124
125 /*!
126 \brief enable the temperature sensor channel
127 \param[in] none
128 \param[out] none
129 \retval none
130 */
adc_tempsensor_enable(void)131 void adc_tempsensor_enable(void)
132 {
133 /* enable the temperature sensor and vrefint channel */
134 ADC_CTL1(ADC0) |= ADC_CTL1_TSVEN;
135 }
136
137 /*!
138 \brief disable the temperature sensor channel
139 \param[in] none
140 \param[out] none
141 \retval none
142 */
adc_tempsensor_disable(void)143 void adc_tempsensor_disable(void)
144 {
145 /* disable the temperature sensor and vrefint channel */
146 ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVEN;
147 }
148
149 /*!
150 \brief enable vrefint channel
151 \param[in] none
152 \param[out] none
153 \retval none
154 */
adc_vrefint_enable(void)155 void adc_vrefint_enable(void)
156 {
157 ADC_CTL1(ADC0) |= ADC_CTL1_INREFEN;
158 }
159
160 /*!
161 \brief disable vrefint channel
162 \param[in] none
163 \param[out] none
164 \retval none
165 */
adc_vrefint_disable(void)166 void adc_vrefint_disable(void)
167 {
168 ADC_CTL1(ADC0) &= ~ADC_CTL1_INREFEN;
169 }
170
171 /*!
172 \brief configure ADC discontinuous mode
173 \param[in] adc_periph: ADCx, x=0,1
174 \param[in] adc_channel_group: select the channel group
175 only one parameter can be selected which is shown as below:
176 \arg ADC_REGULAR_CHANNEL: regular channel group
177 \arg ADC_INSERTED_CHANNEL: inserted channel group
178 \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel
179 \param[in] length: number of conversions in discontinuous mode,the number can be 1..8
180 for regular channel, the number has no effect for inserted channel
181 \param[out] none
182 \retval none
183 */
adc_discontinuous_mode_config(uint32_t adc_periph,uint8_t adc_channel_group,uint8_t length)184 void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
185 {
186 ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC ));
187 switch(adc_channel_group){
188 case ADC_REGULAR_CHANNEL:
189 /* configure the number of conversions in discontinuous mode */
190 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
191 ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U));
192 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
193 break;
194 case ADC_INSERTED_CHANNEL:
195 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
196 break;
197 case ADC_CHANNEL_DISCON_DISABLE:
198 default:
199 break;
200 }
201 }
202
203 /*!
204 \brief configure the ADC0 sync mode
205 \param[in] mode: ADC0 mode
206 only one parameter can be selected which is shown as below:
207 \arg ADC_MODE_FREE: all the ADCs work independently
208 \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
209 \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
210 \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
211 \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
212 \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
213 \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
214 \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
215 \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
216 \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
217 \param[out] none
218 \retval none
219 */
adc_mode_config(uint32_t mode)220 void adc_mode_config(uint32_t mode)
221 {
222 ADC_CTL0(ADC0) &= ~((uint32_t)ADC_CTL0_SYNCM);
223 ADC_CTL0(ADC0) |= mode;
224 }
225
226 /*!
227 \brief configure ADC special function
228 \param[in] adc_periph: ADCx, x=0,1
229 \param[in] function: the function to configure
230 one or more parameters can be selected which is shown as below:
231 \arg ADC_SCAN_MODE: scan mode select
232 \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
233 \arg ADC_CONTINUOUS_MODE: continuous mode select
234 \param[in] newvalue: ENABLE or DISABLE
235 \param[out] none
236 \retval none
237 */
adc_special_function_config(uint32_t adc_periph,uint32_t function,ControlStatus newvalue)238 void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue)
239 {
240 if(newvalue){
241 /* enable ADC scan mode */
242 if(0U != (function & ADC_SCAN_MODE)){
243 ADC_CTL0(adc_periph) |= (uint32_t)ADC_SCAN_MODE;
244 }
245 /* enable ADC inserted channel group convert automatically */
246 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
247 ADC_CTL0(adc_periph) |= (uint32_t)ADC_INSERTED_CHANNEL_AUTO;
248 }
249 /* enable ADC continuous mode */
250 if(0U != (function & ADC_CONTINUOUS_MODE)){
251 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CONTINUOUS_MODE;
252 }
253 }else{
254 /* disable ADC scan mode */
255 if(0U != (function & ADC_SCAN_MODE)){
256 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_SCAN_MODE);
257 }
258 /* disable ADC inserted channel group convert automatically */
259 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
260 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_INSERTED_CHANNEL_AUTO);
261 }
262 /* disable ADC continuous mode */
263 if(0U != (function & ADC_CONTINUOUS_MODE)){
264 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CONTINUOUS_MODE);
265 }
266 }
267 }
268
269 /*!
270 \brief configure ADC data alignment
271 \param[in] adc_periph: ADCx, x=0,1
272 \param[in] data_alignment: data alignment select
273 only one parameter can be selected which is shown as below:
274 \arg ADC_DATAALIGN_RIGHT: right alignment
275 \arg ADC_DATAALIGN_LEFT: left alignment
276 \param[out] none
277 \retval none
278 */
adc_data_alignment_config(uint32_t adc_periph,uint32_t data_alignment)279 void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment)
280 {
281 if(ADC_DATAALIGN_RIGHT != data_alignment){
282 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_DAL;
283 }else{
284 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
285 }
286 }
287
288 /*!
289 \brief configure the length of regular channel group or inserted channel group
290 \param[in] adc_periph: ADCx, x=0,1
291 \param[in] adc_channel_group: select the channel group
292 only one parameter can be selected which is shown as below:
293 \arg ADC_REGULAR_CHANNEL: regular channel group
294 \arg ADC_INSERTED_CHANNEL: inserted channel group
295 \param[in] length: the length of the channel
296 regular channel 1-16
297 inserted channel 1-4
298 \param[out] none
299 \retval none
300 */
adc_channel_length_config(uint32_t adc_periph,uint8_t adc_channel_group,uint32_t length)301 void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
302 {
303 switch(adc_channel_group){
304 case ADC_REGULAR_CHANNEL:
305 /* configure the length of regular channel group */
306 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
307 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U));
308 break;
309 case ADC_INSERTED_CHANNEL:
310 /* configure the length of inserted channel group */
311 ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
312 ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U));
313 break;
314 default:
315 break;
316 }
317 }
318
319 /*!
320 \brief configure ADC regular channel
321 \param[in] adc_periph: ADCx, x=0,1
322 \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15
323 \param[in] adc_channel: the selected ADC channel
324 only one parameter can be selected which is shown as below:
325 \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
326 \param[in] sample_time: the sample time value
327 only one parameter can be selected which is shown as below:
328 \arg ADC_SAMPLETIME_2POINT5: 2.5 cycles
329 \arg ADC_SAMPLETIME_14POINT5: 14.5 cycles
330 \arg ADC_SAMPLETIME_27POINT5: 27.5 cycles
331 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
332 \arg ADC_SAMPLETIME_83POINT5: 83.5 cycles
333 \arg ADC_SAMPLETIME_111POINT5: 111.5 cycles
334 \arg ADC_SAMPLETIME_143POINT5: 143.5 cycles
335 \arg ADC_SAMPLETIME_479POINT5: 479.5 cycles
336 \param[out] none
337 \retval none
338 */
adc_regular_channel_config(uint32_t adc_periph,uint8_t rank,uint8_t adc_channel,uint32_t sample_time)339 void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
340 {
341 uint32_t rsq,sampt;
342
343 /* configure ADC regular sequence */
344 if(rank < 6U){
345 rsq = ADC_RSQ2(adc_periph);
346 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
347 rsq |= ((uint32_t)adc_channel << (5U*rank));
348 ADC_RSQ2(adc_periph) = rsq;
349 }else if(rank < 12U){
350 rsq = ADC_RSQ1(adc_periph);
351 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
352 rsq |= ((uint32_t)adc_channel << (5U*(rank-6U)));
353 ADC_RSQ1(adc_periph) = rsq;
354 }else if(rank < 16U){
355 rsq = ADC_RSQ0(adc_periph);
356 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
357 rsq |= ((uint32_t)adc_channel << (5U*(rank-12U)));
358 ADC_RSQ0(adc_periph) = rsq;
359 }else{
360 }
361
362 /* configure ADC sampling time */
363 if(adc_channel < 10U){
364 sampt = ADC_SAMPT1(adc_periph);
365 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
366 sampt |= (uint32_t)(sample_time << (3U*adc_channel));
367 ADC_SAMPT1(adc_periph) = sampt;
368 }else if(adc_channel < 18U){
369 sampt = ADC_SAMPT0(adc_periph);
370 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
371 sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U)));
372 ADC_SAMPT0(adc_periph) = sampt;
373 }else{
374 /* illegal parameters */
375 }
376 }
377
378 /*!
379 \brief configure ADC inserted channel
380 \param[in] adc_periph: ADCx, x=0,1
381 \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
382 \param[in] adc_channel: the selected ADC channel
383 only one parameter can be selected which is shown as below:
384 \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
385 \param[in] sample_time: The sample time value
386 only one parameter can be selected which is shown as below:
387 \arg ADC_SAMPLETIME_2POINT5: 2.5 cycles
388 \arg ADC_SAMPLETIME_14POINT5: 14.5 cycles
389 \arg ADC_SAMPLETIME_27POINT5: 27.5 cycles
390 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
391 \arg ADC_SAMPLETIME_83POINT5: 83.5 cycles
392 \arg ADC_SAMPLETIME_111POINT5: 111.5 cycles
393 \arg ADC_SAMPLETIME_143POINT5: 143.5 cycles
394 \arg ADC_SAMPLETIME_479POINT5: 479.5 cycles
395 \param[out] none
396 \retval none
397 */
adc_inserted_channel_config(uint32_t adc_periph,uint8_t rank,uint8_t adc_channel,uint32_t sample_time)398 void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
399 {
400 uint8_t inserted_length;
401 uint32_t isq, sampt;
402
403 /* get inserted channel group length */
404 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
405
406 /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
407 isq = ADC_ISQ(adc_periph);
408 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (5U * ((3U + rank) - inserted_length))));
409 isq |= ((uint32_t)adc_channel << (5U * ((3U + rank) - inserted_length)));
410 ADC_ISQ(adc_periph) = isq;
411
412 /* ADC sampling time config */
413 if(adc_channel < 10U){
414 sampt = ADC_SAMPT1(adc_periph);
415 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel)));
416 sampt |= (uint32_t) sample_time << (3U*adc_channel);
417 ADC_SAMPT1(adc_periph) = sampt;
418 }else if(adc_channel < 18U){
419 sampt = ADC_SAMPT0(adc_periph);
420 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U))));
421 sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U)));
422 ADC_SAMPT0(adc_periph) = sampt;
423 }else{
424 }
425 }
426
427 /*!
428 \brief configure ADC inserted channel offset
429 \param[in] adc_periph: ADCx, x=0,1
430 \param[in] inserted_channel : insert channel select
431 only one parameter can be selected which is shown as below:
432 \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel0
433 \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel1
434 \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel2
435 \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel3
436 \param[in] offset : the offset data
437 \param[out] none
438 \retval none
439 */
adc_inserted_channel_offset_config(uint32_t adc_periph,uint8_t inserted_channel,uint16_t offset)440 void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
441 {
442 uint8_t inserted_length;
443 uint32_t num = 0U;
444
445 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
446 num = (uint32_t)3U - ((uint32_t)inserted_length - (uint32_t)inserted_channel);
447
448 if(num <= 3U){
449 /* calculate the offset of the register */
450 num = num * 4U;
451 /* configure the offset of the selected channels */
452 REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
453 }
454 }
455
456 /*!
457 \brief configure ADC external trigger
458 \param[in] adc_periph: ADCx, x=0,1
459 \param[in] adc_channel_group: select the channel group
460 only one parameter can be selected which is shown as below:
461 \arg ADC_REGULAR_CHANNEL: regular channel group
462 \arg ADC_INSERTED_CHANNEL: inserted channel group
463 \param[in] newvalue: ENABLE or DISABLE
464 \param[out] none
465 \retval none
466 */
adc_external_trigger_config(uint32_t adc_periph,uint8_t adc_channel_group,ControlStatus newvalue)467 void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
468 {
469 if(newvalue){
470 /* external trigger enable for regular channel */
471 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
472 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ETERC;
473 }
474 /* external trigger enable for inserted channel */
475 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
476 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ETEIC;
477 }
478 }else{
479 /* external trigger disable for regular channel */
480 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
481 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETERC);
482 }
483 /* external trigger disable for inserted channel */
484 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
485 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETEIC);
486 }
487 }
488 }
489
490 /*!
491 \brief configure ADC external trigger source
492 \param[in] adc_periph: ADCx, x=0,1
493 \param[in] adc_channel_group: select the channel group
494 only one parameter can be selected which is shown as below:
495 \arg ADC_REGULAR_CHANNEL: regular channel group
496 \arg ADC_INSERTED_CHANNEL: inserted channel group
497 \param[in] external_trigger_source: regular or inserted group trigger source
498 only one parameter can be selected which is shown as below:
499 for regular channel:
500 \arg ADC0_1_EXTTRIG_REGULAR_TRIGSEL: TRIGSEL select
501 \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger
502 for inserted channel:
503 \arg ADC0_1_EXTTRIG_INSERTED_TRIGSEL: TRIGSEL select
504 \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger
505 \param[out] none
506 \retval none
507 */
adc_external_trigger_source_config(uint32_t adc_periph,uint8_t adc_channel_group,uint32_t external_trigger_source)508 void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
509 {
510 switch(adc_channel_group){
511 case ADC_REGULAR_CHANNEL:
512 /* external trigger select for regular channel */
513 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
514 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
515 break;
516 case ADC_INSERTED_CHANNEL:
517 /* external trigger select for inserted channel */
518 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
519 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
520 break;
521 default:
522 break;
523 }
524 }
525
526 /*!
527 \brief enable ADC software trigger
528 \param[in] adc_periph: ADCx, x=0,1
529 \param[in] adc_channel_group: select the channel group
530 only one parameter can be selected which is shown as below:
531 \arg ADC_REGULAR_CHANNEL: regular channel group
532 \arg ADC_INSERTED_CHANNEL: inserted channel group
533 \param[out] none
534 \retval none
535 */
adc_software_trigger_enable(uint32_t adc_periph,uint8_t adc_channel_group)536 void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
537 {
538 /* enable regular group channel software trigger */
539 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
540 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST;
541 }
542 /* enable inserted channel group software trigger */
543 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
544 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST;
545 }
546 }
547
548 /*!
549 \brief read ADC regular group data register
550 \param[in] adc_periph: ADCx, x=0,1
551 \param[in] none
552 \param[out] none
553 \retval the conversion value: 0~0xFFFF
554 */
adc_regular_data_read(uint32_t adc_periph)555 uint16_t adc_regular_data_read(uint32_t adc_periph)
556 {
557 return (uint16_t)(ADC_RDATA(adc_periph));
558 }
559
560 /*!
561 \brief read ADC inserted group data register
562 \param[in] adc_periph: ADCx, x=0,1
563 \param[in] inserted_channel: inserted channel select
564 only one parameter can be selected which is shown as below:
565 \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel0
566 \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel1
567 \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel2
568 \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel3
569 \param[out] none
570 \retval the conversion value: 0~0xFFFF
571 */
adc_inserted_data_read(uint32_t adc_periph,uint8_t inserted_channel)572 uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel)
573 {
574 uint32_t idata;
575 /* read the data of the selected channel */
576 switch(inserted_channel){
577 case ADC_INSERTED_CHANNEL_0:
578 idata = ADC_IDATA0(adc_periph);
579 break;
580 case ADC_INSERTED_CHANNEL_1:
581 idata = ADC_IDATA1(adc_periph);
582 break;
583 case ADC_INSERTED_CHANNEL_2:
584 idata = ADC_IDATA2(adc_periph);
585 break;
586 case ADC_INSERTED_CHANNEL_3:
587 idata = ADC_IDATA3(adc_periph);
588 break;
589 default:
590 idata = 0U;
591 break;
592 }
593 return (uint16_t)idata;
594 }
595
596 /*!
597 \brief read the last ADC0 and ADC1 conversion result data in sync mode
598 \param[in] none
599 \param[out] none
600 \retval the conversion value: 0~0xFFFFFFFF
601 */
adc_sync_mode_convert_value_read(void)602 uint32_t adc_sync_mode_convert_value_read(void)
603 {
604 /* return conversion value */
605 return ADC_RDATA(ADC0);
606 }
607
608 /*!
609 \brief configure ADC analog watchdog 0 single channel
610 \param[in] adc_periph: ADCx, x=0,1
611 \param[in] adc_channel: the selected ADC channel
612 only one parameter can be selected which is shown as below:
613 \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
614 \param[out] none
615 \retval none
616 */
adc_watchdog0_single_channel_enable(uint32_t adc_periph,uint8_t adc_channel)617 void adc_watchdog0_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
618 {
619 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC | ADC_CTL0_WD0CHSEL);
620
621 ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
622 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC);
623 }
624
625 /*!
626 \brief configure ADC analog watchdog 0 group channel
627 \param[in] adc_periph: ADCx, x=0,1
628 \param[in] adc_channel_group: the channel group use analog watchdog 0
629 only one parameter can be selected which is shown as below:
630 \arg ADC_REGULAR_CHANNEL: regular channel group
631 \arg ADC_INSERTED_CHANNEL: inserted channel group
632 \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
633 \param[out] none
634 \retval none
635 */
adc_watchdog0_group_channel_enable(uint32_t adc_periph,uint8_t adc_channel_group)636 void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
637 {
638 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC);
639 /* select the group */
640 switch(adc_channel_group){
641 case ADC_REGULAR_CHANNEL:
642 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWD0EN;
643 break;
644 case ADC_INSERTED_CHANNEL:
645 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_IWD0EN;
646 break;
647 case ADC_REGULAR_INSERTED_CHANNEL:
648 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN);
649 break;
650 default:
651 break;
652 }
653 }
654
655 /*!
656 \brief disable ADC analog watchdog 0
657 \param[in] adc_periph: ADCx, x=0,1
658 \param[out] none
659 \retval none
660 */
adc_watchdog0_disable(uint32_t adc_periph)661 void adc_watchdog0_disable(uint32_t adc_periph)
662 {
663 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC | ADC_CTL0_WD0CHSEL);
664 }
665
666 /*!
667 \brief configure ADC analog watchdog 1 channel
668 \param[in] adc_periph: ADCx, x=0,1
669 \param[in] adc_channel: the channel use analog watchdog 1
670 one or more parameters can be selected which is shown as below:
671 \arg ADC_AWD1_SELECTION_CHANNEL_x, ADC_AWD1_SELECTION_CHANNEL_ALL: ADC channel analog watchdog 1/2 selection
672 \param[in] newvalue: ENABLE or DISABLE
673 \param[out] none
674 \retval none
675 */
adc_watchdog1_channel_config(uint32_t adc_periph,uint32_t adc_channel,ControlStatus newvalue)676 void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue)
677 {
678 if(ENABLE == newvalue){
679 ADC_WD1SR(adc_periph) |= (uint32_t)adc_channel;
680 }else{
681 ADC_WD1SR(adc_periph) &= ~((uint32_t)adc_channel);
682 }
683 }
684
685 /*!
686 \brief disable ADC analog watchdog 1
687 \param[in] adc_periph: ADCx, x=0,1
688 \param[out] none
689 \retval none
690 */
adc_watchdog1_disable(uint32_t adc_periph)691 void adc_watchdog1_disable(uint32_t adc_periph)
692 {
693 ADC_WD1SR(adc_periph) &= (uint32_t)~(ADC_WD1SR_AWD1CS);
694 }
695
696 /*!
697 \brief configure ADC analog watchdog 0 threshold
698 \param[in] adc_periph: ADCx, x=0,1
699 \param[in] low_threshold: analog watchdog 0 low threshold, 0..4095
700 \param[in] high_threshold: analog watchdog 0 high threshold, 0..4095
701 \param[out] none
702 \retval none
703 */
adc_watchdog0_threshold_config(uint32_t adc_periph,uint16_t low_threshold,uint16_t high_threshold)704 void adc_watchdog0_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
705 {
706 ADC_WDLT0(adc_periph) = (uint32_t)WDLT0_WDLT0(low_threshold);
707 ADC_WDHT0(adc_periph) = (uint32_t)WDHT0_WDHT0(high_threshold);
708 }
709
710 /*!
711 \brief configure ADC analog watchdog 1 threshold
712 \param[in] adc_periph: ADCx, x=0,1
713 \param[in] low_threshold: analog watchdog 1 low threshold, 0..255
714 \param[in] high_threshold: analog watchdog 1 high threshold, 0..255
715 \param[out] none
716 \retval none
717 */
adc_watchdog1_threshold_config(uint32_t adc_periph,uint8_t low_threshold,uint8_t high_threshold)718 void adc_watchdog1_threshold_config(uint32_t adc_periph, uint8_t low_threshold, uint8_t high_threshold)
719 {
720 ADC_WDT1(adc_periph) &= ~((uint32_t)(ADC_WDT1_WDLT1 | ADC_WDT1_WDHT1));
721 /* configure ADC analog watchdog 1 threshold */
722 ADC_WDT1(adc_periph) |= (uint32_t)WDT1_WDLT1(low_threshold);
723 ADC_WDT1(adc_periph) |= (uint32_t)WDT1_WDHT1(high_threshold);
724 }
725
726 /*!
727 \brief configure ADC resolution
728 \param[in] adc_periph: ADCx, x=0,1
729 \param[in] resolution: ADC resolution
730 only one parameter can be selected which is shown as below:
731 \arg ADC_RESOLUTION_12B: 12-bit ADC resolution
732 \arg ADC_RESOLUTION_10B: 10-bit ADC resolution
733 \arg ADC_RESOLUTION_8B: 8-bit ADC resolution
734 \arg ADC_RESOLUTION_6B: 6-bit ADC resolution
735 \param[out] none
736 \retval none
737 */
adc_resolution_config(uint32_t adc_periph,uint32_t resolution)738 void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
739 {
740 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES);
741 ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution;
742 }
743
744 /*!
745 \brief configure ADC oversample mode
746 \param[in] adc_periph: ADCx, x=0,1
747 \param[in] mode: ADC oversampling mode
748 only one parameter can be selected which is shown as below:
749 \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger
750 \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger
751 \param[in] shift: ADC oversampling shift
752 only one parameter can be selected which is shown as below:
753 \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
754 \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
755 \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
756 \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
757 \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
758 \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
759 \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
760 \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
761 \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
762 \param[in] ratio: ADC oversampling ratio
763 only one parameter can be selected which is shown as below:
764 \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2
765 \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4
766 \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8
767 \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16
768 \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32
769 \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64
770 \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128
771 \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256
772 \param[out] none
773 \retval none
774 */
adc_oversample_mode_config(uint32_t adc_periph,uint32_t mode,uint16_t shift,uint8_t ratio)775 void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio)
776 {
777 /* configure ADC oversampling mode */
778 if(ADC_OVERSAMPLING_ONE_CONVERT == mode){
779 ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS;
780 }else{
781 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
782 }
783 /* configure the shift and ratio */
784 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
785 ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio);
786 }
787
788 /*!
789 \brief enable ADC oversample mode
790 \param[in] adc_periph: ADCx, x=0,1
791 \param[out] none
792 \retval none
793 */
adc_oversample_mode_enable(uint32_t adc_periph)794 void adc_oversample_mode_enable(uint32_t adc_periph)
795 {
796 ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_OVSEN;
797 }
798
799 /*!
800 \brief disable ADC oversample mode
801 \param[in] adc_periph: ADCx, x=0,1
802 \param[out] none
803 \retval none
804 */
adc_oversample_mode_disable(uint32_t adc_periph)805 void adc_oversample_mode_disable(uint32_t adc_periph)
806 {
807 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
808 }
809
810 /*!
811 \brief get the ADC flag
812 \param[in] adc_periph: ADCx, x=0,1
813 \param[in] flag: the ADC flag bits
814 only one parameter can be selected which is shown as below:
815 \arg ADC_FLAG_WDE0: analog watchdog 0 event flag
816 \arg ADC_FLAG_EOC: end of group conversion flag
817 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
818 \arg ADC_FLAG_STIC: start flag of inserted channel group
819 \arg ADC_FLAG_STRC: start flag of regular channel group
820 \arg ADC_FLAG_WDE1: analog watchdog 1 event flag
821 \param[out] none
822 \retval FlagStatus: SET or RESET
823 */
adc_flag_get(uint32_t adc_periph,uint32_t flag)824 FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t flag)
825 {
826 FlagStatus reval = RESET;
827 if(ADC_STAT(adc_periph) & flag){
828 reval = SET;
829 }
830 return reval;
831 }
832
833 /*!
834 \brief clear the ADC flag
835 \param[in] adc_periph: ADCx, x=0,1
836 \param[in] flag: the ADC flag
837 one or more parameters can be selected which is shown as below:
838 \arg ADC_FLAG_WDE0: analog watchdog 0 event flag
839 \arg ADC_FLAG_EOC: end of group conversion flag
840 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
841 \arg ADC_FLAG_STIC: start flag of inserted channel group
842 \arg ADC_FLAG_STRC: start flag of regular channel group
843 \arg ADC_FLAG_WDE1: analog watchdog 1 event flag
844 \param[out] none
845 \retval none
846 */
adc_flag_clear(uint32_t adc_periph,uint32_t flag)847 void adc_flag_clear(uint32_t adc_periph , uint32_t flag)
848 {
849 ADC_STAT(adc_periph) = ~((uint32_t)flag);
850 }
851
852 /*!
853 \brief enable ADC interrupt
854 \param[in] adc_periph: ADCx, x=0,1,2
855 \param[in] interrupt: the ADC interrupt
856 one or more parameters can be selected which is shown as below:
857 \arg ADC_INT_WDE0: analog watchdog 0 interrupt flag
858 \arg ADC_INT_EOC: end of group conversion interrupt flag
859 \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
860 \arg ADC_INT_WDE1: analog watchdog 1 interrupt flag
861 \param[out] none
862 \retval none
863 */
adc_interrupt_enable(uint32_t adc_periph,uint32_t interrupt)864 void adc_interrupt_enable(uint32_t adc_periph , uint32_t interrupt)
865 {
866 switch(interrupt){
867 /* enable analog watchdog 0 interrupt */
868 case ADC_INT_WDE0:
869 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_WDE0IE;
870 break;
871 /* enable end of group conversion interrupt */
872 case ADC_INT_EOC:
873 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOCIE;
874 break;
875 /* enable end of inserted group conversion interrupt */
876 case ADC_INT_EOIC:
877 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOICIE;
878 break;
879 /* enable analog watchdog 1 interrupt */
880 case ADC_INT_WDE1:
881 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_WDE1IE;
882 break;
883 default:
884 break;
885 }
886 }
887
888 /*!
889 \brief disable ADC interrupt
890 \param[in] adc_periph: ADCx, x=0,1
891 \param[in] interrupt: the ADC interrupt flag
892 one or more parameters can be selected which is shown as below:
893 \arg ADC_INT_WDE0: analog watchdog 0 interrupt flag
894 \arg ADC_INT_EOC: end of group conversion interrupt flag
895 \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
896 \arg ADC_INT_WDE1: analog watchdog 1 interrupt flag
897 \param[out] none
898 \retval none
899 */
adc_interrupt_disable(uint32_t adc_periph,uint32_t interrupt)900 void adc_interrupt_disable(uint32_t adc_periph, uint32_t interrupt)
901 {
902 switch(interrupt){
903 /* disable analog watchdog 0 interrupt */
904 case ADC_INT_WDE0:
905 ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_WDE0IE;
906 break;
907 /* disable end of group conversion interrupt */
908 case ADC_INT_EOC:
909 ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOCIE;
910 break;
911 /* disable end of inserted group conversion interrupt */
912 case ADC_INT_EOIC:
913 ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOICIE;
914 break;
915 /* disable analog watchdog 1 interrupt */
916 case ADC_INT_WDE1:
917 ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_WDE1IE;
918 break;
919 default:
920 break;
921 }
922 }
923
924 /*!
925 \brief get ADC interrupt flag
926 \param[in] adc_periph: ADCx, x=0,1
927 \param[in] int_flag: the ADC interrupt
928 only one parameter can be selected which is shown as below:
929 \arg ADC_INT_FLAG_WDE0: analog watchdog 0 interrupt flag
930 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
931 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
932 \arg ADC_INT_FLAG_WDE1: analog watchdog 1 interrupt flag
933 \param[out] none
934 \retval FlagStatus: SET or RESET
935 */
adc_interrupt_flag_get(uint32_t adc_periph,uint32_t int_flag)936 FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t int_flag)
937 {
938 FlagStatus interrupt_flag = RESET;
939 uint32_t state;
940 /* check the interrupt bits */
941 switch(int_flag){
942 case ADC_INT_FLAG_WDE0:
943 state = ADC_STAT(adc_periph) & ADC_STAT_WDE0;
944 if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state){
945 interrupt_flag = SET;
946 }
947 break;
948 case ADC_INT_FLAG_EOC:
949 state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
950 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
951 interrupt_flag = SET;
952 }
953 break;
954 case ADC_INT_FLAG_EOIC:
955 state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
956 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
957 interrupt_flag = SET;
958 }
959 break;
960 case ADC_INT_FLAG_WDE1:
961 state = ADC_STAT(adc_periph) & ADC_STAT_WDE1;
962 if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state){
963 interrupt_flag = SET;
964 }
965 break;
966 default:
967 break;
968 }
969 return interrupt_flag;
970 }
971
972 /*!
973 \brief clear ADC interrupt flag
974 \param[in] adc_periph: ADCx, x=0,1
975 \param[in] int_flag: the ADC interrupt flag
976 only one parameter can be selected which is shown as below:
977 \arg ADC_INT_FLAG_WDE0: analog watchdog 0 interrupt flag
978 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
979 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
980 \arg ADC_INT_FLAG_WDE1: analog watchdog 1 interrupt flag
981 \param[out] none
982 \retval none
983 */
adc_interrupt_flag_clear(uint32_t adc_periph,uint32_t int_flag)984 void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t int_flag)
985 {
986 ADC_STAT(adc_periph) = ~((uint32_t)int_flag);
987 }
988
