1 /*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #pragma once
8
9 #include "soc/adc_periph.h"
10 #include "hal/adc_types.h"
11 #include "soc/rtc_io_struct.h"
12 #include "soc/sens_struct.h"
13 #include "soc/syscon_struct.h"
14 #include "soc/rtc_cntl_struct.h"
15 #include <stdbool.h>
16 #include "hal/misc.h"
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 typedef enum {
23 ADC_NUM_1 = 0, /*!< SAR ADC 1 */
24 ADC_NUM_2 = 1, /*!< SAR ADC 2 */
25 ADC_NUM_MAX,
26 } adc_ll_num_t;
27
28 typedef enum {
29 ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
30 ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
31 ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */
32 ADC_POWER_MAX, /*!< For parameter check. */
33 } adc_ll_power_t;
34
35 typedef enum {
36 ADC_RTC_DATA_OK = 0,
37 } adc_ll_rtc_raw_data_t;
38
39 typedef enum {
40 ADC_LL_CTRL_RTC = 0, ///< For ADC1 and ADC2. Select RTC controller.
41 ADC_LL_CTRL_ULP = 1, ///< For ADC1 and ADC2. Select ULP controller.
42 ADC_LL_CTRL_DIG = 2, ///< For ADC1 and ADC2. Select DIG controller.
43 ADC_LL_CTRL_PWDET = 3, ///< For ADC2. Select PWDET controller.
44 } adc_ll_controller_t;
45
46 /**
47 * @brief ADC digital controller (DMA mode) work mode.
48 *
49 * @note The conversion mode affects the sampling frequency:
50 * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
51 * SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
52 * BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
53 * ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
54 */
55 typedef enum {
56 ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion
57 ADC_LL_DIGI_CONV_ONLY_ADC2 = 1, // Only use ADC2 for conversion
58 ADC_LL_DIGI_CONV_BOTH_UNIT = 2, // Use Both ADC1 and ADC2 for conversion simultaneously
59 ADC_LL_DIGI_CONV_ALTER_UNIT = 3 // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
60 } adc_ll_digi_convert_mode_t;
61
62 //Need a unit test for bit_width
63 typedef struct {
64 union {
65 struct {
66 uint8_t atten: 2;
67 uint8_t bit_width: 2; //ADC resolution. 0: 9 bit; 1: 10 bit; 2: 11 bit; 3: 12 bit
68 uint8_t channel: 4;
69 };
70 uint8_t val;
71 };
72 } __attribute__((packed)) adc_ll_digi_pattern_table_t;
73
74 typedef enum {
75 ADC_HALL_CTRL_ULP = 0x0,/*!< Hall sensor controlled by ULP */
76 ADC_HALL_CTRL_RTC = 0x1 /*!< Hall sensor controlled by RTC */
77 } adc_ll_hall_controller_t ;
78
79 /*---------------------------------------------------------------
80 Digital controller setting
81 ---------------------------------------------------------------*/
82
83 /**
84 * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms.
85 *
86 * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor.
87 * @param start_wait Delay time after open xpd.
88 * @param standby_wait Delay time to close xpd.
89 */
adc_ll_digi_set_fsm_time(uint32_t rst_wait,uint32_t start_wait,uint32_t standby_wait)90 static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
91 {
92 // Internal FSM reset wait time
93 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, rstb_wait, rst_wait);
94 // Internal FSM start wait time
95 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, start_wait, start_wait);
96 // Internal FSM standby wait time
97 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, standby_wait, standby_wait);
98 }
99
100 /**
101 * Set adc sample cycle.
102 *
103 * @note Normally, please use default value.
104 * @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
105 */
adc_ll_set_sample_cycle(uint32_t sample_cycle)106 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
107 {
108 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, sample_cycle, sample_cycle);
109 }
110
111 /**
112 * ADC module clock division factor setting. ADC clock divided from APB clock.
113 *
114 * @param div Division factor.
115 */
adc_ll_digi_set_clk_div(uint32_t div)116 static inline void adc_ll_digi_set_clk_div(uint32_t div)
117 {
118 /* ADC clock divided from APB clk, e.g. 80 / 2 = 40Mhz, */
119 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div);
120 }
121
122 /**
123 * Set adc max conversion number for digital controller.
124 * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
125 *
126 * @param meas_num Max conversion number. Range: 0 ~ 255.
127 */
adc_ll_digi_set_convert_limit_num(uint32_t meas_num)128 static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
129 {
130 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl2, max_meas_num, meas_num);
131 }
132
133 /**
134 * Enable max conversion number detection for digital controller.
135 * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
136 */
adc_ll_digi_convert_limit_enable(void)137 static inline void adc_ll_digi_convert_limit_enable(void)
138 {
139 SYSCON.saradc_ctrl2.meas_num_limit = 1;
140 }
141
142 /**
143 * Disable max conversion number detection for digital controller.
144 * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
145 */
adc_ll_digi_convert_limit_disable(void)146 static inline void adc_ll_digi_convert_limit_disable(void)
147 {
148 SYSCON.saradc_ctrl2.meas_num_limit = 0;
149 }
150
151 /**
152 * Set adc conversion mode for digital controller.
153 *
154 * @note ESP32 only support ADC1 single mode.
155 * @note For `data_sar_sel` register:
156 * 1: [15] unit, [14:11] channel, [10:0] data, 11-bit-width at most. Only work under `ADC_LL_DIGI_CONV_BOTH_UNIT` or `ADC_LL_DIGI_CONV_ALTER_UNIT` mode.
157 * 0: [15:12] channel, [11:0] data, 12-bit-width at most. Only work under `ADC_LL_DIGI_CONV_ONLY_ADC1` or `ADC_LL_DIGI_CONV_ONLY_ADC2` mode
158 *
159 * @param mode Conversion mode select.
160 */
adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)161 static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
162 {
163 if (mode == ADC_LL_DIGI_CONV_ONLY_ADC1) {
164 SYSCON.saradc_ctrl.work_mode = 0;
165 SYSCON.saradc_ctrl.sar_sel = 0;
166 SYSCON.saradc_ctrl.data_sar_sel = 0;
167 } else if (mode == ADC_LL_DIGI_CONV_ONLY_ADC2) {
168 SYSCON.saradc_ctrl.work_mode = 0;
169 SYSCON.saradc_ctrl.sar_sel = 1;
170 SYSCON.saradc_ctrl.data_sar_sel = 0;
171 } else if (mode == ADC_LL_DIGI_CONV_BOTH_UNIT) {
172 SYSCON.saradc_ctrl.work_mode = 1;
173 SYSCON.saradc_ctrl.data_sar_sel = 1;
174 } else if (mode == ADC_LL_DIGI_CONV_ALTER_UNIT) {
175 SYSCON.saradc_ctrl.work_mode = 2;
176 SYSCON.saradc_ctrl.data_sar_sel = 1;
177 }
178 }
179
180 /**
181 * ADC module Digital output data invert or not.
182 *
183 * @prarm adc_n ADC unit.
184 */
adc_ll_digi_output_invert(adc_ll_num_t adc_n,bool inv_en)185 static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en)
186 {
187 if (adc_n == ADC_NUM_1) {
188 SYSCON.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
189 } else { // adc_n == ADC_NUM_2
190 SYSCON.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
191 }
192 }
193
194 /**
195 * Set I2S DMA data source for digital controller.
196 *
197 * @param src 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix
198 */
adc_ll_digi_set_data_source(bool src)199 static inline void adc_ll_digi_set_data_source(bool src)
200 {
201 SYSCON.saradc_ctrl.data_to_i2s = src;
202 }
203
204 /**
205 * Set pattern table length for digital controller.
206 * The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
207 * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
208 * pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself.
209 *
210 * @param adc_n ADC unit.
211 * @param patt_len Items range: 1 ~ 16.
212 */
adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n,uint32_t patt_len)213 static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len)
214 {
215 if (adc_n == ADC_NUM_1) {
216 SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1;
217 } else { // adc_n == ADC_NUM_2
218 SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1;
219 }
220 }
221
222 /**
223 * Set pattern table lenth for digital controller.
224 * The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
225 * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
226 * pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself.
227 *
228 * @param adc_n ADC unit.
229 * @param pattern_index Items index. Range: 0 ~ 15.
230 * @param pattern Stored conversion rules, see ``adc_digi_pattern_table_t``.
231 */
adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n,uint32_t pattern_index,adc_digi_pattern_config_t table)232 static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
233 {
234 uint32_t tab;
235 uint8_t index = pattern_index / 4;
236 uint8_t offset = (pattern_index % 4) * 8;
237 adc_ll_digi_pattern_table_t pattern = {0};
238 uint8_t bit_width;
239
240 switch (table.bit_width) {
241 case 9:
242 bit_width = 0x0;
243 break;
244 case 10:
245 bit_width = 0x1;
246 break;
247 case 11:
248 bit_width = 0x2;
249 break;
250 case 12:
251 bit_width = 0x3;
252 break;
253 default:
254 bit_width = 0x3;
255 }
256 pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4);
257
258 if (table.unit == ADC_NUM_1) {
259 tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value
260 tab &= (~(0xFF000000 >> offset)); // clear old data
261 tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
262 SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back
263 } else { // adc_n == ADC_NUM_2
264 tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value
265 tab &= (~(0xFF000000 >> offset)); // clear old data
266 tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
267 SYSCON.saradc_sar2_patt_tab[index] = tab; // Write back
268 }
269 }
270
271 /**
272 * Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
273 *
274 * @param adc_n ADC unit.
275 */
adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n)276 static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n)
277 {
278 if (adc_n == ADC_NUM_1) {
279 SYSCON.saradc_ctrl.sar1_patt_p_clear = 1;
280 SYSCON.saradc_ctrl.sar1_patt_p_clear = 0;
281 } else { // adc_n == ADC_NUM_2
282 SYSCON.saradc_ctrl.sar2_patt_p_clear = 1;
283 SYSCON.saradc_ctrl.sar2_patt_p_clear = 0;
284 }
285 }
286
287 /**
288 * Disable clock for ADC digital controller.
289 * @note Not used for esp32
290 */
adc_ll_digi_controller_clk_disable(void)291 static inline void adc_ll_digi_controller_clk_disable(void)
292 {
293 //Leave here for compatibility
294 }
295
296 /*---------------------------------------------------------------
297 PWDET(Power detect) controller setting
298 ---------------------------------------------------------------*/
299 /**
300 * Set adc cct for PWDET controller.
301 *
302 * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
303 * @param cct Range: 0 ~ 7.
304 */
adc_ll_pwdet_set_cct(uint32_t cct)305 static inline void adc_ll_pwdet_set_cct(uint32_t cct)
306 {
307 /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
308 SENS.sar_start_force.sar2_pwdet_cct = cct;
309 }
310
311 /**
312 * Get adc cct for PWDET controller.
313 *
314 * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
315 * @return cct Range: 0 ~ 7.
316 */
adc_ll_pwdet_get_cct(void)317 static inline uint32_t adc_ll_pwdet_get_cct(void)
318 {
319 /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
320 return SENS.sar_start_force.sar2_pwdet_cct;
321 }
322
323 /*---------------------------------------------------------------
324 RTC controller setting
325 ---------------------------------------------------------------*/
326 /**
327 * ADC SAR clock division factor setting. ADC SAR clock divided from `RTC_FAST_CLK`.
328 *
329 * @param div Division factor.
330 */
adc_ll_set_sar_clk_div(adc_ll_num_t adc_n,uint32_t div)331 static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
332 {
333 if (adc_n == ADC_NUM_1) {
334 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
335 } else { // adc_n == ADC_NUM_2
336 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
337 }
338 }
339
340 /**
341 * Set adc output data format for RTC controller.
342 *
343 * @param adc_n ADC unit.
344 * @param bits Output data bits width option, see ``adc_bits_width_t``.
345 */
adc_ll_rtc_set_output_format(adc_ll_num_t adc_n,adc_bits_width_t bits)346 static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits)
347 {
348 if (adc_n == ADC_NUM_1) {
349 SENS.sar_start_force.sar1_bit_width = bits;
350 SENS.sar_read_ctrl.sar1_sample_bit = bits;
351 } else { // adc_n == ADC_NUM_2
352 SENS.sar_start_force.sar2_bit_width = bits;
353 SENS.sar_read_ctrl2.sar2_sample_bit = bits;
354 }
355 }
356
357 /**
358 * Enable adc channel to start convert.
359 *
360 * @note Only one channel can be selected in once measurement.
361 *
362 * @param adc_n ADC unit.
363 * @param channel ADC channel number for each ADCn.
364 */
adc_ll_rtc_enable_channel(adc_ll_num_t adc_n,int channel)365 static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
366 {
367 if (adc_n == ADC_NUM_1) {
368 SENS.sar_meas_start1.sar1_en_pad = (1 << channel); //only one channel is selected.
369 } else { // adc_n == ADC_NUM_2
370 SENS.sar_meas_start2.sar2_en_pad = (1 << channel); //only one channel is selected.
371 }
372 }
373
374 /**
375 * Disable adc channel to start convert.
376 *
377 * @note Only one channel can be selected in once measurement.
378 *
379 * @param adc_n ADC unit.
380 */
adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)381 static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
382 {
383 if (adc_n == ADC_NUM_1) {
384 SENS.sar_meas_start1.sar1_en_pad = 0; //only one channel is selected.
385 } else { // adc_n == ADC_NUM_2
386 SENS.sar_meas_start2.sar2_en_pad = 0; //only one channel is selected.
387 }
388 }
389
390 /**
391 * Start conversion once by software for RTC controller.
392 *
393 * @note It may be block to wait conversion idle for ADC1.
394 *
395 * @param adc_n ADC unit.
396 * @param channel ADC channel number for each ADCn.
397 */
adc_ll_rtc_start_convert(adc_ll_num_t adc_n,int channel)398 static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
399 {
400 if (adc_n == ADC_NUM_1) {
401 while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
402 SENS.sar_meas_start1.meas1_start_sar = 0;
403 SENS.sar_meas_start1.meas1_start_sar = 1;
404 } else { // adc_n == ADC_NUM_2
405 SENS.sar_meas_start2.meas2_start_sar = 0; //start force 0
406 SENS.sar_meas_start2.meas2_start_sar = 1; //start force 1
407 }
408 }
409
410 /**
411 * Check the conversion done flag for each ADCn for RTC controller.
412 *
413 * @param adc_n ADC unit.
414 * @return
415 * -true : The conversion process is finish.
416 * -false : The conversion process is not finish.
417 */
adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)418 static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
419 {
420 bool ret = true;
421 if (adc_n == ADC_NUM_1) {
422 ret = (bool)SENS.sar_meas_start1.meas1_done_sar;
423 } else { // adc_n == ADC_NUM_2
424 ret = (bool)SENS.sar_meas_start2.meas2_done_sar;
425 }
426 return ret;
427 }
428
429 /**
430 * Get the converted value for each ADCn for RTC controller.
431 *
432 * @param adc_n ADC unit.
433 * @return
434 * - Converted value.
435 */
adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)436 static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
437 {
438 int ret_val = 0;
439 if (adc_n == ADC_NUM_1) {
440 ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar);
441 } else { // adc_n == ADC_NUM_2
442 ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar);
443 }
444 return ret_val;
445 }
446
447 /**
448 * ADC module RTC output data invert or not.
449 *
450 * @param adc_n ADC unit.
451 */
adc_ll_rtc_output_invert(adc_ll_num_t adc_n,bool inv_en)452 static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
453 {
454 if (adc_n == ADC_NUM_1) {
455 SENS.sar_read_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
456 } else { // adc_n == ADC_NUM_2
457 SENS.sar_read_ctrl2.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
458 }
459 }
460
461 /**
462 * Analyze whether the obtained raw data is correct.
463 *
464 * @param adc_n ADC unit.
465 * @param raw_data ADC raw data input (convert value).
466 * @return
467 * - 0: The data is correct to use.
468 */
adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n,uint16_t raw_data)469 static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data)
470 {
471 /* ADC1 don't need check data */
472 return ADC_RTC_DATA_OK;
473 }
474
475 /**
476 * Set the attenuation of a particular channel on ADCn.
477 */
adc_ll_set_atten(adc_ll_num_t adc_n,adc_channel_t channel,adc_atten_t atten)478 static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
479 {
480 if (adc_n == ADC_NUM_1) {
481 SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
482 } else { // adc_n == ADC_NUM_2
483 SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
484 }
485 }
486
487 /**
488 * Get the attenuation of a particular channel on ADCn.
489 *
490 * @param adc_n ADC unit.
491 * @param channel ADCn channel number.
492 * @return atten The attenuation option.
493 */
adc_ll_get_atten(adc_ll_num_t adc_n,adc_channel_t channel)494 static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel)
495 {
496 if (adc_n == ADC_NUM_1) {
497 return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3);
498 } else {
499 return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);
500 }
501 }
502
503 /*---------------------------------------------------------------
504 Common setting
505 ---------------------------------------------------------------*/
506 /**
507 * Set ADC module power management.
508 *
509 * @param manage Set ADC power status.
510 */
adc_ll_set_power_manage(adc_ll_power_t manage)511 static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
512 {
513 /* Bit1 0:Fsm 1: SW mode
514 Bit0 0:SW mode power down 1: SW mode power on */
515 if (manage == ADC_POWER_SW_ON) {
516 SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
517 } else if (manage == ADC_POWER_BY_FSM) {
518 SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
519 } else if (manage == ADC_POWER_SW_OFF) {
520 SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
521 }
522 }
523
524 /**
525 * Set ADC module controller.
526 * There are five SAR ADC controllers:
527 * Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
528 * Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
529 * the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
530 *
531 * @param adc_n ADC unit.
532 * @param ctrl ADC controller.
533 */
adc_ll_set_controller(adc_ll_num_t adc_n,adc_ll_controller_t ctrl)534 static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
535 {
536 if (adc_n == ADC_NUM_1) {
537 switch ( ctrl ) {
538 case ADC_LL_CTRL_RTC:
539 SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
540 SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
541 SENS.sar_meas_start1.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
542 SENS.sar_touch_ctrl1.xpd_hall_force = 1; // 1: SW control HALL power; 0: ULP FSM control HALL power.
543 SENS.sar_touch_ctrl1.hall_phase_force = 1; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
544 break;
545 case ADC_LL_CTRL_ULP:
546 SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
547 SENS.sar_meas_start1.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
548 SENS.sar_meas_start1.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
549 SENS.sar_touch_ctrl1.xpd_hall_force = 0; // 1: SW control HALL power; 0: ULP FSM control HALL power.
550 SENS.sar_touch_ctrl1.hall_phase_force = 0; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
551 break;
552 case ADC_LL_CTRL_DIG:
553 SENS.sar_read_ctrl.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
554 SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
555 SENS.sar_meas_start1.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
556 SENS.sar_touch_ctrl1.xpd_hall_force = 1; // 1: SW control HALL power; 0: ULP FSM control HALL power.
557 SENS.sar_touch_ctrl1.hall_phase_force = 1; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
558 break;
559 default:
560 break;
561 }
562 } else { // adc_n == ADC_NUM_2
563 switch ( ctrl ) {
564 case ADC_LL_CTRL_RTC:
565 SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
566 SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
567 SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
568 SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
569 SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
570 break;
571 case ADC_LL_CTRL_ULP:
572 SENS.sar_meas_start2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
573 SENS.sar_meas_start2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
574 SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
575 SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
576 SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
577 break;
578 case ADC_LL_CTRL_DIG:
579 SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
580 SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
581 SENS.sar_read_ctrl2.sar2_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
582 SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
583 SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
584 break;
585 case ADC_LL_CTRL_PWDET: // currently only used by Wi-Fi
586 SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
587 SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
588 SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
589 SENS.sar_read_ctrl2.sar2_pwdet_force = 1; // 1: Select power detect control; 0: Select RTC control.
590 SYSCON.saradc_ctrl.sar2_mux = 0; // 1: Select digital control; 0: Select power detect control.
591 break;
592 default:
593 break;
594 }
595 }
596 }
597
598 /**
599 * Close ADC AMP module if don't use it for power save.
600 */
adc_ll_amp_disable(void)601 static inline void adc_ll_amp_disable(void)
602 {
603 //channel is set in the convert function
604 SENS.sar_meas_wait2.force_xpd_amp = SENS_FORCE_XPD_AMP_PD;
605 //disable FSM, it's only used by the LNA.
606 SENS.sar_meas_ctrl.amp_rst_fb_fsm = 0;
607 SENS.sar_meas_ctrl.amp_short_ref_fsm = 0;
608 SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0;
609 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait1, 1);
610 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1);
611 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait2, sar_amp_wait3, 1);
612 }
613
614 /*---------------------------------------------------------------
615 Hall sensor setting
616 ---------------------------------------------------------------*/
617
618 /**
619 * Enable hall sensor.
620 */
adc_ll_hall_enable(void)621 static inline void adc_ll_hall_enable(void)
622 {
623 RTCIO.hall_sens.xpd_hall = 1;
624 }
625
626 /**
627 * Disable hall sensor.
628 */
adc_ll_hall_disable(void)629 static inline void adc_ll_hall_disable(void)
630 {
631 RTCIO.hall_sens.xpd_hall = 0;
632 }
633
634 /**
635 * Reverse phase of hall sensor.
636 */
adc_ll_hall_phase_enable(void)637 static inline void adc_ll_hall_phase_enable(void)
638 {
639 RTCIO.hall_sens.hall_phase = 1;
640 }
641
642 /**
643 * Don't reverse phase of hall sensor.
644 */
adc_ll_hall_phase_disable(void)645 static inline void adc_ll_hall_phase_disable(void)
646 {
647 RTCIO.hall_sens.hall_phase = 0;
648 }
649
650 /**
651 * Set hall sensor controller.
652 *
653 * @param hall_ctrl Hall controller.
654 */
adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl)655 static inline void adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl)
656 {
657 SENS.sar_touch_ctrl1.xpd_hall_force = hall_ctrl; // 1: SW control HALL power; 0: ULP FSM control HALL power.
658 SENS.sar_touch_ctrl1.hall_phase_force = hall_ctrl; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
659 }
660
661 /**
662 * Output ADC internal reference voltage to channels, only available for ADC2 on ESP32.
663 *
664 * This function routes the internal reference voltage of ADCn to one of
665 * ADC2's channels. This reference voltage can then be manually measured
666 * for calibration purposes.
667 *
668 * @param[in] adc ADC unit select
669 * @param[in] channel ADC2 channel number
670 * @param[in] en Enable/disable the reference voltage output
671 */
adc_ll_vref_output(adc_ll_num_t adc,adc_channel_t channel,bool en)672 static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
673 {
674 if (adc != ADC_NUM_2) return;
675
676 if (en) {
677 RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode
678 //set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2)
679 RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels
680 //set ent
681 RTCCNTL.test_mux.ent_rtc = 1;
682 //set sar2_en_test
683 SENS.sar_start_force.sar2_en_test = 1;
684 //set sar2 en force
685 SENS.sar_meas_start2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW
686 //set en_pad for channels 7,8,9 (bits 0x380)
687 SENS.sar_meas_start2.sar2_en_pad = 1 << channel;
688 } else {
689 RTCCNTL.test_mux.dtest_rtc = 0; //Config test mux to route v_ref to ADC2 Channels
690 //set ent
691 RTCCNTL.test_mux.ent_rtc = 0;
692 //set sar2_en_test
693 SENS.sar_start_force.sar2_en_test = 0;
694 //set sar2 en force
695 SENS.sar_meas_start2.sar2_en_pad_force = 0; //Pad bitmap controlled by SW
696 //set en_pad for channels 7,8,9 (bits 0x380)
697 SENS.sar_meas_start2.sar2_en_pad = 0;
698 }
699 }
700
701 #ifdef __cplusplus
702 }
703 #endif
704
