1 /*
2 * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <sys/param.h>
8 #include "sdkconfig.h"
9 #include "hal/adc_hal.h"
10 #include "hal/assert.h"
11 #include "soc/lldesc.h"
12 #include "soc/soc_caps.h"
13
14 #if CONFIG_IDF_TARGET_ESP32
15 //ADC utilises I2S0 DMA on ESP32
16 #include "hal/i2s_hal.h"
17 #include "hal/i2s_types.h"
18 #include "soc/i2s_struct.h"
19 #endif
20
21 #if CONFIG_IDF_TARGET_ESP32S2
22 //ADC utilises SPI3 DMA on ESP32S2
23 #include "hal/spi_ll.h"
24 #include "soc/spi_struct.h"
25 #endif
26
27 /*---------------------------------------------------------------
28 Define all ADC DMA required operations here
29 ---------------------------------------------------------------*/
30 #if SOC_GDMA_SUPPORTED
31 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) gdma_ll_rx_clear_interrupt_status(dev, chan, mask)
32 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask, true)
33 #define adc_dma_ll_rx_disable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask, false)
34 #define adc_dma_ll_rx_reset_channel(dev, chan) gdma_ll_rx_reset_channel(dev, chan)
35 #define adc_dma_ll_rx_stop(dev, chan) gdma_ll_rx_stop(dev, chan)
36 #define adc_dma_ll_rx_start(dev, chan, addr) do { \
37 gdma_ll_rx_set_desc_addr(dev, chan, (uint32_t)addr); \
38 gdma_ll_rx_start(dev, chan); \
39 } while (0)
40 #define adc_ll_digi_dma_set_eof_num(dev, num) adc_ll_digi_dma_set_eof_num(num)
41 #define adc_ll_digi_reset(dev) adc_ll_digi_reset()
42 #define adc_ll_digi_trigger_enable(dev) adc_ll_digi_trigger_enable()
43 #define adc_ll_digi_trigger_disable(dev) adc_ll_digi_trigger_disable()
44
45 //ADC utilises SPI3 DMA on ESP32S2
46 #elif CONFIG_IDF_TARGET_ESP32S2
47 #define adc_dma_ll_rx_get_intr(dev, mask) spi_ll_get_intr(dev, mask)
48 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) spi_ll_clear_intr(dev, mask)
49 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) spi_ll_enable_intr(dev, mask)
50 #define adc_dma_ll_rx_disable_intr(dev, chan, mask) spi_ll_disable_intr(dev, mask)
51 #define adc_dma_ll_rx_reset_channel(dev, chan) spi_dma_ll_rx_reset(dev, chan)
52 #define adc_dma_ll_rx_stop(dev, chan) spi_dma_ll_rx_stop(dev, chan)
53 #define adc_dma_ll_rx_start(dev, chan, addr) spi_dma_ll_rx_start(dev, chan, addr)
54 #define adc_dma_ll_get_in_suc_eof_desc_addr(dev, chan) spi_dma_ll_get_in_suc_eof_desc_addr(dev, chan)
55 #define adc_ll_digi_dma_set_eof_num(dev, num) adc_ll_digi_dma_set_eof_num(num)
56 #define adc_ll_digi_reset(dev) adc_ll_digi_reset()
57 #define adc_ll_digi_trigger_enable(dev) adc_ll_digi_trigger_enable()
58 #define adc_ll_digi_trigger_disable(dev) adc_ll_digi_trigger_disable()
59
60 //ADC utilises I2S0 DMA on ESP32
61 #else //CONFIG_IDF_TARGET_ESP32
62 #define adc_dma_ll_rx_get_intr(dev, mask) ({i2s_ll_get_intr_status(dev) & mask;})
63 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) i2s_ll_clear_intr_status(dev, mask)
64 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) do {((i2s_dev_t *)(dev))->int_ena.val |= mask;} while (0)
65 #define adc_dma_ll_rx_disable_intr(dev, chan, mask) do {((i2s_dev_t *)(dev))->int_ena.val &= ~mask;} while (0)
66 #define adc_dma_ll_rx_reset_channel(dev, chan) i2s_ll_rx_reset_dma(dev)
67 #define adc_dma_ll_rx_stop(dev, chan) i2s_ll_rx_stop_link(dev)
68 #define adc_dma_ll_rx_start(dev, chan, address) do { \
69 ((i2s_dev_t *)(dev))->in_link.addr = (uint32_t)(address); \
70 i2s_ll_enable_dma(dev, 1); \
71 ((i2s_dev_t *)(dev))->in_link.start = 1; \
72 } while (0)
73 #define adc_dma_ll_get_in_suc_eof_desc_addr(dev, chan) ({uint32_t addr; i2s_ll_rx_get_eof_des_addr(dev, &addr); addr;})
74 #define adc_ll_digi_dma_set_eof_num(dev, num) do {((i2s_dev_t *)(dev))->rx_eof_num = num;} while (0)
75 #define adc_ll_digi_reset(dev) do { \
76 i2s_ll_rx_reset(dev); \
77 i2s_ll_rx_reset_fifo(dev); \
78 } while (0)
79 #define adc_ll_digi_trigger_enable(dev) i2s_ll_rx_start(dev)
80 #define adc_ll_digi_trigger_disable(dev) i2s_ll_rx_stop(dev)
81 #define adc_ll_digi_dma_enable() adc_ll_digi_set_data_source(1) //Will this influence I2S0
82 #define adc_ll_digi_dma_disable() adc_ll_digi_set_data_source(0)
83
84 //ESP32 ADC uses the DMA through I2S. The I2S needs to be configured.
85 #define I2S_BASE_CLK (160 * 1000 * 1000)
86 #define SAMPLE_BITS 16
87 #define ADC_LL_CLKM_DIV_NUM_DEFAULT 2
88 #define ADC_LL_CLKM_DIV_B_DEFAULT 0
89 #define ADC_LL_CLKM_DIV_A_DEFAULT 1
90
91 #endif
92
93
94
adc_hal_dma_ctx_config(adc_hal_dma_ctx_t * hal,const adc_hal_dma_config_t * config)95 void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *config)
96 {
97 hal->desc_dummy_head.next = hal->rx_desc;
98 hal->dev = config->dev;
99 hal->eof_desc_num = config->eof_desc_num;
100 hal->eof_step = config->eof_step;
101 hal->dma_chan = config->dma_chan;
102 hal->eof_num = config->eof_num;
103 }
104
adc_hal_digi_init(adc_hal_dma_ctx_t * hal)105 void adc_hal_digi_init(adc_hal_dma_ctx_t *hal)
106 {
107 // Set internal FSM wait time, fixed value.
108 adc_ll_digi_set_fsm_time(ADC_LL_FSM_RSTB_WAIT_DEFAULT, ADC_LL_FSM_START_WAIT_DEFAULT,
109 ADC_LL_FSM_STANDBY_WAIT_DEFAULT);
110 adc_ll_set_sample_cycle(ADC_LL_SAMPLE_CYCLE_DEFAULT);
111 adc_hal_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
112 adc_ll_digi_output_invert(ADC_UNIT_1, ADC_LL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
113 adc_ll_digi_output_invert(ADC_UNIT_2, ADC_LL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
114 adc_ll_digi_set_clk_div(ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT);
115
116 adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
117 adc_dma_ll_rx_enable_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
118 adc_ll_digi_dma_set_eof_num(hal->dev, hal->eof_num);
119 #if CONFIG_IDF_TARGET_ESP32
120 i2s_ll_rx_set_sample_bit(hal->dev, SAMPLE_BITS, SAMPLE_BITS);
121 i2s_ll_rx_enable_mono_mode(hal->dev, 1);
122 i2s_ll_rx_force_enable_fifo_mod(hal->dev, 1);
123 i2s_ll_enable_builtin_adc(hal->dev, 1);
124 #endif
125
126 adc_oneshot_ll_disable_all_unit();
127 }
128
adc_hal_digi_deinit(adc_hal_dma_ctx_t * hal)129 void adc_hal_digi_deinit(adc_hal_dma_ctx_t *hal)
130 {
131 adc_ll_digi_trigger_disable(hal->dev);
132 adc_ll_digi_dma_disable();
133 adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
134 adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
135 adc_ll_digi_reset(hal->dev);
136 adc_ll_digi_controller_clk_disable();
137 }
138
139 /*---------------------------------------------------------------
140 DMA read
141 ---------------------------------------------------------------*/
get_convert_mode(adc_digi_convert_mode_t convert_mode)142 static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t convert_mode)
143 {
144 #if CONFIG_IDF_TARGET_ESP32 || SOC_ADC_DIGI_CONTROLLER_NUM == 1
145 return ADC_LL_DIGI_CONV_ONLY_ADC1;
146 #elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
147 switch (convert_mode) {
148 case ADC_CONV_SINGLE_UNIT_1:
149 return ADC_LL_DIGI_CONV_ONLY_ADC1;
150 case ADC_CONV_SINGLE_UNIT_2:
151 return ADC_LL_DIGI_CONV_ONLY_ADC2;
152 case ADC_CONV_BOTH_UNIT:
153 return ADC_LL_DIGI_CONV_BOTH_UNIT;
154 case ADC_CONV_ALTER_UNIT:
155 return ADC_LL_DIGI_CONV_ALTER_UNIT;
156 default:
157 abort();
158 }
159 #endif
160 }
161
162 /**
163 * For esp32s2 and later chips
164 * - Set ADC digital controller clock division factor. The clock is divided from `APLL` or `APB` clock.
165 * Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1).
166 * - Enable clock and select clock source for ADC digital controller.
167 * For esp32, use I2S clock
168 */
adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t * hal,adc_continuous_clk_src_t clk_src,uint32_t clk_src_freq_hz,uint32_t sample_freq_hz)169 static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuous_clk_src_t clk_src, uint32_t clk_src_freq_hz, uint32_t sample_freq_hz)
170 {
171 #if !CONFIG_IDF_TARGET_ESP32
172 uint32_t interval = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / sample_freq_hz;
173 //set sample interval
174 adc_ll_digi_set_trigger_interval(interval);
175 //Here we set the clock divider factor to make the digital clock to 5M Hz
176 adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT);
177 adc_ll_digi_clk_sel(clk_src);
178 #else
179 i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_SRC_DEFAULT); /*!< Clock from PLL_D2_CLK(160M)*/
180 uint32_t bclk_div = 16;
181 uint32_t bclk = sample_freq_hz * 2;
182 uint32_t mclk = bclk * bclk_div;
183 i2s_ll_mclk_div_t mclk_div = {};
184 i2s_hal_calc_mclk_precise_division(I2S_BASE_CLK, mclk, &mclk_div);
185 i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
186 i2s_ll_rx_set_bck_div_num(hal->dev, bclk_div);
187 #endif
188 }
189
adc_hal_digi_controller_config(adc_hal_dma_ctx_t * hal,const adc_hal_digi_ctrlr_cfg_t * cfg)190 void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg)
191 {
192 #if (SOC_ADC_DIGI_CONTROLLER_NUM == 1)
193 //Only one pattern table, this variable is for readability
194 const int pattern_both = 0;
195
196 adc_ll_digi_clear_pattern_table(pattern_both);
197 adc_ll_digi_set_pattern_table_len(pattern_both, cfg->adc_pattern_len);
198 for (int i = 0; i < cfg->adc_pattern_len; i++) {
199 adc_ll_digi_set_pattern_table(pattern_both, i, cfg->adc_pattern[i]);
200 }
201
202 #elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
203 uint32_t adc1_pattern_idx = 0;
204 uint32_t adc2_pattern_idx = 0;
205
206 adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
207 adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
208
209 for (int i = 0; i < cfg->adc_pattern_len; i++) {
210 if (cfg->adc_pattern[i].unit == ADC_UNIT_1) {
211 adc_ll_digi_set_pattern_table(ADC_UNIT_1, adc1_pattern_idx, cfg->adc_pattern[i]);
212 adc1_pattern_idx++;
213 } else if (cfg->adc_pattern[i].unit == ADC_UNIT_2) {
214 adc_ll_digi_set_pattern_table(ADC_UNIT_2, adc2_pattern_idx, cfg->adc_pattern[i]);
215 adc2_pattern_idx++;
216 } else {
217 abort();
218 }
219 }
220 adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, adc1_pattern_idx);
221 adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, adc2_pattern_idx);
222
223 #endif
224
225 adc_ll_digi_convert_limit_enable(ADC_LL_DEFAULT_CONV_LIMIT_EN);
226 adc_ll_digi_set_convert_limit_num(ADC_LL_DEFAULT_CONV_LIMIT_NUM);
227 adc_ll_digi_set_convert_mode(get_convert_mode(cfg->conv_mode));
228
229 //clock and sample frequency
230 adc_hal_digi_sample_freq_config(hal, cfg->clk_src, cfg->clk_src_freq_hz, cfg->sample_freq_hz);
231 }
232
adc_hal_digi_dma_link_descriptors(dma_descriptor_t * desc,uint8_t * data_buf,uint32_t per_eof_size,uint32_t eof_step,uint32_t eof_num)233 static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t per_eof_size, uint32_t eof_step, uint32_t eof_num)
234 {
235 HAL_ASSERT(((uint32_t)data_buf % 4) == 0);
236 HAL_ASSERT((per_eof_size % 4) == 0);
237 uint32_t n = 0;
238 dma_descriptor_t *desc_head = desc;
239
240 while (eof_num--) {
241 uint32_t eof_size = per_eof_size;
242
243 for (int i = 0; i < eof_step; i++) {
244 uint32_t this_len = eof_size;
245 if (this_len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) {
246 this_len = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
247 }
248
249 desc[n] = (dma_descriptor_t) {
250 .dw0.size = this_len,
251 .dw0.length = 0,
252 .dw0.suc_eof = 0,
253 .dw0.owner = 1,
254 .buffer = data_buf,
255 .next = &desc[n+1]
256 };
257 eof_size -= this_len;
258 data_buf += this_len;
259 n++;
260 }
261 }
262 desc[n-1].next = desc_head;
263 }
264
adc_hal_digi_start(adc_hal_dma_ctx_t * hal,uint8_t * data_buf)265 void adc_hal_digi_start(adc_hal_dma_ctx_t *hal, uint8_t *data_buf)
266 {
267 //stop peripheral and DMA
268 adc_hal_digi_stop(hal);
269
270 //reset DMA
271 adc_dma_ll_rx_reset_channel(hal->dev, hal->dma_chan);
272 //reset peripheral
273 adc_ll_digi_reset(hal->dev);
274
275 //reset the current descriptor address
276 hal->cur_desc_ptr = &hal->desc_dummy_head;
277 adc_hal_digi_dma_link_descriptors(hal->rx_desc, data_buf, hal->eof_num * SOC_ADC_DIGI_DATA_BYTES_PER_CONV, hal->eof_step, hal->eof_desc_num);
278
279 //start DMA
280 adc_dma_ll_rx_start(hal->dev, hal->dma_chan, (lldesc_t *)hal->rx_desc);
281 //connect DMA and peripheral
282 adc_ll_digi_dma_enable();
283 //start ADC
284 adc_ll_digi_trigger_enable(hal->dev);
285 }
286
287 #if !SOC_GDMA_SUPPORTED
adc_hal_get_desc_addr(adc_hal_dma_ctx_t * hal)288 intptr_t adc_hal_get_desc_addr(adc_hal_dma_ctx_t *hal)
289 {
290 return adc_dma_ll_get_in_suc_eof_desc_addr(hal->dev, hal->dma_chan);
291 }
292
adc_hal_check_event(adc_hal_dma_ctx_t * hal,uint32_t mask)293 bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask)
294 {
295 return adc_dma_ll_rx_get_intr(hal->dev, mask);
296 }
297 #endif //#if !SOC_GDMA_SUPPORTED
298
adc_hal_get_reading_result(adc_hal_dma_ctx_t * hal,const intptr_t eof_desc_addr,uint8_t ** buffer,uint32_t * len)299 adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len)
300 {
301 HAL_ASSERT(hal->cur_desc_ptr);
302
303 if (!hal->cur_desc_ptr->next) {
304 return ADC_HAL_DMA_DESC_NULL;
305 }
306
307 if ((intptr_t)hal->cur_desc_ptr == eof_desc_addr) {
308 return ADC_HAL_DMA_DESC_WAITING;
309 }
310
311 uint8_t *buffer_start = NULL;
312 uint32_t eof_len = 0;
313 dma_descriptor_t *eof_desc = hal->cur_desc_ptr;
314
315 //Find the eof list start
316 eof_desc = eof_desc->next;
317 eof_desc->dw0.owner = 1;
318 buffer_start = eof_desc->buffer;
319 eof_len += eof_desc->dw0.length;
320 if ((intptr_t)eof_desc == eof_desc_addr) {
321 goto valid;
322 }
323
324 //Find the eof list end
325 for (int i = 1; i < hal->eof_step; i++) {
326 eof_desc = eof_desc->next;
327 eof_desc->dw0.owner = 1;
328 eof_len += eof_desc->dw0.length;
329 if ((intptr_t)eof_desc == eof_desc_addr) {
330 goto valid;
331 }
332 }
333
334 valid:
335 hal->cur_desc_ptr = eof_desc;
336 *buffer = buffer_start;
337 *len = eof_len;
338
339 return ADC_HAL_DMA_DESC_VALID;
340 }
341
adc_hal_digi_clr_intr(adc_hal_dma_ctx_t * hal,uint32_t mask)342 void adc_hal_digi_clr_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)
343 {
344 adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, mask);
345 }
346
adc_hal_digi_dis_intr(adc_hal_dma_ctx_t * hal,uint32_t mask)347 void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)
348 {
349 adc_dma_ll_rx_disable_intr(hal->dev, hal->dma_chan, mask);
350 }
351
adc_hal_digi_stop(adc_hal_dma_ctx_t * hal)352 void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal)
353 {
354 //stop ADC
355 adc_ll_digi_trigger_disable(hal->dev);
356 //stop DMA
357 adc_dma_ll_rx_stop(hal->dev, hal->dma_chan);
358 //disconnect DMA and peripheral
359 adc_ll_digi_dma_disable();
360 }
361
362 #if ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER
adc_hal_digi_clr_eof(void)363 void adc_hal_digi_clr_eof(void)
364 {
365 adc_ll_digi_dma_clr_eof();
366 }
367 #endif
368
