1 // Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdlib.h>
16 #include <ctype.h>
17 #include "sdkconfig.h"
18 #include "esp_types.h"
19 #include "esp_log.h"
20 #include "sys/lock.h"
21 #include "freertos/FreeRTOS.h"
22 #include "freertos/xtensa_api.h"
23 #include "freertos/semphr.h"
24 #include "freertos/timers.h"
25 #include "esp_pm.h"
26 #include "esp_intr_alloc.h"
27 #include "driver/periph_ctrl.h"
28 #include "driver/rtc_io.h"
29 #include "driver/rtc_cntl.h"
30 #include "driver/gpio.h"
31 #include "driver/adc.h"
32 #include "esp32s2/esp_efuse_rtc_table.h"
33
34 #include "hal/adc_types.h"
35 #include "hal/adc_hal.h"
36
37 #define ADC_CHECK_RET(fun_ret) ({ \
38 if (fun_ret != ESP_OK) { \
39 ESP_LOGE(ADC_TAG,"%s:%d\n",__FUNCTION__,__LINE__); \
40 return ESP_FAIL; \
41 } \
42 })
43
44 static const char *ADC_TAG = "ADC";
45
46 #define ADC_CHECK(a, str, ret_val) ({ \
47 if (!(a)) { \
48 ESP_LOGE(ADC_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
49 return (ret_val); \
50 } \
51 })
52
53 #define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
54
55 #define ADC_CHANNEL_CHECK(periph, channel) ADC_CHECK(channel < SOC_ADC_CHANNEL_NUM(periph), "ADC"#periph" channel error", ESP_ERR_INVALID_ARG)
56
57 extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
58 #define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
59 #define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
60
61 #ifdef CONFIG_PM_ENABLE
62 static esp_pm_lock_handle_t s_adc_digi_arbiter_lock = NULL;
63 #endif //CONFIG_PM_ENABLE
64
65 esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten);
66
67 /*---------------------------------------------------------------
68 Digital controller setting
69 ---------------------------------------------------------------*/
adc_digi_init(void)70 esp_err_t adc_digi_init(void)
71 {
72 adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
73 ADC_ENTER_CRITICAL();
74 adc_hal_init();
75 adc_hal_arbiter_config(&config);
76 ADC_EXIT_CRITICAL();
77
78 adc_hal_calibration_init(ADC_NUM_1);
79 adc_hal_calibration_init(ADC_NUM_2);
80
81 return ESP_OK;
82 }
83
adc_digi_deinit(void)84 esp_err_t adc_digi_deinit(void)
85 {
86 #ifdef CONFIG_PM_ENABLE
87 if (s_adc_digi_arbiter_lock) {
88 esp_pm_lock_delete(s_adc_digi_arbiter_lock);
89 s_adc_digi_arbiter_lock = NULL;
90 }
91 #endif
92 adc_power_release();
93 ADC_ENTER_CRITICAL();
94 adc_hal_digi_deinit();
95 ADC_EXIT_CRITICAL();
96 return ESP_OK;
97 }
98
adc_digi_controller_config(const adc_digi_config_t * config)99 esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
100 {
101 #ifdef CONFIG_PM_ENABLE
102 esp_err_t err;
103 if (s_adc_digi_arbiter_lock == NULL) {
104 if (config->dig_clk.use_apll) {
105 err = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "adc_dma", &s_adc_digi_arbiter_lock);
106 } else {
107 err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc_dma", &s_adc_digi_arbiter_lock);
108 }
109 if (err != ESP_OK) {
110 s_adc_digi_arbiter_lock = NULL;
111 ESP_LOGE(ADC_TAG, "ADC-DMA pm lock error");
112 return err;
113 }
114 }
115 #endif //CONFIG_PM_ENABLE
116
117 if (config->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
118 for (int i = 0; i < config->adc1_pattern_len; i++) {
119 adc_cal_offset(ADC_NUM_1, config->adc1_pattern[i].channel, config->adc1_pattern[i].atten);
120 }
121 }
122 if (config->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
123 for (int i = 0; i < config->adc2_pattern_len; i++) {
124 adc_cal_offset(ADC_NUM_2, config->adc2_pattern[i].channel, config->adc2_pattern[i].atten);
125 }
126 }
127
128 /* If enable digtal controller, adc xpd should always on. */
129 adc_power_acquire();
130 ADC_ENTER_CRITICAL();
131 adc_hal_digi_controller_config(config);
132 ADC_EXIT_CRITICAL();
133 return ESP_OK;
134 }
135
adc_arbiter_config(adc_unit_t adc_unit,adc_arbiter_t * config)136 esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config)
137 {
138 if (adc_unit & ADC_UNIT_1) {
139 return ESP_ERR_NOT_SUPPORTED;
140 }
141 ADC_ENTER_CRITICAL();
142 adc_hal_arbiter_config(config);
143 ADC_EXIT_CRITICAL();
144 return ESP_OK;
145 }
146
147 /**
148 * @brief Set ADC module controller.
149 * There are five SAR ADC controllers:
150 * Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
151 * Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
152 * the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
153 *
154 * @note Only ADC2 support arbiter to switch controllers automatically. Access to the ADC is based on the priority of the controller.
155 * @note For ADC1, Controller access is mutually exclusive.
156 *
157 * @param adc_unit ADC unit.
158 * @param ctrl ADC controller, Refer to `adc_ll_controller_t`.
159 *
160 * @return
161 * - ESP_OK Success
162 */
adc_set_controller(adc_unit_t adc_unit,adc_ll_controller_t ctrl)163 esp_err_t adc_set_controller(adc_unit_t adc_unit, adc_ll_controller_t ctrl)
164 {
165 adc_arbiter_t config = {0};
166 adc_arbiter_t cfg = ADC_ARBITER_CONFIG_DEFAULT();
167
168 if (adc_unit & ADC_UNIT_1) {
169 adc_hal_set_controller(ADC_NUM_1, ctrl);
170 }
171 if (adc_unit & ADC_UNIT_2) {
172 adc_hal_set_controller(ADC_NUM_2, ctrl);
173 switch (ctrl) {
174 case ADC2_CTRL_FORCE_PWDET:
175 config.pwdet_pri = 2;
176 config.mode = ADC_ARB_MODE_SHIELD;
177 adc_hal_arbiter_config(&config);
178 adc_hal_set_controller(ADC_NUM_2, ADC2_CTRL_PWDET);
179 break;
180 case ADC2_CTRL_FORCE_RTC:
181 config.rtc_pri = 2;
182 config.mode = ADC_ARB_MODE_SHIELD;
183 adc_hal_arbiter_config(&config);
184 adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);
185 break;
186 case ADC2_CTRL_FORCE_ULP:
187 config.rtc_pri = 2;
188 config.mode = ADC_ARB_MODE_SHIELD;
189 adc_hal_arbiter_config(&config);
190 adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_ULP);
191 break;
192 case ADC2_CTRL_FORCE_DIG:
193 config.dig_pri = 2;
194 config.mode = ADC_ARB_MODE_SHIELD;
195 adc_hal_arbiter_config(&config);
196 adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_DIG);
197 break;
198 default:
199 adc_hal_arbiter_config(&cfg);
200 break;
201 }
202 }
203 return ESP_OK;
204 }
205
adc_digi_start(void)206 esp_err_t adc_digi_start(void)
207 {
208 #ifdef CONFIG_PM_ENABLE
209 ADC_CHECK((s_adc_digi_arbiter_lock), "Should start after call `adc_digi_controller_config`", ESP_FAIL);
210 esp_pm_lock_acquire(s_adc_digi_arbiter_lock);
211 #endif
212 ADC_ENTER_CRITICAL();
213 adc_hal_digi_enable();
214 ADC_EXIT_CRITICAL();
215 return ESP_OK;
216 }
217
adc_digi_stop(void)218 esp_err_t adc_digi_stop(void)
219 {
220 #ifdef CONFIG_PM_ENABLE
221 if (s_adc_digi_arbiter_lock) {
222 esp_pm_lock_release(s_adc_digi_arbiter_lock);
223 }
224 #endif
225 ADC_ENTER_CRITICAL();
226 adc_hal_digi_disable();
227 ADC_EXIT_CRITICAL();
228 return ESP_OK;
229 }
230
231 /**
232 * @brief Reset FSM of adc digital controller.
233 *
234 * @return
235 * - ESP_OK Success
236 */
adc_digi_reset(void)237 esp_err_t adc_digi_reset(void)
238 {
239 ADC_ENTER_CRITICAL();
240 adc_hal_digi_reset();
241 adc_hal_digi_clear_pattern_table(ADC_NUM_1);
242 adc_hal_digi_clear_pattern_table(ADC_NUM_2);
243 ADC_EXIT_CRITICAL();
244 return ESP_OK;
245 }
246
247 /*************************************/
248 /* Digital controller filter setting */
249 /*************************************/
250
adc_digi_filter_reset(adc_digi_filter_idx_t idx)251 esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx)
252 {
253 ADC_ENTER_CRITICAL();
254 if (idx == ADC_DIGI_FILTER_IDX0) {
255 adc_hal_digi_filter_reset(ADC_NUM_1);
256 } else if (idx == ADC_DIGI_FILTER_IDX1) {
257 adc_hal_digi_filter_reset(ADC_NUM_2);
258 }
259 ADC_EXIT_CRITICAL();
260 return ESP_OK;
261 }
262
adc_digi_filter_set_config(adc_digi_filter_idx_t idx,adc_digi_filter_t * config)263 esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config)
264 {
265 ADC_ENTER_CRITICAL();
266 if (idx == ADC_DIGI_FILTER_IDX0) {
267 adc_hal_digi_filter_set_factor(ADC_NUM_1, config->mode);
268 } else if (idx == ADC_DIGI_FILTER_IDX1) {
269 adc_hal_digi_filter_set_factor(ADC_NUM_2, config->mode);
270 }
271 ADC_EXIT_CRITICAL();
272 return ESP_OK;
273 }
274
adc_digi_filter_get_config(adc_digi_filter_idx_t idx,adc_digi_filter_t * config)275 esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config)
276 {
277 ADC_ENTER_CRITICAL();
278 if (idx == ADC_DIGI_FILTER_IDX0) {
279 config->adc_unit = ADC_UNIT_1;
280 config->channel = ADC_CHANNEL_MAX;
281 adc_hal_digi_filter_get_factor(ADC_NUM_1, &config->mode);
282 } else if (idx == ADC_DIGI_FILTER_IDX1) {
283 config->adc_unit = ADC_UNIT_2;
284 config->channel = ADC_CHANNEL_MAX;
285 adc_hal_digi_filter_get_factor(ADC_NUM_2, &config->mode);
286 }
287 ADC_EXIT_CRITICAL();
288 return ESP_OK;
289 }
290
adc_digi_filter_enable(adc_digi_filter_idx_t idx,bool enable)291 esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable)
292 {
293 ADC_ENTER_CRITICAL();
294 if (idx == ADC_DIGI_FILTER_IDX0) {
295 adc_hal_digi_filter_enable(ADC_NUM_1, enable);
296 } else if (idx == ADC_DIGI_FILTER_IDX1) {
297 adc_hal_digi_filter_enable(ADC_NUM_2, enable);
298 }
299 ADC_EXIT_CRITICAL();
300 return ESP_OK;
301 }
302
303 /**
304 * @brief Get the filtered data of adc digital controller filter. For debug.
305 * The data after each measurement and filtering is updated to the DMA by the digital controller. But it can also be obtained manually through this API.
306 *
307 * @note For ESP32S2, The filter will filter all the enabled channel data of the each ADC unit at the same time.
308 * @param idx Filter index.
309 * @return Filtered data. if <0, the read data invalid.
310 */
adc_digi_filter_read_data(adc_digi_filter_idx_t idx)311 int adc_digi_filter_read_data(adc_digi_filter_idx_t idx)
312 {
313 if (idx == ADC_DIGI_FILTER_IDX0) {
314 return adc_hal_digi_filter_read_data(ADC_NUM_1);
315 } else if (idx == ADC_DIGI_FILTER_IDX1) {
316 return adc_hal_digi_filter_read_data(ADC_NUM_2);
317 } else {
318 return -1;
319 }
320 }
321
322 /**************************************/
323 /* Digital controller monitor setting */
324 /**************************************/
325
adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx,adc_digi_monitor_t * config)326 esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config)
327 {
328 ADC_ENTER_CRITICAL();
329 if (idx == ADC_DIGI_MONITOR_IDX0) {
330 adc_hal_digi_monitor_config(ADC_NUM_1, config);
331 } else if (idx == ADC_DIGI_MONITOR_IDX1) {
332 adc_hal_digi_monitor_config(ADC_NUM_2, config);
333 }
334 ADC_EXIT_CRITICAL();
335 return ESP_OK;
336 }
337
adc_digi_monitor_enable(adc_digi_monitor_idx_t idx,bool enable)338 esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable)
339 {
340 ADC_ENTER_CRITICAL();
341 if (idx == ADC_DIGI_MONITOR_IDX0) {
342 adc_hal_digi_monitor_enable(ADC_NUM_1, enable);
343 } else if (idx == ADC_DIGI_MONITOR_IDX1) {
344 adc_hal_digi_monitor_enable(ADC_NUM_2, enable);
345 }
346 ADC_EXIT_CRITICAL();
347 return ESP_OK;
348 }
349
350 /**************************************/
351 /* Digital controller intr setting */
352 /**************************************/
353
adc_digi_intr_enable(adc_unit_t adc_unit,adc_digi_intr_t intr_mask)354 esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
355 {
356 ADC_ENTER_CRITICAL();
357 if (adc_unit & ADC_UNIT_1) {
358 adc_hal_digi_intr_enable(ADC_NUM_1, intr_mask);
359 }
360 if (adc_unit & ADC_UNIT_2) {
361 adc_hal_digi_intr_enable(ADC_NUM_2, intr_mask);
362 }
363 ADC_EXIT_CRITICAL();
364 return ESP_OK;
365 }
366
adc_digi_intr_disable(adc_unit_t adc_unit,adc_digi_intr_t intr_mask)367 esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
368 {
369 ADC_ENTER_CRITICAL();
370 if (adc_unit & ADC_UNIT_1) {
371 adc_hal_digi_intr_disable(ADC_NUM_1, intr_mask);
372 }
373 if (adc_unit & ADC_UNIT_2) {
374 adc_hal_digi_intr_disable(ADC_NUM_2, intr_mask);
375 }
376 ADC_EXIT_CRITICAL();
377 return ESP_OK;
378 }
379
adc_digi_intr_clear(adc_unit_t adc_unit,adc_digi_intr_t intr_mask)380 esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
381 {
382 ADC_ENTER_CRITICAL();
383 if (adc_unit & ADC_UNIT_1) {
384 adc_hal_digi_intr_clear(ADC_NUM_1, intr_mask);
385 }
386 if (adc_unit & ADC_UNIT_2) {
387 adc_hal_digi_intr_clear(ADC_NUM_2, intr_mask);
388 }
389 ADC_EXIT_CRITICAL();
390 return ESP_OK;
391 }
392
adc_digi_intr_get_status(adc_unit_t adc_unit)393 uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit)
394 {
395 uint32_t ret = 0;
396 ADC_ENTER_CRITICAL();
397 if (adc_unit & ADC_UNIT_1) {
398 ret = adc_hal_digi_get_intr_status(ADC_NUM_1);
399 }
400 if (adc_unit & ADC_UNIT_2) {
401 ret = adc_hal_digi_get_intr_status(ADC_NUM_2);
402 }
403 ADC_EXIT_CRITICAL();
404 return ret;
405 }
406
407 static uint8_t s_isr_registered = 0;
408 static intr_handle_t s_adc_isr_handle = NULL;
409
adc_digi_isr_register(void (* fn)(void *),void * arg,int intr_alloc_flags)410 esp_err_t adc_digi_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags)
411 {
412 ADC_CHECK((fn != NULL), "Parameter error", ESP_ERR_INVALID_ARG);
413 ADC_CHECK(s_isr_registered == 0, "ADC ISR have installed, can not install again", ESP_FAIL);
414
415 esp_err_t ret = esp_intr_alloc(ETS_APB_ADC_INTR_SOURCE, intr_alloc_flags, fn, arg, &s_adc_isr_handle);
416 if (ret == ESP_OK) {
417 s_isr_registered = 1;
418 }
419 return ret;
420 }
421
adc_digi_isr_deregister(void)422 esp_err_t adc_digi_isr_deregister(void)
423 {
424 esp_err_t ret = ESP_FAIL;
425 if (s_isr_registered) {
426 ret = esp_intr_free(s_adc_isr_handle);
427 if (ret == ESP_OK) {
428 s_isr_registered = 0;
429 }
430 }
431 return ret;
432 }
433
434 /*---------------------------------------------------------------
435 RTC controller setting
436 ---------------------------------------------------------------*/
437
438 /*---------------------------------------------------------------
439 Calibration
440 ---------------------------------------------------------------*/
441
442 static uint16_t s_adc_cali_param[ADC_NUM_MAX][ADC_ATTEN_MAX] = { {0}, {0} };
443
444 //NOTE: according to calibration version, different types of lock may be taken during the process:
445 // 1. Semaphore when reading efuse
446 // 2. Spinlock when actually doing ADC calibration
447 //This function shoudn't be called inside critical section or ISR
adc_get_calibration_offset(adc_ll_num_t adc_n,adc_channel_t channel,adc_atten_t atten,bool no_cal)448 uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool no_cal)
449 {
450 #ifdef CONFIG_IDF_ENV_FPGA
451 return 0;
452 #endif
453
454 if (s_adc_cali_param[adc_n][atten]) {
455 ESP_LOGV(ADC_TAG, "Use calibrated val ADC%d atten=%d: %04X", adc_n, atten, s_adc_cali_param[adc_n][atten]);
456 return (uint32_t)s_adc_cali_param[adc_n][atten];
457 }
458
459 if (no_cal) {
460 return 0; //indicating failure
461 }
462
463 uint32_t dout = 0;
464 // check if we can fetch the values from eFuse.
465 int version = esp_efuse_rtc_table_read_calib_version();
466 if (version == 2) {
467 int tag = esp_efuse_rtc_table_get_tag(version, adc_n + 1, atten, RTCCALIB_V2_PARAM_VINIT);
468 dout = esp_efuse_rtc_table_get_parsed_efuse_value(tag, false);
469 } else {
470 adc_power_acquire();
471 ADC_ENTER_CRITICAL();
472 const bool internal_gnd = true;
473 dout = adc_hal_self_calibration(adc_n, channel, atten, internal_gnd);
474 ADC_EXIT_CRITICAL();
475 adc_power_release();
476 }
477 ESP_LOGD(ADC_TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n, atten, dout);
478 s_adc_cali_param[adc_n][atten] = (uint16_t)dout;
479 return dout;
480 }
481
adc_cal_offset(adc_ll_num_t adc_n,adc_channel_t channel,adc_atten_t atten)482 esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
483 {
484 adc_hal_calibration_init(adc_n);
485 uint32_t cal_val = adc_get_calibration_offset(adc_n, channel, atten, false);
486 ADC_ENTER_CRITICAL();
487 adc_hal_set_calibration_param(adc_n, cal_val);
488 ADC_EXIT_CRITICAL();
489 return ESP_OK;
490 }
491
