1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #include <stdbool.h> 17 #include <stdint.h> 18 #include "sdkconfig.h" 19 #include "soc/soc_caps.h" 20 #include "esp_attr.h" 21 22 /** 23 * @brief ADC unit enumeration. 24 * 25 * @note For ADC digital controller (DMA mode), ESP32 doesn't support `ADC_UNIT_2`, `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER`. 26 */ 27 typedef enum { 28 ADC_UNIT_1 = 1, /*!< SAR ADC 1. */ 29 ADC_UNIT_2 = 2, /*!< SAR ADC 2. */ 30 ADC_UNIT_BOTH = 3, /*!< SAR ADC 1 and 2. */ 31 ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode. */ 32 ADC_UNIT_MAX, 33 } adc_unit_t; 34 35 /** 36 * @brief ADC channels handle. See ``adc1_channel_t``, ``adc2_channel_t``. 37 * 38 * @note For ESP32 ADC1, don't use `ADC_CHANNEL_8`, `ADC_CHANNEL_9`. See ``adc1_channel_t``. 39 */ 40 typedef enum { 41 ADC_CHANNEL_0 = 0, /*!< ADC channel */ 42 ADC_CHANNEL_1, /*!< ADC channel */ 43 ADC_CHANNEL_2, /*!< ADC channel */ 44 ADC_CHANNEL_3, /*!< ADC channel */ 45 ADC_CHANNEL_4, /*!< ADC channel */ 46 ADC_CHANNEL_5, /*!< ADC channel */ 47 ADC_CHANNEL_6, /*!< ADC channel */ 48 ADC_CHANNEL_7, /*!< ADC channel */ 49 ADC_CHANNEL_8, /*!< ADC channel */ 50 ADC_CHANNEL_9, /*!< ADC channel */ 51 ADC_CHANNEL_MAX, 52 } adc_channel_t; 53 54 /** 55 * @brief ADC attenuation parameter. Different parameters determine the range of the ADC. See ``adc1_config_channel_atten``. 56 */ 57 typedef enum { 58 ADC_ATTEN_DB_0 = 0, /*!<No input attenumation, ADC can measure up to approx. 800 mV. */ 59 ADC_ATTEN_DB_2_5 = 1, /*!<The input voltage of ADC will be attenuated, extending the range of measurement to up to approx. 1100 mV. */ 60 ADC_ATTEN_DB_6 = 2, /*!<The input voltage of ADC will be attenuated, extending the range of measurement to up to approx. 1350 mV. */ 61 ADC_ATTEN_DB_11 = 3, /*!<The input voltage of ADC will be attenuated, extending the range of measurement to up to approx. 2600 mV. */ 62 ADC_ATTEN_MAX, 63 } adc_atten_t; 64 65 #ifdef CONFIG_IDF_TARGET_ESP32 66 /** 67 * @brief ESP32 ADC DMA source selection. 68 */ 69 #else 70 /** 71 * @brief ESP32 ADC DMA source selection. 72 * 73 * @deprecated Not applicable on ESP32-S2 because ESP32-S2 doesn't use I2S DMA. 74 */ 75 #endif 76 typedef enum { 77 ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */ 78 ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */ 79 ADC_I2S_DATA_SRC_MAX, 80 } adc_i2s_source_t; 81 82 /** 83 * @brief ADC resolution setting option. 84 * 85 */ 86 typedef enum { 87 #if CONFIG_IDF_TARGET_ESP32 88 ADC_WIDTH_BIT_9 = 0, /*!< ADC capture width is 9Bit. */ 89 ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. */ 90 ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. */ 91 ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. */ 92 #elif SOC_ADC_MAX_BITWIDTH == 12 93 ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. */ 94 #elif SOC_ADC_MAX_BITWIDTH == 13 95 ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. */ 96 #endif 97 ADC_WIDTH_MAX, 98 } adc_bits_width_t; 99 100 101 /** 102 * @brief ADC digital controller (DMA mode) work mode. 103 * 104 * @note The conversion mode affects the sampling frequency: 105 * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. 106 * SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once. 107 * BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time. 108 * ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately. 109 */ 110 typedef enum { 111 ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1. */ 112 ADC_CONV_SINGLE_UNIT_2 = 2, /*!< SAR ADC 2. */ 113 ADC_CONV_BOTH_UNIT = 3, /*!< SAR ADC 1 and 2. */ 114 ADC_CONV_ALTER_UNIT = 7, /*!< SAR ADC 1 and 2 alternative mode. */ 115 ADC_CONV_UNIT_MAX, 116 } adc_digi_convert_mode_t; 117 118 /** 119 * @brief ADC digital controller (DMA mode) conversion rules setting. 120 */ 121 typedef struct { 122 union { 123 struct { 124 uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration. Modification of attenuation affects the range of measurements. 125 0: measurement range 0 - 800mV, 126 1: measurement range 0 - 1100mV, 127 2: measurement range 0 - 1350mV, 128 3: measurement range 0 - 2600mV. */ 129 #if CONFIG_IDF_TARGET_ESP32 130 uint8_t bit_width: 2; /*!< ADC resolution. 131 - 0: 9 bit; 132 - 1: 10 bit; 133 - 2: 11 bit; 134 - 3: 12 bit. */ 135 int8_t channel: 4; /*!< ADC channel index. */ 136 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 137 uint8_t reserved: 2; /*!< reserved0 */ 138 uint8_t channel: 4; /*!< ADC channel index. */ 139 #elif CONFIG_IDF_TARGET_ESP32C3 140 uint8_t channel: 3; /*!< ADC channel index. */ 141 uint8_t unit: 1; /*!< ADC unit index. */ 142 uint8_t reserved: 2; /*!< reserved0 */ 143 #endif 144 }; 145 uint8_t val; /*!<Raw data value */ 146 }; 147 } adc_digi_pattern_table_t; 148 149 /** 150 * @brief ADC digital controller (DMA mode) output data format option. 151 */ 152 typedef enum { 153 ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`). 154 Note: For single convert mode. */ 155 ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`). 156 Note: For multi or alter convert mode. */ 157 ADC_DIGI_FORMAT_MAX, 158 } adc_digi_output_format_t; 159 160 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 161 /** 162 * @brief ADC digital controller (DMA mode) output data format. 163 * Used to analyze the acquired ADC (DMA) data. 164 * 165 * @note ESP32-S2: 166 * Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data. 167 */ 168 typedef struct { 169 union { 170 struct { 171 uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */ 172 uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2: 173 If (channel < ADC_CHANNEL_MAX), The data is valid. 174 If (channel > ADC_CHANNEL_MAX), The data is invalid. */ 175 } type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */ 176 struct { 177 uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */ 178 uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2: 179 If (channel < ADC_CHANNEL_MAX), The data is valid. 180 If (channel > ADC_CHANNEL_MAX), The data is invalid. */ 181 uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */ 182 } type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */ 183 uint16_t val; /*!<Raw data value */ 184 }; 185 } adc_digi_output_data_t; 186 #endif 187 #if CONFIG_IDF_TARGET_ESP32C3 188 /** 189 * @brief ADC digital controller (DMA mode) output data format. 190 * Used to analyze the acquired ADC (DMA) data. 191 */ 192 typedef struct { 193 union { 194 struct { 195 uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */ 196 uint32_t reserved12: 1; /*!<Reserved12. */ 197 uint32_t channel: 3; /*!<ADC channel index info. 198 If (channel < ADC_CHANNEL_MAX), The data is valid. 199 If (channel > ADC_CHANNEL_MAX), The data is invalid. */ 200 uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */ 201 uint32_t reserved17_31: 15; /*!<Reserved17. */ 202 } type2; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_11BIT` */ 203 uint32_t val; /*!<Raw data value */ 204 }; 205 } adc_digi_output_data_t; 206 #endif 207 208 #if !CONFIG_IDF_TARGET_ESP32 209 210 /** 211 * @brief ADC digital controller (DMA mode) clock system setting. 212 * Calculation formula: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1). 213 * 214 * @note: The clocks of the DAC digital controller use the ADC digital controller clock divider. 215 */ 216 typedef struct { 217 bool use_apll; /*!<true: use APLL clock; false: use APB clock. */ 218 uint32_t div_num; /*!<Division factor. Range: 0 ~ 255. 219 Note: When a higher frequency clock is used (the division factor is less than 9), 220 the ADC reading value will be slightly offset. */ 221 uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */ 222 uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */ 223 } adc_digi_clk_t; 224 225 #endif //!CONFIG_IDF_TARGET_ESP32 226 227 /** 228 * @brief ADC digital controller (DMA mode) configuration parameters. 229 * 230 * Example setting: When using ADC1 channel0 to measure voltage, the sampling rate is required to be 1 kHz: 231 * 232 * +---------------------+--------+--------+--------+ 233 * | sample rate | 1 kHz | 1 kHz | 1 kHz | 234 * +---------------------+--------+--------+--------+ 235 * | conv_mode | single | both | alter | 236 * | adc1_pattern_len | 1 | 1 | 1 | 237 * | dig_clk.use_apll | 0 | 0 | 0 | 238 * | dig_clk.div_num | 99 | 99 | 99 | 239 * | dig_clk.div_b | 0 | 0 | 0 | 240 * | dig_clk.div_a | 0 | 0 | 0 | 241 * | interval | 400 | 400 | 200 | 242 * +---------------------+--------+--------+--------+ 243 * | `trigger_meas_freq` | 1 kHz | 1 kHz | 2 kHz | 244 * +---------------------+--------+--------+--------+ 245 * 246 * Explanation of the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA outputs: 247 * 248 * +---------------------+--------+--------+--------+ 249 * | conv_mode | single | both | alter | 250 * +---------------------+--------+--------+--------+ 251 * | trigger meas times | 1 | 1 | 1 | 252 * +---------------------+--------+--------+--------+ 253 * | conv_limit_num | +1 | +1 | +1 | 254 * | dma_eof_num | +1 | +2 | +1 | 255 * | dma output (byte) | +2 | +4 | +2 | 256 * +---------------------+--------+--------+--------+ 257 */ 258 typedef struct { 259 bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times. 260 If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */ 261 uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */ 262 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 263 uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting). 264 The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection, 265 resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the 266 pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */ 267 uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */ 268 adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */ 269 adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */ 270 adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */ 271 adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */ 272 #elif CONFIG_IDF_TARGET_ESP32C3 273 uint32_t adc_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 7 (0: Don't change the pattern table setting). 274 The pattern table that defines the conversion rules for each SAR ADC. Each table has 7 items, in which channel selection, 275 resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the 276 pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */ 277 adc_digi_pattern_table_t *adc_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc_pattern_len`. */ 278 #endif 279 #if CONFIG_IDF_TARGET_ESP32S2 280 uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement. 281 The unit is the divided clock. Range: 40 ~ 4095. 282 Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``. 283 Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */ 284 adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t``. 285 Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */ 286 uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller. 287 If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA. 288 Note: The converted data in the DMA in link buffer will be multiple of two bytes. */ 289 #elif CONFIG_IDF_TARGET_ESP32C3 290 uint32_t sample_freq_hz; /*!< The expected ADC sampling frequency in Hz. Range: 611Hz ~ 83333Hz 291 Fs = Fd / interval / 2 292 Fs: sampling frequency; 293 Fd: digital controller frequency, no larger than 5M for better performance 294 interval: interval between 2 measurement trigger signal, the smallest interval should not be smaller than the ADC measurement period, the largest interval should not be larger than 4095 */ 295 #endif 296 } adc_digi_config_t; 297 298 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 299 /** 300 * @brief ADC digital controller (DMA mode) interrupt type options. 301 */ 302 typedef enum { 303 ADC_DIGI_INTR_MASK_MONITOR = 0x1, 304 ADC_DIGI_INTR_MASK_MEAS_DONE = 0x2, 305 ADC_DIGI_INTR_MASK_ALL = 0x3, 306 } adc_digi_intr_t; 307 FLAG_ATTR(adc_digi_intr_t) 308 #endif 309 310 #if !CONFIG_IDF_TARGET_ESP32 311 312 /** 313 * @brief ADC arbiter work mode option. 314 * 315 * @note ESP32-S2: Only ADC2 support arbiter. 316 */ 317 typedef enum { 318 ADC_ARB_MODE_SHIELD,/*!<Force shield arbiter, Select the highest priority controller to work. */ 319 ADC_ARB_MODE_FIX, /*!<Fixed priority switch controller mode. */ 320 ADC_ARB_MODE_LOOP, /*!<Loop priority switch controller mode. Each controller has the same priority, 321 and the arbiter will switch to the next controller after the measurement is completed. */ 322 } adc_arbiter_mode_t; 323 324 /** 325 * @brief ADC arbiter work mode and priority setting. 326 * 327 * @note ESP32-S2: Only ADC2 support arbiter. 328 */ 329 typedef struct { 330 adc_arbiter_mode_t mode; /*!<Refer to ``adc_arbiter_mode_t``. Note: only support ADC2. */ 331 uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */ 332 uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */ 333 uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */ 334 } adc_arbiter_t; 335 336 /** 337 * @brief ADC arbiter default configuration. 338 * 339 * @note ESP32S2: Only ADC2 supports (needs) an arbiter. 340 */ 341 #define ADC_ARBITER_CONFIG_DEFAULT() { \ 342 .mode = ADC_ARB_MODE_FIX, \ 343 .rtc_pri = 1, \ 344 .dig_pri = 0, \ 345 .pwdet_pri = 2, \ 346 } 347 348 /** 349 * @brief ADC digital controller (DMA mode) filter index options. 350 * 351 * @note For ESP32-S2, The filter object of the ADC is fixed. 352 */ 353 typedef enum { 354 ADC_DIGI_FILTER_IDX0 = 0, /*!<The filter index 0. 355 For ESP32-S2, It can only be used to filter all enabled channels of ADC1 unit at the same time. */ 356 ADC_DIGI_FILTER_IDX1, /*!<The filter index 1. 357 For ESP32-S2, It can only be used to filter all enabled channels of ADC2 unit at the same time. */ 358 ADC_DIGI_FILTER_IDX_MAX 359 } adc_digi_filter_idx_t; 360 361 /** 362 * @brief ADC digital controller (DMA mode) filter type options. 363 * Expression: filter_data = (k-1)/k * last_data + new_data / k. 364 */ 365 typedef enum { 366 #if CONFIG_IDF_TARGET_ESP32C3 367 ADC_DIGI_FILTER_DIS = -1, /*!< Disable filter */ 368 #endif 369 ADC_DIGI_FILTER_IIR_2 = 0, /*!<The filter mode is first-order IIR filter. The coefficient is 2. */ 370 ADC_DIGI_FILTER_IIR_4, /*!<The filter mode is first-order IIR filter. The coefficient is 4. */ 371 ADC_DIGI_FILTER_IIR_8, /*!<The filter mode is first-order IIR filter. The coefficient is 8. */ 372 ADC_DIGI_FILTER_IIR_16, /*!<The filter mode is first-order IIR filter. The coefficient is 16. */ 373 ADC_DIGI_FILTER_IIR_64, /*!<The filter mode is first-order IIR filter. The coefficient is 64. */ 374 ADC_DIGI_FILTER_IIR_MAX 375 } adc_digi_filter_mode_t; 376 377 /** 378 * @brief ADC digital controller (DMA mode) filter configuration. 379 * 380 * @note For ESP32-S2, The filter object of the ADC is fixed. 381 * @note For ESP32-S2, The filter object is always all enabled channels. 382 */ 383 typedef struct { 384 adc_unit_t adc_unit; /*!<Set adc unit number for filter. 385 For ESP32-S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. */ 386 adc_channel_t channel; /*!<Set adc channel number for filter. 387 For ESP32-S2, it's always `ADC_CHANNEL_MAX` */ 388 adc_digi_filter_mode_t mode;/*!<Set adc filter mode for filter. See ``adc_digi_filter_mode_t``. */ 389 } adc_digi_filter_t; 390 391 /** 392 * @brief ADC digital controller (DMA mode) monitor index options. 393 * 394 * @note For ESP32-S2, The monitor object of the ADC is fixed. 395 */ 396 typedef enum { 397 ADC_DIGI_MONITOR_IDX0 = 0, /*!<The monitor index 0. 398 For ESP32-S2, It can only be used to monitor all enabled channels of ADC1 unit at the same time. */ 399 ADC_DIGI_MONITOR_IDX1, /*!<The monitor index 1. 400 For ESP32-S2, It can only be used to monitor all enabled channels of ADC2 unit at the same time. */ 401 ADC_DIGI_MONITOR_IDX_MAX 402 } adc_digi_monitor_idx_t; 403 404 /** 405 * @brief Set monitor mode of adc digital controller. 406 * MONITOR_HIGH:If ADC_OUT > threshold, Generates monitor interrupt. 407 * MONITOR_LOW: If ADC_OUT < threshold, Generates monitor interrupt. 408 */ 409 typedef enum { 410 #if CONFIG_IDF_TARGET_ESP32C3 411 ADC_DIGI_MONITOR_DIS = 0, /*!<Disable monitor. */ 412 ADC_DIGI_MONITOR_EN, /*!<If ADC_OUT < threshold, Generates monitor interrupt. */ 413 /*!<If ADC_OUT > threshold, Generates monitor interrupt. */ 414 #else 415 ADC_DIGI_MONITOR_HIGH = 0, /*!<If ADC_OUT > threshold, Generates monitor interrupt. */ 416 ADC_DIGI_MONITOR_LOW, /*!<If ADC_OUT < threshold, Generates monitor interrupt. */ 417 #endif 418 ADC_DIGI_MONITOR_MAX 419 } adc_digi_monitor_mode_t; 420 421 /** 422 * @brief ADC digital controller (DMA mode) monitor configuration. 423 * 424 * @note For ESP32-S2, The monitor object of the ADC is fixed. 425 * @note For ESP32-S2, The monitor object is always all enabled channels. 426 */ 427 typedef struct { 428 adc_unit_t adc_unit; /*!<Set adc unit number for monitor. 429 For ESP32-S2, monitor IDX0/IDX1 can only be used to monitor all enabled channels of ADC1/ADC2 unit at the same time. */ 430 adc_channel_t channel; /*!<Set adc channel number for monitor. 431 For ESP32-S2, it's always `ADC_CHANNEL_MAX` */ 432 adc_digi_monitor_mode_t mode; /*!<Set adc monitor mode. See ``adc_digi_monitor_mode_t``. */ 433 #if CONFIG_IDF_TARGET_ESP32C3 434 uint32_t h_threshold; /*!<Set monitor threshold of adc digital controller. */ 435 uint32_t l_threshold; /*!<Set monitor threshold of adc digital controller. */ 436 #else 437 uint32_t threshold; /*!<Set monitor threshold of adc digital controller. */ 438 #endif 439 } adc_digi_monitor_t; 440 441 #endif // CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 442
