1 /*!
2 \file gd32l23x_adc.c
3 \brief ADC driver
4
5 \version 2021-08-04, V1.0.0, firmware for GD32L23x
6 */
7
8 /*
9 Copyright (c) 2021, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32l23x_adc.h"
36
37 /* discontinuous mode macro*/
38 #define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)0x01U)
39
40 /* ADC regular channel macro */
41 #define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)0x06U)
42 #define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)0x0CU)
43 #define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)0x05U)
44
45 /* ADC sampling time macro */
46 #define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)0x0AU)
47 #define ADC_CHANNEL_SAMPLE_NINETEEN ((uint8_t)0x13U)
48 #define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)0x03U)
49
50 /* ADC inserted channel macro */
51 #define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)0x05U)
52 #define ADC_INSERTED_CHANNEL_SHIFT_OFFSET ((uint8_t)0x0FU)
53
54 /* ADC inserted channel offset macro */
55 #define ADC_OFFSET_LENGTH ((uint8_t)0x03U)
56 #define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)0x04U)
57
58 /*!
59 \brief reset ADC
60 \param[in] none
61 \param[out] none
62 \retval none
63 */
adc_deinit(void)64 void adc_deinit(void)
65 {
66 rcu_periph_reset_enable(RCU_ADCRST);
67 rcu_periph_reset_disable(RCU_ADCRST);
68 }
69
70 /*!
71 \brief enable ADC interface
72 \param[in] none
73 \param[out] none
74 \retval none
75 */
adc_enable(void)76 void adc_enable(void)
77 {
78 /* configure ADC charge pulse width counter */
79 adc_charge_pulse_width_counter(320);
80
81 if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)) {
82 /* enable ADC */
83 ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON;
84 }
85 }
86
87 /*!
88 \brief disable ADC interface
89 \param[in] none
90 \param[out] none
91 \retval none
92 */
adc_disable(void)93 void adc_disable(void)
94 {
95 /* disable ADC */
96 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON);
97 }
98
99 /*!
100 \brief ADC calibration and reset calibration
101 \param[in] none
102 \param[out] none
103 \retval none
104 */
adc_calibration_enable(void)105 void adc_calibration_enable(void)
106 {
107 /* reset the selected ADC calibration registers */
108 ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB;
109 /* check the RSTCLB bit state */
110 while((ADC_CTL1 & ADC_CTL1_RSTCLB)) {
111 }
112 /* enable ADC calibration process */
113 ADC_CTL1 |= ADC_CTL1_CLB;
114 /* check the CLB bit state */
115 while((ADC_CTL1 & ADC_CTL1_CLB)) {
116 }
117 }
118
119 /*!
120 \brief enable DMA request
121 \param[in] none
122 \param[out] none
123 \retval none
124 */
adc_dma_mode_enable(void)125 void adc_dma_mode_enable(void)
126 {
127 /* enable DMA request */
128 ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA);
129 }
130
131 /*!
132 \brief disable DMA request
133 \param[in] none
134 \param[out] none
135 \retval none
136 */
adc_dma_mode_disable(void)137 void adc_dma_mode_disable(void)
138 {
139 /* disable DMA request */
140 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA);
141 }
142
143 /*!
144 \brief configure ADC discontinuous mode
145 \param[in] adc_channel_group: select the channel group
146 only one parameter can be selected which is shown as below:
147 \arg ADC_REGULAR_CHANNEL: regular channel group
148 \arg ADC_INSERTED_CHANNEL: inserted channel group
149 \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel
150 \param[in] length: number of conversions in discontinuous mode,the number can be 1..16
151 for regular channel, the number has no effect for inserted channel
152 \param[out] none
153 \retval none
154 */
adc_discontinuous_mode_config(uint8_t adc_channel_group,uint8_t length)155 void adc_discontinuous_mode_config(uint8_t adc_channel_group, uint8_t length)
156 {
157 /* disable discontinuous mode of regular & inserted channel */
158 ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
159 switch(adc_channel_group) {
160 case ADC_REGULAR_CHANNEL:
161 /* configure the number of conversions in discontinuous mode */
162 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM);
163 if((length <= 16U) && (length >= 1U)) {
164 ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
165 }
166 /* enable regular channel group discontinuous mode */
167 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC;
168 break;
169 case ADC_INSERTED_CHANNEL:
170 /* enable inserted channel group discontinuous mode */
171 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC;
172 break;
173 case ADC_CHANNEL_DISCON_DISABLE:
174 /* disable discontinuous mode of regular & inserted channel */
175 default:
176 break;
177 }
178 }
179
180 /*!
181 \brief configure ADC special function
182 \param[in] function: the function to configure
183 one or more parameters can be selected which is shown as below:
184 \arg ADC_SCAN_MODE: scan mode select
185 \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
186 \arg ADC_CONTINUOUS_MODE: continuous mode select
187 \param[in] newvalue: ENABLE or DISABLE
188 \param[out] none
189 \retval none
190 */
adc_special_function_config(uint32_t function,ControlStatus newvalue)191 void adc_special_function_config(uint32_t function, ControlStatus newvalue)
192 {
193 if(newvalue) {
194 /* enable ADC scan mode */
195 if(RESET != (function & ADC_SCAN_MODE)) {
196 ADC_CTL0 |= (uint32_t)ADC_SCAN_MODE;
197 }
198 /* enable ADC inserted channel group convert automatically */
199 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) {
200 ADC_CTL0 |= (uint32_t)ADC_INSERTED_CHANNEL_AUTO;
201 }
202 /* enable ADC continuous mode */
203 if(RESET != (function & ADC_CONTINUOUS_MODE)) {
204 ADC_CTL1 |= (uint32_t)ADC_CONTINUOUS_MODE;
205 }
206 } else {
207 /* disable ADC scan mode */
208 if(RESET != (function & ADC_SCAN_MODE)) {
209 ADC_CTL0 &= ~((uint32_t)ADC_SCAN_MODE);
210 }
211 /* disable ADC inserted channel group convert automatically */
212 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) {
213 ADC_CTL0 &= ~((uint32_t)ADC_INSERTED_CHANNEL_AUTO);
214 }
215 /* disable ADC continuous mode */
216 if(RESET != (function & ADC_CONTINUOUS_MODE)) {
217 ADC_CTL1 &= ~((uint32_t)ADC_CONTINUOUS_MODE);
218 }
219 }
220 }
221
222 /*!
223 \brief configure temperature sensor, internal reference voltage channel, VBAT channel or VSLCD channel function
224 \param[in] function: temperature sensor or internal reference voltage channel or VBAT channel or VSLCD channel function
225 only one parameter can be selected which is shown as below:
226 \arg ADC_TEMP_CHANNEL_SWITCH: channel 16 (temperature sensor) switch of ADC
227 \arg ADC_INTERNAL_CHANNEL_SWITCH: channel 17 (internal reference voltage) switch of ADC
228 \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/3 voltage of external battery) switch of ADC
229 \arg ADC_VSLCD_CHANNEL_SWITCH: channel 19 (1/3 voltage of VSLCD) switch of ADC
230 \param[in] newvalue: ENABLE or DISABLE
231 \param[out] none
232 \retval none
233 */
adc_channel_16_to_19(uint32_t function,ControlStatus newvalue)234 void adc_channel_16_to_19(uint32_t function, ControlStatus newvalue)
235 {
236 if(newvalue) {
237 if(RESET != (function & ADC_TEMP_CHANNEL_SWITCH)) {
238 /* enable ADC VBAT channel */
239 ADC_CTL1 |= ADC_TEMP_CHANNEL_SWITCH;
240 }
241 if(RESET != (function & ADC_INTERNAL_CHANNEL_SWITCH)) {
242 /* enable ADC VREF and Temperature channel */
243 ADC_CTL1 |= ADC_INTERNAL_CHANNEL_SWITCH;
244 }
245 if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) {
246 /* enable ADC VREF and Temperature channel */
247 ADC_CTL1 |= ADC_VBAT_CHANNEL_SWITCH;
248 }
249 if(RESET != (function & ADC_VSLCD_CHANNEL_SWITCH)) {
250 /* enable ADC VREF and Temperature channel */
251 ADC_CTL1 |= ADC_VSLCD_CHANNEL_SWITCH;
252 }
253 } else {
254 if(RESET != (function & ADC_TEMP_CHANNEL_SWITCH)) {
255 /* disable ADC VBAT channel */
256 ADC_CTL1 &= ~ADC_TEMP_CHANNEL_SWITCH;
257 }
258 if(RESET != (function & ADC_INTERNAL_CHANNEL_SWITCH)) {
259 /* disable ADC VREF and temperature channel */
260 ADC_CTL1 &= ~ADC_INTERNAL_CHANNEL_SWITCH;
261 }
262 if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)) {
263 /* disable ADC VREF and temperature channel */
264 ADC_CTL1 &= ~ADC_VBAT_CHANNEL_SWITCH;
265 }
266 if(RESET != (function & ADC_VSLCD_CHANNEL_SWITCH)) {
267 /* disable ADC VREF and temperature channel */
268 ADC_CTL1 &= ~ADC_VSLCD_CHANNEL_SWITCH;
269 }
270 }
271 }
272
273 /*!
274 \brief configure ADC data alignment
275 \param[in] data_alignment: data alignment select
276 only one parameter can be selected which is shown as below:
277 \arg ADC_DATAALIGN_RIGHT: right alignment
278 \arg ADC_DATAALIGN_LEFT: left alignment
279 \param[out] none
280 \retval none
281 */
adc_data_alignment_config(uint32_t data_alignment)282 void adc_data_alignment_config(uint32_t data_alignment)
283 {
284 if(ADC_DATAALIGN_RIGHT != data_alignment) {
285 /* left alignment */
286 ADC_CTL1 |= ADC_CTL1_DAL;
287 } else {
288 /* right alignment */
289 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL);
290 }
291 }
292
293 /*!
294 \brief configure the length of regular channel group or inserted channel group
295 \param[in] adc_channel_group: select the channel group
296 only one parameter can be selected which is shown as below:
297 \arg ADC_REGULAR_CHANNEL: regular channel group
298 \arg ADC_INSERTED_CHANNEL: inserted channel group
299 \param[in] length: the length of the channel
300 regular channel 1-16
301 inserted channel 1-4
302 \param[out] none
303 \retval none
304 */
adc_channel_length_config(uint8_t adc_channel_group,uint32_t length)305 void adc_channel_length_config(uint8_t adc_channel_group, uint32_t length)
306 {
307 switch(adc_channel_group) {
308 case ADC_REGULAR_CHANNEL:
309 /* configure the length of regular channel group */
310 if((length >= 1U) && (length <= 16U)) {
311 ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL);
312 ADC_RSQ0 |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
313 }
314 break;
315 case ADC_INSERTED_CHANNEL:
316 /* configure the length of inserted channel group */
317 if((length >= 1U) && (length <= 4U)) {
318 ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL);
319 ADC_ISQ |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
320 }
321 break;
322 default:
323 break;
324 }
325 }
326
327 /*!
328 \brief configure ADC regular channel
329 \param[in] rank: the regular group sequence rank, this parameter must be between 0 to 15
330 \param[in] adc_channel: the selected ADC channel
331 only one parameter can be selected which is shown as below:
332 \arg ADC_CHANNEL_x(x=0..19): ADC Channelx
333 \param[in] sample_time: the sample time value
334 only one parameter can be selected which is shown as below:
335 \arg ADC_SAMPLETIME_2POINT5: 2.5 cycles
336 \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
337 \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
338 \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
339 \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
340 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
341 \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
342 \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
343 \param[out] none
344 \retval none
345 */
adc_regular_channel_config(uint8_t rank,uint8_t adc_channel,uint32_t sample_time)346 void adc_regular_channel_config(uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
347 {
348 uint32_t rsq, sampt;
349
350 /* configure ADC regular sequence */
351 if(rank < ADC_REGULAR_CHANNEL_RANK_SIX) {
352 /* the regular group sequence rank is smaller than six */
353 rsq = ADC_RSQ2;
354 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank)));
355 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
356 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank));
357 ADC_RSQ2 = rsq;
358 } else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE) {
359 /* the regular group sequence rank is smaller than twelve */
360 rsq = ADC_RSQ1;
361 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX))));
362 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
363 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX)));
364 ADC_RSQ1 = rsq;
365 } else {
366 /* the regular group sequence rank is larger than twelve */
367 rsq = ADC_RSQ0;
368 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE))));
369 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
370 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE)));
371 ADC_RSQ0 = rsq;
372 }
373
374 /* configure ADC sampling time */
375 if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
376 /* the regular group sequence rank is smaller than ten */
377 sampt = ADC_SAMPT1;
378 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
379 /* channel sample time set*/
380 sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel));
381 ADC_SAMPT1 = sampt;
382 } else if(adc_channel <= ADC_CHANNEL_SAMPLE_NINETEEN) {
383 /* the regular group sequence rank is smaller than eleven */
384 sampt = ADC_SAMPT0;
385 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
386 /* channel sample time set*/
387 sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)));
388 ADC_SAMPT0 = sampt;
389 } else {
390 /* illegal parameters */
391 }
392 }
393
394 /*!
395 \brief configure ADC inserted channel
396 \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
397 \param[in] adc_channel: the selected ADC channel
398 only one parameter can be selected which is shown as below:
399 \arg ADC_CHANNEL_x(x=0..19): ADC Channelx
400 \param[in] sample_time: The sample time value
401 only one parameter can be selected which is shown as below:
402 \arg ADC_SAMPLETIME_2POINT5: 2.5 cycles
403 \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
404 \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
405 \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
406 \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
407 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
408 \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
409 \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
410 \param[out] none
411 \retval none
412 */
adc_inserted_channel_config(uint8_t rank,uint8_t adc_channel,uint32_t sample_time)413 void adc_inserted_channel_config(uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
414 {
415 uint8_t inserted_length;
416 uint32_t isq, sampt;
417
418 /* get inserted channel group length */
419 inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
420 /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
421 if(rank < 4U) {
422 isq = ADC_ISQ;
423 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_OFFSET - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)));
424 isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_OFFSET - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH));
425 ADC_ISQ = isq;
426 }
427
428 /* configure ADC sampling time */
429 if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
430 /* the inserted group sequence rank is smaller than ten */
431 sampt = ADC_SAMPT1;
432 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
433 /* channel sample time set*/
434 sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel);
435 ADC_SAMPT1 = sampt;
436 } else if(adc_channel <= ADC_CHANNEL_SAMPLE_NINETEEN) {
437 /* the inserted group sequence rank is smaller than eighteen */
438 sampt = ADC_SAMPT0;
439 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
440 /* channel sample time set*/
441 sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)));
442 ADC_SAMPT0 = sampt;
443 } else {
444 /* illegal parameters */
445 }
446 }
447
448 /*!
449 \brief configure ADC inserted channel offset
450 \param[in] inserted_channel: inserted channel select
451 only one parameter can be selected which is shown as below:
452 \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
453 \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
454 \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
455 \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
456 \param[in] offset: the offset data
457 \param[out] none
458 \retval none
459 */
adc_inserted_channel_offset_config(uint8_t inserted_channel,uint16_t offset)460 void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset)
461 {
462 uint8_t inserted_length;
463 uint32_t num = 0U;
464
465 inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
466 num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
467
468 if(num <= ADC_OFFSET_LENGTH) {
469 /* calculate the offset of the register */
470 num = num * ADC_OFFSET_SHIFT_LENGTH;
471 /* configure the offset of the selected channels */
472 REG32(ADC + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
473 }
474 }
475
476 /*!
477 \brief configure ADC external trigger
478 \param[in] adc_channel_group: select the channel group
479 only one parameter can be selected which is shown as below:
480 \arg ADC_REGULAR_CHANNEL: regular channel group
481 \arg ADC_INSERTED_CHANNEL: inserted channel group
482 \param[in] newvalue: ENABLE or DISABLE
483 \param[out] none
484 \retval none
485 */
adc_external_trigger_config(uint8_t adc_channel_group,ControlStatus newvalue)486 void adc_external_trigger_config(uint8_t adc_channel_group, ControlStatus newvalue)
487 {
488 if(newvalue) {
489 /* external trigger enable for regular channel */
490 if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
491 ADC_CTL1 |= (uint32_t)ADC_CTL1_ETERC;
492 }
493 /* external trigger enable for inserted channel */
494 if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
495 ADC_CTL1 |= (uint32_t)ADC_CTL1_ETEIC;
496 }
497 } else {
498 /* external trigger disable for regular channel */
499 if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
500 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETERC);
501 }
502 /* external trigger disable for inserted channel */
503 if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
504 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETEIC);
505 }
506 }
507 }
508
509 /*!
510 \brief configure ADC external trigger source
511 \param[in] adc_channel_group: select the channel group
512 only one parameter can be selected which is shown as below:
513 \arg ADC_REGULAR_CHANNEL: regular channel group
514 \arg ADC_INSERTED_CHANNEL: inserted channel group
515 \param[in] external_trigger_source: regular or inserted group trigger source
516 only one parameter can be selected which is shown as below:
517 for regular channel:
518 \arg ADC_EXTTRIG_REGULAR_T8_CH0: external trigger TIMER8 CH0 event select for regular channel
519 \arg ADC_EXTTRIG_REGULAR_T8_CH1: external trigger TIMER8 CH1 event select for regular channel
520 \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger TIMER1 CH1 event select for regular channel
521 \arg ADC_EXTTRIG_REGULAR_T2_TRGO: external trigger TIMER2 TRGO event select for regular channel
522 \arg ADC_EXTTRIG_REGULAR_T11_CH0: external trigger TIMER11 CH0 event select for regular channel
523 \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger interrupt line 11 select for regular channel
524 \arg ADC_EXTTRIG_REGULAR_NONE: external trigger software event select for regular channel
525 for inserted channel:
526 \arg ADC_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select for inserted channel
527 \arg ADC_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select for inserted channel
528 \arg ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select for inserted channel
529 \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 event select for inserted channel
530 \arg ADC_EXTTRIG_INSERTED_NONE: external trigger software event select for inserted channel
531 \param[out] none
532 \retval none
533 */
adc_external_trigger_source_config(uint8_t adc_channel_group,uint32_t external_trigger_source)534 void adc_external_trigger_source_config(uint8_t adc_channel_group, uint32_t external_trigger_source)
535 {
536 switch(adc_channel_group) {
537 case ADC_REGULAR_CHANNEL:
538 /* configure ADC regular group external trigger source */
539 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC);
540 ADC_CTL1 |= (uint32_t)external_trigger_source;
541 break;
542 case ADC_INSERTED_CHANNEL:
543 /* configure ADC inserted group external trigger source */
544 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC);
545 ADC_CTL1 |= (uint32_t)external_trigger_source;
546 break;
547 default:
548 break;
549 }
550 }
551
552 /*!
553 \brief enable ADC software trigger
554 \param[in] adc_channel_group: select the channel group
555 only one parameter can be selected which is shown as below:
556 \arg ADC_REGULAR_CHANNEL: regular channel group
557 \arg ADC_INSERTED_CHANNEL: inserted channel group
558 \param[out] none
559 \retval none
560 */
adc_software_trigger_enable(uint8_t adc_channel_group)561 void adc_software_trigger_enable(uint8_t adc_channel_group)
562 {
563 /* enable regular group channel software trigger */
564 if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
565 ADC_CTL1 |= (uint32_t)ADC_CTL1_SWRCST;
566 }
567 /* enable inserted channel group software trigger */
568 if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
569 ADC_CTL1 |= (uint32_t)ADC_CTL1_SWICST;
570 }
571 }
572
573 /*!
574 \brief read ADC regular group data register
575 \param[in] none
576 \param[out] none
577 \retval the conversion value: 0~0xFFFF
578 */
adc_regular_data_read(void)579 uint16_t adc_regular_data_read(void)
580 {
581 return ((uint16_t)(ADC_RDATA));
582 }
583
584 /*!
585 \brief read ADC inserted group data register
586 \param[in] inserted_channel: inserted channel select
587 only one parameter can be selected which is shown as below:
588 \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
589 \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
590 \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
591 \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
592 \param[out] none
593 \retval the conversion value: 0~0xFFFF
594 */
adc_inserted_data_read(uint8_t inserted_channel)595 uint16_t adc_inserted_data_read(uint8_t inserted_channel)
596 {
597 uint32_t idata;
598 /* read the data of the selected channel */
599 switch(inserted_channel) {
600 case ADC_INSERTED_CHANNEL_0:
601 /* read the data of channel 0 */
602 idata = ADC_IDATA0;
603 break;
604 case ADC_INSERTED_CHANNEL_1:
605 /* read the data of channel 1 */
606 idata = ADC_IDATA1;
607 break;
608 case ADC_INSERTED_CHANNEL_2:
609 /* read the data of channel 2 */
610 idata = ADC_IDATA2;
611 break;
612 case ADC_INSERTED_CHANNEL_3:
613 /* read the data of channel 3 */
614 idata = ADC_IDATA3;
615 break;
616 default:
617 idata = 0U;
618 break;
619 }
620 return ((uint16_t)idata);
621 }
622
623 /*!
624 \brief enable ADC analog watchdog single channel
625 \param[in] adc_channel: the selected ADC channel
626 only one parameter can be selected which is shown as below:
627 \arg ADC_CHANNEL_x: ADC Channelx(x=0..19)
628 \param[out] none
629 \retval none
630 */
adc_watchdog_single_channel_enable(uint8_t adc_channel)631 void adc_watchdog_single_channel_enable(uint8_t adc_channel)
632 {
633 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
634
635 ADC_CTL0 |= (uint32_t)adc_channel;
636 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
637 }
638
639 /*!
640 \brief enable ADC analog watchdog group channel
641 \param[in] adc_channel_group: the channel group use analog watchdog
642 only one parameter can be selected which is shown as below:
643 \arg ADC_REGULAR_CHANNEL: regular channel group
644 \arg ADC_INSERTED_CHANNEL: inserted channel group
645 \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
646 \param[out] none
647 \retval none
648 */
adc_watchdog_group_channel_enable(uint8_t adc_channel_group)649 void adc_watchdog_group_channel_enable(uint8_t adc_channel_group)
650 {
651 ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC));
652 /* select the group */
653 switch(adc_channel_group) {
654 case ADC_REGULAR_CHANNEL:
655 /* regular channel analog watchdog enable */
656 ADC_CTL0 |= (uint32_t) ADC_CTL0_RWDEN;
657 break;
658 case ADC_INSERTED_CHANNEL:
659 /* inserted channel analog watchdog enable */
660 ADC_CTL0 |= (uint32_t) ADC_CTL0_IWDEN;
661 break;
662 case ADC_REGULAR_INSERTED_CHANNEL:
663 /* regular and inserted channel analog watchdog enable */
664 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
665 break;
666 default:
667 break;
668 }
669 }
670
671 /*!
672 \brief disable ADC analog watchdog
673 \param[in] none
674 \param[out] none
675 \retval none
676 */
adc_watchdog_disable(void)677 void adc_watchdog_disable(void)
678 {
679 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
680 }
681
682 /*!
683 \brief configure ADC analog watchdog threshold
684 \param[in] low_threshold: analog watchdog low threshold, 0..4095
685 \param[in] high_threshold: analog watchdog high threshold, 0..4095
686 \param[out] none
687 \retval none
688 */
adc_watchdog_threshold_config(uint16_t low_threshold,uint16_t high_threshold)689 void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold)
690 {
691 /* configure ADC analog watchdog low threshold */
692 ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold);
693 /* configure ADC analog watchdog high threshold */
694 ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold);
695 }
696
697 /*!
698 \brief configure ADC resolution
699 \param[in] resolution: ADC resolution
700 only one parameter can be selected which is shown as below:
701 \arg ADC_RESOLUTION_12B: 12-bit ADC resolution
702 \arg ADC_RESOLUTION_10B: 10-bit ADC resolution
703 \arg ADC_RESOLUTION_8B: 8-bit ADC resolution
704 \arg ADC_RESOLUTION_6B: 6-bit ADC resolution
705 \param[out] none
706 \retval none
707 */
adc_resolution_config(uint32_t resolution)708 void adc_resolution_config(uint32_t resolution)
709 {
710 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES);
711 ADC_CTL0 |= (uint32_t)resolution;
712 }
713
714 /*!
715 \brief configure ADC oversample mode
716 \param[in] mode: ADC oversampling mode
717 only one parameter can be selected which is shown as below:
718 \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger
719 \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger
720 \param[in] shift: ADC oversampling shift
721 only one parameter can be selected which is shown as below:
722 \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
723 \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
724 \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
725 \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
726 \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
727 \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
728 \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
729 \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
730 \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
731 \param[in] ratio: ADC oversampling ratio
732 only one parameter can be selected which is shown as below:
733 \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2
734 \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4
735 \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8
736 \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16
737 \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32
738 \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64
739 \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128
740 \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256
741 \param[out] none
742 \retval none
743 */
adc_oversample_mode_config(uint32_t mode,uint16_t shift,uint8_t ratio)744 void adc_oversample_mode_config(uint32_t mode, uint16_t shift, uint8_t ratio)
745 {
746 /* configure ADC oversampling mode */
747 if(ADC_OVERSAMPLING_ONE_CONVERT == mode) {
748 ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS;
749 } else {
750 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
751 }
752 /* configure the shift and ratio */
753 ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
754 ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio);
755 }
756
757 /*!
758 \brief enable ADC oversample mode
759 \param[in] none
760 \param[out] none
761 \retval none
762 */
adc_oversample_mode_enable(void)763 void adc_oversample_mode_enable(void)
764 {
765 ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN;
766 }
767
768 /*!
769 \brief disable ADC oversample mode
770 \param[in] none
771 \param[out] none
772 \retval none
773 */
adc_oversample_mode_disable(void)774 void adc_oversample_mode_disable(void)
775 {
776 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
777 }
778
779 /*!
780 \brief configure ADC charge pulse width counter
781 \param[in] value: ADC charge pulse width counter value
782 \param[out] none
783 \retval none
784 */
adc_charge_pulse_width_counter(uint32_t value)785 void adc_charge_pulse_width_counter(uint32_t value)
786 {
787 ADC_CCTL = (uint32_t)CCTL_CCNT(value);
788 }
789
790 /*!
791 \brief get the ADC charge flag
792 \param[in] flag: the ADC charge flag
793 \arg ADC_FLAG_CHARGE: ADC charge flag
794 \param[out] none
795 \retval FlagStatus: SET or RESET
796 */
adc_charge_flag_get(uint32_t flag)797 FlagStatus adc_charge_flag_get(uint32_t flag)
798 {
799 FlagStatus reval = RESET;
800 if(ADC_CCTL & flag) {
801 reval = SET;
802 }
803 return reval;
804 }
805
806 /*!
807 \brief get the flag of ADC regular channel software start conversion
808 \param[in] none
809 \param[out] none
810 \retval FlagStatus: SET or RESET
811 */
adc_regular_software_startconv_flag_get(void)812 FlagStatus adc_regular_software_startconv_flag_get(void)
813 {
814 FlagStatus reval = RESET;
815 if((uint32_t)RESET != (ADC_STAT & ADC_STAT_STRC)) {
816 reval = SET;
817 }
818 return reval;
819 }
820
821 /*!
822 \brief get the flag of ADC inserted channel software start conversion
823 \param[in] none
824 \param[out] none
825 \retval FlagStatus: SET or RESET
826 */
adc_inserted_software_startconv_flag_get(void)827 FlagStatus adc_inserted_software_startconv_flag_get(void)
828 {
829 FlagStatus reval = RESET;
830 if((uint32_t)RESET != (ADC_STAT & ADC_STAT_STIC)) {
831 reval = SET;
832 }
833 return reval;
834 }
835
836 /*!
837 \brief get ADC flag
838 \param[in] flag: ADC flag
839 only one parameter can be selected which is shown as below:
840 \arg ADC_FLAG_WDE: analog watchdog event flag
841 \arg ADC_FLAG_EOC: end of group conversion flag
842 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
843 \arg ADC_FLAG_STIC: start flag of inserted channel group
844 \arg ADC_FLAG_STRC: start flag of regular channel group
845 \param[out] none
846 \retval FlagStatus: SET or RESET
847 */
adc_flag_get(uint32_t flag)848 FlagStatus adc_flag_get(uint32_t flag)
849 {
850 FlagStatus reval = RESET;
851 if(ADC_STAT & flag) {
852 reval = SET;
853 }
854 return reval;
855 }
856
857 /*!
858 \brief clear ADC flag
859 \param[in] flag: ADC flag
860 only one parameter can be selected which is shown as below:
861 \arg ADC_FLAG_WDE: analog watchdog event flag
862 \arg ADC_FLAG_EOC: end of group conversion flag
863 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
864 \arg ADC_FLAG_STIC: start flag of inserted channel group
865 \arg ADC_FLAG_STRC: start flag of regular channel group
866 \param[out] none
867 \retval none
868 */
adc_flag_clear(uint32_t flag)869 void adc_flag_clear(uint32_t flag)
870 {
871 ADC_STAT &= ~((uint32_t)flag);
872 }
873
874 /*!
875 \brief enable ADC interrupt
876 \param[in] interrupt: ADC interrupt
877 only one parameter can be selected which is shown as below:
878 \arg ADC_INT_WDE: analog watchdog interrupt
879 \arg ADC_INT_EOC: end of group conversion interrupt
880 \arg ADC_INT_EOIC: end of inserted group conversion interrupt
881 \param[out] none
882 \retval none
883 */
adc_interrupt_enable(uint32_t interrupt)884 void adc_interrupt_enable(uint32_t interrupt)
885 {
886 switch(interrupt) {
887 case ADC_INT_WDE:
888 /* enable analog watchdog interrupt */
889 ADC_CTL0 |= (uint32_t) ADC_CTL0_WDEIE;
890 break;
891 case ADC_INT_EOC:
892 /* enable end of group conversion interrupt */
893 ADC_CTL0 |= (uint32_t) ADC_CTL0_EOCIE;
894 break;
895 case ADC_INT_EOIC:
896 /* enable end of inserted group conversion interrupt */
897 ADC_CTL0 |= (uint32_t) ADC_CTL0_EOICIE;
898 break;
899 default:
900 break;
901 }
902 }
903
904 /*!
905 \brief disable ADC interrupt
906 \param[in] interrupt: ADC interrupt
907 only one parameter can be selected which is shown as below:
908 \arg ADC_INT_WDE: analog watchdog interrupt
909 \arg ADC_INT_EOC: end of group conversion interrupt
910 \arg ADC_INT_EOIC: end of inserted group conversion interrupt
911 \param[out] none
912 \retval none
913 */
adc_interrupt_disable(uint32_t interrupt)914 void adc_interrupt_disable(uint32_t interrupt)
915 {
916 switch(interrupt) {
917 /* select the interrupt source */
918 case ADC_INT_WDE:
919 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_WDEIE);
920 break;
921 case ADC_INT_EOC:
922 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_EOCIE);
923 break;
924 case ADC_INT_EOIC:
925 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_EOICIE);
926 break;
927 default:
928 break;
929 }
930 }
931
932 /*!
933 \brief get ADC interrupt flag
934 \param[in] int_flag: ADC interrupt flag
935 only one parameter can be selected which is shown as below:
936 \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag
937 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
938 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
939 \param[out] none
940 \retval FlagStatus: SET or RESET
941 */
adc_interrupt_flag_get(uint32_t int_flag)942 FlagStatus adc_interrupt_flag_get(uint32_t int_flag)
943 {
944 FlagStatus interrupt_flag = RESET;
945 uint32_t state;
946 /* check the interrupt flags */
947 switch(int_flag) {
948 case ADC_INT_FLAG_WDE:
949 /* get the ADC analog watchdog interrupt flags */
950 state = ADC_STAT & ADC_STAT_WDE;
951 if((ADC_CTL0 & ADC_CTL0_WDEIE) && state) {
952 interrupt_flag = SET;
953 }
954 break;
955 case ADC_INT_FLAG_EOC:
956 /* get the ADC end of group conversion interrupt flags */
957 state = ADC_STAT & ADC_STAT_EOC;
958 if((ADC_CTL0 & ADC_CTL0_EOCIE) && state) {
959 interrupt_flag = SET;
960 }
961 break;
962 case ADC_INT_FLAG_EOIC:
963 /* get the ADC end of inserted group conversion interrupt flags */
964 state = ADC_STAT & ADC_STAT_EOIC;
965 if((ADC_CTL0 & ADC_CTL0_EOICIE) && state) {
966 interrupt_flag = SET;
967 }
968 break;
969 default:
970 break;
971 }
972 return interrupt_flag;
973 }
974
975 /*!
976 \brief clear ADC interrupt flag
977 \param[in] int_flag: ADC interrupt flag
978 only one parameter can be selected which is shown as below:
979 \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag
980 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
981 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
982 \param[out] none
983 \retval none
984 */
adc_interrupt_flag_clear(uint32_t int_flag)985 void adc_interrupt_flag_clear(uint32_t int_flag)
986 {
987 ADC_STAT &= ~((uint32_t)int_flag);
988 }
989
