1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup mcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup mcr 67 * @defgroup mcr_registers MCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 69 * @details Misc Control. 70 */ 71 72 /** 73 * @ingroup mcr_registers 74 * Structure type to access the MCR Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0; 78 __IO uint32_t rst; /**< <tt>\b 0x04:</tt> MCR RST Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> MCR CLKCTRL Register */ 80 __IO uint32_t aincomp; /**< <tt>\b 0x0C:</tt> MCR AINCOMP Register */ 81 __IO uint32_t lppioctrl; /**< <tt>\b 0x10:</tt> MCR LPPIOCTRL Register */ 82 __R uint32_t rsv_0x14_0x23[4]; 83 __IO uint32_t pclkdis; /**< <tt>\b 0x24:</tt> MCR PCLKDIS Register */ 84 __R uint32_t rsv_0x28_0x33[3]; 85 __IO uint32_t aeskey; /**< <tt>\b 0x34:</tt> MCR AESKEY Register */ 86 __IO uint32_t adc_cfg0; /**< <tt>\b 0x38:</tt> MCR ADC_CFG0 Register */ 87 __IO uint32_t adc_cfg1; /**< <tt>\b 0x3C:</tt> MCR ADC_CFG1 Register */ 88 __IO uint32_t adc_cfg2; /**< <tt>\b 0x40:</tt> MCR ADC_CFG2 Register */ 89 __IO uint32_t adc_cfg3; /**< <tt>\b 0x44:</tt> MCR ADC_CFG3 Register */ 90 } mxc_mcr_regs_t; 91 92 /* Register offsets for module MCR */ 93 /** 94 * @ingroup mcr_registers 95 * @defgroup MCR_Register_Offsets Register Offsets 96 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 97 * @{ 98 */ 99 #define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ 100 #define MXC_R_MCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */ 101 #define MXC_R_MCR_AINCOMP ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: <tt> 0x000C</tt> */ 102 #define MXC_R_MCR_LPPIOCTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 103 #define MXC_R_MCR_PCLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: <tt> 0x0024</tt> */ 104 #define MXC_R_MCR_AESKEY ((uint32_t)0x00000034UL) /**< Offset from MCR Base Address: <tt> 0x0034</tt> */ 105 #define MXC_R_MCR_ADC_CFG0 ((uint32_t)0x00000038UL) /**< Offset from MCR Base Address: <tt> 0x0038</tt> */ 106 #define MXC_R_MCR_ADC_CFG1 ((uint32_t)0x0000003CUL) /**< Offset from MCR Base Address: <tt> 0x003C</tt> */ 107 #define MXC_R_MCR_ADC_CFG2 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: <tt> 0x0040</tt> */ 108 #define MXC_R_MCR_ADC_CFG3 ((uint32_t)0x00000044UL) /**< Offset from MCR Base Address: <tt> 0x0044</tt> */ 109 /**@} end of group mcr_registers */ 110 111 /** 112 * @ingroup mcr_registers 113 * @defgroup MCR_RST MCR_RST 114 * @brief Low Power Reset Control Register 115 * @{ 116 */ 117 #define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */ 118 #define MXC_F_MCR_RST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */ 119 120 #define MXC_F_MCR_RST_LPTMR1_POS 1 /**< RST_LPTMR1 Position */ 121 #define MXC_F_MCR_RST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */ 122 123 #define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */ 124 #define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */ 125 126 #define MXC_F_MCR_RST_RTC_POS 3 /**< RST_RTC Position */ 127 #define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */ 128 129 /**@} end of group MCR_RST_Register */ 130 131 /** 132 * @ingroup mcr_registers 133 * @defgroup MCR_CLKCTRL MCR_CLKCTRL 134 * @brief Clock Control. 135 * @{ 136 */ 137 #define MXC_F_MCR_CLKCTRL_ERTCO_PD_POS 16 /**< CLKCTRL_ERTCO_PD Position */ 138 #define MXC_F_MCR_CLKCTRL_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_PD_POS)) /**< CLKCTRL_ERTCO_PD Mask */ 139 140 #define MXC_F_MCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 141 #define MXC_F_MCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 142 143 /**@} end of group MCR_CLKCTRL_Register */ 144 145 /** 146 * @ingroup mcr_registers 147 * @defgroup MCR_AINCOMP MCR_AINCOMP 148 * @brief AIN Comparator. 149 * @{ 150 */ 151 #define MXC_F_MCR_AINCOMP_PD_POS 0 /**< AINCOMP_PD Position */ 152 #define MXC_F_MCR_AINCOMP_PD ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_PD_POS)) /**< AINCOMP_PD Mask */ 153 154 #define MXC_F_MCR_AINCOMP_HYST_POS 2 /**< AINCOMP_HYST Position */ 155 #define MXC_F_MCR_AINCOMP_HYST ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_HYST_POS)) /**< AINCOMP_HYST Mask */ 156 157 #define MXC_F_MCR_AINCOMP_NSEL_COMP0_POS 16 /**< AINCOMP_NSEL_COMP0 Position */ 158 #define MXC_F_MCR_AINCOMP_NSEL_COMP0 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_NSEL_COMP0_POS)) /**< AINCOMP_NSEL_COMP0 Mask */ 159 160 #define MXC_F_MCR_AINCOMP_PSEL_COMP0_POS 20 /**< AINCOMP_PSEL_COMP0 Position */ 161 #define MXC_F_MCR_AINCOMP_PSEL_COMP0 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_PSEL_COMP0_POS)) /**< AINCOMP_PSEL_COMP0 Mask */ 162 163 #define MXC_F_MCR_AINCOMP_NSEL_COMP1_POS 24 /**< AINCOMP_NSEL_COMP1 Position */ 164 #define MXC_F_MCR_AINCOMP_NSEL_COMP1 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_NSEL_COMP1_POS)) /**< AINCOMP_NSEL_COMP1 Mask */ 165 166 #define MXC_F_MCR_AINCOMP_PSEL_COMP1_POS 28 /**< AINCOMP_PSEL_COMP1 Position */ 167 #define MXC_F_MCR_AINCOMP_PSEL_COMP1 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_PSEL_COMP1_POS)) /**< AINCOMP_PSEL_COMP1 Mask */ 168 169 /**@} end of group MCR_AINCOMP_Register */ 170 171 /** 172 * @ingroup mcr_registers 173 * @defgroup MCR_LPPIOCTRL MCR_LPPIOCTRL 174 * @brief Low Power Peripheral IO Control Register. 175 * @{ 176 */ 177 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS 0 /**< LPPIOCTRL_LPTMR0_I Position */ 178 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS)) /**< LPPIOCTRL_LPTMR0_I Mask */ 179 180 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS 1 /**< LPPIOCTRL_LPTMR0_O Position */ 181 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS)) /**< LPPIOCTRL_LPTMR0_O Mask */ 182 183 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS 2 /**< LPPIOCTRL_LPTMR1_I Position */ 184 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS)) /**< LPPIOCTRL_LPTMR1_I Mask */ 185 186 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS 3 /**< LPPIOCTRL_LPTMR1_O Position */ 187 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS)) /**< LPPIOCTRL_LPTMR1_O Mask */ 188 189 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS 4 /**< LPPIOCTRL_LPUART0_RX Position */ 190 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS)) /**< LPPIOCTRL_LPUART0_RX Mask */ 191 192 #define MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS 5 /**< LPPIOCTRL_LPUART0_TX Position */ 193 #define MXC_F_MCR_LPPIOCTRL_LPUART0_TX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS)) /**< LPPIOCTRL_LPUART0_TX Mask */ 194 195 #define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS 6 /**< LPPIOCTRL_LPUART0_CTS Position */ 196 #define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS)) /**< LPPIOCTRL_LPUART0_CTS Mask */ 197 198 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS 7 /**< LPPIOCTRL_LPUART0_RTS Position */ 199 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS)) /**< LPPIOCTRL_LPUART0_RTS Mask */ 200 201 /**@} end of group MCR_LPPIOCTRL_Register */ 202 203 /** 204 * @ingroup mcr_registers 205 * @defgroup MCR_PCLKDIS MCR_PCLKDIS 206 * @brief Low Power Peripheral Clock Disable. 207 * @{ 208 */ 209 #define MXC_F_MCR_PCLKDIS_LPTMR0_POS 0 /**< PCLKDIS_LPTMR0 Position */ 210 #define MXC_F_MCR_PCLKDIS_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPTMR0_POS)) /**< PCLKDIS_LPTMR0 Mask */ 211 212 #define MXC_F_MCR_PCLKDIS_LPTMR1_POS 1 /**< PCLKDIS_LPTMR1 Position */ 213 #define MXC_F_MCR_PCLKDIS_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPTMR1_POS)) /**< PCLKDIS_LPTMR1 Mask */ 214 215 #define MXC_F_MCR_PCLKDIS_LPUART0_POS 2 /**< PCLKDIS_LPUART0 Position */ 216 #define MXC_F_MCR_PCLKDIS_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPUART0_POS)) /**< PCLKDIS_LPUART0 Mask */ 217 218 /**@} end of group MCR_PCLKDIS_Register */ 219 220 /** 221 * @ingroup mcr_registers 222 * @defgroup MCR_AESKEY MCR_AESKEY 223 * @brief AES Key Pointer and Status. 224 * @{ 225 */ 226 #define MXC_F_MCR_AESKEY_PTR_POS 0 /**< AESKEY_PTR Position */ 227 #define MXC_F_MCR_AESKEY_PTR ((uint32_t)(0xFFFFUL << MXC_F_MCR_AESKEY_PTR_POS)) /**< AESKEY_PTR Mask */ 228 229 /**@} end of group MCR_AESKEY_Register */ 230 231 /** 232 * @ingroup mcr_registers 233 * @defgroup MCR_ADC_CFG0 MCR_ADC_CFG0 234 * @brief ADC Cfig Register0. 235 * @{ 236 */ 237 #define MXC_F_MCR_ADC_CFG0_LP_5K_DIS_POS 0 /**< ADC_CFG0_LP_5K_DIS Position */ 238 #define MXC_F_MCR_ADC_CFG0_LP_5K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_LP_5K_DIS_POS)) /**< ADC_CFG0_LP_5K_DIS Mask */ 239 240 #define MXC_F_MCR_ADC_CFG0_LP_50K_DIS_POS 1 /**< ADC_CFG0_LP_50K_DIS Position */ 241 #define MXC_F_MCR_ADC_CFG0_LP_50K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_LP_50K_DIS_POS)) /**< ADC_CFG0_LP_50K_DIS Mask */ 242 243 #define MXC_F_MCR_ADC_CFG0_EXT_REF_POS 2 /**< ADC_CFG0_EXT_REF Position */ 244 #define MXC_F_MCR_ADC_CFG0_EXT_REF ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_EXT_REF_POS)) /**< ADC_CFG0_EXT_REF Mask */ 245 246 #define MXC_F_MCR_ADC_CFG0_REF_SEL_POS 3 /**< ADC_CFG0_REF_SEL Position */ 247 #define MXC_F_MCR_ADC_CFG0_REF_SEL ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_REF_SEL_POS)) /**< ADC_CFG0_REF_SEL Mask */ 248 249 /**@} end of group MCR_ADC_CFG0_Register */ 250 251 /** 252 * @ingroup mcr_registers 253 * @defgroup MCR_ADC_CFG1 MCR_ADC_CFG1 254 * @brief ADC Config Register1. 255 * @{ 256 */ 257 #define MXC_F_MCR_ADC_CFG1_CH0_PU_DYN_POS 0 /**< ADC_CFG1_CH0_PU_DYN Position */ 258 #define MXC_F_MCR_ADC_CFG1_CH0_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH0_PU_DYN_POS)) /**< ADC_CFG1_CH0_PU_DYN Mask */ 259 260 #define MXC_F_MCR_ADC_CFG1_CH1_PU_DYN_POS 1 /**< ADC_CFG1_CH1_PU_DYN Position */ 261 #define MXC_F_MCR_ADC_CFG1_CH1_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH1_PU_DYN_POS)) /**< ADC_CFG1_CH1_PU_DYN Mask */ 262 263 #define MXC_F_MCR_ADC_CFG1_CH2_PU_DYN_POS 2 /**< ADC_CFG1_CH2_PU_DYN Position */ 264 #define MXC_F_MCR_ADC_CFG1_CH2_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH2_PU_DYN_POS)) /**< ADC_CFG1_CH2_PU_DYN Mask */ 265 266 #define MXC_F_MCR_ADC_CFG1_CH3_PU_DYN_POS 3 /**< ADC_CFG1_CH3_PU_DYN Position */ 267 #define MXC_F_MCR_ADC_CFG1_CH3_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH3_PU_DYN_POS)) /**< ADC_CFG1_CH3_PU_DYN Mask */ 268 269 #define MXC_F_MCR_ADC_CFG1_CH4_PU_DYN_POS 4 /**< ADC_CFG1_CH4_PU_DYN Position */ 270 #define MXC_F_MCR_ADC_CFG1_CH4_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH4_PU_DYN_POS)) /**< ADC_CFG1_CH4_PU_DYN Mask */ 271 272 #define MXC_F_MCR_ADC_CFG1_CH5_PU_DYN_POS 5 /**< ADC_CFG1_CH5_PU_DYN Position */ 273 #define MXC_F_MCR_ADC_CFG1_CH5_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH5_PU_DYN_POS)) /**< ADC_CFG1_CH5_PU_DYN Mask */ 274 275 #define MXC_F_MCR_ADC_CFG1_CH6_PU_DYN_POS 6 /**< ADC_CFG1_CH6_PU_DYN Position */ 276 #define MXC_F_MCR_ADC_CFG1_CH6_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH6_PU_DYN_POS)) /**< ADC_CFG1_CH6_PU_DYN Mask */ 277 278 #define MXC_F_MCR_ADC_CFG1_CH7_PU_DYN_POS 7 /**< ADC_CFG1_CH7_PU_DYN Position */ 279 #define MXC_F_MCR_ADC_CFG1_CH7_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH7_PU_DYN_POS)) /**< ADC_CFG1_CH7_PU_DYN Mask */ 280 281 #define MXC_F_MCR_ADC_CFG1_CH8_PU_DYN_POS 8 /**< ADC_CFG1_CH8_PU_DYN Position */ 282 #define MXC_F_MCR_ADC_CFG1_CH8_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH8_PU_DYN_POS)) /**< ADC_CFG1_CH8_PU_DYN Mask */ 283 284 #define MXC_F_MCR_ADC_CFG1_CH9_PU_DYN_POS 9 /**< ADC_CFG1_CH9_PU_DYN Position */ 285 #define MXC_F_MCR_ADC_CFG1_CH9_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH9_PU_DYN_POS)) /**< ADC_CFG1_CH9_PU_DYN Mask */ 286 287 #define MXC_F_MCR_ADC_CFG1_CH10_PU_DYN_POS 10 /**< ADC_CFG1_CH10_PU_DYN Position */ 288 #define MXC_F_MCR_ADC_CFG1_CH10_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH10_PU_DYN_POS)) /**< ADC_CFG1_CH10_PU_DYN Mask */ 289 290 #define MXC_F_MCR_ADC_CFG1_CH11_PU_DYN_POS 11 /**< ADC_CFG1_CH11_PU_DYN Position */ 291 #define MXC_F_MCR_ADC_CFG1_CH11_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH11_PU_DYN_POS)) /**< ADC_CFG1_CH11_PU_DYN Mask */ 292 293 #define MXC_F_MCR_ADC_CFG1_CH12_PU_DYN_POS 12 /**< ADC_CFG1_CH12_PU_DYN Position */ 294 #define MXC_F_MCR_ADC_CFG1_CH12_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH12_PU_DYN_POS)) /**< ADC_CFG1_CH12_PU_DYN Mask */ 295 296 /**@} end of group MCR_ADC_CFG1_Register */ 297 298 /** 299 * @ingroup mcr_registers 300 * @defgroup MCR_ADC_CFG2 MCR_ADC_CFG2 301 * @brief ADC Config Register2. 302 * @{ 303 */ 304 #define MXC_F_MCR_ADC_CFG2_CH0_POS 0 /**< ADC_CFG2_CH0 Position */ 305 #define MXC_F_MCR_ADC_CFG2_CH0 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH0_POS)) /**< ADC_CFG2_CH0 Mask */ 306 #define MXC_V_MCR_ADC_CFG2_CH0_DIV1 ((uint32_t)0x0UL) /**< ADC_CFG2_CH0_DIV1 Value */ 307 #define MXC_S_MCR_ADC_CFG2_CH0_DIV1 (MXC_V_MCR_ADC_CFG2_CH0_DIV1 << MXC_F_MCR_ADC_CFG2_CH0_POS) /**< ADC_CFG2_CH0_DIV1 Setting */ 308 #define MXC_V_MCR_ADC_CFG2_CH0_DIV2_5K ((uint32_t)0x1UL) /**< ADC_CFG2_CH0_DIV2_5K Value */ 309 #define MXC_S_MCR_ADC_CFG2_CH0_DIV2_5K (MXC_V_MCR_ADC_CFG2_CH0_DIV2_5K << MXC_F_MCR_ADC_CFG2_CH0_POS) /**< ADC_CFG2_CH0_DIV2_5K Setting */ 310 #define MXC_V_MCR_ADC_CFG2_CH0_DIV2_50K ((uint32_t)0x2UL) /**< ADC_CFG2_CH0_DIV2_50K Value */ 311 #define MXC_S_MCR_ADC_CFG2_CH0_DIV2_50K (MXC_V_MCR_ADC_CFG2_CH0_DIV2_50K << MXC_F_MCR_ADC_CFG2_CH0_POS) /**< ADC_CFG2_CH0_DIV2_50K Setting */ 312 313 #define MXC_F_MCR_ADC_CFG2_CH1_POS 2 /**< ADC_CFG2_CH1 Position */ 314 #define MXC_F_MCR_ADC_CFG2_CH1 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH1_POS)) /**< ADC_CFG2_CH1 Mask */ 315 316 #define MXC_F_MCR_ADC_CFG2_CH2_POS 4 /**< ADC_CFG2_CH2 Position */ 317 #define MXC_F_MCR_ADC_CFG2_CH2 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH2_POS)) /**< ADC_CFG2_CH2 Mask */ 318 319 #define MXC_F_MCR_ADC_CFG2_CH3_POS 6 /**< ADC_CFG2_CH3 Position */ 320 #define MXC_F_MCR_ADC_CFG2_CH3 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH3_POS)) /**< ADC_CFG2_CH3 Mask */ 321 322 #define MXC_F_MCR_ADC_CFG2_CH4_POS 8 /**< ADC_CFG2_CH4 Position */ 323 #define MXC_F_MCR_ADC_CFG2_CH4 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH4_POS)) /**< ADC_CFG2_CH4 Mask */ 324 325 #define MXC_F_MCR_ADC_CFG2_CH5_POS 10 /**< ADC_CFG2_CH5 Position */ 326 #define MXC_F_MCR_ADC_CFG2_CH5 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH5_POS)) /**< ADC_CFG2_CH5 Mask */ 327 328 #define MXC_F_MCR_ADC_CFG2_CH6_POS 12 /**< ADC_CFG2_CH6 Position */ 329 #define MXC_F_MCR_ADC_CFG2_CH6 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH6_POS)) /**< ADC_CFG2_CH6 Mask */ 330 331 #define MXC_F_MCR_ADC_CFG2_CH7_POS 14 /**< ADC_CFG2_CH7 Position */ 332 #define MXC_F_MCR_ADC_CFG2_CH7 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH7_POS)) /**< ADC_CFG2_CH7 Mask */ 333 334 #define MXC_F_MCR_ADC_CFG2_CH8_POS 16 /**< ADC_CFG2_CH8 Position */ 335 #define MXC_F_MCR_ADC_CFG2_CH8 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH8_POS)) /**< ADC_CFG2_CH8 Mask */ 336 337 #define MXC_F_MCR_ADC_CFG2_CH9_POS 18 /**< ADC_CFG2_CH9 Position */ 338 #define MXC_F_MCR_ADC_CFG2_CH9 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH9_POS)) /**< ADC_CFG2_CH9 Mask */ 339 340 #define MXC_F_MCR_ADC_CFG2_CH10_POS 20 /**< ADC_CFG2_CH10 Position */ 341 #define MXC_F_MCR_ADC_CFG2_CH10 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH10_POS)) /**< ADC_CFG2_CH10 Mask */ 342 343 #define MXC_F_MCR_ADC_CFG2_CH11_POS 22 /**< ADC_CFG2_CH11 Position */ 344 #define MXC_F_MCR_ADC_CFG2_CH11 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH11_POS)) /**< ADC_CFG2_CH11 Mask */ 345 346 #define MXC_F_MCR_ADC_CFG2_CH12_POS 24 /**< ADC_CFG2_CH12 Position */ 347 #define MXC_F_MCR_ADC_CFG2_CH12 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH12_POS)) /**< ADC_CFG2_CH12 Mask */ 348 349 /**@} end of group MCR_ADC_CFG2_Register */ 350 351 /** 352 * @ingroup mcr_registers 353 * @defgroup MCR_ADC_CFG3 MCR_ADC_CFG3 354 * @brief ADC Config Register3. 355 * @{ 356 */ 357 #define MXC_F_MCR_ADC_CFG3_VREFM_POS 0 /**< ADC_CFG3_VREFM Position */ 358 #define MXC_F_MCR_ADC_CFG3_VREFM ((uint32_t)(0x7FUL << MXC_F_MCR_ADC_CFG3_VREFM_POS)) /**< ADC_CFG3_VREFM Mask */ 359 360 #define MXC_F_MCR_ADC_CFG3_VREFP_POS 8 /**< ADC_CFG3_VREFP Position */ 361 #define MXC_F_MCR_ADC_CFG3_VREFP ((uint32_t)(0x7FUL << MXC_F_MCR_ADC_CFG3_VREFP_POS)) /**< ADC_CFG3_VREFP Mask */ 362 363 #define MXC_F_MCR_ADC_CFG3_IDRV_POS 16 /**< ADC_CFG3_IDRV Position */ 364 #define MXC_F_MCR_ADC_CFG3_IDRV ((uint32_t)(0xFUL << MXC_F_MCR_ADC_CFG3_IDRV_POS)) /**< ADC_CFG3_IDRV Mask */ 365 366 #define MXC_F_MCR_ADC_CFG3_VCM_POS 20 /**< ADC_CFG3_VCM Position */ 367 #define MXC_F_MCR_ADC_CFG3_VCM ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG3_VCM_POS)) /**< ADC_CFG3_VCM Mask */ 368 369 #define MXC_F_MCR_ADC_CFG3_ATB_POS 22 /**< ADC_CFG3_ATB Position */ 370 #define MXC_F_MCR_ADC_CFG3_ATB ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG3_ATB_POS)) /**< ADC_CFG3_ATB Mask */ 371 372 #define MXC_F_MCR_ADC_CFG3_D_IBOOST_POS 24 /**< ADC_CFG3_D_IBOOST Position */ 373 #define MXC_F_MCR_ADC_CFG3_D_IBOOST ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG3_D_IBOOST_POS)) /**< ADC_CFG3_D_IBOOST Mask */ 374 375 /**@} end of group MCR_ADC_CFG3_Register */ 376 377 #ifdef __cplusplus 378 } 379 #endif 380 381 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_ 382
