1 /*
2 * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/logging/log.h>
10 #include <esp_types.h>
11 #include <stdlib.h>
12 #include <ctype.h>
13 #include "sdkconfig.h"
14 #include "esp_log.h"
15 #include "esp_check.h"
16 #include "esp_pm.h"
17 #include "soc/rtc.h"
18 #include "driver/rtc_io.h"
19 #include "sys/lock.h"
20 #include "driver/gpio.h"
21 #include "esp_private/adc_share_hw_ctrl.h"
22 #include "esp_private/sar_periph_ctrl.h"
23 #include "adc1_private.h"
24 #include "hal/adc_types.h"
25 #include "hal/adc_hal.h"
26 #include "hal/adc_hal_common.h"
27 #include "esp_private/periph_ctrl.h"
28 #include "driver/adc_types_legacy.h"
29 #include "esp_clk_tree.h"
30
31 #if SOC_DAC_SUPPORTED
32 #include "hal/dac_types.h"
33 #include "hal/dac_ll.h"
34 #endif
35
36 #if CONFIG_IDF_TARGET_ESP32S3
37 #include "esp_efuse_rtc_calib.h"
38 #endif
39
40
41 static const char *ADC_TAG = "ADC";
42
43 #define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
44
45 //////////////////////// Locks ///////////////////////////////////////////
46 LOG_MODULE_REGISTER(adc_legacy, CONFIG_ADC_LOG_LEVEL);
47
48 extern int rtc_spinlock;
49
50 #define RTC_ENTER_CRITICAL() do { rtc_spinlock = irq_lock(); } while(0)
51 #define RTC_EXIT_CRITICAL() irq_unlock(rtc_spinlock);
52
53 #define DIGI_ENTER_CRITICAL()
54 #define DIGI_EXIT_CRITICAL()
55
56 #define ADC_POWER_ENTER() RTC_ENTER_CRITICAL()
57 #define ADC_POWER_EXIT() RTC_EXIT_CRITICAL()
58
59 #define DIGI_CONTROLLER_ENTER() DIGI_ENTER_CRITICAL()
60 #define DIGI_CONTROLLER_EXIT() DIGI_EXIT_CRITICAL()
61
62 #define SARADC1_ENTER() RTC_ENTER_CRITICAL()
63 #define SARADC1_EXIT() RTC_EXIT_CRITICAL()
64
65 #define SARADC2_ENTER() RTC_ENTER_CRITICAL()
66 #define SARADC2_EXIT() RTC_EXIT_CRITICAL()
67
68 //n stands for ADC unit: 1 for ADC1 and 2 for ADC2. Currently both unit touches the same registers
69 #define VREF_ENTER(n) RTC_ENTER_CRITICAL()
70 #define VREF_EXIT(n) RTC_EXIT_CRITICAL()
71
72 #define FSM_ENTER() RTC_ENTER_CRITICAL()
73 #define FSM_EXIT() RTC_EXIT_CRITICAL()
74
75 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
76 //prevent ADC1 being used by I2S dma and other tasks at the same time.
77 K_MUTEX_DEFINE(adc1_dma_lock);
78 #define SARADC1_ACQUIRE() do { k_mutex_lock(&adc1_dma_lock, K_FOREVER); } while(0)
79 #define SARADC1_RELEASE() do { k_mutex_unlock(&adc1_dma_lock); } while(0)
80 #endif
81 /*
82 In ADC2, there're two locks used for different cases:
83 1. lock shared with app and Wi-Fi:
84 ESP32:
85 When Wi-Fi using the ADC2, we assume it will never stop, so app checks the lock and returns immediately if failed.
86 ESP32S2:
87 The controller's control over the ADC is determined by the arbiter. There is no need to control by lock.
88
89 2. lock shared between tasks:
90 when several tasks sharing the ADC2, we want to guarantee
91 all the requests will be handled.
92 Since conversions are short (about 31us), app returns the lock very soon,
93 we use a spinlock to stand there waiting to do conversions one by one.
94
95 adc2_spinlock should be acquired first, then call `adc_lock_release(ADC_UNIT_2)` or rtc_spinlock.
96 */
97
98 #if CONFIG_IDF_TARGET_ESP32S2
99 #ifdef CONFIG_PM_ENABLE
100 static esp_pm_lock_handle_t s_adc2_arbiter_lock;
101 #endif //CONFIG_PM_ENABLE
102 #endif // !CONFIG_IDF_TARGET_ESP32
103
104 static uint32_t clk_src_freq_hz;
105
106 static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, uint32_t clk_src_freq_hz, int *out_raw);
107
108 /*---------------------------------------------------------------
109 ADC Common
110 ---------------------------------------------------------------*/
adc1_pad_get_io_num(adc1_channel_t channel,gpio_num_t * gpio_num)111 esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
112 {
113 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
114
115 int io = ADC_GET_IO_NUM(ADC_UNIT_1, channel);
116 if (io < 0) {
117 return ESP_ERR_INVALID_ARG;
118 } else {
119 *gpio_num = (gpio_num_t)io;
120 }
121
122 return ESP_OK;
123 }
124
125 #if (SOC_ADC_PERIPH_NUM >= 2)
adc2_pad_get_io_num(adc2_channel_t channel,gpio_num_t * gpio_num)126 esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num)
127 {
128 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
129
130 int io = ADC_GET_IO_NUM(ADC_UNIT_2, channel);
131 if (io < 0) {
132 return ESP_ERR_INVALID_ARG;
133 } else {
134 *gpio_num = (gpio_num_t)io;
135 }
136
137 return ESP_OK;
138 }
139 #endif
140
141 //------------------------------------------------------------RTC Single Read----------------------------------------------//
142 #if SOC_ADC_RTC_CTRL_SUPPORTED
adc_set_clk_div(uint8_t clk_div)143 esp_err_t adc_set_clk_div(uint8_t clk_div)
144 {
145 DIGI_CONTROLLER_ENTER();
146 adc_ll_digi_set_clk_div(clk_div);
147 DIGI_CONTROLLER_EXIT();
148 return ESP_OK;
149 }
150
adc_rtc_chan_init(adc_unit_t adc_unit)151 static void adc_rtc_chan_init(adc_unit_t adc_unit)
152 {
153 if (adc_unit == ADC_UNIT_1) {
154 /* Workaround: Disable the synchronization operation function of ADC1 and DAC.
155 If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage. */
156 #if SOC_DAC_SUPPORTED
157 dac_ll_rtc_sync_by_adc(false);
158 #endif
159 adc_oneshot_ll_output_invert(ADC_UNIT_1, ADC_LL_DATA_INVERT_DEFAULT(ADC_UNIT_1));
160 adc_ll_set_sar_clk_div(ADC_UNIT_1, ADC_LL_SAR_CLK_DIV_DEFAULT(ADC_UNIT_1));
161 #ifdef CONFIG_IDF_TARGET_ESP32
162 adc_ll_hall_disable(); //Disable other peripherals.
163 adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
164 #endif
165 }
166 if (adc_unit == ADC_UNIT_2) {
167 adc_hal_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
168 adc_oneshot_ll_output_invert(ADC_UNIT_2, ADC_LL_DATA_INVERT_DEFAULT(ADC_UNIT_2));
169 adc_ll_set_sar_clk_div(ADC_UNIT_2, ADC_LL_SAR_CLK_DIV_DEFAULT(ADC_UNIT_2));
170 }
171 }
172
adc_common_gpio_init(adc_unit_t adc_unit,adc_channel_t channel)173 esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
174 {
175 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(adc_unit), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
176
177 gpio_num_t gpio_num = 0;
178 //If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run
179 if (adc_unit == ADC_UNIT_1) {
180 gpio_num = ADC_GET_IO_NUM(ADC_UNIT_1, channel);
181
182 } else if (adc_unit == ADC_UNIT_2) {
183 gpio_num = ADC_GET_IO_NUM(ADC_UNIT_2, channel);
184 } else {
185 return ESP_ERR_INVALID_ARG;
186 }
187
188 ESP_RETURN_ON_ERROR(rtc_gpio_init(gpio_num), ADC_TAG, "rtc_gpio_init fail");
189 ESP_RETURN_ON_ERROR(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED), ADC_TAG, "rtc_gpio_set_direction fail");
190 ESP_RETURN_ON_ERROR(rtc_gpio_pulldown_dis(gpio_num), ADC_TAG, "rtc_gpio_pulldown_dis fail");
191 ESP_RETURN_ON_ERROR(rtc_gpio_pullup_dis(gpio_num), ADC_TAG, "rtc_gpio_pullup_dis fail");
192
193 return ESP_OK;
194 }
195
adc_set_data_inv(adc_unit_t adc_unit,bool inv_en)196 esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
197 {
198 if (adc_unit == ADC_UNIT_1) {
199 SARADC1_ENTER();
200 adc_oneshot_ll_output_invert(ADC_UNIT_1, inv_en);
201 SARADC1_EXIT();
202 }
203 if (adc_unit == ADC_UNIT_2) {
204 SARADC2_ENTER();
205 adc_oneshot_ll_output_invert(ADC_UNIT_2, inv_en);
206 SARADC2_EXIT();
207 }
208
209 return ESP_OK;
210 }
211
adc_set_data_width(adc_unit_t adc_unit,adc_bits_width_t width_bit)212 esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
213 {
214 ESP_RETURN_ON_FALSE(width_bit < ADC_WIDTH_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "unsupported bit width");
215 adc_bitwidth_t bitwidth = 0;
216 #if CONFIG_IDF_TARGET_ESP32
217 if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
218 bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
219 } else {
220 switch(width_bit) {
221 case ADC_WIDTH_BIT_9:
222 bitwidth = ADC_BITWIDTH_9;
223 break;
224 case ADC_WIDTH_BIT_10:
225 bitwidth = ADC_BITWIDTH_10;
226 break;
227 case ADC_WIDTH_BIT_11:
228 bitwidth = ADC_BITWIDTH_11;
229 break;
230 case ADC_WIDTH_BIT_12:
231 bitwidth = ADC_BITWIDTH_12;
232 break;
233 default:
234 return ESP_ERR_INVALID_ARG;
235 }
236 }
237 #elif CONFIG_IDF_TARGET_ESP32S2
238 bitwidth = ADC_BITWIDTH_13;
239 #else //esp32s3
240 bitwidth = ADC_BITWIDTH_12;
241 #endif
242
243 if (adc_unit == ADC_UNIT_1) {
244 SARADC1_ENTER();
245 adc_oneshot_ll_set_output_bits(ADC_UNIT_1, bitwidth);
246 SARADC1_EXIT();
247 }
248 if (adc_unit == ADC_UNIT_2) {
249 SARADC2_ENTER();
250 adc_oneshot_ll_set_output_bits(ADC_UNIT_2, bitwidth);
251 SARADC2_EXIT();
252 }
253
254 return ESP_OK;
255 }
256
257 /**
258 * @brief Reset RTC controller FSM.
259 *
260 * @return
261 * - ESP_OK Success
262 */
263 #if !CONFIG_IDF_TARGET_ESP32
adc_rtc_reset(void)264 esp_err_t adc_rtc_reset(void)
265 {
266 FSM_ENTER();
267 adc_ll_rtc_reset();
268 FSM_EXIT();
269 return ESP_OK;
270 }
271 #endif
272
273 /*-------------------------------------------------------------------------------------
274 * ADC1
275 *------------------------------------------------------------------------------------*/
adc1_config_channel_atten(adc1_channel_t channel,adc_atten_t atten)276 esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
277 {
278 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
279 ESP_RETURN_ON_FALSE(atten < SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Atten Err");
280
281 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
282 if (!clk_src_freq_hz) {
283 //should never fail
284 esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
285 }
286 #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
287
288 adc_common_gpio_init(ADC_UNIT_1, channel);
289 SARADC1_ENTER();
290 adc_rtc_chan_init(ADC_UNIT_1);
291 adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
292 SARADC1_EXIT();
293
294 return ESP_OK;
295 }
296
adc1_config_width(adc_bits_width_t width_bit)297 esp_err_t adc1_config_width(adc_bits_width_t width_bit)
298 {
299 ESP_RETURN_ON_FALSE(width_bit < ADC_WIDTH_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "unsupported bit width");
300 adc_bitwidth_t bitwidth = 0;
301 #if CONFIG_IDF_TARGET_ESP32
302 if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
303 bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
304 } else {
305 switch(width_bit) {
306 case ADC_WIDTH_BIT_9:
307 bitwidth = ADC_BITWIDTH_9;
308 break;
309 case ADC_WIDTH_BIT_10:
310 bitwidth = ADC_BITWIDTH_10;
311 break;
312 case ADC_WIDTH_BIT_11:
313 bitwidth = ADC_BITWIDTH_11;
314 break;
315 case ADC_WIDTH_BIT_12:
316 bitwidth = ADC_BITWIDTH_12;
317 break;
318 default:
319 return ESP_ERR_INVALID_ARG;
320 }
321 }
322 #elif CONFIG_IDF_TARGET_ESP32S2
323 bitwidth = ADC_BITWIDTH_13;
324 #else //esp32s3
325 bitwidth = ADC_BITWIDTH_12;
326 #endif
327
328 SARADC1_ENTER();
329 adc_oneshot_ll_set_output_bits(ADC_UNIT_1, bitwidth);
330 SARADC1_EXIT();
331
332 return ESP_OK;
333 }
334
adc1_dma_mode_acquire(void)335 esp_err_t adc1_dma_mode_acquire(void)
336 {
337 /* Use locks to avoid digtal and RTC controller conflicts.
338 for adc1, block until acquire the lock. */
339 SARADC1_ACQUIRE();
340 ESP_LOGD( ADC_TAG, "dma mode takes adc1 lock." );
341
342 sar_periph_ctrl_adc_continuous_power_acquire();
343
344 SARADC1_ENTER();
345 /* switch SARADC into DIG channel */
346 adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
347 SARADC1_EXIT();
348
349 return ESP_OK;
350 }
351
adc1_rtc_mode_acquire(void)352 esp_err_t adc1_rtc_mode_acquire(void)
353 {
354 /* Use locks to avoid digtal and RTC controller conflicts.
355 for adc1, block until acquire the lock. */
356 SARADC1_ACQUIRE();
357 sar_periph_ctrl_adc_oneshot_power_acquire();
358
359 SARADC1_ENTER();
360 /* switch SARADC into RTC channel. */
361 adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_RTC);
362 SARADC1_EXIT();
363
364 return ESP_OK;
365 }
366
adc1_lock_release(void)367 esp_err_t adc1_lock_release(void)
368 {
369 ESP_RETURN_ON_FALSE(adc1_dma_lock.lock_count != 0, ESP_ERR_INVALID_STATE, ADC_TAG, "adc1 lock release called before acquire");
370
371 /* Use locks to avoid digtal and RTC controller conflicts. for adc1, block until acquire the lock. */
372
373 sar_periph_ctrl_adc_oneshot_power_release();
374 SARADC1_RELEASE();
375 return ESP_OK;
376 }
377
adc1_get_raw(adc1_channel_t channel)378 int adc1_get_raw(adc1_channel_t channel)
379 {
380 int adc_value;
381 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
382 adc1_rtc_mode_acquire();
383
384 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
385 adc_atten_t atten = adc_ll_get_atten(ADC_UNIT_1, channel);
386 adc_set_hw_calibration_code(ADC_UNIT_1, atten);
387 #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
388
389 SARADC1_ENTER();
390 #ifdef CONFIG_IDF_TARGET_ESP32
391 adc_ll_hall_disable(); //Disable other peripherals.
392 adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
393 #endif
394 adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_RTC); //Set controller
395 adc_oneshot_ll_set_channel(ADC_UNIT_1, channel);
396 adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &adc_value); //Start conversion, For ADC1, the data always valid.
397 #if !CONFIG_IDF_TARGET_ESP32
398 adc_ll_rtc_reset(); //Reset FSM of rtc controller
399 #endif
400 SARADC1_EXIT();
401
402 adc1_lock_release();
403 return adc_value;
404 }
405
adc1_get_voltage(adc1_channel_t channel)406 int adc1_get_voltage(adc1_channel_t channel) //Deprecated. Use adc1_get_raw() instead
407 {
408 return adc1_get_raw(channel);
409 }
410
411 #if SOC_ULP_SUPPORTED
adc1_ulp_enable(void)412 void adc1_ulp_enable(void)
413 {
414 sar_periph_ctrl_adc_oneshot_power_acquire();
415
416 SARADC1_ENTER();
417 adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
418 /* since most users do not need LNA and HALL with uLP, we disable them here
419 open them in the uLP if needed. */
420 #ifdef CONFIG_IDF_TARGET_ESP32
421 /* disable other peripherals. */
422 adc_ll_hall_disable();
423 adc_ll_amp_disable();
424 #endif
425 SARADC1_EXIT();
426 }
427 #endif
428
429 #if (SOC_ADC_PERIPH_NUM >= 2)
430 /*---------------------------------------------------------------
431 ADC2
432 ---------------------------------------------------------------*/
adc2_config_channel_atten(adc2_channel_t channel,adc_atten_t atten)433 esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
434 {
435 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
436 ESP_RETURN_ON_FALSE(atten <= SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 Atten Err");
437 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
438 if (!clk_src_freq_hz) {
439 //should never fail
440 esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
441 }
442 #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
443
444 adc_common_gpio_init(ADC_UNIT_2, channel);
445
446 #if CONFIG_IDF_TARGET_ESP32
447 /** For ESP32S2 and S3, the right to use ADC2 is controlled by the arbiter, and there is no need to set a lock.*/
448 if (adc_lock_try_acquire(ADC_UNIT_2) != ESP_OK) {
449 //try the lock, return if failed (wifi using).
450 return ESP_ERR_TIMEOUT;
451 }
452 #endif
453
454 //avoid collision with other tasks
455 SARADC2_ENTER();
456 adc_rtc_chan_init(ADC_UNIT_2);
457 adc_oneshot_ll_set_atten(ADC_UNIT_2, channel, atten);
458 SARADC2_EXIT();
459
460 #if CONFIG_IDF_TARGET_ESP32
461 adc_lock_release(ADC_UNIT_2);
462 #endif
463
464 return ESP_OK;
465 }
466
adc2_init(void)467 static inline void adc2_init(void)
468 {
469 #if CONFIG_IDF_TARGET_ESP32S2
470 #ifdef CONFIG_PM_ENABLE
471 /* Lock APB clock. */
472 if (s_adc2_arbiter_lock == NULL) {
473 esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc2", &s_adc2_arbiter_lock);
474 }
475 #endif //CONFIG_PM_ENABLE
476 #endif //CONFIG_IDF_TARGET_ESP32S2
477 }
478
adc2_dac_disable(adc2_channel_t channel)479 static inline void adc2_dac_disable( adc2_channel_t channel)
480 {
481 #if SOC_DAC_SUPPORTED
482 #ifdef CONFIG_IDF_TARGET_ESP32
483 if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 0
484 dac_ll_power_down(DAC_CHAN_0);
485 } else if ( channel == ADC2_CHANNEL_9 ) {
486 dac_ll_power_down(DAC_CHAN_1);
487 }
488 #else
489 if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 0
490 dac_ll_power_down(DAC_CHAN_0);
491 } else if ( channel == ADC2_CHANNEL_7 ) {
492 dac_ll_power_down(DAC_CHAN_1);
493 }
494 #endif
495 #endif // SOC_DAC_SUPPORTED
496 }
497
498 /**
499 * @note For ESP32S2:
500 * The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
501 * Or, the RTC controller will fail when get raw data.
502 * This issue does not occur on digital controllers (DMA mode), and the hardware guarantees that there will be no errors.
503 */
adc2_get_raw(adc2_channel_t channel,adc_bits_width_t width_bit,int * raw_out)504 esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out)
505 {
506 esp_err_t ret = ESP_OK;
507 int adc_value = 0;
508 adc_bitwidth_t bitwidth = 0;
509
510 ESP_RETURN_ON_FALSE(raw_out != NULL, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC out value err");
511 ESP_RETURN_ON_FALSE(channel < ADC2_CHANNEL_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Channel Err");
512 ESP_RETURN_ON_FALSE(width_bit < ADC_WIDTH_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "unsupported bit width");
513 #if CONFIG_IDF_TARGET_ESP32
514 if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
515 bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
516 } else {
517 switch(width_bit) {
518 case ADC_WIDTH_BIT_9:
519 bitwidth = ADC_BITWIDTH_9;
520 break;
521 case ADC_WIDTH_BIT_10:
522 bitwidth = ADC_BITWIDTH_10;
523 break;
524 case ADC_WIDTH_BIT_11:
525 bitwidth = ADC_BITWIDTH_11;
526 break;
527 case ADC_WIDTH_BIT_12:
528 bitwidth = ADC_BITWIDTH_12;
529 break;
530 default:
531 return ESP_ERR_INVALID_ARG;
532 }
533 }
534 #elif CONFIG_IDF_TARGET_ESP32S2
535 bitwidth = ADC_BITWIDTH_13;
536 #else //esp32s3
537 bitwidth = ADC_BITWIDTH_12;
538 #endif
539
540 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
541 adc_atten_t atten = adc_ll_get_atten(ADC_UNIT_2, channel);
542 adc_set_hw_calibration_code(ADC_UNIT_2, atten);
543 #endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
544
545 #if CONFIG_IDF_TARGET_ESP32
546 /** For ESP32S2 and S3, the right to use ADC2 is controlled by the arbiter, and there is no need to set a lock.*/
547 if (adc_lock_try_acquire(ADC_UNIT_2) != ESP_OK) {
548 //try the lock, return if failed (wifi using).
549 return ESP_ERR_TIMEOUT;
550 }
551 #endif
552 sar_periph_ctrl_adc_oneshot_power_acquire(); //in critical section with whole rtc module
553
554 //avoid collision with other tasks
555 adc2_init(); // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
556 SARADC2_ENTER();
557
558 #if SOC_ADC_ARBITER_SUPPORTED
559 adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
560 adc_hal_arbiter_config(&config);
561 #endif
562
563 #ifdef CONFIG_ADC_DISABLE_DAC
564 adc2_dac_disable(channel); //disable other peripherals
565 #endif
566 adc_oneshot_ll_set_output_bits(ADC_UNIT_2, bitwidth);
567
568 #if CONFIG_IDF_TARGET_ESP32
569 adc_ll_set_controller(ADC_UNIT_2, ADC_LL_CTRL_RTC);// set controller
570 #else
571 adc_ll_set_controller(ADC_UNIT_2, ADC_LL_CTRL_ARB);// set controller
572 #endif
573
574 #if CONFIG_IDF_TARGET_ESP32S2
575 #ifdef CONFIG_PM_ENABLE
576 if (s_adc2_arbiter_lock) {
577 esp_pm_lock_acquire(s_adc2_arbiter_lock);
578 }
579 #endif //CONFIG_PM_ENABLE
580 #endif //CONFIG_IDF_TARGET_ESP32
581
582 adc_oneshot_ll_set_channel(ADC_UNIT_2, channel);
583 ret = adc_hal_convert(ADC_UNIT_2, channel, clk_src_freq_hz, &adc_value);
584 if (ret != ESP_OK) {
585 adc_value = -1;
586 }
587
588 #if CONFIG_IDF_TARGET_ESP32S2
589 #ifdef CONFIG_PM_ENABLE
590 /* Release APB clock. */
591 if (s_adc2_arbiter_lock) {
592 esp_pm_lock_release(s_adc2_arbiter_lock);
593 }
594 #endif //CONFIG_PM_ENABLE
595 #endif //CONFIG_IDF_TARGET_ESP32
596 SARADC2_EXIT();
597
598 sar_periph_ctrl_adc_oneshot_power_release();
599 #if CONFIG_IDF_TARGET_ESP32
600 adc_lock_release(ADC_UNIT_2);
601 #endif
602
603 *raw_out = adc_value;
604 return ret;
605 }
606
adc_vref_to_gpio(adc_unit_t adc_unit,gpio_num_t gpio)607 esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
608 {
609 #ifdef CONFIG_IDF_TARGET_ESP32
610 if (adc_unit == ADC_UNIT_1) {
611 return ESP_ERR_INVALID_ARG;
612 }
613 #endif
614 adc2_channel_t ch = ADC2_CHANNEL_MAX;
615 /* Check if the GPIO supported. */
616 for (int i = 0; i < ADC2_CHANNEL_MAX; i++) {
617 if (gpio == ADC_GET_IO_NUM(ADC_UNIT_2, i)) {
618 ch = i;
619 break;
620 }
621 }
622 if (ch == ADC2_CHANNEL_MAX) {
623 return ESP_ERR_INVALID_ARG;
624 }
625
626 sar_periph_ctrl_adc_oneshot_power_acquire();
627 if (adc_unit == ADC_UNIT_1) {
628 VREF_ENTER(1);
629 adc_ll_vref_output(ADC_UNIT_1, ch, true);
630 VREF_EXIT(1);
631 } else if (adc_unit == ADC_UNIT_2) {
632 VREF_ENTER(2);
633 adc_ll_vref_output(ADC_UNIT_2, ch, true);
634 VREF_EXIT(2);
635 }
636
637 //Configure RTC gpio, Only ADC2's channels IO are supported to output reference voltage.
638 adc_common_gpio_init(ADC_UNIT_2, ch);
639 return ESP_OK;
640 }
641
642 #endif //SOC_ADC_RTC_CTRL_SUPPORTED
643 #endif //#if (SOC_ADC_PERIPH_NUM >= 2)
644
645
646 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
647 /*---------------------------------------------------------------
648 Legacy ADC Single Read Mode
649 when RTC controller isn't supported
650 ---------------------------------------------------------------*/
651 #include "esp_check.h"
652
653 int adc_reg_lock;
654 #define ADC_REG_LOCK_ENTER() do { adc_reg_lock = irq_lock(); } while(0)
655 #define ADC_REG_LOCK_EXIT() irq_unlock(adc_reg_lock);
656
657 static adc_atten_t s_atten1_single[ADC1_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC1, used by single read API
658 #if (SOC_ADC_PERIPH_NUM >= 2)
659 static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC2, used by single read API
660 #endif
661
662
adc_digi_get_io_num(adc_unit_t adc_unit,uint8_t adc_channel)663 static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
664 {
665 assert(adc_unit <= SOC_ADC_PERIPH_NUM);
666 uint8_t adc_n = (adc_unit == ADC_UNIT_1) ? 0 : 1;
667 return adc_channel_io_map[adc_n][adc_channel];
668 }
669
adc_digi_gpio_init(adc_unit_t adc_unit,uint16_t channel_mask)670 static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
671 {
672 esp_err_t ret = ESP_OK;
673 uint64_t gpio_mask = 0;
674 uint32_t n = 0;
675 int8_t io = 0;
676 struct gpio_dt_spec gpio;
677
678 gpio.port = DEVICE_DT_GET(DT_NODELABEL(gpio0));
679 gpio.dt_flags = 0;
680 if (!device_is_ready(gpio.port)) {
681 LOG_ERR("gpio0 port not ready");
682 return ESP_FAIL;
683 }
684
685 while (channel_mask) {
686 if (channel_mask & 0x1) {
687 io = adc_digi_get_io_num(adc_unit, n);
688 if (io < 0) {
689 return ESP_ERR_INVALID_ARG;
690 }
691 gpio_mask |= BIT64(io);
692 gpio.pin = io;
693 gpio_pin_configure_dt(&gpio, GPIO_DISCONNECTED);
694 }
695 channel_mask = channel_mask >> 1;
696 n++;
697 }
698
699 return ret;
700 }
701
702 #if CONFIG_IDF_TARGET_ESP32C3
adc_vref_to_gpio(adc_unit_t adc_unit,gpio_num_t gpio)703 esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
704 {
705 esp_err_t ret;
706 uint32_t channel = ADC2_CHANNEL_MAX;
707 if (adc_unit == ADC_UNIT_2) {
708 for (int i = 0; i < ADC2_CHANNEL_MAX; i++) {
709 if (gpio == ADC_GET_IO_NUM(ADC_UNIT_2, i)) {
710 channel = i;
711 break;
712 }
713 }
714 if (channel == ADC2_CHANNEL_MAX) {
715 return ESP_ERR_INVALID_ARG;
716 }
717 }
718
719 sar_periph_ctrl_adc_oneshot_power_acquire();
720 if (adc_unit == ADC_UNIT_1) {
721 RTC_ENTER_CRITICAL();
722 adc_ll_vref_output(ADC_UNIT_1, channel, true);
723 RTC_EXIT_CRITICAL();
724 } else { //ADC_UNIT_2
725 RTC_ENTER_CRITICAL();
726 adc_ll_vref_output(ADC_UNIT_2, channel, true);
727 RTC_EXIT_CRITICAL();
728 }
729
730 ret = adc_digi_gpio_init(ADC_UNIT_2, BIT(channel));
731
732 return ret;
733 }
734 #endif
735
adc1_config_width(adc_bits_width_t width_bit)736 esp_err_t adc1_config_width(adc_bits_width_t width_bit)
737 {
738 //On ESP32C3, the data width is always 12-bits.
739 if (width_bit != ADC_WIDTH_BIT_12) {
740 return ESP_ERR_INVALID_ARG;
741 }
742
743 return ESP_OK;
744 }
745
adc1_config_channel_atten(adc1_channel_t channel,adc_atten_t atten)746 esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
747 {
748 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC1 channel error");
749 ESP_RETURN_ON_FALSE((atten < SOC_ADC_ATTEN_NUM), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Atten Err");
750 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
751 if (!clk_src_freq_hz) {
752 //should never fail
753 esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
754 }
755 #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
756
757 esp_err_t ret = ESP_OK;
758 s_atten1_single[channel] = atten;
759 ret = adc_digi_gpio_init(ADC_UNIT_1, BIT(channel));
760
761 return ret;
762 }
763
adc1_get_raw(adc1_channel_t channel)764 int adc1_get_raw(adc1_channel_t channel)
765 {
766 int raw_out = 0;
767
768 if (adc_lock_try_acquire(ADC_UNIT_1) != ESP_OK) {
769 return ESP_ERR_TIMEOUT;
770 }
771
772 periph_module_enable(PERIPH_SARADC_MODULE);
773 sar_periph_ctrl_adc_oneshot_power_acquire();
774 adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
775
776 adc_atten_t atten = s_atten1_single[channel];
777 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
778 adc_set_hw_calibration_code(ADC_UNIT_1, atten);
779 #endif
780
781 ADC_REG_LOCK_ENTER();
782 adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
783 adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &raw_out);
784 ADC_REG_LOCK_EXIT();
785
786 sar_periph_ctrl_adc_oneshot_power_release();
787 periph_module_disable(PERIPH_SARADC_MODULE);
788 adc_lock_release(ADC_UNIT_1);
789
790 return raw_out;
791 }
792
793 #if (SOC_ADC_PERIPH_NUM >= 2)
adc2_config_channel_atten(adc2_channel_t channel,adc_atten_t atten)794 esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
795 {
796 ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 channel error");
797 ESP_RETURN_ON_FALSE((atten <= ADC_ATTEN_DB_12), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 Atten Err");
798
799 esp_err_t ret = ESP_OK;
800 s_atten2_single[channel] = atten;
801 ret = adc_digi_gpio_init(ADC_UNIT_2, BIT(channel));
802
803 return ret;
804 }
805
adc2_get_raw(adc2_channel_t channel,adc_bits_width_t width_bit,int * raw_out)806 esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out)
807 {
808 //On ESP32C3, the data width is always 12-bits.
809 if (width_bit != ADC_WIDTH_BIT_12) {
810 return ESP_ERR_INVALID_ARG;
811 }
812 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
813 if (!clk_src_freq_hz) {
814 //should never fail
815 esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
816 }
817 #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
818
819 esp_err_t ret = ESP_OK;
820
821 if (adc_lock_try_acquire(ADC_UNIT_2) != ESP_OK) {
822 return ESP_ERR_TIMEOUT;
823 }
824
825 periph_module_enable(PERIPH_SARADC_MODULE);
826 sar_periph_ctrl_adc_oneshot_power_acquire();
827 adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
828
829 adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
830 adc_hal_arbiter_config(&config);
831
832 adc_atten_t atten = s_atten2_single[channel];
833 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
834 adc_set_hw_calibration_code(ADC_UNIT_2, atten);
835 #endif
836
837 ADC_REG_LOCK_ENTER();
838 adc_oneshot_ll_set_atten(ADC_UNIT_2, channel, atten);
839 ret = adc_hal_convert(ADC_UNIT_2, channel, clk_src_freq_hz, raw_out);
840 ADC_REG_LOCK_EXIT();
841
842 sar_periph_ctrl_adc_oneshot_power_release();
843 periph_module_disable(PERIPH_SARADC_MODULE);
844 adc_lock_release(ADC_UNIT_2);
845
846 return ret;
847 }
848 #endif //#if (SOC_ADC_PERIPH_NUM >= 2)
849 #endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
850
851
adc_hal_onetime_start(adc_unit_t adc_n,uint32_t clk_src_freq_hz)852 static void adc_hal_onetime_start(adc_unit_t adc_n, uint32_t clk_src_freq_hz)
853 {
854 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
855 (void)adc_n;
856 /**
857 * There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the
858 * ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller
859 * clock cycle.
860 */
861 uint32_t digi_clk = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1);
862 //Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough.
863 uint32_t delay = (1000 * 1000) / digi_clk + 1;
864 //3 ADC digital controller clock cycle
865 delay = delay * 3;
866 //This coefficient (8) is got from test, and verified from DT. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
867 if (digi_clk >= APB_CLK_FREQ/8) {
868 delay = 0;
869 }
870
871 adc_oneshot_ll_start(false);
872 esp_rom_delay_us(delay);
873 adc_oneshot_ll_start(true);
874
875 //No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
876 #else
877 (void)clk_src_freq_hz;
878 adc_oneshot_ll_start(adc_n);
879 #endif
880 }
881
adc_hal_convert(adc_unit_t adc_n,int channel,uint32_t clk_src_freq_hz,int * out_raw)882 static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, uint32_t clk_src_freq_hz, int *out_raw)
883 {
884
885 uint32_t event = (adc_n == ADC_UNIT_1) ? ADC_LL_EVENT_ADC1_ONESHOT_DONE : ADC_LL_EVENT_ADC2_ONESHOT_DONE;
886 adc_oneshot_ll_clear_event(event);
887 adc_oneshot_ll_disable_all_unit();
888 adc_oneshot_ll_enable(adc_n);
889 adc_oneshot_ll_set_channel(adc_n, channel);
890
891 adc_hal_onetime_start(adc_n, clk_src_freq_hz);
892
893 while (adc_oneshot_ll_get_event(event) != true) {
894 ;
895 }
896
897 *out_raw = adc_oneshot_ll_get_raw_result(adc_n);
898 if (adc_oneshot_ll_raw_check_valid(adc_n, *out_raw) == false) {
899 return ESP_ERR_INVALID_STATE;
900 }
901
902 //HW workaround: when enabling periph clock, this should be false
903 adc_oneshot_ll_disable_all_unit();
904
905 return ESP_OK;
906 }
907
