1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_GPIO_STRUCT_H_ 15 #define _SOC_GPIO_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct gpio_dev_s { 24 uint32_t bt_select; /*NA*/ 25 uint32_t out; /*GPIO0~31 output value*/ 26 uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/ 27 uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ 28 union { 29 struct { 30 uint32_t data: 8; /*GPIO32~39 output value*/ 31 uint32_t reserved8: 24; 32 }; 33 uint32_t val; 34 } out1; 35 union { 36 struct { 37 uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/ 38 uint32_t reserved8: 24; 39 }; 40 uint32_t val; 41 } out1_w1ts; 42 union { 43 struct { 44 uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/ 45 uint32_t reserved8: 24; 46 }; 47 uint32_t val; 48 } out1_w1tc; 49 union { 50 struct { 51 uint32_t sel: 8; /*SDIO PADS on/off control from outside*/ 52 uint32_t reserved8: 24; 53 }; 54 uint32_t val; 55 } sdio_select; 56 uint32_t enable; /*GPIO0~31 output enable*/ 57 uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/ 58 uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ 59 union { 60 struct { 61 uint32_t data: 8; /*GPIO32~39 output enable*/ 62 uint32_t reserved8: 24; 63 }; 64 uint32_t val; 65 } enable1; 66 union { 67 struct { 68 uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/ 69 uint32_t reserved8: 24; 70 }; 71 uint32_t val; 72 } enable1_w1ts; 73 union { 74 struct { 75 uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/ 76 uint32_t reserved8: 24; 77 }; 78 uint32_t val; 79 } enable1_w1tc; 80 union { 81 struct { 82 uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]} . Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */ 83 uint32_t reserved16:16; 84 }; 85 uint32_t val; 86 } strap; 87 uint32_t in; /*GPIO0~31 input value*/ 88 union { 89 struct { 90 uint32_t data: 8; /*GPIO32~39 input value*/ 91 uint32_t reserved8: 24; 92 }; 93 uint32_t val; 94 } in1; 95 uint32_t status; /*GPIO0~31 interrupt status*/ 96 uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/ 97 uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ 98 union { 99 struct { 100 uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/ 101 uint32_t reserved8: 24; 102 }; 103 uint32_t val; 104 } status1; 105 union { 106 struct { 107 uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/ 108 uint32_t reserved8: 24; 109 }; 110 uint32_t val; 111 } status1_w1ts; 112 union { 113 struct { 114 uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/ 115 uint32_t reserved8: 24; 116 }; 117 uint32_t val; 118 } status1_w1tc; 119 uint32_t reserved_5c; 120 uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/ 121 uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/ 122 uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/ 123 uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/ 124 uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ 125 union { 126 struct { 127 uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/ 128 uint32_t reserved8: 24; 129 }; 130 uint32_t val; 131 } acpu_int1; 132 union { 133 struct { 134 uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ 135 uint32_t reserved8: 24; 136 }; 137 uint32_t val; 138 } acpu_nmi_int1; 139 union { 140 struct { 141 uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/ 142 uint32_t reserved8: 24; 143 }; 144 uint32_t val; 145 } pcpu_int1; 146 union { 147 struct { 148 uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ 149 uint32_t reserved8: 24; 150 }; 151 uint32_t val; 152 } pcpu_nmi_int1; 153 union { 154 struct { 155 uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/ 156 uint32_t reserved8: 24; 157 }; 158 uint32_t val; 159 } cpusdio_int1; 160 union { 161 struct { 162 uint32_t reserved0: 2; 163 uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ 164 uint32_t reserved3: 4; 165 uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 166 uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ 167 uint32_t config: 2; /*NA*/ 168 uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 169 uint32_t reserved18: 14; 170 }; 171 uint32_t val; 172 } pin[40]; 173 union { 174 struct { 175 uint32_t rtc_max: 10; 176 uint32_t reserved10: 21; 177 uint32_t start: 1; 178 }; 179 uint32_t val; 180 } cali_conf; 181 union { 182 struct { 183 uint32_t value_sync2: 20; 184 uint32_t reserved20: 10; 185 uint32_t rdy_real: 1; 186 uint32_t rdy_sync2: 1; 187 }; 188 uint32_t val; 189 } cali_data; 190 union { 191 struct { 192 uint32_t func_sel: 6; /*select one of the 256 inputs*/ 193 uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/ 194 uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ 195 uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ 196 }; 197 uint32_t val; 198 } func_in_sel_cfg[256]; 199 union { 200 struct { 201 uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/ 202 uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ 203 uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ 204 uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ 205 uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ 206 }; 207 uint32_t val; 208 } func_out_sel_cfg[40]; 209 } gpio_dev_t; 210 extern gpio_dev_t GPIO; 211 212 #ifdef __cplusplus 213 } 214 #endif 215 216 #endif /* _SOC_GPIO_STRUCT_H_ */ 217
