1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_ACCESSCTRL_H 9 #define _HARDWARE_STRUCTS_ACCESSCTRL_H 10 11 /** 12 * \file rp2350/accessctrl.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/accessctrl.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_accessctrl 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/accessctrl.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(ACCESSCTRL_LOCK_OFFSET) // ACCESSCTRL_LOCK 28 // Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master 29 // 0x00000008 [3] DEBUG (0) 30 // 0x00000004 [2] DMA (1) 31 // 0x00000002 [1] CORE1 (0) 32 // 0x00000001 [0] CORE0 (0) 33 io_rw_32 lock; 34 35 _REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) // ACCESSCTRL_FORCE_CORE_NS 36 // Force core 1's bus accesses to always be Non-secure, no matter the core's internal state 37 // 0x00000002 [1] CORE1 (0) 38 io_rw_32 force_core_ns; 39 40 _REG_(ACCESSCTRL_CFGRESET_OFFSET) // ACCESSCTRL_CFGRESET 41 // Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers 42 // 0x00000001 [0] CFGRESET (0) 43 io_wo_32 cfgreset; 44 45 // (Description copied from array index 0 register ACCESSCTRL_GPIO_NSMASK0 applies similarly to other array indexes) 46 _REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) // ACCESSCTRL_GPIO_NSMASK0 47 // Control whether GPIO0 48 // 0xffffffff [31:0] GPIO_NSMASK0 (0x00000000) 49 io_rw_32 gpio_nsmask[2]; 50 51 _REG_(ACCESSCTRL_ROM_OFFSET) // ACCESSCTRL_ROM 52 // Control access to ROM. Defaults to fully open access. 53 // 0x00000080 [7] DBG (1) If 1, ROM can be accessed by the debugger, at... 54 // 0x00000040 [6] DMA (1) If 1, ROM can be accessed by the DMA, at... 55 // 0x00000020 [5] CORE1 (1) If 1, ROM can be accessed by core 1, at... 56 // 0x00000010 [4] CORE0 (1) If 1, ROM can be accessed by core 0, at... 57 // 0x00000008 [3] SP (1) If 1, ROM can be accessed from a Secure, Privileged context 58 // 0x00000004 [2] SU (1) If 1, and SP is also set, ROM can be accessed from a... 59 // 0x00000002 [1] NSP (1) If 1, ROM can be accessed from a Non-secure, Privileged context 60 // 0x00000001 [0] NSU (1) If 1, and NSP is also set, ROM can be accessed from a... 61 io_rw_32 rom; 62 63 _REG_(ACCESSCTRL_XIP_MAIN_OFFSET) // ACCESSCTRL_XIP_MAIN 64 // Control access to XIP_MAIN. Defaults to fully open access. 65 // 0x00000080 [7] DBG (1) If 1, XIP_MAIN can be accessed by the debugger, at... 66 // 0x00000040 [6] DMA (1) If 1, XIP_MAIN can be accessed by the DMA, at... 67 // 0x00000020 [5] CORE1 (1) If 1, XIP_MAIN can be accessed by core 1, at... 68 // 0x00000010 [4] CORE0 (1) If 1, XIP_MAIN can be accessed by core 0, at... 69 // 0x00000008 [3] SP (1) If 1, XIP_MAIN can be accessed from a Secure, Privileged context 70 // 0x00000004 [2] SU (1) If 1, and SP is also set, XIP_MAIN can be accessed from... 71 // 0x00000002 [1] NSP (1) If 1, XIP_MAIN can be accessed from a Non-secure,... 72 // 0x00000001 [0] NSU (1) If 1, and NSP is also set, XIP_MAIN can be accessed from... 73 io_rw_32 xip_main; 74 75 // (Description copied from array index 0 register ACCESSCTRL_SRAM0 applies similarly to other array indexes) 76 _REG_(ACCESSCTRL_SRAM0_OFFSET) // ACCESSCTRL_SRAM0 77 // Control access to SRAM0. Defaults to fully open access. 78 // 0x00000080 [7] DBG (1) If 1, SRAM0 can be accessed by the debugger, at... 79 // 0x00000040 [6] DMA (1) If 1, SRAM0 can be accessed by the DMA, at... 80 // 0x00000020 [5] CORE1 (1) If 1, SRAM0 can be accessed by core 1, at... 81 // 0x00000010 [4] CORE0 (1) If 1, SRAM0 can be accessed by core 0, at... 82 // 0x00000008 [3] SP (1) If 1, SRAM0 can be accessed from a Secure, Privileged context 83 // 0x00000004 [2] SU (1) If 1, and SP is also set, SRAM0 can be accessed from a... 84 // 0x00000002 [1] NSP (1) If 1, SRAM0 can be accessed from a Non-secure, Privileged context 85 // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SRAM0 can be accessed from a... 86 io_rw_32 sram[10]; 87 88 _REG_(ACCESSCTRL_DMA_OFFSET) // ACCESSCTRL_DMA 89 // Control access to DMA. Defaults to Secure access from any master. 90 // 0x00000080 [7] DBG (1) If 1, DMA can be accessed by the debugger, at... 91 // 0x00000040 [6] DMA (1) If 1, DMA can be accessed by the DMA, at... 92 // 0x00000020 [5] CORE1 (1) If 1, DMA can be accessed by core 1, at... 93 // 0x00000010 [4] CORE0 (1) If 1, DMA can be accessed by core 0, at... 94 // 0x00000008 [3] SP (1) If 1, DMA can be accessed from a Secure, Privileged context 95 // 0x00000004 [2] SU (1) If 1, and SP is also set, DMA can be accessed from a... 96 // 0x00000002 [1] NSP (0) If 1, DMA can be accessed from a Non-secure, Privileged context 97 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, DMA can be accessed from a... 98 io_rw_32 dma; 99 100 _REG_(ACCESSCTRL_USBCTRL_OFFSET) // ACCESSCTRL_USBCTRL 101 // Control access to USBCTRL. Defaults to Secure access from any master. 102 // 0x00000080 [7] DBG (1) If 1, USBCTRL can be accessed by the debugger, at... 103 // 0x00000040 [6] DMA (1) If 1, USBCTRL can be accessed by the DMA, at... 104 // 0x00000020 [5] CORE1 (1) If 1, USBCTRL can be accessed by core 1, at... 105 // 0x00000010 [4] CORE0 (1) If 1, USBCTRL can be accessed by core 0, at... 106 // 0x00000008 [3] SP (1) If 1, USBCTRL can be accessed from a Secure, Privileged context 107 // 0x00000004 [2] SU (1) If 1, and SP is also set, USBCTRL can be accessed from a... 108 // 0x00000002 [1] NSP (0) If 1, USBCTRL can be accessed from a Non-secure,... 109 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, USBCTRL can be accessed from... 110 io_rw_32 usbctrl; 111 112 // (Description copied from array index 0 register ACCESSCTRL_PIO0 applies similarly to other array indexes) 113 _REG_(ACCESSCTRL_PIO0_OFFSET) // ACCESSCTRL_PIO0 114 // Control access to PIO0. Defaults to Secure access from any master. 115 // 0x00000080 [7] DBG (1) If 1, PIO0 can be accessed by the debugger, at... 116 // 0x00000040 [6] DMA (1) If 1, PIO0 can be accessed by the DMA, at... 117 // 0x00000020 [5] CORE1 (1) If 1, PIO0 can be accessed by core 1, at... 118 // 0x00000010 [4] CORE0 (1) If 1, PIO0 can be accessed by core 0, at... 119 // 0x00000008 [3] SP (1) If 1, PIO0 can be accessed from a Secure, Privileged context 120 // 0x00000004 [2] SU (1) If 1, and SP is also set, PIO0 can be accessed from a... 121 // 0x00000002 [1] NSP (0) If 1, PIO0 can be accessed from a Non-secure, Privileged context 122 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PIO0 can be accessed from a... 123 io_rw_32 pio[3]; 124 125 _REG_(ACCESSCTRL_CORESIGHT_TRACE_OFFSET) // ACCESSCTRL_CORESIGHT_TRACE 126 // Control access to CORESIGHT_TRACE. Defaults to Secure, Privileged processor or debug access only. 127 // 0x00000080 [7] DBG (1) If 1, CORESIGHT_TRACE can be accessed by the debugger,... 128 // 0x00000040 [6] DMA (0) If 1, CORESIGHT_TRACE can be accessed by the DMA, at... 129 // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_TRACE can be accessed by core 1, at... 130 // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_TRACE can be accessed by core 0, at... 131 // 0x00000008 [3] SP (1) If 1, CORESIGHT_TRACE can be accessed from a Secure,... 132 // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_TRACE can be... 133 // 0x00000002 [1] NSP (0) If 1, CORESIGHT_TRACE can be accessed from a Non-secure,... 134 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_TRACE can be... 135 io_rw_32 coresight_trace; 136 137 _REG_(ACCESSCTRL_CORESIGHT_PERIPH_OFFSET) // ACCESSCTRL_CORESIGHT_PERIPH 138 // Control access to CORESIGHT_PERIPH. Defaults to Secure, Privileged processor or debug access only. 139 // 0x00000080 [7] DBG (1) If 1, CORESIGHT_PERIPH can be accessed by the debugger,... 140 // 0x00000040 [6] DMA (0) If 1, CORESIGHT_PERIPH can be accessed by the DMA, at... 141 // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_PERIPH can be accessed by core 1, at... 142 // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_PERIPH can be accessed by core 0, at... 143 // 0x00000008 [3] SP (1) If 1, CORESIGHT_PERIPH can be accessed from a Secure,... 144 // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_PERIPH can be... 145 // 0x00000002 [1] NSP (0) If 1, CORESIGHT_PERIPH can be accessed from a... 146 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_PERIPH can be... 147 io_rw_32 coresight_periph; 148 149 _REG_(ACCESSCTRL_SYSINFO_OFFSET) // ACCESSCTRL_SYSINFO 150 // Control access to SYSINFO. Defaults to fully open access. 151 // 0x00000080 [7] DBG (1) If 1, SYSINFO can be accessed by the debugger, at... 152 // 0x00000040 [6] DMA (1) If 1, SYSINFO can be accessed by the DMA, at... 153 // 0x00000020 [5] CORE1 (1) If 1, SYSINFO can be accessed by core 1, at... 154 // 0x00000010 [4] CORE0 (1) If 1, SYSINFO can be accessed by core 0, at... 155 // 0x00000008 [3] SP (1) If 1, SYSINFO can be accessed from a Secure, Privileged context 156 // 0x00000004 [2] SU (1) If 1, and SP is also set, SYSINFO can be accessed from a... 157 // 0x00000002 [1] NSP (1) If 1, SYSINFO can be accessed from a Non-secure,... 158 // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SYSINFO can be accessed from... 159 io_rw_32 sysinfo; 160 161 _REG_(ACCESSCTRL_RESETS_OFFSET) // ACCESSCTRL_RESETS 162 // Control access to RESETS. Defaults to Secure access from any master. 163 // 0x00000080 [7] DBG (1) If 1, RESETS can be accessed by the debugger, at... 164 // 0x00000040 [6] DMA (1) If 1, RESETS can be accessed by the DMA, at... 165 // 0x00000020 [5] CORE1 (1) If 1, RESETS can be accessed by core 1, at... 166 // 0x00000010 [4] CORE0 (1) If 1, RESETS can be accessed by core 0, at... 167 // 0x00000008 [3] SP (1) If 1, RESETS can be accessed from a Secure, Privileged context 168 // 0x00000004 [2] SU (1) If 1, and SP is also set, RESETS can be accessed from a... 169 // 0x00000002 [1] NSP (0) If 1, RESETS can be accessed from a Non-secure,... 170 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RESETS can be accessed from a... 171 io_rw_32 resets; 172 173 // (Description copied from array index 0 register ACCESSCTRL_IO_BANK0 applies similarly to other array indexes) 174 _REG_(ACCESSCTRL_IO_BANK0_OFFSET) // ACCESSCTRL_IO_BANK0 175 // Control access to IO_BANK0. Defaults to Secure access from any master. 176 // 0x00000080 [7] DBG (1) If 1, IO_BANK0 can be accessed by the debugger, at... 177 // 0x00000040 [6] DMA (1) If 1, IO_BANK0 can be accessed by the DMA, at... 178 // 0x00000020 [5] CORE1 (1) If 1, IO_BANK0 can be accessed by core 1, at... 179 // 0x00000010 [4] CORE0 (1) If 1, IO_BANK0 can be accessed by core 0, at... 180 // 0x00000008 [3] SP (1) If 1, IO_BANK0 can be accessed from a Secure, Privileged context 181 // 0x00000004 [2] SU (1) If 1, and SP is also set, IO_BANK0 can be accessed from... 182 // 0x00000002 [1] NSP (0) If 1, IO_BANK0 can be accessed from a Non-secure,... 183 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, IO_BANK0 can be accessed from... 184 io_rw_32 io_bank[2]; 185 186 _REG_(ACCESSCTRL_PADS_BANK0_OFFSET) // ACCESSCTRL_PADS_BANK0 187 // Control access to PADS_BANK0. Defaults to Secure access from any master. 188 // 0x00000080 [7] DBG (1) If 1, PADS_BANK0 can be accessed by the debugger, at... 189 // 0x00000040 [6] DMA (1) If 1, PADS_BANK0 can be accessed by the DMA, at... 190 // 0x00000020 [5] CORE1 (1) If 1, PADS_BANK0 can be accessed by core 1, at... 191 // 0x00000010 [4] CORE0 (1) If 1, PADS_BANK0 can be accessed by core 0, at... 192 // 0x00000008 [3] SP (1) If 1, PADS_BANK0 can be accessed from a Secure,... 193 // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_BANK0 can be accessed... 194 // 0x00000002 [1] NSP (0) If 1, PADS_BANK0 can be accessed from a Non-secure,... 195 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_BANK0 can be accessed... 196 io_rw_32 pads_bank0; 197 198 _REG_(ACCESSCTRL_PADS_QSPI_OFFSET) // ACCESSCTRL_PADS_QSPI 199 // Control access to PADS_QSPI. Defaults to Secure access from any master. 200 // 0x00000080 [7] DBG (1) If 1, PADS_QSPI can be accessed by the debugger, at... 201 // 0x00000040 [6] DMA (1) If 1, PADS_QSPI can be accessed by the DMA, at... 202 // 0x00000020 [5] CORE1 (1) If 1, PADS_QSPI can be accessed by core 1, at... 203 // 0x00000010 [4] CORE0 (1) If 1, PADS_QSPI can be accessed by core 0, at... 204 // 0x00000008 [3] SP (1) If 1, PADS_QSPI can be accessed from a Secure, Privileged context 205 // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_QSPI can be accessed from... 206 // 0x00000002 [1] NSP (0) If 1, PADS_QSPI can be accessed from a Non-secure,... 207 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_QSPI can be accessed... 208 io_rw_32 pads_qspi; 209 210 _REG_(ACCESSCTRL_BUSCTRL_OFFSET) // ACCESSCTRL_BUSCTRL 211 // Control access to BUSCTRL. Defaults to Secure access from any master. 212 // 0x00000080 [7] DBG (1) If 1, BUSCTRL can be accessed by the debugger, at... 213 // 0x00000040 [6] DMA (1) If 1, BUSCTRL can be accessed by the DMA, at... 214 // 0x00000020 [5] CORE1 (1) If 1, BUSCTRL can be accessed by core 1, at... 215 // 0x00000010 [4] CORE0 (1) If 1, BUSCTRL can be accessed by core 0, at... 216 // 0x00000008 [3] SP (1) If 1, BUSCTRL can be accessed from a Secure, Privileged context 217 // 0x00000004 [2] SU (1) If 1, and SP is also set, BUSCTRL can be accessed from a... 218 // 0x00000002 [1] NSP (0) If 1, BUSCTRL can be accessed from a Non-secure,... 219 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, BUSCTRL can be accessed from... 220 io_rw_32 busctrl; 221 222 _REG_(ACCESSCTRL_ADC0_OFFSET) // ACCESSCTRL_ADC0 223 // Control access to ADC0. Defaults to Secure access from any master. 224 // 0x00000080 [7] DBG (1) If 1, ADC0 can be accessed by the debugger, at... 225 // 0x00000040 [6] DMA (1) If 1, ADC0 can be accessed by the DMA, at... 226 // 0x00000020 [5] CORE1 (1) If 1, ADC0 can be accessed by core 1, at... 227 // 0x00000010 [4] CORE0 (1) If 1, ADC0 can be accessed by core 0, at... 228 // 0x00000008 [3] SP (1) If 1, ADC0 can be accessed from a Secure, Privileged context 229 // 0x00000004 [2] SU (1) If 1, and SP is also set, ADC0 can be accessed from a... 230 // 0x00000002 [1] NSP (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context 231 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC0 can be accessed from a... 232 io_rw_32 adc0; 233 234 _REG_(ACCESSCTRL_HSTX_OFFSET) // ACCESSCTRL_HSTX 235 // Control access to HSTX. Defaults to Secure access from any master. 236 // 0x00000080 [7] DBG (1) If 1, HSTX can be accessed by the debugger, at... 237 // 0x00000040 [6] DMA (1) If 1, HSTX can be accessed by the DMA, at... 238 // 0x00000020 [5] CORE1 (1) If 1, HSTX can be accessed by core 1, at... 239 // 0x00000010 [4] CORE0 (1) If 1, HSTX can be accessed by core 0, at... 240 // 0x00000008 [3] SP (1) If 1, HSTX can be accessed from a Secure, Privileged context 241 // 0x00000004 [2] SU (1) If 1, and SP is also set, HSTX can be accessed from a... 242 // 0x00000002 [1] NSP (0) If 1, HSTX can be accessed from a Non-secure, Privileged context 243 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, HSTX can be accessed from a... 244 io_rw_32 hstx; 245 246 // (Description copied from array index 0 register ACCESSCTRL_I2C0 applies similarly to other array indexes) 247 _REG_(ACCESSCTRL_I2C0_OFFSET) // ACCESSCTRL_I2C0 248 // Control access to I2C0. Defaults to Secure access from any master. 249 // 0x00000080 [7] DBG (1) If 1, I2C0 can be accessed by the debugger, at... 250 // 0x00000040 [6] DMA (1) If 1, I2C0 can be accessed by the DMA, at... 251 // 0x00000020 [5] CORE1 (1) If 1, I2C0 can be accessed by core 1, at... 252 // 0x00000010 [4] CORE0 (1) If 1, I2C0 can be accessed by core 0, at... 253 // 0x00000008 [3] SP (1) If 1, I2C0 can be accessed from a Secure, Privileged context 254 // 0x00000004 [2] SU (1) If 1, and SP is also set, I2C0 can be accessed from a... 255 // 0x00000002 [1] NSP (0) If 1, I2C0 can be accessed from a Non-secure, Privileged context 256 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, I2C0 can be accessed from a... 257 io_rw_32 i2c[2]; 258 259 _REG_(ACCESSCTRL_PWM_OFFSET) // ACCESSCTRL_PWM 260 // Control access to PWM. Defaults to Secure access from any master. 261 // 0x00000080 [7] DBG (1) If 1, PWM can be accessed by the debugger, at... 262 // 0x00000040 [6] DMA (1) If 1, PWM can be accessed by the DMA, at... 263 // 0x00000020 [5] CORE1 (1) If 1, PWM can be accessed by core 1, at... 264 // 0x00000010 [4] CORE0 (1) If 1, PWM can be accessed by core 0, at... 265 // 0x00000008 [3] SP (1) If 1, PWM can be accessed from a Secure, Privileged context 266 // 0x00000004 [2] SU (1) If 1, and SP is also set, PWM can be accessed from a... 267 // 0x00000002 [1] NSP (0) If 1, PWM can be accessed from a Non-secure, Privileged context 268 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PWM can be accessed from a... 269 io_rw_32 pwm; 270 271 // (Description copied from array index 0 register ACCESSCTRL_SPI0 applies similarly to other array indexes) 272 _REG_(ACCESSCTRL_SPI0_OFFSET) // ACCESSCTRL_SPI0 273 // Control access to SPI0. Defaults to Secure access from any master. 274 // 0x00000080 [7] DBG (1) If 1, SPI0 can be accessed by the debugger, at... 275 // 0x00000040 [6] DMA (1) If 1, SPI0 can be accessed by the DMA, at... 276 // 0x00000020 [5] CORE1 (1) If 1, SPI0 can be accessed by core 1, at... 277 // 0x00000010 [4] CORE0 (1) If 1, SPI0 can be accessed by core 0, at... 278 // 0x00000008 [3] SP (1) If 1, SPI0 can be accessed from a Secure, Privileged context 279 // 0x00000004 [2] SU (1) If 1, and SP is also set, SPI0 can be accessed from a... 280 // 0x00000002 [1] NSP (0) If 1, SPI0 can be accessed from a Non-secure, Privileged context 281 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SPI0 can be accessed from a... 282 io_rw_32 spi[2]; 283 284 // (Description copied from array index 0 register ACCESSCTRL_TIMER0 applies similarly to other array indexes) 285 _REG_(ACCESSCTRL_TIMER0_OFFSET) // ACCESSCTRL_TIMER0 286 // Control access to TIMER0. Defaults to Secure access from any master. 287 // 0x00000080 [7] DBG (1) If 1, TIMER0 can be accessed by the debugger, at... 288 // 0x00000040 [6] DMA (1) If 1, TIMER0 can be accessed by the DMA, at... 289 // 0x00000020 [5] CORE1 (1) If 1, TIMER0 can be accessed by core 1, at... 290 // 0x00000010 [4] CORE0 (1) If 1, TIMER0 can be accessed by core 0, at... 291 // 0x00000008 [3] SP (1) If 1, TIMER0 can be accessed from a Secure, Privileged context 292 // 0x00000004 [2] SU (1) If 1, and SP is also set, TIMER0 can be accessed from a... 293 // 0x00000002 [1] NSP (0) If 1, TIMER0 can be accessed from a Non-secure,... 294 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TIMER0 can be accessed from a... 295 io_rw_32 timer[2]; 296 297 // (Description copied from array index 0 register ACCESSCTRL_UART0 applies similarly to other array indexes) 298 _REG_(ACCESSCTRL_UART0_OFFSET) // ACCESSCTRL_UART0 299 // Control access to UART0. Defaults to Secure access from any master. 300 // 0x00000080 [7] DBG (1) If 1, UART0 can be accessed by the debugger, at... 301 // 0x00000040 [6] DMA (1) If 1, UART0 can be accessed by the DMA, at... 302 // 0x00000020 [5] CORE1 (1) If 1, UART0 can be accessed by core 1, at... 303 // 0x00000010 [4] CORE0 (1) If 1, UART0 can be accessed by core 0, at... 304 // 0x00000008 [3] SP (1) If 1, UART0 can be accessed from a Secure, Privileged context 305 // 0x00000004 [2] SU (1) If 1, and SP is also set, UART0 can be accessed from a... 306 // 0x00000002 [1] NSP (0) If 1, UART0 can be accessed from a Non-secure, Privileged context 307 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, UART0 can be accessed from a... 308 io_rw_32 uart[2]; 309 310 _REG_(ACCESSCTRL_OTP_OFFSET) // ACCESSCTRL_OTP 311 // Control access to OTP. Defaults to Secure access from any master. 312 // 0x00000080 [7] DBG (1) If 1, OTP can be accessed by the debugger, at... 313 // 0x00000040 [6] DMA (1) If 1, OTP can be accessed by the DMA, at... 314 // 0x00000020 [5] CORE1 (1) If 1, OTP can be accessed by core 1, at... 315 // 0x00000010 [4] CORE0 (1) If 1, OTP can be accessed by core 0, at... 316 // 0x00000008 [3] SP (1) If 1, OTP can be accessed from a Secure, Privileged context 317 // 0x00000004 [2] SU (1) If 1, and SP is also set, OTP can be accessed from a... 318 // 0x00000002 [1] NSP (0) If 1, OTP can be accessed from a Non-secure, Privileged context 319 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, OTP can be accessed from a... 320 io_rw_32 otp; 321 322 _REG_(ACCESSCTRL_TBMAN_OFFSET) // ACCESSCTRL_TBMAN 323 // Control access to TBMAN. Defaults to Secure access from any master. 324 // 0x00000080 [7] DBG (1) If 1, TBMAN can be accessed by the debugger, at... 325 // 0x00000040 [6] DMA (1) If 1, TBMAN can be accessed by the DMA, at... 326 // 0x00000020 [5] CORE1 (1) If 1, TBMAN can be accessed by core 1, at... 327 // 0x00000010 [4] CORE0 (1) If 1, TBMAN can be accessed by core 0, at... 328 // 0x00000008 [3] SP (1) If 1, TBMAN can be accessed from a Secure, Privileged context 329 // 0x00000004 [2] SU (1) If 1, and SP is also set, TBMAN can be accessed from a... 330 // 0x00000002 [1] NSP (0) If 1, TBMAN can be accessed from a Non-secure, Privileged context 331 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TBMAN can be accessed from a... 332 io_rw_32 tbman; 333 334 _REG_(ACCESSCTRL_POWMAN_OFFSET) // ACCESSCTRL_POWMAN 335 // Control access to POWMAN. Defaults to Secure, Privileged processor or debug access only. 336 // 0x00000080 [7] DBG (1) If 1, POWMAN can be accessed by the debugger, at... 337 // 0x00000040 [6] DMA (0) If 1, POWMAN can be accessed by the DMA, at... 338 // 0x00000020 [5] CORE1 (1) If 1, POWMAN can be accessed by core 1, at... 339 // 0x00000010 [4] CORE0 (1) If 1, POWMAN can be accessed by core 0, at... 340 // 0x00000008 [3] SP (1) If 1, POWMAN can be accessed from a Secure, Privileged context 341 // 0x00000004 [2] SU (0) If 1, and SP is also set, POWMAN can be accessed from a... 342 // 0x00000002 [1] NSP (0) If 1, POWMAN can be accessed from a Non-secure,... 343 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, POWMAN can be accessed from a... 344 io_rw_32 powman; 345 346 _REG_(ACCESSCTRL_TRNG_OFFSET) // ACCESSCTRL_TRNG 347 // Control access to TRNG. Defaults to Secure, Privileged processor or debug access only. 348 // 0x00000080 [7] DBG (1) If 1, TRNG can be accessed by the debugger, at... 349 // 0x00000040 [6] DMA (0) If 1, TRNG can be accessed by the DMA, at... 350 // 0x00000020 [5] CORE1 (1) If 1, TRNG can be accessed by core 1, at... 351 // 0x00000010 [4] CORE0 (1) If 1, TRNG can be accessed by core 0, at... 352 // 0x00000008 [3] SP (1) If 1, TRNG can be accessed from a Secure, Privileged context 353 // 0x00000004 [2] SU (0) If 1, and SP is also set, TRNG can be accessed from a... 354 // 0x00000002 [1] NSP (0) If 1, TRNG can be accessed from a Non-secure, Privileged context 355 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TRNG can be accessed from a... 356 io_rw_32 trng; 357 358 _REG_(ACCESSCTRL_SHA256_OFFSET) // ACCESSCTRL_SHA256 359 // Control access to SHA256. Defaults to Secure, Privileged access only. 360 // 0x00000080 [7] DBG (1) If 1, SHA256 can be accessed by the debugger, at... 361 // 0x00000040 [6] DMA (1) If 1, SHA256 can be accessed by the DMA, at... 362 // 0x00000020 [5] CORE1 (1) If 1, SHA256 can be accessed by core 1, at... 363 // 0x00000010 [4] CORE0 (1) If 1, SHA256 can be accessed by core 0, at... 364 // 0x00000008 [3] SP (1) If 1, SHA256 can be accessed from a Secure, Privileged context 365 // 0x00000004 [2] SU (0) If 1, and SP is also set, SHA256 can be accessed from a... 366 // 0x00000002 [1] NSP (0) If 1, SHA256 can be accessed from a Non-secure,... 367 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SHA256 can be accessed from a... 368 io_rw_32 sha256; 369 370 _REG_(ACCESSCTRL_SYSCFG_OFFSET) // ACCESSCTRL_SYSCFG 371 // Control access to SYSCFG. Defaults to Secure, Privileged processor or debug access only. 372 // 0x00000080 [7] DBG (1) If 1, SYSCFG can be accessed by the debugger, at... 373 // 0x00000040 [6] DMA (0) If 1, SYSCFG can be accessed by the DMA, at... 374 // 0x00000020 [5] CORE1 (1) If 1, SYSCFG can be accessed by core 1, at... 375 // 0x00000010 [4] CORE0 (1) If 1, SYSCFG can be accessed by core 0, at... 376 // 0x00000008 [3] SP (1) If 1, SYSCFG can be accessed from a Secure, Privileged context 377 // 0x00000004 [2] SU (0) If 1, and SP is also set, SYSCFG can be accessed from a... 378 // 0x00000002 [1] NSP (0) If 1, SYSCFG can be accessed from a Non-secure,... 379 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SYSCFG can be accessed from a... 380 io_rw_32 syscfg; 381 382 _REG_(ACCESSCTRL_CLOCKS_OFFSET) // ACCESSCTRL_CLOCKS 383 // Control access to CLOCKS. Defaults to Secure, Privileged processor or debug access only. 384 // 0x00000080 [7] DBG (1) If 1, CLOCKS can be accessed by the debugger, at... 385 // 0x00000040 [6] DMA (0) If 1, CLOCKS can be accessed by the DMA, at... 386 // 0x00000020 [5] CORE1 (1) If 1, CLOCKS can be accessed by core 1, at... 387 // 0x00000010 [4] CORE0 (1) If 1, CLOCKS can be accessed by core 0, at... 388 // 0x00000008 [3] SP (1) If 1, CLOCKS can be accessed from a Secure, Privileged context 389 // 0x00000004 [2] SU (0) If 1, and SP is also set, CLOCKS can be accessed from a... 390 // 0x00000002 [1] NSP (0) If 1, CLOCKS can be accessed from a Non-secure,... 391 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CLOCKS can be accessed from a... 392 io_rw_32 clocks; 393 394 _REG_(ACCESSCTRL_XOSC_OFFSET) // ACCESSCTRL_XOSC 395 // Control access to XOSC. Defaults to Secure, Privileged processor or debug access only. 396 // 0x00000080 [7] DBG (1) If 1, XOSC can be accessed by the debugger, at... 397 // 0x00000040 [6] DMA (0) If 1, XOSC can be accessed by the DMA, at... 398 // 0x00000020 [5] CORE1 (1) If 1, XOSC can be accessed by core 1, at... 399 // 0x00000010 [4] CORE0 (1) If 1, XOSC can be accessed by core 0, at... 400 // 0x00000008 [3] SP (1) If 1, XOSC can be accessed from a Secure, Privileged context 401 // 0x00000004 [2] SU (0) If 1, and SP is also set, XOSC can be accessed from a... 402 // 0x00000002 [1] NSP (0) If 1, XOSC can be accessed from a Non-secure, Privileged context 403 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XOSC can be accessed from a... 404 io_rw_32 xosc; 405 406 _REG_(ACCESSCTRL_ROSC_OFFSET) // ACCESSCTRL_ROSC 407 // Control access to ROSC. Defaults to Secure, Privileged processor or debug access only. 408 // 0x00000080 [7] DBG (1) If 1, ROSC can be accessed by the debugger, at... 409 // 0x00000040 [6] DMA (0) If 1, ROSC can be accessed by the DMA, at... 410 // 0x00000020 [5] CORE1 (1) If 1, ROSC can be accessed by core 1, at... 411 // 0x00000010 [4] CORE0 (1) If 1, ROSC can be accessed by core 0, at... 412 // 0x00000008 [3] SP (1) If 1, ROSC can be accessed from a Secure, Privileged context 413 // 0x00000004 [2] SU (0) If 1, and SP is also set, ROSC can be accessed from a... 414 // 0x00000002 [1] NSP (0) If 1, ROSC can be accessed from a Non-secure, Privileged context 415 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ROSC can be accessed from a... 416 io_rw_32 rosc; 417 418 _REG_(ACCESSCTRL_PLL_SYS_OFFSET) // ACCESSCTRL_PLL_SYS 419 // Control access to PLL_SYS. Defaults to Secure, Privileged processor or debug access only. 420 // 0x00000080 [7] DBG (1) If 1, PLL_SYS can be accessed by the debugger, at... 421 // 0x00000040 [6] DMA (0) If 1, PLL_SYS can be accessed by the DMA, at... 422 // 0x00000020 [5] CORE1 (1) If 1, PLL_SYS can be accessed by core 1, at... 423 // 0x00000010 [4] CORE0 (1) If 1, PLL_SYS can be accessed by core 0, at... 424 // 0x00000008 [3] SP (1) If 1, PLL_SYS can be accessed from a Secure, Privileged context 425 // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_SYS can be accessed from a... 426 // 0x00000002 [1] NSP (0) If 1, PLL_SYS can be accessed from a Non-secure,... 427 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_SYS can be accessed from... 428 io_rw_32 pll_sys; 429 430 _REG_(ACCESSCTRL_PLL_USB_OFFSET) // ACCESSCTRL_PLL_USB 431 // Control access to PLL_USB. Defaults to Secure, Privileged processor or debug access only. 432 // 0x00000080 [7] DBG (1) If 1, PLL_USB can be accessed by the debugger, at... 433 // 0x00000040 [6] DMA (0) If 1, PLL_USB can be accessed by the DMA, at... 434 // 0x00000020 [5] CORE1 (1) If 1, PLL_USB can be accessed by core 1, at... 435 // 0x00000010 [4] CORE0 (1) If 1, PLL_USB can be accessed by core 0, at... 436 // 0x00000008 [3] SP (1) If 1, PLL_USB can be accessed from a Secure, Privileged context 437 // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_USB can be accessed from a... 438 // 0x00000002 [1] NSP (0) If 1, PLL_USB can be accessed from a Non-secure,... 439 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_USB can be accessed from... 440 io_rw_32 pll_usb; 441 442 _REG_(ACCESSCTRL_TICKS_OFFSET) // ACCESSCTRL_TICKS 443 // Control access to TICKS. Defaults to Secure, Privileged processor or debug access only. 444 // 0x00000080 [7] DBG (1) If 1, TICKS can be accessed by the debugger, at... 445 // 0x00000040 [6] DMA (0) If 1, TICKS can be accessed by the DMA, at... 446 // 0x00000020 [5] CORE1 (1) If 1, TICKS can be accessed by core 1, at... 447 // 0x00000010 [4] CORE0 (1) If 1, TICKS can be accessed by core 0, at... 448 // 0x00000008 [3] SP (1) If 1, TICKS can be accessed from a Secure, Privileged context 449 // 0x00000004 [2] SU (0) If 1, and SP is also set, TICKS can be accessed from a... 450 // 0x00000002 [1] NSP (0) If 1, TICKS can be accessed from a Non-secure, Privileged context 451 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TICKS can be accessed from a... 452 io_rw_32 ticks; 453 454 _REG_(ACCESSCTRL_WATCHDOG_OFFSET) // ACCESSCTRL_WATCHDOG 455 // Control access to WATCHDOG. Defaults to Secure, Privileged processor or debug access only. 456 // 0x00000080 [7] DBG (1) If 1, WATCHDOG can be accessed by the debugger, at... 457 // 0x00000040 [6] DMA (0) If 1, WATCHDOG can be accessed by the DMA, at... 458 // 0x00000020 [5] CORE1 (1) If 1, WATCHDOG can be accessed by core 1, at... 459 // 0x00000010 [4] CORE0 (1) If 1, WATCHDOG can be accessed by core 0, at... 460 // 0x00000008 [3] SP (1) If 1, WATCHDOG can be accessed from a Secure, Privileged context 461 // 0x00000004 [2] SU (0) If 1, and SP is also set, WATCHDOG can be accessed from... 462 // 0x00000002 [1] NSP (0) If 1, WATCHDOG can be accessed from a Non-secure,... 463 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, WATCHDOG can be accessed from... 464 io_rw_32 watchdog; 465 466 _REG_(ACCESSCTRL_RSM_OFFSET) // ACCESSCTRL_RSM 467 // Control access to RSM. Defaults to Secure, Privileged processor or debug access only. 468 // 0x00000080 [7] DBG (1) If 1, RSM can be accessed by the debugger, at... 469 // 0x00000040 [6] DMA (0) If 1, RSM can be accessed by the DMA, at... 470 // 0x00000020 [5] CORE1 (1) If 1, RSM can be accessed by core 1, at... 471 // 0x00000010 [4] CORE0 (1) If 1, RSM can be accessed by core 0, at... 472 // 0x00000008 [3] SP (1) If 1, RSM can be accessed from a Secure, Privileged context 473 // 0x00000004 [2] SU (0) If 1, and SP is also set, RSM can be accessed from a... 474 // 0x00000002 [1] NSP (0) If 1, RSM can be accessed from a Non-secure, Privileged context 475 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RSM can be accessed from a... 476 io_rw_32 rsm; 477 478 _REG_(ACCESSCTRL_XIP_CTRL_OFFSET) // ACCESSCTRL_XIP_CTRL 479 // Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only. 480 // 0x00000080 [7] DBG (1) If 1, XIP_CTRL can be accessed by the debugger, at... 481 // 0x00000040 [6] DMA (0) If 1, XIP_CTRL can be accessed by the DMA, at... 482 // 0x00000020 [5] CORE1 (1) If 1, XIP_CTRL can be accessed by core 1, at... 483 // 0x00000010 [4] CORE0 (1) If 1, XIP_CTRL can be accessed by core 0, at... 484 // 0x00000008 [3] SP (1) If 1, XIP_CTRL can be accessed from a Secure, Privileged context 485 // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_CTRL can be accessed from... 486 // 0x00000002 [1] NSP (0) If 1, XIP_CTRL can be accessed from a Non-secure,... 487 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_CTRL can be accessed from... 488 io_rw_32 xip_ctrl; 489 490 _REG_(ACCESSCTRL_XIP_QMI_OFFSET) // ACCESSCTRL_XIP_QMI 491 // Control access to XIP_QMI. Defaults to Secure, Privileged processor or debug access only. 492 // 0x00000080 [7] DBG (1) If 1, XIP_QMI can be accessed by the debugger, at... 493 // 0x00000040 [6] DMA (0) If 1, XIP_QMI can be accessed by the DMA, at... 494 // 0x00000020 [5] CORE1 (1) If 1, XIP_QMI can be accessed by core 1, at... 495 // 0x00000010 [4] CORE0 (1) If 1, XIP_QMI can be accessed by core 0, at... 496 // 0x00000008 [3] SP (1) If 1, XIP_QMI can be accessed from a Secure, Privileged context 497 // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_QMI can be accessed from a... 498 // 0x00000002 [1] NSP (0) If 1, XIP_QMI can be accessed from a Non-secure,... 499 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_QMI can be accessed from... 500 io_rw_32 xip_qmi; 501 502 _REG_(ACCESSCTRL_XIP_AUX_OFFSET) // ACCESSCTRL_XIP_AUX 503 // Control access to XIP_AUX. Defaults to Secure, Privileged access only. 504 // 0x00000080 [7] DBG (1) If 1, XIP_AUX can be accessed by the debugger, at... 505 // 0x00000040 [6] DMA (1) If 1, XIP_AUX can be accessed by the DMA, at... 506 // 0x00000020 [5] CORE1 (1) If 1, XIP_AUX can be accessed by core 1, at... 507 // 0x00000010 [4] CORE0 (1) If 1, XIP_AUX can be accessed by core 0, at... 508 // 0x00000008 [3] SP (1) If 1, XIP_AUX can be accessed from a Secure, Privileged context 509 // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_AUX can be accessed from a... 510 // 0x00000002 [1] NSP (0) If 1, XIP_AUX can be accessed from a Non-secure,... 511 // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_AUX can be accessed from... 512 io_rw_32 xip_aux; 513 } accessctrl_hw_t; 514 515 #define accessctrl_hw ((accessctrl_hw_t *)ACCESSCTRL_BASE) 516 static_assert(sizeof (accessctrl_hw_t) == 0x00ec, ""); 517 518 #endif // _HARDWARE_STRUCTS_ACCESSCTRL_H 519 520
