1 /**
2 ******************************************************************************
3 * @file a3g4250d_reg.c
4 * @author Sensors Software Solution Team
5 * @brief A3G4250D driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "a3g4250d_reg.h"
21
22 /**
23 * @defgroup A3G4250D
24 * @brief This file provides a set of functions needed to drive the
25 * a3g4250d enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup A3G4250D_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
a3g4250d_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak a3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
a3g4250d_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak a3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup A3G4250D_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
a3g4250d_from_fs245dps_to_mdps(int16_t lsb)97 float_t a3g4250d_from_fs245dps_to_mdps(int16_t lsb)
98 {
99 return ((float_t)lsb * 8.75f);
100 }
101
a3g4250d_from_lsb_to_celsius(int16_t lsb)102 float_t a3g4250d_from_lsb_to_celsius(int16_t lsb)
103 {
104 return ((float_t)lsb + 25.0f);
105 }
106
107 /**
108 * @}
109 *
110 */
111
112 /**
113 * @defgroup A3G4250D_data_generation
114 * @brief This section groups all the functions concerning
115 * data generation
116 * @{
117 *
118 */
119
120 /**
121 * @brief Accelerometer data rate selection.[set]
122 *
123 * @param ctx Read / write interface definitions.(ptr)
124 * @param val Change the values of dr in reg CTRL_REG1
125 * @retval Interface status (MANDATORY: return 0 -> no Error).
126 *
127 */
a3g4250d_data_rate_set(const stmdev_ctx_t * ctx,a3g4250d_dr_t val)128 int32_t a3g4250d_data_rate_set(const stmdev_ctx_t *ctx, a3g4250d_dr_t val)
129 {
130 a3g4250d_ctrl_reg1_t ctrl_reg1;
131 int32_t ret;
132
133 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
134 (uint8_t *)&ctrl_reg1, 1);
135
136 if (ret == 0)
137 {
138 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
139 ctrl_reg1.pd = ((uint8_t)val & 0x0FU);
140 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG1,
141 (uint8_t *)&ctrl_reg1, 1);
142 }
143
144 return ret;
145 }
146
147 /**
148 * @brief Accelerometer data rate selection.[get]
149 *
150 * @param ctx Read / write interface definitions.(ptr)
151 * @param val Get the values of dr in reg CTRL_REG1.(ptr)
152 * @retval Interface status (MANDATORY: return 0 -> no Error).
153 *
154 */
a3g4250d_data_rate_get(const stmdev_ctx_t * ctx,a3g4250d_dr_t * val)155 int32_t a3g4250d_data_rate_get(const stmdev_ctx_t *ctx, a3g4250d_dr_t *val)
156 {
157 a3g4250d_ctrl_reg1_t ctrl_reg1;
158 int32_t ret;
159
160 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
161 (uint8_t *)&ctrl_reg1, 1);
162
163 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd)
164 {
165 case A3G4250D_ODR_OFF:
166 *val = A3G4250D_ODR_OFF;
167 break;
168
169 case A3G4250D_ODR_SLEEP:
170 *val = A3G4250D_ODR_SLEEP;
171 break;
172
173 case A3G4250D_ODR_100Hz:
174 *val = A3G4250D_ODR_100Hz;
175 break;
176
177 case A3G4250D_ODR_200Hz:
178 *val = A3G4250D_ODR_200Hz;
179 break;
180
181 case A3G4250D_ODR_400Hz:
182 *val = A3G4250D_ODR_400Hz;
183 break;
184
185 case A3G4250D_ODR_800Hz:
186 *val = A3G4250D_ODR_800Hz;
187 break;
188
189 default:
190 *val = A3G4250D_ODR_OFF;
191 break;
192 }
193
194 return ret;
195 }
196
197 /**
198 * @brief The STATUS_REG register is read by the primary interface.[get]
199 *
200 * @param ctx Read / write interface definitions.(ptr)
201 * @param val registers STATUS_REG
202 * @retval Interface status (MANDATORY: return 0 -> no Error).
203 *
204 */
a3g4250d_status_reg_get(const stmdev_ctx_t * ctx,a3g4250d_status_reg_t * val)205 int32_t a3g4250d_status_reg_get(const stmdev_ctx_t *ctx, a3g4250d_status_reg_t *val)
206 {
207 int32_t ret;
208
209 ret = a3g4250d_read_reg(ctx, A3G4250D_STATUS_REG, (uint8_t *) val, 1);
210
211 return ret;
212 }
213
214 /**
215 * @brief Accelerometer new data available.[get]
216 *
217 * @param ctx Read / write interface definitions.(ptr)
218 * @param val Change the values of "zyxda" in reg STATUS_REG.(ptr)
219 * @retval Interface status (MANDATORY: return 0 -> no Error).
220 *
221 */
a3g4250d_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)222 int32_t a3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
223 {
224 a3g4250d_status_reg_t status_reg;
225 int32_t ret;
226
227 ret = a3g4250d_read_reg(ctx, A3G4250D_STATUS_REG,
228 (uint8_t *)&status_reg, 1);
229 *val = status_reg.zyxda;
230
231 return ret;
232 }
233 /**
234 * @}
235 *
236 */
237
238 /**
239 * @defgroup A3G4250D_Dataoutput
240 * @brief This section groups all the data output functions.
241 * @{
242 *
243 */
244
245 /**
246 * @brief Temperature data.[get]
247 *
248 * @param ctx Read / write interface definitions.(ptr)
249 * @param buff Buffer that stores the data read.(ptr)
250 * @retval Interface status (MANDATORY: return 0 -> no Error).
251 *
252 */
a3g4250d_temperature_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)253 int32_t a3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
254 {
255 int32_t ret;
256
257 ret = a3g4250d_read_reg(ctx, A3G4250D_OUT_TEMP, buff, 1);
258
259 return ret;
260 }
261
262 /**
263 * @brief Angular rate sensor. The value is expressed as a 16-bit word in
264 * two’s complement.[get]
265 *
266 * @param ctx Read / write interface definitions.(ptr)
267 * @param buff Buffer that stores the data read.(ptr)
268 * @retval Interface status (MANDATORY: return 0 -> no Error).
269 *
270 */
a3g4250d_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)271 int32_t a3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
272 {
273 uint8_t buff[6];
274 int32_t ret;
275
276 ret = a3g4250d_read_reg(ctx, A3G4250D_OUT_X_L, buff, 6);
277 val[0] = (int16_t)buff[1];
278 val[0] = (val[0] * 256) + (int16_t)buff[0];
279 val[1] = (int16_t)buff[3];
280 val[1] = (val[1] * 256) + (int16_t)buff[2];
281 val[2] = (int16_t)buff[5];
282 val[2] = (val[2] * 256) + (int16_t)buff[4];
283
284 return ret;
285 }
286
287 /**
288 * @}
289 *
290 */
291
292 /**
293 * @defgroup A3G4250D_common
294 * @brief This section groups common useful functions.
295 * @{
296 *
297 */
298
299 /**
300 * @brief Device Who amI.[get]
301 *
302 * @param ctx Read / write interface definitions.(ptr)
303 * @param buff Buffer that stores the data read.(ptr)
304 * @retval Interface status (MANDATORY: return 0 -> no Error).
305 *
306 */
a3g4250d_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)307 int32_t a3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
308 {
309 int32_t ret;
310
311 ret = a3g4250d_read_reg(ctx, A3G4250D_WHO_AM_I, buff, 1);
312
313 return ret;
314 }
315
316 /**
317 * @brief Angular rate sensor self-test enable. [set]
318 *
319 * @param ctx Read / write interface definitions.(ptr)
320 * @param val change the values of st in reg CTRL_REG4.
321 * @retval Interface status (MANDATORY: return 0 -> no Error).
322 *
323 */
a3g4250d_self_test_set(const stmdev_ctx_t * ctx,a3g4250d_st_t val)324 int32_t a3g4250d_self_test_set(const stmdev_ctx_t *ctx, a3g4250d_st_t val)
325 {
326 a3g4250d_ctrl_reg4_t ctrl_reg4;
327 int32_t ret;
328
329 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
330 (uint8_t *)&ctrl_reg4, 1);
331
332 if (ret == 0)
333 {
334 ctrl_reg4.st = (uint8_t)val;
335 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,
336 (uint8_t *)&ctrl_reg4, 1);
337 }
338
339 return ret;
340 }
341
342 /**
343 * @brief Angular rate sensor self-test enable. [get]
344 *
345 * @param ctx Read / write interface definitions.(ptr)
346 * @param val Get the values of st in reg CTRL_REG4.(ptr)
347 * @retval Interface status (MANDATORY: return 0 -> no Error).
348 *
349 */
a3g4250d_self_test_get(const stmdev_ctx_t * ctx,a3g4250d_st_t * val)350 int32_t a3g4250d_self_test_get(const stmdev_ctx_t *ctx, a3g4250d_st_t *val)
351 {
352 a3g4250d_ctrl_reg4_t ctrl_reg4;
353 int32_t ret;
354
355 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
356 (uint8_t *)&ctrl_reg4, 1);
357
358 switch (ctrl_reg4.st)
359 {
360 case A3G4250D_GY_ST_DISABLE:
361 *val = A3G4250D_GY_ST_DISABLE;
362 break;
363
364 case A3G4250D_GY_ST_POSITIVE:
365 *val = A3G4250D_GY_ST_POSITIVE;
366 break;
367
368 case A3G4250D_GY_ST_NEGATIVE:
369 *val = A3G4250D_GY_ST_NEGATIVE;
370 break;
371
372 default:
373 *val = A3G4250D_GY_ST_DISABLE;
374 break;
375 }
376
377 return ret;
378 }
379
380 /**
381 * @brief Big/Little Endian data selection.[set]
382 *
383 * @param ctx Read / write interface definitions.(ptr)
384 * @param val Change the values of "ble" in reg CTRL_REG4.
385 * @retval Interface status (MANDATORY: return 0 -> no Error).
386 *
387 */
a3g4250d_data_format_set(const stmdev_ctx_t * ctx,a3g4250d_ble_t val)388 int32_t a3g4250d_data_format_set(const stmdev_ctx_t *ctx, a3g4250d_ble_t val)
389 {
390 a3g4250d_ctrl_reg4_t ctrl_reg4;
391 int32_t ret;
392
393 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
394 (uint8_t *)&ctrl_reg4, 1);
395
396 if (ret == 0)
397 {
398 ctrl_reg4.ble = (uint8_t)val;
399 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,
400 (uint8_t *)&ctrl_reg4, 1);
401 }
402
403 return ret;
404 }
405
406 /**
407 * @brief Big/Little Endian data selection.[get]
408 *
409 * @param ctx Read / write interface definitions.(ptr)
410 * @param val Get the values of "ble" in reg CTRL_REG4.(ptr)
411 * @retval Interface status (MANDATORY: return 0 -> no Error).
412 *
413 */
a3g4250d_data_format_get(const stmdev_ctx_t * ctx,a3g4250d_ble_t * val)414 int32_t a3g4250d_data_format_get(const stmdev_ctx_t *ctx, a3g4250d_ble_t *val)
415 {
416 a3g4250d_ctrl_reg4_t ctrl_reg4;
417 int32_t ret;
418
419 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
420 (uint8_t *)&ctrl_reg4, 1);
421
422 switch (ctrl_reg4.ble)
423 {
424 case A3G4250D_AUX_LSB_AT_LOW_ADD:
425 *val = A3G4250D_AUX_LSB_AT_LOW_ADD;
426 break;
427
428 case A3G4250D_AUX_MSB_AT_LOW_ADD:
429 *val = A3G4250D_AUX_MSB_AT_LOW_ADD;
430 break;
431
432 default:
433 *val = A3G4250D_AUX_LSB_AT_LOW_ADD;
434 break;
435 }
436
437 return ret;
438 }
439
440 /**
441 * @brief Reboot memory content. Reload the calibration parameters.[set]
442 *
443 * @param ctx Read / write interface definitions.(ptr)
444 * @param val Change the values of boot in reg CTRL_REG5.
445 * @retval Interface status (MANDATORY: return 0 -> no Error).
446 *
447 */
a3g4250d_boot_set(const stmdev_ctx_t * ctx,uint8_t val)448 int32_t a3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
449 {
450 a3g4250d_ctrl_reg5_t ctrl_reg5;
451 int32_t ret;
452
453 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
454 (uint8_t *)&ctrl_reg5, 1);
455
456 if (ret == 0)
457 {
458 ctrl_reg5.boot = val;
459 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
460 (uint8_t *)&ctrl_reg5, 1);
461 }
462
463 return ret;
464 }
465
466 /**
467 * @brief Reboot memory content. Reload the calibration parameters.[get]
468 *
469 * @param ctx Read / write interface definitions.(ptr)
470 * @param val Get the values of boot in reg CTRL_REG5.(ptr)
471 * @retval Interface status (MANDATORY: return 0 -> no Error).
472 *
473 */
a3g4250d_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)474 int32_t a3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
475 {
476 a3g4250d_ctrl_reg5_t ctrl_reg5;
477 int32_t ret;
478
479 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
480 (uint8_t *)&ctrl_reg5, 1);
481 *val = ctrl_reg5.boot;
482
483 return ret;
484 }
485
486 /**
487 * @}
488 *
489 */
490
491 /**
492 * @defgroup A3G4250D_filters
493 * @brief This section group all the functions concerning the
494 * filters configuration.
495 * @{
496 *
497 */
498
499 /**
500 * @brief Lowpass filter bandwidth selection.[set]
501 *
502 * @param ctx Read / write interface definitions.(ptr)
503 * @param val Change the values of "bw" in reg CTRL_REG1.
504 * @retval Interface status (MANDATORY: return 0 -> no Error).
505 *
506 */
a3g4250d_lp_bandwidth_set(const stmdev_ctx_t * ctx,a3g4250d_bw_t val)507 int32_t a3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_bw_t val)
508 {
509 a3g4250d_ctrl_reg1_t ctrl_reg1;
510 int32_t ret;
511
512 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
513 (uint8_t *)&ctrl_reg1, 1);
514
515 if (ret == 0)
516 {
517 ctrl_reg1.bw = (uint8_t)val;
518 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG1,
519 (uint8_t *)&ctrl_reg1, 1);
520 }
521
522 return ret;
523 }
524
525 /**
526 * @brief Lowpass filter bandwidth selection.[get]
527 *
528 * @param ctx Read / write interface definitions.(ptr)
529 * @param val Get the values of "bw" in reg CTRL_REG1.(ptr)
530 * @retval Interface status (MANDATORY: return 0 -> no Error).
531 *
532 */
a3g4250d_lp_bandwidth_get(const stmdev_ctx_t * ctx,a3g4250d_bw_t * val)533 int32_t a3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_bw_t *val)
534 {
535 a3g4250d_ctrl_reg1_t ctrl_reg1;
536 int32_t ret;
537
538 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1,
539 (uint8_t *)&ctrl_reg1, 1);
540
541 switch (ctrl_reg1.bw)
542 {
543 case A3G4250D_CUT_OFF_LOW:
544 *val = A3G4250D_CUT_OFF_LOW;
545 break;
546
547 case A3G4250D_CUT_OFF_MEDIUM:
548 *val = A3G4250D_CUT_OFF_MEDIUM;
549 break;
550
551 case A3G4250D_CUT_OFF_HIGH:
552 *val = A3G4250D_CUT_OFF_HIGH;
553 break;
554
555 case A3G4250D_CUT_OFF_VERY_HIGH:
556 *val = A3G4250D_CUT_OFF_VERY_HIGH;
557 break;
558
559 default:
560 *val = A3G4250D_CUT_OFF_LOW;
561 break;
562 }
563
564 return ret;
565 }
566
567 /**
568 * @brief High-pass filter bandwidth selection.[set]
569 *
570 * @param ctx Read / write interface definitions.(ptr)
571 * @param val Change the values of "hpcf" in reg CTRL_REG2.
572 * @retval Interface status (MANDATORY: return 0 -> no Error).
573 *
574 */
a3g4250d_hp_bandwidth_set(const stmdev_ctx_t * ctx,a3g4250d_hpcf_t val)575 int32_t a3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t val)
576 {
577 a3g4250d_ctrl_reg2_t ctrl_reg2;
578 int32_t ret;
579
580 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
581 (uint8_t *)&ctrl_reg2, 1);
582
583 if (ret == 0)
584 {
585 ctrl_reg2.hpcf = (uint8_t)val;
586 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG2,
587 (uint8_t *)&ctrl_reg2, 1);
588 }
589
590 return ret;
591 }
592
593 /**
594 * @brief High-pass filter bandwidth selection.[get]
595 *
596 * @param ctx Read / write interface definitions.(ptr)
597 * @param val Get the values of hpcf in reg CTRL_REG2.(ptr)
598 * @retval Interface status (MANDATORY: return 0 -> no Error).
599 *
600 */
a3g4250d_hp_bandwidth_get(const stmdev_ctx_t * ctx,a3g4250d_hpcf_t * val)601 int32_t a3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val)
602 {
603 a3g4250d_ctrl_reg2_t ctrl_reg2;
604 int32_t ret;
605
606 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
607 (uint8_t *)&ctrl_reg2, 1);
608
609 switch (ctrl_reg2.hpcf)
610 {
611 case A3G4250D_HP_LEVEL_0:
612 *val = A3G4250D_HP_LEVEL_0;
613 break;
614
615 case A3G4250D_HP_LEVEL_1:
616 *val = A3G4250D_HP_LEVEL_1;
617 break;
618
619 case A3G4250D_HP_LEVEL_2:
620 *val = A3G4250D_HP_LEVEL_2;
621 break;
622
623 case A3G4250D_HP_LEVEL_3:
624 *val = A3G4250D_HP_LEVEL_3;
625 break;
626
627 case A3G4250D_HP_LEVEL_4:
628 *val = A3G4250D_HP_LEVEL_4;
629 break;
630
631 case A3G4250D_HP_LEVEL_5:
632 *val = A3G4250D_HP_LEVEL_5;
633 break;
634
635 case A3G4250D_HP_LEVEL_6:
636 *val = A3G4250D_HP_LEVEL_6;
637 break;
638
639 case A3G4250D_HP_LEVEL_7:
640 *val = A3G4250D_HP_LEVEL_7;
641 break;
642
643 case A3G4250D_HP_LEVEL_8:
644 *val = A3G4250D_HP_LEVEL_8;
645 break;
646
647 case A3G4250D_HP_LEVEL_9:
648 *val = A3G4250D_HP_LEVEL_9;
649 break;
650
651 default:
652 *val = A3G4250D_HP_LEVEL_0;
653 break;
654 }
655
656 return ret;
657 }
658
659 /**
660 * @brief High-pass filter mode selection. [set]
661 *
662 * @param ctx Read / write interface definitions.(ptr)
663 * @param val Change the values of "hpm" in reg CTRL_REG2.
664 * @retval Interface status (MANDATORY: return 0 -> no Error).
665 *
666 */
a3g4250d_hp_mode_set(const stmdev_ctx_t * ctx,a3g4250d_hpm_t val)667 int32_t a3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, a3g4250d_hpm_t val)
668 {
669 a3g4250d_ctrl_reg2_t ctrl_reg2;
670 int32_t ret;
671
672 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
673 (uint8_t *)&ctrl_reg2, 1);
674
675 if (ret == 0)
676 {
677 ctrl_reg2.hpm = (uint8_t)val;
678 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG2,
679 (uint8_t *)&ctrl_reg2, 1);
680 }
681
682 return ret;
683 }
684
685 /**
686 * @brief High-pass filter mode selection. [get]
687 *
688 * @param ctx Read / write interface definitions.(ptr)
689 * @param val Get the values of hpm in reg CTRL_REG2.(ptr)
690 * @retval Interface status (MANDATORY: return 0 -> no Error).
691 *
692 */
a3g4250d_hp_mode_get(const stmdev_ctx_t * ctx,a3g4250d_hpm_t * val)693 int32_t a3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, a3g4250d_hpm_t *val)
694 {
695 a3g4250d_ctrl_reg2_t ctrl_reg2;
696 int32_t ret;
697
698 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2,
699 (uint8_t *)&ctrl_reg2, 1);
700
701 switch (ctrl_reg2.hpm)
702 {
703 case A3G4250D_HP_NORMAL_MODE_WITH_RST:
704 *val = A3G4250D_HP_NORMAL_MODE_WITH_RST;
705 break;
706
707 case A3G4250D_HP_REFERENCE_SIGNAL:
708 *val = A3G4250D_HP_REFERENCE_SIGNAL;
709 break;
710
711 case A3G4250D_HP_NORMAL_MODE:
712 *val = A3G4250D_HP_NORMAL_MODE;
713 break;
714
715 case A3G4250D_HP_AUTO_RESET_ON_INT:
716 *val = A3G4250D_HP_AUTO_RESET_ON_INT;
717 break;
718
719 default:
720 *val = A3G4250D_HP_NORMAL_MODE_WITH_RST;
721 break;
722 }
723
724 return ret;
725 }
726
727 /**
728 * @brief Out/FIFO selection path. [set]
729 *
730 * @param ctx Read / write interface definitions.(ptr)
731 * @param val Change the values of "out_sel" in reg CTRL_REG5.
732 * @retval Interface status (MANDATORY: return 0 -> no Error).
733 *
734 */
a3g4250d_filter_path_set(const stmdev_ctx_t * ctx,a3g4250d_out_sel_t val)735 int32_t a3g4250d_filter_path_set(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t val)
736 {
737 a3g4250d_ctrl_reg5_t ctrl_reg5;
738 int32_t ret;
739
740 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
741 (uint8_t *)&ctrl_reg5, 1);
742
743 if (ret == 0)
744 {
745 ctrl_reg5.out_sel = (uint8_t)val & 0x03U;
746 ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
747 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
748 (uint8_t *)&ctrl_reg5, 1);
749 }
750
751 return ret;
752 }
753
754 /**
755 * @brief Out/FIFO selection path. [get]
756 *
757 * @param ctx Read / write interface definitions.(ptr)
758 * @param val Get the values of out_sel in reg CTRL_REG5.(ptr)
759 * @retval Interface status (MANDATORY: return 0 -> no Error).
760 *
761 */
a3g4250d_filter_path_get(const stmdev_ctx_t * ctx,a3g4250d_out_sel_t * val)762 int32_t a3g4250d_filter_path_get(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val)
763 {
764 a3g4250d_ctrl_reg5_t ctrl_reg5;
765 int32_t ret;
766
767 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
768 (uint8_t *)&ctrl_reg5, 1);
769
770 switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.out_sel)
771 {
772 case A3G4250D_ONLY_LPF1_ON_OUT:
773 *val = A3G4250D_ONLY_LPF1_ON_OUT;
774 break;
775
776 case A3G4250D_LPF1_HP_ON_OUT:
777 *val = A3G4250D_LPF1_HP_ON_OUT;
778 break;
779
780 case A3G4250D_LPF1_LPF2_ON_OUT:
781 *val = A3G4250D_LPF1_LPF2_ON_OUT;
782 break;
783
784 case A3G4250D_LPF1_HP_LPF2_ON_OUT:
785 *val = A3G4250D_LPF1_HP_LPF2_ON_OUT;
786 break;
787
788 default:
789 *val = A3G4250D_ONLY_LPF1_ON_OUT;
790 break;
791 }
792
793 return ret;
794 }
795
796 /**
797 * @brief Interrupt generator selection path.[set]
798 *
799 * @param ctx Read / write interface definitions.(ptr)
800 * @param val Change the values of int1_sel in reg CTRL_REG5
801 * @retval Interface status (MANDATORY: return 0 -> no Error).
802 *
803 */
a3g4250d_filter_path_internal_set(const stmdev_ctx_t * ctx,a3g4250d_int1_sel_t val)804 int32_t a3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx,
805 a3g4250d_int1_sel_t val)
806 {
807 a3g4250d_ctrl_reg5_t ctrl_reg5;
808 int32_t ret;
809
810 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
811 (uint8_t *)&ctrl_reg5, 1);
812
813 if (ret == 0)
814 {
815 ctrl_reg5.int1_sel = (uint8_t)val & 0x03U;
816 ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
817 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
818 (uint8_t *)&ctrl_reg5, 1);
819 }
820
821 return ret;
822 }
823
824 /**
825 * @brief Interrupt generator selection path.[get]
826 *
827 * @param ctx Read / write interface definitions.(ptr)
828 * @param val Get the values of int1_sel in reg CTRL_REG5.(ptr)
829 * @retval Interface status (MANDATORY: return 0 -> no Error).
830 *
831 */
a3g4250d_filter_path_internal_get(const stmdev_ctx_t * ctx,a3g4250d_int1_sel_t * val)832 int32_t a3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx,
833 a3g4250d_int1_sel_t *val)
834 {
835 a3g4250d_ctrl_reg5_t ctrl_reg5;
836 int32_t ret;
837
838 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
839 (uint8_t *)&ctrl_reg5, 1);
840
841 switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.int1_sel)
842 {
843 case A3G4250D_ONLY_LPF1_ON_INT:
844 *val = A3G4250D_ONLY_LPF1_ON_INT;
845 break;
846
847 case A3G4250D_LPF1_HP_ON_INT:
848 *val = A3G4250D_LPF1_HP_ON_INT;
849 break;
850
851 case A3G4250D_LPF1_LPF2_ON_INT:
852 *val = A3G4250D_LPF1_LPF2_ON_INT;
853 break;
854
855 case A3G4250D_LPF1_HP_LPF2_ON_INT:
856 *val = A3G4250D_LPF1_HP_LPF2_ON_INT;
857 break;
858
859 default:
860 *val = A3G4250D_ONLY_LPF1_ON_INT;
861 break;
862 }
863
864 return ret;
865 }
866
867 /**
868 * @brief Reference value for high-pass filter.[set]
869 *
870 * @param ctx Read / write interface definitions.(ptr)
871 * @param val Change the values of ref in reg REFERENCE
872 * @retval Interface status (MANDATORY: return 0 -> no Error).
873 *
874 */
a3g4250d_hp_reference_value_set(const stmdev_ctx_t * ctx,uint8_t val)875 int32_t a3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val)
876 {
877 a3g4250d_reference_t reference;
878 int32_t ret;
879
880 ret = a3g4250d_read_reg(ctx, A3G4250D_REFERENCE,
881 (uint8_t *)&reference, 1);
882
883 if (ret == 0)
884 {
885 reference.ref = val;
886 ret = a3g4250d_write_reg(ctx, A3G4250D_REFERENCE,
887 (uint8_t *)&reference, 1);
888 }
889
890 return ret;
891 }
892
893 /**
894 * @brief Reference value for high-pass filter.[get]
895 *
896 * @param ctx Read / write interface definitions.(ptr)
897 * @param val Get the values of ref in reg REFERENCE.(ptr)
898 * @retval Interface status (MANDATORY: return 0 -> no Error).
899 *
900 */
a3g4250d_hp_reference_value_get(const stmdev_ctx_t * ctx,uint8_t * val)901 int32_t a3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx,
902 uint8_t *val)
903 {
904 a3g4250d_reference_t reference;
905 int32_t ret;
906
907 ret = a3g4250d_read_reg(ctx, A3G4250D_REFERENCE,
908 (uint8_t *)&reference, 1);
909 *val = reference.ref;
910
911 return ret;
912 }
913
914 /**
915 * @}
916 *
917 */
918
919 /**
920 * @defgroup A3G4250D_serial_interface
921 * @brief This section groups all the functions concerning main serial
922 * interface management.
923 * @{
924 *
925 */
926
927 /**
928 * @brief SPI Serial Interface Mode selection.[set]
929 *
930 * @param ctx Read / write interface definitions.(ptr)
931 * @param val Change the values of sim in reg CTRL_REG4
932 * @retval Interface status (MANDATORY: return 0 -> no Error).
933 *
934 */
a3g4250d_spi_mode_set(const stmdev_ctx_t * ctx,a3g4250d_sim_t val)935 int32_t a3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, a3g4250d_sim_t val)
936 {
937 a3g4250d_ctrl_reg4_t ctrl_reg4;
938 int32_t ret;
939
940 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
941 (uint8_t *)&ctrl_reg4, 1);
942
943 if (ret == 0)
944 {
945 ctrl_reg4.sim = (uint8_t)val;
946 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG4,
947 (uint8_t *)&ctrl_reg4, 1);
948 }
949
950 return ret;
951 }
952
953 /**
954 * @brief SPI Serial Interface Mode selection.[get]
955 *
956 * @param ctx Read / write interface definitions.(ptr)
957 * @param val Get the values of sim in reg CTRL_REG4.(ptr)
958 * @retval Interface status (MANDATORY: return 0 -> no Error).
959 *
960 */
a3g4250d_spi_mode_get(const stmdev_ctx_t * ctx,a3g4250d_sim_t * val)961 int32_t a3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, a3g4250d_sim_t *val)
962 {
963 a3g4250d_ctrl_reg4_t ctrl_reg4;
964 int32_t ret;
965
966 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4,
967 (uint8_t *)&ctrl_reg4, 1);
968
969 switch (ctrl_reg4.sim)
970 {
971 case A3G4250D_SPI_4_WIRE:
972 *val = A3G4250D_SPI_4_WIRE;
973 break;
974
975 case A3G4250D_SPI_3_WIRE:
976 *val = A3G4250D_SPI_3_WIRE;
977 break;
978
979 default:
980 *val = A3G4250D_SPI_4_WIRE;
981 break;
982 }
983
984 return ret;
985 }
986
987 /**
988 * @}
989 *
990 */
991
992 /**
993 * @defgroup A3G4250D_interrupt_pins
994 * @brief This section groups all the functions that
995 * manage interrupt pins
996 * @{
997 *
998 */
999
1000
1001 /**
1002 * @brief Select the signal that need to route on int1 pad.[set]
1003 *
1004 * @param ctx Read / write interface definitions.(ptr)
1005 * @param val Configure CTRL_REG3 int1 pad
1006 * @retval Interface status (MANDATORY: return 0 -> no Error).
1007 *
1008 */
a3g4250d_pin_int1_route_set(const stmdev_ctx_t * ctx,a3g4250d_int1_route_t val)1009 int32_t a3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx,
1010 a3g4250d_int1_route_t val)
1011 {
1012 a3g4250d_ctrl_reg3_t ctrl_reg3;
1013 int32_t ret;
1014
1015 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1016 (uint8_t *)&ctrl_reg3, 1);
1017
1018 if (ret == 0)
1019 {
1020 ctrl_reg3.i1_int1 = val.i1_int1;
1021 ctrl_reg3.i1_boot = val.i1_boot;
1022 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
1023 (uint8_t *)&ctrl_reg3, 1);
1024 }
1025
1026 return ret;
1027 }
1028
1029 /**
1030 * @brief Select the signal that need to route on int1 pad.[get]
1031 *
1032 * @param ctx Read / write interface definitions.(ptr)
1033 * @param val Read CTRL_REG3 int1 pad.(ptr)
1034 * @retval Interface status (MANDATORY: return 0 -> no Error).
1035 *
1036 */
1037
a3g4250d_pin_int1_route_get(const stmdev_ctx_t * ctx,a3g4250d_int1_route_t * val)1038 int32_t a3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx,
1039 a3g4250d_int1_route_t *val)
1040 {
1041 a3g4250d_ctrl_reg3_t ctrl_reg3;
1042 int32_t ret;
1043
1044 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1045 (uint8_t *)&ctrl_reg3, 1);
1046 val->i1_int1 = ctrl_reg3.i1_int1;
1047 val->i1_boot = ctrl_reg3.i1_boot;
1048
1049 return ret;
1050 }
1051 /**
1052 * @brief Select the signal that need to route on int2 pad.[set]
1053 *
1054 * @param ctx Read / write interface definitions.(ptr)
1055 * @param val Configure CTRL_REG3 int2 pad
1056 * @retval Interface status (MANDATORY: return 0 -> no Error).
1057 *
1058 */
a3g4250d_pin_int2_route_set(const stmdev_ctx_t * ctx,a3g4250d_int2_route_t val)1059 int32_t a3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx,
1060 a3g4250d_int2_route_t val)
1061 {
1062 a3g4250d_ctrl_reg3_t ctrl_reg3;
1063 int32_t ret;
1064
1065 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1066 (uint8_t *)&ctrl_reg3, 1);
1067
1068 if (ret == 0)
1069 {
1070 ctrl_reg3.i2_empty = val.i2_empty;
1071 ctrl_reg3.i2_orun = val.i2_orun;
1072 ctrl_reg3.i2_wtm = val.i2_wtm;
1073 ctrl_reg3.i2_drdy = val.i2_drdy;
1074 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
1075 (uint8_t *)&ctrl_reg3, 1);
1076 }
1077
1078 return ret;
1079 }
1080
1081 /**
1082 * @brief Select the signal that need to route on int2 pad.[get]
1083 *
1084 * @param ctx Read / write interface definitions.(ptr)
1085 * @param val Read CTRL_REG3 int2 pad.(ptr)
1086 * @retval Interface status (MANDATORY: return 0 -> no Error).
1087 *
1088 */
a3g4250d_pin_int2_route_get(const stmdev_ctx_t * ctx,a3g4250d_int2_route_t * val)1089 int32_t a3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx,
1090 a3g4250d_int2_route_t *val)
1091 {
1092 a3g4250d_ctrl_reg3_t ctrl_reg3;
1093 int32_t ret;
1094
1095 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1096 (uint8_t *)&ctrl_reg3, 1);
1097 val->i2_empty = ctrl_reg3.i2_empty;
1098 val->i2_orun = ctrl_reg3.i2_orun;
1099 val->i2_wtm = ctrl_reg3.i2_wtm;
1100 val->i2_drdy = ctrl_reg3.i2_drdy;
1101
1102 return ret;
1103 }
1104 /**
1105 * @brief Push-pull/open drain selection on interrupt pads.[set]
1106 *
1107 * @param ctx Read / write interface definitions.(ptr)
1108 * @param val Change the values of pp_od in reg CTRL_REG3
1109 * @retval Interface status (MANDATORY: return 0 -> no Error).
1110 *
1111 */
1112
a3g4250d_pin_mode_set(const stmdev_ctx_t * ctx,a3g4250d_pp_od_t val)1113 int32_t a3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, a3g4250d_pp_od_t val)
1114 {
1115 a3g4250d_ctrl_reg3_t ctrl_reg3;
1116 int32_t ret;
1117
1118 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1119 (uint8_t *)&ctrl_reg3, 1);
1120
1121 if (ret == 0)
1122 {
1123 ctrl_reg3.pp_od = (uint8_t)val;
1124 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
1125 (uint8_t *)&ctrl_reg3, 1);
1126 }
1127
1128 return ret;
1129 }
1130
1131 /**
1132 * @brief Push-pull/open drain selection on interrupt pads.[get]
1133 *
1134 * @param ctx Read / write interface definitions.(ptr)
1135 * @param val Get the values of pp_od in reg CTRL_REG3.(ptr)
1136 * @retval Interface status (MANDATORY: return 0 -> no Error).
1137 *
1138 */
a3g4250d_pin_mode_get(const stmdev_ctx_t * ctx,a3g4250d_pp_od_t * val)1139 int32_t a3g4250d_pin_mode_get(const stmdev_ctx_t *ctx,
1140 a3g4250d_pp_od_t *val)
1141 {
1142 a3g4250d_ctrl_reg3_t ctrl_reg3;
1143 int32_t ret;
1144
1145 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1146 (uint8_t *)&ctrl_reg3, 1);
1147
1148 switch (ctrl_reg3.pp_od)
1149 {
1150 case A3G4250D_PUSH_PULL:
1151 *val = A3G4250D_PUSH_PULL;
1152 break;
1153
1154 case A3G4250D_OPEN_DRAIN:
1155 *val = A3G4250D_OPEN_DRAIN;
1156 break;
1157
1158 default:
1159 *val = A3G4250D_PUSH_PULL;
1160 break;
1161 }
1162
1163 return ret;
1164 }
1165
1166 /**
1167 * @brief Pin active-high/low.[set]
1168 *
1169 * @param ctx Read / write interface definitions.(ptr)
1170 * @param val Change the values of h_lactive in reg CTRL_REG3.
1171 * @retval Interface status (MANDATORY: return 0 -> no Error).
1172 *
1173 */
a3g4250d_pin_polarity_set(const stmdev_ctx_t * ctx,a3g4250d_h_lactive_t val)1174 int32_t a3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx,
1175 a3g4250d_h_lactive_t val)
1176 {
1177 a3g4250d_ctrl_reg3_t ctrl_reg3;
1178 int32_t ret;
1179
1180 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1181 (uint8_t *)&ctrl_reg3, 1);
1182
1183 if (ret == 0)
1184 {
1185 ctrl_reg3.h_lactive = (uint8_t)val;
1186 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG3,
1187 (uint8_t *)&ctrl_reg3, 1);
1188 }
1189
1190 return ret;
1191 }
1192
1193 /**
1194 * @brief Pin active-high/low.[get]
1195 *
1196 * @param ctx Read / write interface definitions.(ptr)
1197 * @param val Get the values of h_lactive in reg CTRL_REG3.(ptr)
1198 * @retval Interface status (MANDATORY: return 0 -> no Error).
1199 *
1200 */
a3g4250d_pin_polarity_get(const stmdev_ctx_t * ctx,a3g4250d_h_lactive_t * val)1201 int32_t a3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx,
1202 a3g4250d_h_lactive_t *val)
1203 {
1204 a3g4250d_ctrl_reg3_t ctrl_reg3;
1205 int32_t ret;
1206
1207 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3,
1208 (uint8_t *)&ctrl_reg3, 1);
1209
1210 switch (ctrl_reg3.h_lactive)
1211 {
1212 case A3G4250D_ACTIVE_HIGH:
1213 *val = A3G4250D_ACTIVE_HIGH;
1214 break;
1215
1216 case A3G4250D_ACTIVE_LOW:
1217 *val = A3G4250D_ACTIVE_LOW;
1218 break;
1219
1220 default:
1221 *val = A3G4250D_ACTIVE_HIGH;
1222 break;
1223 }
1224
1225 return ret;
1226 }
1227
1228 /**
1229 * @brief Latched/pulsed interrupt.[set]
1230 *
1231 * @param ctx Read / write interface definitions.(ptr)
1232 * @param val Change the values of lir in reg INT1_CFG.
1233 * @retval Interface status (MANDATORY: return 0 -> no Error).
1234 *
1235 */
a3g4250d_int_notification_set(const stmdev_ctx_t * ctx,a3g4250d_lir_t val)1236 int32_t a3g4250d_int_notification_set(const stmdev_ctx_t *ctx, a3g4250d_lir_t val)
1237 {
1238 a3g4250d_int1_cfg_t int1_cfg;
1239 int32_t ret;
1240
1241 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1242
1243 if (ret == 0)
1244 {
1245 int1_cfg.lir = (uint8_t)val;
1246 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1247 }
1248
1249 return ret;
1250 }
1251
1252 /**
1253 * @brief Latched/pulsed interrupt.[get]
1254 *
1255 * @param ctx Read / write interface definitions.(ptr)
1256 * @param val Get the values of lir in reg INT1_CFG.(ptr)
1257 * @retval Interface status (MANDATORY: return 0 -> no Error).
1258 *
1259 */
a3g4250d_int_notification_get(const stmdev_ctx_t * ctx,a3g4250d_lir_t * val)1260 int32_t a3g4250d_int_notification_get(const stmdev_ctx_t *ctx, a3g4250d_lir_t *val)
1261 {
1262 a3g4250d_int1_cfg_t int1_cfg;
1263 int32_t ret;
1264
1265 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1266
1267 switch (int1_cfg.lir)
1268 {
1269 case A3G4250D_INT_PULSED:
1270 *val = A3G4250D_INT_PULSED;
1271 break;
1272
1273 case A3G4250D_INT_LATCHED:
1274 *val = A3G4250D_INT_LATCHED;
1275 break;
1276
1277 default:
1278 *val = A3G4250D_INT_PULSED;
1279 break;
1280 }
1281
1282 return ret;
1283 }
1284
1285 /**
1286 * @}
1287 *
1288 */
1289
1290 /**
1291 * @defgroup A3G4250D_ interrupt_on_threshold
1292 * @brief This section groups all the functions that manage the event
1293 * generation on threshold.
1294 * @{
1295 *
1296 */
1297
1298 /**
1299 * @brief Configure the interrupt threshold sign.[set]
1300 *
1301 * @param ctx Read / write interface definitions.(ptr)
1302 * @param val Struct of registers INT1_CFG
1303 * @retval Interface status (MANDATORY: return 0 -> no Error).
1304 *
1305 */
a3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t * ctx,a3g4250d_int1_cfg_t * val)1306 int32_t a3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1307 a3g4250d_int1_cfg_t *val)
1308 {
1309 int32_t ret;
1310
1311 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *) val, 1);
1312
1313 return ret;
1314 }
1315
1316 /**
1317 * @brief Configure the interrupt threshold sign.[get]
1318 *
1319 * @param ctx Read / write interface definitions.(ptr)
1320 * @param val Struct of registers from INT1_CFG to.(ptr)
1321 * @retval Interface status (MANDATORY: return 0 -> no Error).
1322 *
1323 */
a3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t * ctx,a3g4250d_int1_cfg_t * val)1324 int32_t a3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1325 a3g4250d_int1_cfg_t *val)
1326 {
1327 int32_t ret;
1328
1329 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *) val, 1);
1330
1331 return ret;
1332 }
1333 /**
1334 * @brief AND/OR combination of interrupt events.[set]
1335 *
1336 * @param ctx Read / write interface definitions.(ptr)
1337 * @param val Change the values of and_or in reg INT1_CFG
1338 * @retval Interface status (MANDATORY: return 0 -> no Error).
1339 *
1340 */
a3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t * ctx,a3g4250d_and_or_t val)1341 int32_t a3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1342 a3g4250d_and_or_t val)
1343 {
1344 a3g4250d_int1_cfg_t int1_cfg;
1345 int32_t ret;
1346
1347 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1348
1349 if (ret == 0)
1350 {
1351 int1_cfg.and_or = (uint8_t)val;
1352 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1353 }
1354
1355 return ret;
1356 }
1357
1358 /**
1359 * @brief AND/OR combination of interrupt events.[get]
1360 *
1361 * @param ctx Read / write interface definitions.(ptr)
1362 * @param val Get the values of and_or in reg INT1_CFG.(ptr)
1363 * @retval Interface status (MANDATORY: return 0 -> no Error).
1364 *
1365 */
a3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t * ctx,a3g4250d_and_or_t * val)1366 int32_t a3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1367 a3g4250d_and_or_t *val)
1368 {
1369 a3g4250d_int1_cfg_t int1_cfg;
1370 int32_t ret;
1371
1372 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1373
1374 switch (int1_cfg.and_or)
1375 {
1376 case A3G4250D_INT1_ON_TH_OR:
1377 *val = A3G4250D_INT1_ON_TH_OR;
1378 break;
1379
1380 case A3G4250D_INT1_ON_TH_AND:
1381 *val = A3G4250D_INT1_ON_TH_AND;
1382 break;
1383
1384 default:
1385 *val = A3G4250D_INT1_ON_TH_OR;
1386 break;
1387 }
1388
1389 return ret;
1390 }
1391
1392 /**
1393 * @brief int_on_threshold_src: [get]
1394 *
1395 * @param ctx Read / write interface definitions.(ptr)
1396 * @param val Union of registers from INT1_SRC to.(ptr)
1397 * @retval Interface status (MANDATORY: return 0 -> no Error).
1398 *
1399 */
a3g4250d_int_on_threshold_src_get(const stmdev_ctx_t * ctx,a3g4250d_int1_src_t * val)1400 int32_t a3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx,
1401 a3g4250d_int1_src_t *val)
1402 {
1403 int32_t ret;
1404
1405 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_SRC, (uint8_t *) val, 1);
1406
1407 return ret;
1408 }
1409
1410 /**
1411 * @brief Interrupt threshold on X.[set]
1412 *
1413 * @param ctx Read / write interface definitions.(ptr)
1414 * @param val Change the values of thsx in reg INT1_TSH_XH
1415 * @retval Interface status (MANDATORY: return 0 -> no Error).
1416 *
1417 */
a3g4250d_int_x_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1418 int32_t a3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1419 {
1420 a3g4250d_int1_tsh_xh_t int1_tsh_xh;
1421 a3g4250d_int1_tsh_xl_t int1_tsh_xl;
1422 int32_t ret;
1423
1424 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XH,
1425 (uint8_t *)&int1_tsh_xh, 1);
1426
1427 if (ret == 0)
1428 {
1429 int1_tsh_xh.thsx = (uint8_t)(val / 256U) & 0x7FU;
1430 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_XH,
1431 (uint8_t *)&int1_tsh_xh, 1);
1432 }
1433
1434 if (ret == 0)
1435 {
1436 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XL,
1437 (uint8_t *)&int1_tsh_xl, 1);
1438 }
1439
1440 if (ret == 0)
1441 {
1442 int1_tsh_xl.thsx = (uint8_t)(val - (int1_tsh_xh.thsx * 256U));
1443 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_XL,
1444 (uint8_t *)&int1_tsh_xl, 1);
1445 }
1446
1447 return ret;
1448 }
1449
1450 /**
1451 * @brief Interrupt threshold on X.[get]
1452 *
1453 * @param ctx Read / write interface definitions.(ptr)
1454 * @param val Get the values of thsx in reg INT1_TSH_XH.(ptr)
1455 * @retval Interface status (MANDATORY: return 0 -> no Error).
1456 *
1457 */
a3g4250d_int_x_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1458 int32_t a3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1459 {
1460 a3g4250d_int1_tsh_xh_t int1_tsh_xh;
1461 a3g4250d_int1_tsh_xl_t int1_tsh_xl;
1462 int32_t ret;
1463
1464 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XH,
1465 (uint8_t *)&int1_tsh_xh, 1);
1466
1467 if (ret == 0)
1468 {
1469 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_XL,
1470 (uint8_t *)&int1_tsh_xl, 1);
1471 *val = int1_tsh_xh.thsx;
1472 *val = *val * 256U;
1473 *val += int1_tsh_xl.thsx;
1474 }
1475
1476 return ret;
1477 }
1478
1479 /**
1480 * @brief Interrupt threshold on Y.[set]
1481 *
1482 * @param ctx Read / write interface definitions.(ptr)
1483 * @param val Change the values of thsy in reg INT1_TSH_YH
1484 * @retval Interface status (MANDATORY: return 0 -> no Error).
1485 *
1486 */
a3g4250d_int_y_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1487 int32_t a3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1488 {
1489 a3g4250d_int1_tsh_yh_t int1_tsh_yh;
1490 a3g4250d_int1_tsh_yl_t int1_tsh_yl;
1491 int32_t ret;
1492
1493 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YH,
1494 (uint8_t *)&int1_tsh_yh, 1);
1495 int1_tsh_yh.thsy = (uint8_t)(val / 256U) & 0x7FU;
1496
1497 if (ret == 0)
1498 {
1499 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_YH,
1500 (uint8_t *)&int1_tsh_yh, 1);
1501 }
1502
1503 if (ret == 0)
1504 {
1505 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YL,
1506 (uint8_t *)&int1_tsh_yl, 1);
1507 int1_tsh_yl.thsy = (uint8_t)(val - (int1_tsh_yh.thsy * 256U));
1508 }
1509
1510 if (ret == 0)
1511 {
1512 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_YL,
1513 (uint8_t *)&int1_tsh_yl, 1);
1514 }
1515
1516 return ret;
1517 }
1518
1519 /**
1520 * @brief Interrupt threshold on Y.[get]
1521 *
1522 * @param ctx Read / write interface definitions.(ptr)
1523 * @param val Get the values of thsy in reg INT1_TSH_YH.(ptr)
1524 * @retval Interface status (MANDATORY: return 0 -> no Error).
1525 *
1526 */
a3g4250d_int_y_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1527 int32_t a3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1528 {
1529 a3g4250d_int1_tsh_yh_t int1_tsh_yh;
1530 a3g4250d_int1_tsh_yl_t int1_tsh_yl;
1531 int32_t ret;
1532
1533 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YH,
1534 (uint8_t *)&int1_tsh_yh, 1);
1535
1536 if (ret == 0)
1537 {
1538 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YL,
1539 (uint8_t *)&int1_tsh_yl, 1);
1540 *val = int1_tsh_yh.thsy;
1541 *val = *val * 256U;
1542 *val += int1_tsh_yl.thsy;
1543 }
1544
1545 return ret;
1546 }
1547
1548 /**
1549 * @brief Interrupt threshold on Z.[set]
1550 *
1551 * @param ctx Read / write interface definitions.(ptr)
1552 * @param val Change the values of thsz in reg INT1_TSH_ZH.
1553 * @retval Interface status (MANDATORY: return 0 -> no Error).
1554 *
1555 */
a3g4250d_int_z_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1556 int32_t a3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1557 {
1558 a3g4250d_int1_tsh_zh_t int1_tsh_zh;
1559 a3g4250d_int1_tsh_zl_t int1_tsh_zl;
1560 int32_t ret;
1561
1562 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZH,
1563 (uint8_t *)&int1_tsh_zh, 1);
1564 int1_tsh_zh.thsz = (uint8_t)(val / 256U) & 0x7FU;;
1565
1566 if (ret == 0)
1567 {
1568 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_ZH,
1569 (uint8_t *)&int1_tsh_zh, 1);
1570 }
1571
1572 if (ret == 0)
1573 {
1574 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZL,
1575 (uint8_t *)&int1_tsh_zl, 1);
1576 int1_tsh_zl.thsz = (uint8_t)(val - (int1_tsh_zh.thsz * 256U));
1577 }
1578
1579 if (ret == 0)
1580 {
1581 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_TSH_ZL,
1582 (uint8_t *)&int1_tsh_zl, 1);
1583 }
1584
1585 return ret;
1586 }
1587
1588 /**
1589 * @brief Interrupt threshold on Z.[get]
1590 *
1591 * @param ctx Read / write interface definitions.(ptr)
1592 * @param val Get the values of thsz in reg INT1_TSH_ZH.(ptr)
1593 * @retval Interface status (MANDATORY: return 0 -> no Error).
1594 *
1595 */
a3g4250d_int_z_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1596 int32_t a3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1597 {
1598 a3g4250d_int1_tsh_zh_t int1_tsh_zh;
1599 a3g4250d_int1_tsh_zl_t int1_tsh_zl;
1600 int32_t ret;
1601
1602 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZH,
1603 (uint8_t *)&int1_tsh_zh, 1);
1604
1605 if (ret == 0)
1606 {
1607 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZL,
1608 (uint8_t *)&int1_tsh_zl, 1);
1609 *val = int1_tsh_zh.thsz;
1610 *val = *val * 256U;
1611 *val += int1_tsh_zl.thsz;
1612 }
1613
1614 return ret;
1615 }
1616
1617 /**
1618 * @brief Durationvalue.[set]
1619 *
1620 * @param ctx Read / write interface definitions.(ptr)
1621 * @param val Change the values of d in reg INT1_DURATION
1622 * @retval Interface status (MANDATORY: return 0 -> no Error).
1623 *
1624 */
a3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1625 int32_t a3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx,
1626 uint8_t val)
1627 {
1628 a3g4250d_int1_duration_t int1_duration;
1629 int32_t ret;
1630
1631 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_DURATION,
1632 (uint8_t *)&int1_duration, 1);
1633
1634 if (ret == 0)
1635 {
1636 int1_duration.d = val;
1637
1638 if (val != PROPERTY_DISABLE)
1639 {
1640 int1_duration.wait = PROPERTY_ENABLE;
1641 }
1642
1643 else
1644 {
1645 int1_duration.wait = PROPERTY_DISABLE;
1646 }
1647
1648 ret = a3g4250d_write_reg(ctx, A3G4250D_INT1_DURATION,
1649 (uint8_t *)&int1_duration, 1);
1650 }
1651
1652 return ret;
1653 }
1654
1655 /**
1656 * @brief Durationvalue.[get]
1657 *
1658 * @param ctx Read / write interface definitions.(ptr)
1659 * @param val Get the values of d in reg INT1_DURATION.(ptr)
1660 * @retval Interface status (MANDATORY: return 0 -> no Error).
1661 *
1662 */
a3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1663 int32_t a3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx,
1664 uint8_t *val)
1665 {
1666 a3g4250d_int1_duration_t int1_duration;
1667 int32_t ret;
1668
1669 ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_DURATION,
1670 (uint8_t *)&int1_duration, 1);
1671 *val = int1_duration.d;
1672
1673 return ret;
1674 }
1675
1676 /**
1677 * @}
1678 *
1679 */
1680
1681 /**
1682 * @defgroup A3G4250D_fifo
1683 * @brief This section group all the functions concerning the fifo usage
1684 * @{
1685 *
1686 */
1687
1688 /**
1689 * @brief FIFOenable.[set]
1690 *
1691 * @param ctx Read / write interface definitions.(ptr)
1692 * @param val Change the values of fifo_en in reg CTRL_REG5
1693 * @retval Interface status (MANDATORY: return 0 -> no Error).
1694 *
1695 */
a3g4250d_fifo_enable_set(const stmdev_ctx_t * ctx,uint8_t val)1696 int32_t a3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val)
1697 {
1698 a3g4250d_ctrl_reg5_t ctrl_reg5;
1699 int32_t ret;
1700
1701 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
1702 (uint8_t *)&ctrl_reg5, 1);
1703
1704 if (ret == 0)
1705 {
1706 ctrl_reg5.fifo_en = val;
1707 ret = a3g4250d_write_reg(ctx, A3G4250D_CTRL_REG5,
1708 (uint8_t *)&ctrl_reg5, 1);
1709 }
1710
1711 return ret;
1712 }
1713
1714 /**
1715 * @brief FIFOenable.[get]
1716 *
1717 * @param ctx Read / write interface definitions.(ptr)
1718 * @param val Get the values of fifo_en in reg CTRL_REG5.(ptr)
1719 * @retval Interface status (MANDATORY: return 0 -> no Error).
1720 *
1721 */
a3g4250d_fifo_enable_get(const stmdev_ctx_t * ctx,uint8_t * val)1722 int32_t a3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val)
1723 {
1724 a3g4250d_ctrl_reg5_t ctrl_reg5;
1725 int32_t ret;
1726
1727 ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5,
1728 (uint8_t *)&ctrl_reg5, 1);
1729 *val = ctrl_reg5.fifo_en;
1730
1731 return ret;
1732 }
1733
1734 /**
1735 * @brief FIFO watermark level selection.[set]
1736 *
1737 * @param ctx Read / write interface definitions.(ptr)
1738 * @param val Change the values of wtm in reg FIFO_CTRL_REG
1739 * @retval Interface status (MANDATORY: return 0 -> no Error).
1740 *
1741 */
a3g4250d_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1742 int32_t a3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1743 {
1744 a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1745 int32_t ret;
1746
1747 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
1748 (uint8_t *)&fifo_ctrl_reg, 1);
1749
1750 if (ret == 0)
1751 {
1752 fifo_ctrl_reg.wtm = val;
1753 ret = a3g4250d_write_reg(ctx, A3G4250D_FIFO_CTRL_REG,
1754 (uint8_t *)&fifo_ctrl_reg, 1);
1755 }
1756
1757 return ret;
1758 }
1759
1760 /**
1761 * @brief FIFO watermark level selection.[get]
1762 *
1763 * @param ctx Read / write interface definitions.(ptr)
1764 * @param val Get the values of wtm in reg FIFO_CTRL_REG.(ptr)
1765 * @retval Interface status (MANDATORY: return 0 -> no Error).
1766 *
1767 */
a3g4250d_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1768 int32_t a3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1769 {
1770 a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1771 int32_t ret;
1772
1773 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
1774 (uint8_t *)&fifo_ctrl_reg, 1);
1775 *val = fifo_ctrl_reg.wtm;
1776
1777 return ret;
1778 }
1779
1780 /**
1781 * @brief FIFO mode selection.[set]
1782 *
1783 * @param ctx Read / write interface definitions.(ptr)
1784 * @param val Change the values of fm in reg FIFO_CTRL_REG
1785 * @retval Interface status (MANDATORY: return 0 -> no Error).
1786 *
1787 */
a3g4250d_fifo_mode_set(const stmdev_ctx_t * ctx,a3g4250d_fifo_mode_t val)1788 int32_t a3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx,
1789 a3g4250d_fifo_mode_t val)
1790 {
1791 a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1792 int32_t ret;
1793
1794 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
1795 (uint8_t *)&fifo_ctrl_reg, 1);
1796
1797 if (ret == 0)
1798 {
1799 fifo_ctrl_reg.fm = (uint8_t)val;
1800 ret = a3g4250d_write_reg(ctx, A3G4250D_FIFO_CTRL_REG,
1801 (uint8_t *)&fifo_ctrl_reg, 1);
1802 }
1803
1804 return ret;
1805 }
1806
1807 /**
1808 * @brief FIFO mode selection.[get]
1809 *
1810 * @param ctx Read / write interface definitions.(ptr)
1811 * @param val Get the values of fm in reg FIFO_CTRL_REG.(ptr)
1812 * @retval Interface status (MANDATORY: return 0 -> no Error).
1813 *
1814 */
a3g4250d_fifo_mode_get(const stmdev_ctx_t * ctx,a3g4250d_fifo_mode_t * val)1815 int32_t a3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx,
1816 a3g4250d_fifo_mode_t *val)
1817 {
1818 a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1819 int32_t ret;
1820
1821 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG,
1822 (uint8_t *)&fifo_ctrl_reg, 1);
1823
1824 switch (fifo_ctrl_reg.fm)
1825 {
1826 case A3G4250D_FIFO_BYPASS_MODE:
1827 *val = A3G4250D_FIFO_BYPASS_MODE;
1828 break;
1829
1830 case A3G4250D_FIFO_MODE:
1831 *val = A3G4250D_FIFO_MODE;
1832 break;
1833
1834 case A3G4250D_FIFO_STREAM_MODE:
1835 *val = A3G4250D_FIFO_STREAM_MODE;
1836 break;
1837
1838 default:
1839 *val = A3G4250D_FIFO_BYPASS_MODE;
1840 break;
1841 }
1842
1843 return ret;
1844 }
1845
1846 /**
1847 * @brief FIFO stored data level[get]
1848 *
1849 * @param ctx Read / write interface definitions.(ptr)
1850 * @param val Get the values of fss in reg FIFO_SRC_REG.(ptr)
1851 * @retval Interface status (MANDATORY: return 0 -> no Error).
1852 *
1853 */
a3g4250d_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)1854 int32_t a3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
1855 {
1856 a3g4250d_fifo_src_reg_t fifo_src_reg;
1857 int32_t ret;
1858
1859 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
1860 (uint8_t *)&fifo_src_reg, 1);
1861 *val = fifo_src_reg.fss;
1862
1863 return ret;
1864 }
1865
1866 /**
1867 * @brief FIFOemptybit.[get]
1868 *
1869 * @param ctx Read / write interface definitions.(ptr)
1870 * @param val Get the values of empty in reg FIFO_SRC_REG.(ptr)
1871 * @retval Interface status (MANDATORY: return 0 -> no Error).
1872 *
1873 */
a3g4250d_fifo_empty_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1874 int32_t a3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1875 {
1876 a3g4250d_fifo_src_reg_t fifo_src_reg;
1877 int32_t ret;
1878
1879 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
1880 (uint8_t *)&fifo_src_reg, 1);
1881 *val = fifo_src_reg.empty;
1882
1883 return ret;
1884 }
1885
1886 /**
1887 * @brief Overrun bit status.[get]
1888 *
1889 * @param ctx Read / write interface definitions.(ptr)
1890 * @param val Get the values of ovrn in reg FIFO_SRC_REG.(ptr)
1891 * @retval Interface status (MANDATORY: return 0 -> no Error).
1892 *
1893 */
a3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1894 int32_t a3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1895 {
1896 a3g4250d_fifo_src_reg_t fifo_src_reg;
1897 int32_t ret;
1898
1899 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
1900 (uint8_t *)&fifo_src_reg, 1);
1901 *val = fifo_src_reg.ovrn;
1902
1903 return ret;
1904 }
1905
1906 /**
1907 * @brief Watermark status:[get]
1908 * 0: FIFO filling is lower than WTM level;
1909 * 1: FIFO filling is equal or higher than WTM level)
1910 *
1911 * @param ctx Read / write interface definitions.(ptr)
1912 * @param val Get the values of wtm in reg FIFO_SRC_REG.(ptr)
1913 * @retval Interface status (MANDATORY: return 0 -> no Error).
1914 *
1915 */
1916
a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1917 int32_t a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1918 {
1919 a3g4250d_fifo_src_reg_t fifo_src_reg;
1920 int32_t ret;
1921
1922 ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG,
1923 (uint8_t *)&fifo_src_reg, 1);
1924 *val = fifo_src_reg.wtm;
1925
1926 return ret;
1927 }
1928
1929 /**
1930 * @}
1931 *
1932 */
1933
1934 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1935
