1/*
2 * Copyright (c) 2024 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/offsets.h>
8
9#include <xtensa/config/tie.h>
10#include <xtensa/config/tie-asm.h>
11
12/*
13 * Load the HiFi registers from the hifi buffer in the BSA. Round the address
14 * of this buffer up to XCHAL_CP1_SA_ALIGN bytes to guarantee the necessary
15 * alignment.
16 *
17 * Upon entry ...
18 * A0 - return address (do not modify)
19 * A1 - address of BSA (do not modify)
20 * A2 - available for use
21 * A3 - available for use
22 */
23.global _xtensa_hifi_load
24.align 4
25_xtensa_hifi_load:
26        addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
27        movi a3, ~(XCHAL_CP1_SA_ALIGN - 1)
28        and a2, a2, a3
29
30        xchal_cp1_load a2 a3 a3 a3 a3    /* Only A2 and A3 are used by macro */
31
32	ret
33
34/*
35 * Save the HiFi registers into the hifi buffer in the BSA. Round the address
36 * of this buffer up to XCHAL_CP1_SA_ALIGN bytes to guarantee the necessary
37 * alignment.
38 *
39 * A0 - return address (do not modify)
40 * A1 - address of BSA (do not modify)
41 * A2 - available for use
42 * A3 - available for use
43 */
44.global _xtensa_hifi_save
45.align 4
46_xtensa_hifi_save:
47        addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
48        movi a3, ~(XCHAL_CP1_SA_ALIGN - 1)
49        and a2, a2, a3
50
51        xchal_cp1_store a2 a3 a3 a3 a3  /* Only A2 and A3 are used by macro */
52
53	ret
54