1/*
2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
7 */
8/*
9 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining
12 * a copy of this software and associated documentation files (the
13 * "Software"), to deal in the Software without restriction, including
14 * without limitation the rights to use, copy, modify, merge, publish,
15 * distribute, sublicense, and/or sell copies of the Software, and to
16 * permit persons to whom the Software is furnished to do so, subject to
17 * the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included
20 * in all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
26 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 */
30
31/*
32 * Xtensa interrupt handling data and assembly routines.
33 * Also see xtensa_intr.c and xtensa_vectors.S.
34 */
35
36#include <xtensa/hal.h>
37#include <xtensa/config/core.h>
38
39#include "xtensa/xtensa_context.h"
40
41/*
42 * When compiling for G0-only, we don't have FreeRTOS component.
43 * In fact, FreeRTOS component is only used for the configuration, so only the
44 * macro portNUM_PROCESSORS needs to be defined (in the build file).
45 */
46#if __has_include("freertos/FreeRTOSConfig.h")
47    #include "freertos/FreeRTOSConfig.h"
48#endif
49
50#if XCHAL_HAVE_INTERRUPTS
51
52/*
53-------------------------------------------------------------------------------
54  INTENABLE virtualization information.
55-------------------------------------------------------------------------------
56*/
57
58
59#if XT_USE_SWPRI
60/* Warning - this is not multicore-compatible. */
61    .data
62    .global _xt_intdata
63    .align  8
64_xt_intdata:
65    .global _xt_intenable
66    .type   _xt_intenable,@object
67    .size   _xt_intenable,4
68    .global _xt_vpri_mask
69    .type   _xt_vpri_mask,@object
70    .size   _xt_vpri_mask,4
71
72_xt_intenable:     .word   0             /* Virtual INTENABLE     */
73_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
74#endif
75
76/*
77-------------------------------------------------------------------------------
78  Table of C-callable interrupt handlers for each interrupt. Note that not all
79  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
80  dispatched to a C handler by default.
81
82  Stored as:
83  int 0 cpu 0
84  int 0 cpu 1
85  ...
86  int 0 cpu n
87  int 1 cpu 0
88  int 1 cpu 1
89  etc
90-------------------------------------------------------------------------------
91*/
92
93    .data
94    .global _xt_interrupt_table
95    .align  8
96
97_xt_interrupt_table:
98
99    .set    i, 0
100    .rept   XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS
101    .word   xt_unhandled_interrupt      /* handler address               */
102    .word   i                           /* handler arg (default: intnum) */
103    .set    i, i+1
104    .endr
105
106#endif /* XCHAL_HAVE_INTERRUPTS */
107
108
109#if XCHAL_HAVE_EXCEPTIONS
110
111/*
112-------------------------------------------------------------------------------
113  Table of C-callable exception handlers for each exception. Note that not all
114  slots will be active, because some exceptions (e.g. coprocessor exceptions)
115  are always handled by the OS and cannot be hooked by user handlers.
116
117  Stored as:
118  exc 0 cpu 0
119  exc 0 cpu 1
120  ...
121  exc 0 cpu n
122  exc 1 cpu 0
123  exc 1 cpu 1
124  etc
125-------------------------------------------------------------------------------
126*/
127
128    .data
129    .global _xt_exception_table
130    .align  4
131
132_xt_exception_table:
133    .rept   XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS
134    .word   xt_unhandled_exception    /* handler address */
135    .endr
136
137#endif
138
139
140/*
141-------------------------------------------------------------------------------
142  unsigned int xt_ints_on ( unsigned int mask )
143
144  Enables a set of interrupts. Does not simply set INTENABLE directly, but
145  computes it as a function of the current virtual priority if XT_USE_SWPRI is
146  enabled.
147  Can be called from interrupt handlers.
148-------------------------------------------------------------------------------
149*/
150
151    .text
152    .align  4
153    .global xt_ints_on
154    .type   xt_ints_on,@function
155
156xt_ints_on:
157
158    ENTRY0
159
160#if XCHAL_HAVE_INTERRUPTS
161#if XT_USE_SWPRI
162    movi    a3, 0
163    movi    a4, _xt_intdata
164    xsr     a3, INTENABLE        /* Disables all interrupts   */
165    rsync
166    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
167    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
168    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
169    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
170    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
171    wsr     a5, INTENABLE        /* Reenable interrupts       */
172    mov     a2, a3               /* Previous mask             */
173#else
174    movi    a3, 0
175    xsr     a3, INTENABLE        /* Disables all interrupts   */
176    rsync
177    or      a2, a3, a2           /* set bits in mask */
178    wsr     a2, INTENABLE        /* Re-enable ints */
179    rsync
180    mov     a2, a3               /* return prev mask */
181#endif
182#else
183    movi    a2, 0                /* Return zero */
184#endif
185    RET0
186
187    .size   xt_ints_on, . - xt_ints_on
188
189
190/*
191-------------------------------------------------------------------------------
192  unsigned int xt_ints_off ( unsigned int mask )
193
194  Disables a set of interrupts. Does not simply set INTENABLE directly,
195  but computes it as a function of the current virtual priority if XT_USE_SWPRI is
196  enabled.
197  Can be called from interrupt handlers.
198-------------------------------------------------------------------------------
199*/
200
201    .text
202    .align  4
203    .global xt_ints_off
204    .type   xt_ints_off,@function
205
206xt_ints_off:
207
208    ENTRY0
209#if XCHAL_HAVE_INTERRUPTS
210#if XT_USE_SWPRI
211    movi    a3, 0
212    movi    a4, _xt_intdata
213    xsr     a3, INTENABLE        /* Disables all interrupts    */
214    rsync
215    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
216    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
217    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
218    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
219    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
220    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
221    wsr     a5, INTENABLE        /* Reenable interrupts        */
222    mov     a2, a3               /* Previous mask              */
223#else
224    movi    a4, 0
225    xsr     a4, INTENABLE        /* Disables all interrupts   */
226    rsync
227    or      a3, a4, a2           /* set bits in mask */
228    xor     a3, a3, a2           /* invert bits in mask set in mask, essentially clearing them */
229    wsr     a3, INTENABLE        /* Re-enable ints */
230    rsync
231    mov     a2, a4               /* return prev mask */
232#endif
233#else
234    movi    a2, 0                /* return zero */
235#endif
236    RET0
237
238    .size   xt_ints_off, . - xt_ints_off
239