1 /** 2 * \file 3 * 4 * \brief SPI related functionality declaration. 5 * 6 * Copyright (C) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 44 #ifndef _HPL_SPI_S_SYNC_H_INCLUDED 45 #define _HPL_SPI_S_SYNC_H_INCLUDED 46 47 #include <hpl_spi_sync.h> 48 49 /** 50 * \addtogroup hpl_spi HPL SPI 51 * 52 *@{ 53 */ 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 /** Uses common SPI async device driver. */ 60 #define _spi_s_sync_dev _spi_sync_dev 61 62 /** 63 * \brief Initialize SPI for access without interrupts 64 * It will load default hardware configuration and software struct. 65 * \param[in, out] dev Pointer to the SPI device instance. 66 * \param[in] hw Pointer to the hardware base. 67 * \return Operation status. 68 * \retval ERR_INVALID_ARG Input parameter problem. 69 * \retval ERR_BUSY SPI hardware not ready (resetting). 70 * \retval ERR_DENIED SPI has been enabled. 71 * \retval 0 Operation done successfully. 72 */ 73 int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); 74 75 /** 76 * \brief Initialize SPI for access with interrupts 77 * Disable, reset the hardware and the software struct. 78 * \param[in, out] dev Pointer to the SPI device instance. 79 * \return Operation status. 80 * \retval 0 Operation done successfully. 81 */ 82 int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); 83 84 /** 85 * \brief Enable SPI for access without interrupts 86 * \param[in, out] dev Pointer to the SPI device instance. 87 * \return Operation status. 88 * \retval ERR_BUSY SPI hardware not ready (resetting). 89 * \retval 0 Operation done successfully. 90 */ 91 int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); 92 93 /** 94 * \brief Disable SPI for access without interrupts 95 * Disable SPI. Deactivate all CS pins if works as master. 96 * \param[in, out] dev Pointer to the SPI device instance. 97 * \return Operation status. 98 * \retval 0 Operation done successfully. 99 */ 100 int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); 101 102 /** 103 * \brief Set SPI transfer mode 104 * Set SPI transfer mode (\ref spi_transfer_mode), 105 * which controls clock polarity and clock phase. 106 * Mode 0: leading edge is rising edge, data sample on leading edge. 107 * Mode 1: leading edge is rising edge, data sample on trailing edge. 108 * Mode 2: leading edge is falling edge, data sample on leading edge. 109 * Mode 3: leading edge is falling edge, data sample on trailing edge. 110 * \param[in, out] dev Pointer to the SPI device instance. 111 * \param[in] mode The SPI transfer mode. 112 * \return Operation status. 113 * \retval ERR_BUSY SPI is not ready to accept new setting. 114 * \retval 0 Operation done successfully. 115 */ 116 int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); 117 118 /** 119 * \brief Set SPI baudrate 120 * \param[in, out] dev Pointer to the SPI device instance. 121 * \param[in] char_size The character size, see \ref spi_char_size. 122 * \return Operation status. 123 * \retval ERR_INVALID_ARG The character size is not supported. 124 * \retval ERR_BUSY SPI is not ready to accept new setting. 125 * \retval 0 Operation done successfully. 126 */ 127 int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); 128 129 /** 130 * \brief Set SPI data order 131 * \param[in, out] dev Pointer to the SPI device instance. 132 * \param[in] dord SPI data order (LSB/MSB first). 133 * \return Operation status. 134 * \retval ERR_INVALID_ARG The character size is not supported. 135 * \retval ERR_BUSY SPI is not ready to accept new setting. 136 * \retval 0 Operation done successfully. 137 */ 138 int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); 139 140 /** 141 * \brief Enable interrupt on character output 142 * 143 * Enable interrupt when a new character can be written 144 * to the SPI device. 145 * 146 * \param[in] dev Pointer to the SPI device instance 147 * \param[in] state true = enable output interrupt 148 * false = disable output interrupt 149 * 150 * \return Status code 151 * \retval 0 Ok status 152 */ 153 int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); 154 155 /** 156 * \brief Enable interrupt on character input 157 * 158 * Enable interrupt when a new character is ready to be 159 * read from the SPI device. 160 * 161 * \param[in] dev Pointer to the SPI device instance 162 * \param[in] state true = enable input interrupts 163 * false = disable input interrupt 164 * 165 * \return Status code 166 * \retval 0 OK Status 167 */ 168 int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); 169 170 /** 171 * \brief Read one character to SPI device instance 172 * \param[in, out] dev Pointer to the SPI device instance. 173 * 174 * \return Character read from SPI module 175 */ 176 uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); 177 178 /** 179 * \brief Write one character to assigned buffer 180 * \param[in, out] dev Pointer to the SPI device instance. 181 * \param[in] data 182 * 183 * \return Status code of write operation 184 * \retval 0 Write operation OK 185 */ 186 int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); 187 188 /** 189 * \brief Check if TX ready 190 * 191 * \param[in] dev Pointer to the SPI device instance 192 * 193 * \return TX ready state 194 * \retval true TX ready 195 * \retval false TX not ready 196 */ 197 bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); 198 199 /** 200 * \brief Check if RX character ready 201 * 202 * \param[in] dev Pointer to the SPI device instance 203 * 204 * \return RX character ready state 205 * \retval true RX character ready 206 * \retval false RX character not ready 207 */ 208 bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); 209 210 /** 211 * \brief Check if SS deactiviation detected 212 * 213 * \param[in] dev Pointer to the SPI device instance 214 * 215 * \return SS deactiviation state 216 * \retval true SS deactiviation detected 217 * \retval false SS deactiviation not detected 218 */ 219 bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); 220 221 /** 222 * \brief Check if error is detected 223 * 224 * \param[in] dev Pointer to the SPI device instance 225 * 226 * \return Error detection state 227 * \retval true Error detected 228 * \retval false Error not detected 229 */ 230 bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); 231 232 #ifdef __cplusplus 233 } 234 #endif 235 236 /**@}*/ 237 #endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ 238
