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/trusted-firmware-a-latest/drivers/st/clk/
Dclk-stm32-core.h224 #define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ argument
239 #define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ argument
258 #define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ argument
269 #define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ argument
295 #define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ argument
361 #define CLK_OSC(idx, _idx, _parent, _osc_id) \ argument
372 #define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ argument
Dclk-stm32mp13.c1707 #define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\ argument
1762 #define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\ argument