1 /**
2 * \file
3 *
4 * \brief SAM 32k Oscillators Controller.
5 *
6 * Copyright (C) 2015 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43 #include <hpl_init.h>
44 #include <compiler.h>
45 #include <hpl_osc32kctrl_config.h>
46
47 /**
48 * \brief Initialize 32 kHz clock sources
49 */
_osc32kctrl_init_sources(void)50 void _osc32kctrl_init_sources(void)
51 {
52 void * hw = (void *)OSC32KCTRL;
53 uint16_t calib = 0;
54
55 #if CONF_XOSC32K_CONFIG == 1
56 hri_osc32kctrl_write_XOSC32K_reg(hw,
57 OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP)
58 | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
59 | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
60 | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos)
61 | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos)
62 | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos)
63 | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos));
64
65 #endif
66
67 #if CONF_OSC32K_CONFIG == 1
68 /* OSC32K calibration value at bit 12:6 of memory 0x00806020 */
69 calib = (*((uint32_t *)0x00806020) & 0x0001FC0) >> 6;
70 hri_osc32kctrl_write_OSC32K_reg(hw,
71 #if CONF_OSC32K_CALIB_ENABLE == 1
72 OSC32KCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) |
73 #else
74 OSC32KCTRL_OSC32K_CALIB(calib) |
75 #endif
76 OSC32KCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP)
77 | (CONF_OSC32K_ONDEMAND << OSC32KCTRL_OSC32K_ONDEMAND_Pos)
78 | (CONF_OSC32K_RUNSTDBY << OSC32KCTRL_OSC32K_RUNSTDBY_Pos)
79 | (CONF_OSC32K_EN1K << OSC32KCTRL_OSC32K_EN1K_Pos)
80 | (CONF_OSC32K_EN32K << OSC32KCTRL_OSC32K_EN32K_Pos)
81 | (CONF_OSC32K_ENABLE << OSC32KCTRL_OSC32K_ENABLE_Pos));
82 #endif
83 #if CONF_OSCULP32K_CONFIG == 1
84 calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
85 hri_osc32kctrl_write_OSCULP32K_reg(hw,
86 #if CONF_OSC32K_CALIB_ENABLE == 1
87 OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB)
88 #else
89 OSC32KCTRL_OSCULP32K_CALIB(calib)
90 #endif
91 );
92 #endif
93
94 #if CONF_XOSC32K_CONFIG
95 #if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0
96 while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw))
97 ;
98 #endif
99 #endif
100 #if CONF_OSC32K_CONFIG == 1
101 #if CONF_OSC32K_ENABLE == 1 && CONF_OSC32K_ONDEMAND == 0
102 while (!hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(hw))
103 ;
104 #endif
105 #endif
106
107 hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
108 (void)calib;
109 }
110
