1 /*
2 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <stdint.h>
10 #include <stdio.h>
11
12 #include <arch.h>
13 #include <arch_helpers.h>
14 #include <common/debug.h>
15 #include <common/fdt_wrappers.h>
16 #include <drivers/clk.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/st/stm32mp_clkfunc.h>
19 #include <drivers/st/stm32mp1_clk.h>
20 #include <drivers/st/stm32mp1_rcc.h>
21 #include <dt-bindings/clock/stm32mp1-clksrc.h>
22 #include <lib/mmio.h>
23 #include <lib/spinlock.h>
24 #include <lib/utils_def.h>
25 #include <libfdt.h>
26 #include <plat/common/platform.h>
27
28 #include <platform_def.h>
29
30 #define MAX_HSI_HZ 64000000
31 #define USB_PHY_48_MHZ 48000000
32
33 #define TIMEOUT_US_200MS U(200000)
34 #define TIMEOUT_US_1S U(1000000)
35
36 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
37 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
38 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
39 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS
40 #define OSCRDY_TIMEOUT TIMEOUT_US_1S
41
42 const char *stm32mp_osc_node_label[NB_OSC] = {
43 [_LSI] = "clk-lsi",
44 [_LSE] = "clk-lse",
45 [_HSI] = "clk-hsi",
46 [_HSE] = "clk-hse",
47 [_CSI] = "clk-csi",
48 [_I2S_CKIN] = "i2s_ckin",
49 };
50
51 enum stm32mp1_parent_id {
52 /* Oscillators are defined in enum stm32mp_osc_id */
53
54 /* Other parent source */
55 _HSI_KER = NB_OSC,
56 _HSE_KER,
57 _HSE_KER_DIV2,
58 _HSE_RTC,
59 _CSI_KER,
60 _PLL1_P,
61 _PLL1_Q,
62 _PLL1_R,
63 _PLL2_P,
64 _PLL2_Q,
65 _PLL2_R,
66 _PLL3_P,
67 _PLL3_Q,
68 _PLL3_R,
69 _PLL4_P,
70 _PLL4_Q,
71 _PLL4_R,
72 _ACLK,
73 _PCLK1,
74 _PCLK2,
75 _PCLK3,
76 _PCLK4,
77 _PCLK5,
78 _HCLK6,
79 _HCLK2,
80 _CK_PER,
81 _CK_MPU,
82 _CK_MCU,
83 _USB_PHY_48,
84 _PARENT_NB,
85 _UNKNOWN_ID = 0xff,
86 };
87
88 /* Lists only the parent clock we are interested in */
89 enum stm32mp1_parent_sel {
90 _I2C12_SEL,
91 _I2C35_SEL,
92 _STGEN_SEL,
93 _I2C46_SEL,
94 _SPI6_SEL,
95 _UART1_SEL,
96 _RNG1_SEL,
97 _UART6_SEL,
98 _UART24_SEL,
99 _UART35_SEL,
100 _UART78_SEL,
101 _SDMMC12_SEL,
102 _SDMMC3_SEL,
103 _QSPI_SEL,
104 _FMC_SEL,
105 _AXIS_SEL,
106 _MCUS_SEL,
107 _USBPHY_SEL,
108 _USBO_SEL,
109 _MPU_SEL,
110 _CKPER_SEL,
111 _RTC_SEL,
112 _PARENT_SEL_NB,
113 _UNKNOWN_SEL = 0xff,
114 };
115
116 /* State the parent clock ID straight related to a clock */
117 static const uint8_t parent_id_clock_id[_PARENT_NB] = {
118 [_HSE] = CK_HSE,
119 [_HSI] = CK_HSI,
120 [_CSI] = CK_CSI,
121 [_LSE] = CK_LSE,
122 [_LSI] = CK_LSI,
123 [_I2S_CKIN] = _UNKNOWN_ID,
124 [_USB_PHY_48] = _UNKNOWN_ID,
125 [_HSI_KER] = CK_HSI,
126 [_HSE_KER] = CK_HSE,
127 [_HSE_KER_DIV2] = CK_HSE_DIV2,
128 [_HSE_RTC] = _UNKNOWN_ID,
129 [_CSI_KER] = CK_CSI,
130 [_PLL1_P] = PLL1_P,
131 [_PLL1_Q] = PLL1_Q,
132 [_PLL1_R] = PLL1_R,
133 [_PLL2_P] = PLL2_P,
134 [_PLL2_Q] = PLL2_Q,
135 [_PLL2_R] = PLL2_R,
136 [_PLL3_P] = PLL3_P,
137 [_PLL3_Q] = PLL3_Q,
138 [_PLL3_R] = PLL3_R,
139 [_PLL4_P] = PLL4_P,
140 [_PLL4_Q] = PLL4_Q,
141 [_PLL4_R] = PLL4_R,
142 [_ACLK] = CK_AXI,
143 [_PCLK1] = CK_AXI,
144 [_PCLK2] = CK_AXI,
145 [_PCLK3] = CK_AXI,
146 [_PCLK4] = CK_AXI,
147 [_PCLK5] = CK_AXI,
148 [_CK_PER] = CK_PER,
149 [_CK_MPU] = CK_MPU,
150 [_CK_MCU] = CK_MCU,
151 };
152
clock_id2parent_id(unsigned long id)153 static unsigned int clock_id2parent_id(unsigned long id)
154 {
155 unsigned int n;
156
157 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) {
158 if (parent_id_clock_id[n] == id) {
159 return n;
160 }
161 }
162
163 return _UNKNOWN_ID;
164 }
165
166 enum stm32mp1_pll_id {
167 _PLL1,
168 _PLL2,
169 _PLL3,
170 _PLL4,
171 _PLL_NB
172 };
173
174 enum stm32mp1_div_id {
175 _DIV_P,
176 _DIV_Q,
177 _DIV_R,
178 _DIV_NB,
179 };
180
181 enum stm32mp1_clksrc_id {
182 CLKSRC_MPU,
183 CLKSRC_AXI,
184 CLKSRC_MCU,
185 CLKSRC_PLL12,
186 CLKSRC_PLL3,
187 CLKSRC_PLL4,
188 CLKSRC_RTC,
189 CLKSRC_MCO1,
190 CLKSRC_MCO2,
191 CLKSRC_NB
192 };
193
194 enum stm32mp1_clkdiv_id {
195 CLKDIV_MPU,
196 CLKDIV_AXI,
197 CLKDIV_MCU,
198 CLKDIV_APB1,
199 CLKDIV_APB2,
200 CLKDIV_APB3,
201 CLKDIV_APB4,
202 CLKDIV_APB5,
203 CLKDIV_RTC,
204 CLKDIV_MCO1,
205 CLKDIV_MCO2,
206 CLKDIV_NB
207 };
208
209 enum stm32mp1_pllcfg {
210 PLLCFG_M,
211 PLLCFG_N,
212 PLLCFG_P,
213 PLLCFG_Q,
214 PLLCFG_R,
215 PLLCFG_O,
216 PLLCFG_NB
217 };
218
219 enum stm32mp1_pllcsg {
220 PLLCSG_MOD_PER,
221 PLLCSG_INC_STEP,
222 PLLCSG_SSCG_MODE,
223 PLLCSG_NB
224 };
225
226 enum stm32mp1_plltype {
227 PLL_800,
228 PLL_1600,
229 PLL_TYPE_NB
230 };
231
232 struct stm32mp1_pll {
233 uint8_t refclk_min;
234 uint8_t refclk_max;
235 };
236
237 struct stm32mp1_clk_gate {
238 uint16_t offset;
239 uint8_t bit;
240 uint8_t index;
241 uint8_t set_clr;
242 uint8_t secure;
243 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
244 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
245 };
246
247 struct stm32mp1_clk_sel {
248 uint16_t offset;
249 uint8_t src;
250 uint8_t msk;
251 uint8_t nb_parent;
252 const uint8_t *parent;
253 };
254
255 #define REFCLK_SIZE 4
256 struct stm32mp1_clk_pll {
257 enum stm32mp1_plltype plltype;
258 uint16_t rckxselr;
259 uint16_t pllxcfgr1;
260 uint16_t pllxcfgr2;
261 uint16_t pllxfracr;
262 uint16_t pllxcr;
263 uint16_t pllxcsgr;
264 enum stm32mp_osc_id refclk[REFCLK_SIZE];
265 };
266
267 /* Clocks with selectable source and non set/clr register access */
268 #define _CLK_SELEC(sec, off, b, idx, s) \
269 { \
270 .offset = (off), \
271 .bit = (b), \
272 .index = (idx), \
273 .set_clr = 0, \
274 .secure = (sec), \
275 .sel = (s), \
276 .fixed = _UNKNOWN_ID, \
277 }
278
279 /* Clocks with fixed source and non set/clr register access */
280 #define _CLK_FIXED(sec, off, b, idx, f) \
281 { \
282 .offset = (off), \
283 .bit = (b), \
284 .index = (idx), \
285 .set_clr = 0, \
286 .secure = (sec), \
287 .sel = _UNKNOWN_SEL, \
288 .fixed = (f), \
289 }
290
291 /* Clocks with selectable source and set/clr register access */
292 #define _CLK_SC_SELEC(sec, off, b, idx, s) \
293 { \
294 .offset = (off), \
295 .bit = (b), \
296 .index = (idx), \
297 .set_clr = 1, \
298 .secure = (sec), \
299 .sel = (s), \
300 .fixed = _UNKNOWN_ID, \
301 }
302
303 /* Clocks with fixed source and set/clr register access */
304 #define _CLK_SC_FIXED(sec, off, b, idx, f) \
305 { \
306 .offset = (off), \
307 .bit = (b), \
308 .index = (idx), \
309 .set_clr = 1, \
310 .secure = (sec), \
311 .sel = _UNKNOWN_SEL, \
312 .fixed = (f), \
313 }
314
315 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \
316 [_ ## _label ## _SEL] = { \
317 .offset = _rcc_selr, \
318 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \
319 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \
320 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \
321 .parent = (_parents), \
322 .nb_parent = ARRAY_SIZE(_parents) \
323 }
324
325 #define _CLK_PLL(idx, type, off1, off2, off3, \
326 off4, off5, off6, \
327 p1, p2, p3, p4) \
328 [(idx)] = { \
329 .plltype = (type), \
330 .rckxselr = (off1), \
331 .pllxcfgr1 = (off2), \
332 .pllxcfgr2 = (off3), \
333 .pllxfracr = (off4), \
334 .pllxcr = (off5), \
335 .pllxcsgr = (off6), \
336 .refclk[0] = (p1), \
337 .refclk[1] = (p2), \
338 .refclk[2] = (p3), \
339 .refclk[3] = (p4), \
340 }
341
342 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
343
344 #define SEC 1
345 #define N_S 0
346
347 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
348 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK),
349 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
350 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK),
351 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
352 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
353 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
354 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
355 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
356 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK),
357 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
358 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
359
360 #if defined(IMAGE_BL32)
361 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
362 #endif
363 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
364 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
373
374 #if defined(IMAGE_BL32)
375 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
376 #endif
377 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
378
379 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
380
381 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
382 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
383 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
384
385 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
386 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
387 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
388 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
389 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
390 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5),
393 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5),
394 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5),
395 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
396
397 #if defined(IMAGE_BL32)
398 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
399 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
400 #endif
401
402 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
403 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
409 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
410 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
411 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
412 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
413
414 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5),
415 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5),
416 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5),
417 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL),
418 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5),
419
420 #if defined(IMAGE_BL2)
421 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
422 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
423 #endif
424 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
425 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
426 #if defined(IMAGE_BL32)
427 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
428 #endif
429
430 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL),
431 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
432 };
433
434 static const uint8_t i2c12_parents[] = {
435 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
436 };
437
438 static const uint8_t i2c35_parents[] = {
439 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
440 };
441
442 static const uint8_t stgen_parents[] = {
443 _HSI_KER, _HSE_KER
444 };
445
446 static const uint8_t i2c46_parents[] = {
447 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
448 };
449
450 static const uint8_t spi6_parents[] = {
451 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
452 };
453
454 static const uint8_t usart1_parents[] = {
455 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
456 };
457
458 static const uint8_t rng1_parents[] = {
459 _CSI, _PLL4_R, _LSE, _LSI
460 };
461
462 static const uint8_t uart6_parents[] = {
463 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
464 };
465
466 static const uint8_t uart234578_parents[] = {
467 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
468 };
469
470 static const uint8_t sdmmc12_parents[] = {
471 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER
472 };
473
474 static const uint8_t sdmmc3_parents[] = {
475 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER
476 };
477
478 static const uint8_t qspi_parents[] = {
479 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
480 };
481
482 static const uint8_t fmc_parents[] = {
483 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
484 };
485
486 static const uint8_t axiss_parents[] = {
487 _HSI, _HSE, _PLL2_P
488 };
489
490 static const uint8_t mcuss_parents[] = {
491 _HSI, _HSE, _CSI, _PLL3_P
492 };
493
494 static const uint8_t usbphy_parents[] = {
495 _HSE_KER, _PLL4_R, _HSE_KER_DIV2
496 };
497
498 static const uint8_t usbo_parents[] = {
499 _PLL4_R, _USB_PHY_48
500 };
501
502 static const uint8_t mpu_parents[] = {
503 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */
504 };
505
506 static const uint8_t per_parents[] = {
507 _HSI, _HSE, _CSI,
508 };
509
510 static const uint8_t rtc_parents[] = {
511 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC
512 };
513
514 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
515 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
516 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
517 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents),
518 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents),
519 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
520 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
521 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
522 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents),
523 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents),
524 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
525 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
526 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
527 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
528 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents),
529 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents),
530 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
531 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
532 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
533 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents),
534 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents),
535 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
536 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
537 };
538
539 /* Define characteristic of PLL according type */
540 #define DIVN_MIN 24
541 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
542 [PLL_800] = {
543 .refclk_min = 4,
544 .refclk_max = 16,
545 },
546 [PLL_1600] = {
547 .refclk_min = 8,
548 .refclk_max = 16,
549 },
550 };
551
552 /* PLLNCFGR2 register divider by output */
553 static const uint8_t pllncfgr2[_DIV_NB] = {
554 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
555 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
556 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
557 };
558
559 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
560 _CLK_PLL(_PLL1, PLL_1600,
561 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
562 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
563 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
564 _CLK_PLL(_PLL2, PLL_1600,
565 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
566 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
567 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
568 _CLK_PLL(_PLL3, PLL_800,
569 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
570 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
571 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
572 _CLK_PLL(_PLL4, PLL_800,
573 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
574 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
575 _HSI, _HSE, _CSI, _I2S_CKIN),
576 };
577
578 /* Prescaler table lookups for clock computation */
579 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
580 static const uint8_t stm32mp1_mcu_div[16] = {
581 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
582 };
583
584 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
585 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
586 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
587 static const uint8_t stm32mp1_mpu_apbx_div[8] = {
588 0, 1, 2, 3, 4, 4, 4, 4
589 };
590
591 /* div = /1 /2 /3 /4 */
592 static const uint8_t stm32mp1_axi_div[8] = {
593 1, 2, 3, 4, 4, 4, 4, 4
594 };
595
596 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = {
597 [_HSI] = "HSI",
598 [_HSE] = "HSE",
599 [_CSI] = "CSI",
600 [_LSI] = "LSI",
601 [_LSE] = "LSE",
602 [_I2S_CKIN] = "I2S_CKIN",
603 [_HSI_KER] = "HSI_KER",
604 [_HSE_KER] = "HSE_KER",
605 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
606 [_HSE_RTC] = "HSE_RTC",
607 [_CSI_KER] = "CSI_KER",
608 [_PLL1_P] = "PLL1_P",
609 [_PLL1_Q] = "PLL1_Q",
610 [_PLL1_R] = "PLL1_R",
611 [_PLL2_P] = "PLL2_P",
612 [_PLL2_Q] = "PLL2_Q",
613 [_PLL2_R] = "PLL2_R",
614 [_PLL3_P] = "PLL3_P",
615 [_PLL3_Q] = "PLL3_Q",
616 [_PLL3_R] = "PLL3_R",
617 [_PLL4_P] = "PLL4_P",
618 [_PLL4_Q] = "PLL4_Q",
619 [_PLL4_R] = "PLL4_R",
620 [_ACLK] = "ACLK",
621 [_PCLK1] = "PCLK1",
622 [_PCLK2] = "PCLK2",
623 [_PCLK3] = "PCLK3",
624 [_PCLK4] = "PCLK4",
625 [_PCLK5] = "PCLK5",
626 [_HCLK6] = "KCLK6",
627 [_HCLK2] = "HCLK2",
628 [_CK_PER] = "CK_PER",
629 [_CK_MPU] = "CK_MPU",
630 [_CK_MCU] = "CK_MCU",
631 [_USB_PHY_48] = "USB_PHY_48",
632 };
633
634 /* RCC clock device driver private */
635 static unsigned long stm32mp1_osc[NB_OSC];
636 static struct spinlock reg_lock;
637 static unsigned int gate_refcounts[NB_GATES];
638 static struct spinlock refcount_lock;
639
gate_ref(unsigned int idx)640 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
641 {
642 return &stm32mp1_clk_gate[idx];
643 }
644
645 #if defined(IMAGE_BL32)
gate_is_non_secure(const struct stm32mp1_clk_gate * gate)646 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate)
647 {
648 return gate->secure == N_S;
649 }
650 #endif
651
clk_sel_ref(unsigned int idx)652 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
653 {
654 return &stm32mp1_clk_sel[idx];
655 }
656
pll_ref(unsigned int idx)657 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
658 {
659 return &stm32mp1_clk_pll[idx];
660 }
661
stm32mp1_clk_lock(struct spinlock * lock)662 static void stm32mp1_clk_lock(struct spinlock *lock)
663 {
664 if (stm32mp_lock_available()) {
665 /* Assume interrupts are masked */
666 spin_lock(lock);
667 }
668 }
669
stm32mp1_clk_unlock(struct spinlock * lock)670 static void stm32mp1_clk_unlock(struct spinlock *lock)
671 {
672 if (stm32mp_lock_available()) {
673 spin_unlock(lock);
674 }
675 }
676
stm32mp1_rcc_is_secure(void)677 bool stm32mp1_rcc_is_secure(void)
678 {
679 uintptr_t rcc_base = stm32mp_rcc_base();
680 uint32_t mask = RCC_TZCR_TZEN;
681
682 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
683 }
684
stm32mp1_rcc_is_mckprot(void)685 bool stm32mp1_rcc_is_mckprot(void)
686 {
687 uintptr_t rcc_base = stm32mp_rcc_base();
688 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT;
689
690 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
691 }
692
stm32mp1_clk_rcc_regs_lock(void)693 void stm32mp1_clk_rcc_regs_lock(void)
694 {
695 stm32mp1_clk_lock(®_lock);
696 }
697
stm32mp1_clk_rcc_regs_unlock(void)698 void stm32mp1_clk_rcc_regs_unlock(void)
699 {
700 stm32mp1_clk_unlock(®_lock);
701 }
702
stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)703 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)
704 {
705 if (idx >= NB_OSC) {
706 return 0;
707 }
708
709 return stm32mp1_osc[idx];
710 }
711
stm32mp1_clk_get_gated_id(unsigned long id)712 static int stm32mp1_clk_get_gated_id(unsigned long id)
713 {
714 unsigned int i;
715
716 for (i = 0U; i < NB_GATES; i++) {
717 if (gate_ref(i)->index == id) {
718 return i;
719 }
720 }
721
722 ERROR("%s: clk id %lu not found\n", __func__, id);
723
724 return -EINVAL;
725 }
726
stm32mp1_clk_get_sel(int i)727 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
728 {
729 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);
730 }
731
stm32mp1_clk_get_fixed_parent(int i)732 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
733 {
734 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed);
735 }
736
stm32mp1_clk_get_parent(unsigned long id)737 static int stm32mp1_clk_get_parent(unsigned long id)
738 {
739 const struct stm32mp1_clk_sel *sel;
740 uint32_t p_sel;
741 int i;
742 enum stm32mp1_parent_id p;
743 enum stm32mp1_parent_sel s;
744 uintptr_t rcc_base = stm32mp_rcc_base();
745
746 /* Few non gateable clock have a static parent ID, find them */
747 i = (int)clock_id2parent_id(id);
748 if (i != _UNKNOWN_ID) {
749 return i;
750 }
751
752 i = stm32mp1_clk_get_gated_id(id);
753 if (i < 0) {
754 panic();
755 }
756
757 p = stm32mp1_clk_get_fixed_parent(i);
758 if (p < _PARENT_NB) {
759 return (int)p;
760 }
761
762 s = stm32mp1_clk_get_sel(i);
763 if (s == _UNKNOWN_SEL) {
764 return -EINVAL;
765 }
766 if (s >= _PARENT_SEL_NB) {
767 panic();
768 }
769
770 sel = clk_sel_ref(s);
771 p_sel = (mmio_read_32(rcc_base + sel->offset) &
772 (sel->msk << sel->src)) >> sel->src;
773 if (p_sel < sel->nb_parent) {
774 return (int)sel->parent[p_sel];
775 }
776
777 return -EINVAL;
778 }
779
stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll * pll)780 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
781 {
782 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr);
783 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
784
785 return stm32mp1_clk_get_fixed(pll->refclk[src]);
786 }
787
788 /*
789 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
790 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
791 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
792 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
793 */
stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll * pll)794 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
795 {
796 unsigned long refclk, fvco;
797 uint32_t cfgr1, fracr, divm, divn;
798 uintptr_t rcc_base = stm32mp_rcc_base();
799
800 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
801 fracr = mmio_read_32(rcc_base + pll->pllxfracr);
802
803 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
804 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
805
806 refclk = stm32mp1_pll_get_fref(pll);
807
808 /*
809 * With FRACV :
810 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
811 * Without FRACV
812 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
813 */
814 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
815 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
816 RCC_PLLNFRACR_FRACV_SHIFT;
817 unsigned long long numerator, denominator;
818
819 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
820 numerator = refclk * numerator;
821 denominator = ((unsigned long long)divm + 1U) << 13;
822 fvco = (unsigned long)(numerator / denominator);
823 } else {
824 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
825 }
826
827 return fvco;
828 }
829
stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,enum stm32mp1_div_id div_id)830 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
831 enum stm32mp1_div_id div_id)
832 {
833 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
834 unsigned long dfout;
835 uint32_t cfgr2, divy;
836
837 if (div_id >= _DIV_NB) {
838 return 0;
839 }
840
841 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2);
842 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
843
844 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
845
846 return dfout;
847 }
848
get_clock_rate(int p)849 static unsigned long get_clock_rate(int p)
850 {
851 uint32_t reg, clkdiv;
852 unsigned long clock = 0;
853 uintptr_t rcc_base = stm32mp_rcc_base();
854
855 switch (p) {
856 case _CK_MPU:
857 /* MPU sub system */
858 reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
859 switch (reg & RCC_SELR_SRC_MASK) {
860 case RCC_MPCKSELR_HSI:
861 clock = stm32mp1_clk_get_fixed(_HSI);
862 break;
863 case RCC_MPCKSELR_HSE:
864 clock = stm32mp1_clk_get_fixed(_HSE);
865 break;
866 case RCC_MPCKSELR_PLL:
867 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
868 break;
869 case RCC_MPCKSELR_PLL_MPUDIV:
870 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
871
872 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
873 clkdiv = reg & RCC_MPUDIV_MASK;
874 clock >>= stm32mp1_mpu_div[clkdiv];
875 break;
876 default:
877 break;
878 }
879 break;
880 /* AXI sub system */
881 case _ACLK:
882 case _HCLK2:
883 case _HCLK6:
884 case _PCLK4:
885 case _PCLK5:
886 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
887 switch (reg & RCC_SELR_SRC_MASK) {
888 case RCC_ASSCKSELR_HSI:
889 clock = stm32mp1_clk_get_fixed(_HSI);
890 break;
891 case RCC_ASSCKSELR_HSE:
892 clock = stm32mp1_clk_get_fixed(_HSE);
893 break;
894 case RCC_ASSCKSELR_PLL:
895 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
896 break;
897 default:
898 break;
899 }
900
901 /* System clock divider */
902 reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
903 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
904
905 switch (p) {
906 case _PCLK4:
907 reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
908 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
909 break;
910 case _PCLK5:
911 reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
912 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
913 break;
914 default:
915 break;
916 }
917 break;
918 /* MCU sub system */
919 case _CK_MCU:
920 case _PCLK1:
921 case _PCLK2:
922 case _PCLK3:
923 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);
924 switch (reg & RCC_SELR_SRC_MASK) {
925 case RCC_MSSCKSELR_HSI:
926 clock = stm32mp1_clk_get_fixed(_HSI);
927 break;
928 case RCC_MSSCKSELR_HSE:
929 clock = stm32mp1_clk_get_fixed(_HSE);
930 break;
931 case RCC_MSSCKSELR_CSI:
932 clock = stm32mp1_clk_get_fixed(_CSI);
933 break;
934 case RCC_MSSCKSELR_PLL:
935 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
936 break;
937 default:
938 break;
939 }
940
941 /* MCU clock divider */
942 reg = mmio_read_32(rcc_base + RCC_MCUDIVR);
943 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
944
945 switch (p) {
946 case _PCLK1:
947 reg = mmio_read_32(rcc_base + RCC_APB1DIVR);
948 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
949 break;
950 case _PCLK2:
951 reg = mmio_read_32(rcc_base + RCC_APB2DIVR);
952 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
953 break;
954 case _PCLK3:
955 reg = mmio_read_32(rcc_base + RCC_APB3DIVR);
956 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
957 break;
958 case _CK_MCU:
959 default:
960 break;
961 }
962 break;
963 case _CK_PER:
964 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
965 switch (reg & RCC_SELR_SRC_MASK) {
966 case RCC_CPERCKSELR_HSI:
967 clock = stm32mp1_clk_get_fixed(_HSI);
968 break;
969 case RCC_CPERCKSELR_HSE:
970 clock = stm32mp1_clk_get_fixed(_HSE);
971 break;
972 case RCC_CPERCKSELR_CSI:
973 clock = stm32mp1_clk_get_fixed(_CSI);
974 break;
975 default:
976 break;
977 }
978 break;
979 case _HSI:
980 case _HSI_KER:
981 clock = stm32mp1_clk_get_fixed(_HSI);
982 break;
983 case _CSI:
984 case _CSI_KER:
985 clock = stm32mp1_clk_get_fixed(_CSI);
986 break;
987 case _HSE:
988 case _HSE_KER:
989 clock = stm32mp1_clk_get_fixed(_HSE);
990 break;
991 case _HSE_KER_DIV2:
992 clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
993 break;
994 case _HSE_RTC:
995 clock = stm32mp1_clk_get_fixed(_HSE);
996 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;
997 break;
998 case _LSI:
999 clock = stm32mp1_clk_get_fixed(_LSI);
1000 break;
1001 case _LSE:
1002 clock = stm32mp1_clk_get_fixed(_LSE);
1003 break;
1004 /* PLL */
1005 case _PLL1_P:
1006 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
1007 break;
1008 case _PLL1_Q:
1009 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
1010 break;
1011 case _PLL1_R:
1012 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
1013 break;
1014 case _PLL2_P:
1015 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
1016 break;
1017 case _PLL2_Q:
1018 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
1019 break;
1020 case _PLL2_R:
1021 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
1022 break;
1023 case _PLL3_P:
1024 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
1025 break;
1026 case _PLL3_Q:
1027 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
1028 break;
1029 case _PLL3_R:
1030 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
1031 break;
1032 case _PLL4_P:
1033 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
1034 break;
1035 case _PLL4_Q:
1036 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
1037 break;
1038 case _PLL4_R:
1039 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
1040 break;
1041 /* Other */
1042 case _USB_PHY_48:
1043 clock = USB_PHY_48_MHZ;
1044 break;
1045 default:
1046 break;
1047 }
1048
1049 return clock;
1050 }
1051
__clk_enable(struct stm32mp1_clk_gate const * gate)1052 static void __clk_enable(struct stm32mp1_clk_gate const *gate)
1053 {
1054 uintptr_t rcc_base = stm32mp_rcc_base();
1055
1056 VERBOSE("Enable clock %u\n", gate->index);
1057
1058 if (gate->set_clr != 0U) {
1059 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
1060 } else {
1061 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
1062 }
1063 }
1064
__clk_disable(struct stm32mp1_clk_gate const * gate)1065 static void __clk_disable(struct stm32mp1_clk_gate const *gate)
1066 {
1067 uintptr_t rcc_base = stm32mp_rcc_base();
1068
1069 VERBOSE("Disable clock %u\n", gate->index);
1070
1071 if (gate->set_clr != 0U) {
1072 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
1073 BIT(gate->bit));
1074 } else {
1075 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
1076 }
1077 }
1078
__clk_is_enabled(struct stm32mp1_clk_gate const * gate)1079 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate)
1080 {
1081 uintptr_t rcc_base = stm32mp_rcc_base();
1082
1083 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
1084 }
1085
1086 /* Oscillators and PLLs are not gated at runtime */
clock_is_always_on(unsigned long id)1087 static bool clock_is_always_on(unsigned long id)
1088 {
1089 switch (id) {
1090 case CK_HSE:
1091 case CK_CSI:
1092 case CK_LSI:
1093 case CK_LSE:
1094 case CK_HSI:
1095 case CK_HSE_DIV2:
1096 case PLL1_Q:
1097 case PLL1_R:
1098 case PLL2_P:
1099 case PLL2_Q:
1100 case PLL2_R:
1101 case PLL3_P:
1102 case PLL3_Q:
1103 case PLL3_R:
1104 case CK_AXI:
1105 case CK_MPU:
1106 case CK_MCU:
1107 case RTC:
1108 return true;
1109 default:
1110 return false;
1111 }
1112 }
1113
__stm32mp1_clk_enable(unsigned long id,bool with_refcnt)1114 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt)
1115 {
1116 const struct stm32mp1_clk_gate *gate;
1117 int i;
1118
1119 if (clock_is_always_on(id)) {
1120 return;
1121 }
1122
1123 i = stm32mp1_clk_get_gated_id(id);
1124 if (i < 0) {
1125 ERROR("Clock %lu can't be enabled\n", id);
1126 panic();
1127 }
1128
1129 gate = gate_ref(i);
1130
1131 if (!with_refcnt) {
1132 __clk_enable(gate);
1133 return;
1134 }
1135
1136 #if defined(IMAGE_BL32)
1137 if (gate_is_non_secure(gate)) {
1138 /* Enable non-secure clock w/o any refcounting */
1139 __clk_enable(gate);
1140 return;
1141 }
1142 #endif
1143
1144 stm32mp1_clk_lock(&refcount_lock);
1145
1146 if (gate_refcounts[i] == 0U) {
1147 __clk_enable(gate);
1148 }
1149
1150 gate_refcounts[i]++;
1151 if (gate_refcounts[i] == UINT_MAX) {
1152 ERROR("Clock %lu refcount reached max value\n", id);
1153 panic();
1154 }
1155
1156 stm32mp1_clk_unlock(&refcount_lock);
1157 }
1158
__stm32mp1_clk_disable(unsigned long id,bool with_refcnt)1159 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt)
1160 {
1161 const struct stm32mp1_clk_gate *gate;
1162 int i;
1163
1164 if (clock_is_always_on(id)) {
1165 return;
1166 }
1167
1168 i = stm32mp1_clk_get_gated_id(id);
1169 if (i < 0) {
1170 ERROR("Clock %lu can't be disabled\n", id);
1171 panic();
1172 }
1173
1174 gate = gate_ref(i);
1175
1176 if (!with_refcnt) {
1177 __clk_disable(gate);
1178 return;
1179 }
1180
1181 #if defined(IMAGE_BL32)
1182 if (gate_is_non_secure(gate)) {
1183 /* Don't disable non-secure clocks */
1184 return;
1185 }
1186 #endif
1187
1188 stm32mp1_clk_lock(&refcount_lock);
1189
1190 if (gate_refcounts[i] == 0U) {
1191 ERROR("Clock %lu refcount reached 0\n", id);
1192 panic();
1193 }
1194 gate_refcounts[i]--;
1195
1196 if (gate_refcounts[i] == 0U) {
1197 __clk_disable(gate);
1198 }
1199
1200 stm32mp1_clk_unlock(&refcount_lock);
1201 }
1202
stm32mp_clk_enable(unsigned long id)1203 static int stm32mp_clk_enable(unsigned long id)
1204 {
1205 __stm32mp1_clk_enable(id, true);
1206
1207 return 0;
1208 }
1209
stm32mp_clk_disable(unsigned long id)1210 static void stm32mp_clk_disable(unsigned long id)
1211 {
1212 __stm32mp1_clk_disable(id, true);
1213 }
1214
stm32mp_clk_is_enabled(unsigned long id)1215 static bool stm32mp_clk_is_enabled(unsigned long id)
1216 {
1217 int i;
1218
1219 if (clock_is_always_on(id)) {
1220 return true;
1221 }
1222
1223 i = stm32mp1_clk_get_gated_id(id);
1224 if (i < 0) {
1225 panic();
1226 }
1227
1228 return __clk_is_enabled(gate_ref(i));
1229 }
1230
stm32mp_clk_get_rate(unsigned long id)1231 static unsigned long stm32mp_clk_get_rate(unsigned long id)
1232 {
1233 uintptr_t rcc_base = stm32mp_rcc_base();
1234 int p = stm32mp1_clk_get_parent(id);
1235 uint32_t prescaler, timpre;
1236 unsigned long parent_rate;
1237
1238 if (p < 0) {
1239 return 0;
1240 }
1241
1242 parent_rate = get_clock_rate(p);
1243
1244 switch (id) {
1245 case TIM2_K:
1246 case TIM3_K:
1247 case TIM4_K:
1248 case TIM5_K:
1249 case TIM6_K:
1250 case TIM7_K:
1251 case TIM12_K:
1252 case TIM13_K:
1253 case TIM14_K:
1254 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &
1255 RCC_APBXDIV_MASK;
1256 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &
1257 RCC_TIMGXPRER_TIMGXPRE;
1258 break;
1259
1260 case TIM1_K:
1261 case TIM8_K:
1262 case TIM15_K:
1263 case TIM16_K:
1264 case TIM17_K:
1265 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &
1266 RCC_APBXDIV_MASK;
1267 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &
1268 RCC_TIMGXPRER_TIMGXPRE;
1269 break;
1270
1271 default:
1272 return parent_rate;
1273 }
1274
1275 if (prescaler == 0U) {
1276 return parent_rate;
1277 }
1278
1279 return parent_rate * (timpre + 1U) * 2U;
1280 }
1281
stm32mp1_ls_osc_set(bool enable,uint32_t offset,uint32_t mask_on)1282 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
1283 {
1284 uintptr_t address = stm32mp_rcc_base() + offset;
1285
1286 if (enable) {
1287 mmio_setbits_32(address, mask_on);
1288 } else {
1289 mmio_clrbits_32(address, mask_on);
1290 }
1291 }
1292
stm32mp1_hs_ocs_set(bool enable,uint32_t mask_on)1293 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on)
1294 {
1295 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR;
1296 uintptr_t address = stm32mp_rcc_base() + offset;
1297
1298 mmio_write_32(address, mask_on);
1299 }
1300
stm32mp1_osc_wait(bool enable,uint32_t offset,uint32_t mask_rdy)1301 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy)
1302 {
1303 uint64_t timeout;
1304 uint32_t mask_test;
1305 uintptr_t address = stm32mp_rcc_base() + offset;
1306
1307 if (enable) {
1308 mask_test = mask_rdy;
1309 } else {
1310 mask_test = 0;
1311 }
1312
1313 timeout = timeout_init_us(OSCRDY_TIMEOUT);
1314 while ((mmio_read_32(address) & mask_rdy) != mask_test) {
1315 if (timeout_elapsed(timeout)) {
1316 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n",
1317 mask_rdy, address, enable, mmio_read_32(address));
1318 return -ETIMEDOUT;
1319 }
1320 }
1321
1322 return 0;
1323 }
1324
stm32mp1_lse_enable(bool bypass,bool digbyp,uint32_t lsedrv)1325 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv)
1326 {
1327 uint32_t value;
1328 uintptr_t rcc_base = stm32mp_rcc_base();
1329
1330 if (digbyp) {
1331 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
1332 }
1333
1334 if (bypass || digbyp) {
1335 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
1336 }
1337
1338 /*
1339 * Warning: not recommended to switch directly from "high drive"
1340 * to "medium low drive", and vice-versa.
1341 */
1342 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
1343 RCC_BDCR_LSEDRV_SHIFT;
1344
1345 while (value != lsedrv) {
1346 if (value > lsedrv) {
1347 value--;
1348 } else {
1349 value++;
1350 }
1351
1352 mmio_clrsetbits_32(rcc_base + RCC_BDCR,
1353 RCC_BDCR_LSEDRV_MASK,
1354 value << RCC_BDCR_LSEDRV_SHIFT);
1355 }
1356
1357 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON);
1358 }
1359
stm32mp1_lse_wait(void)1360 static void stm32mp1_lse_wait(void)
1361 {
1362 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
1363 VERBOSE("%s: failed\n", __func__);
1364 }
1365 }
1366
stm32mp1_lsi_set(bool enable)1367 static void stm32mp1_lsi_set(bool enable)
1368 {
1369 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
1370
1371 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
1372 VERBOSE("%s: failed\n", __func__);
1373 }
1374 }
1375
stm32mp1_hse_enable(bool bypass,bool digbyp,bool css)1376 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css)
1377 {
1378 uintptr_t rcc_base = stm32mp_rcc_base();
1379
1380 if (digbyp) {
1381 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
1382 }
1383
1384 if (bypass || digbyp) {
1385 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1386 }
1387
1388 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
1389 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
1390 VERBOSE("%s: failed\n", __func__);
1391 }
1392
1393 if (css) {
1394 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1395 }
1396
1397 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
1398 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) &&
1399 (!(digbyp || bypass))) {
1400 panic();
1401 }
1402 #endif
1403 }
1404
stm32mp1_csi_set(bool enable)1405 static void stm32mp1_csi_set(bool enable)
1406 {
1407 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
1408 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
1409 VERBOSE("%s: failed\n", __func__);
1410 }
1411 }
1412
stm32mp1_hsi_set(bool enable)1413 static void stm32mp1_hsi_set(bool enable)
1414 {
1415 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
1416 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
1417 VERBOSE("%s: failed\n", __func__);
1418 }
1419 }
1420
stm32mp1_set_hsidiv(uint8_t hsidiv)1421 static int stm32mp1_set_hsidiv(uint8_t hsidiv)
1422 {
1423 uint64_t timeout;
1424 uintptr_t rcc_base = stm32mp_rcc_base();
1425 uintptr_t address = rcc_base + RCC_OCRDYR;
1426
1427 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
1428 RCC_HSICFGR_HSIDIV_MASK,
1429 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
1430
1431 timeout = timeout_init_us(HSIDIV_TIMEOUT);
1432 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
1433 if (timeout_elapsed(timeout)) {
1434 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
1435 address, mmio_read_32(address));
1436 return -ETIMEDOUT;
1437 }
1438 }
1439
1440 return 0;
1441 }
1442
stm32mp1_hsidiv(unsigned long hsifreq)1443 static int stm32mp1_hsidiv(unsigned long hsifreq)
1444 {
1445 uint8_t hsidiv;
1446 uint32_t hsidivfreq = MAX_HSI_HZ;
1447
1448 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1449 if (hsidivfreq == hsifreq) {
1450 break;
1451 }
1452
1453 hsidivfreq /= 2U;
1454 }
1455
1456 if (hsidiv == 4U) {
1457 ERROR("Invalid clk-hsi frequency\n");
1458 return -1;
1459 }
1460
1461 if (hsidiv != 0U) {
1462 return stm32mp1_set_hsidiv(hsidiv);
1463 }
1464
1465 return 0;
1466 }
1467
stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,unsigned int clksrc,uint32_t * pllcfg,int plloff)1468 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
1469 unsigned int clksrc,
1470 uint32_t *pllcfg, int plloff)
1471 {
1472 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1473 uintptr_t rcc_base = stm32mp_rcc_base();
1474 uintptr_t pllxcr = rcc_base + pll->pllxcr;
1475 enum stm32mp1_plltype type = pll->plltype;
1476 uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
1477 unsigned long refclk;
1478 uint32_t ifrge = 0U;
1479 uint32_t src, value, fracv = 0;
1480 void *fdt;
1481
1482 /* Check PLL output */
1483 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
1484 return false;
1485 }
1486
1487 /* Check current clksrc */
1488 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK;
1489 if (src != (clksrc & RCC_SELR_SRC_MASK)) {
1490 return false;
1491 }
1492
1493 /* Check Div */
1494 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
1495
1496 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1497 (pllcfg[PLLCFG_M] + 1U);
1498
1499 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1500 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1501 return false;
1502 }
1503
1504 if ((type == PLL_800) && (refclk >= 8000000U)) {
1505 ifrge = 1U;
1506 }
1507
1508 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1509 RCC_PLLNCFGR1_DIVN_MASK;
1510 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1511 RCC_PLLNCFGR1_DIVM_MASK;
1512 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1513 RCC_PLLNCFGR1_IFRGE_MASK;
1514 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
1515 return false;
1516 }
1517
1518 /* Fractional configuration */
1519 if (fdt_get_address(&fdt) == 1) {
1520 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
1521 }
1522
1523 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1524 value |= RCC_PLLNFRACR_FRACLE;
1525 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
1526 return false;
1527 }
1528
1529 /* Output config */
1530 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1531 RCC_PLLNCFGR2_DIVP_MASK;
1532 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1533 RCC_PLLNCFGR2_DIVQ_MASK;
1534 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1535 RCC_PLLNCFGR2_DIVR_MASK;
1536 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
1537 return false;
1538 }
1539
1540 return true;
1541 }
1542
stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)1543 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)
1544 {
1545 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1546 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1547
1548 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1549 mmio_clrsetbits_32(pllxcr,
1550 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1551 RCC_PLLNCR_DIVREN,
1552 RCC_PLLNCR_PLLON);
1553 }
1554
stm32mp1_pll_output(enum stm32mp1_pll_id pll_id,uint32_t output)1555 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
1556 {
1557 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1558 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1559 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1560
1561 /* Wait PLL lock */
1562 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
1563 if (timeout_elapsed(timeout)) {
1564 ERROR("PLL%u start failed @ 0x%lx: 0x%x\n",
1565 pll_id, pllxcr, mmio_read_32(pllxcr));
1566 return -ETIMEDOUT;
1567 }
1568 }
1569
1570 /* Start the requested output */
1571 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1572
1573 return 0;
1574 }
1575
stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)1576 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)
1577 {
1578 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1579 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1580 uint64_t timeout;
1581
1582 /* Stop all output */
1583 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1584 RCC_PLLNCR_DIVREN);
1585
1586 /* Stop PLL */
1587 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
1588
1589 timeout = timeout_init_us(PLLRDY_TIMEOUT);
1590 /* Wait PLL stopped */
1591 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
1592 if (timeout_elapsed(timeout)) {
1593 ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n",
1594 pll_id, pllxcr, mmio_read_32(pllxcr));
1595 return -ETIMEDOUT;
1596 }
1597 }
1598
1599 return 0;
1600 }
1601
stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,uint32_t * pllcfg)1602 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,
1603 uint32_t *pllcfg)
1604 {
1605 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1606 uintptr_t rcc_base = stm32mp_rcc_base();
1607 uint32_t value;
1608
1609 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1610 RCC_PLLNCFGR2_DIVP_MASK;
1611 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1612 RCC_PLLNCFGR2_DIVQ_MASK;
1613 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1614 RCC_PLLNCFGR2_DIVR_MASK;
1615 mmio_write_32(rcc_base + pll->pllxcfgr2, value);
1616 }
1617
stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,uint32_t * pllcfg,uint32_t fracv)1618 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,
1619 uint32_t *pllcfg, uint32_t fracv)
1620 {
1621 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1622 uintptr_t rcc_base = stm32mp_rcc_base();
1623 enum stm32mp1_plltype type = pll->plltype;
1624 unsigned long refclk;
1625 uint32_t ifrge = 0;
1626 uint32_t src, value;
1627
1628 src = mmio_read_32(rcc_base + pll->rckxselr) &
1629 RCC_SELR_REFCLK_SRC_MASK;
1630
1631 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1632 (pllcfg[PLLCFG_M] + 1U);
1633
1634 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1635 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1636 return -EINVAL;
1637 }
1638
1639 if ((type == PLL_800) && (refclk >= 8000000U)) {
1640 ifrge = 1U;
1641 }
1642
1643 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1644 RCC_PLLNCFGR1_DIVN_MASK;
1645 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1646 RCC_PLLNCFGR1_DIVM_MASK;
1647 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1648 RCC_PLLNCFGR1_IFRGE_MASK;
1649 mmio_write_32(rcc_base + pll->pllxcfgr1, value);
1650
1651 /* Fractional configuration */
1652 value = 0;
1653 mmio_write_32(rcc_base + pll->pllxfracr, value);
1654
1655 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1656 mmio_write_32(rcc_base + pll->pllxfracr, value);
1657
1658 value |= RCC_PLLNFRACR_FRACLE;
1659 mmio_write_32(rcc_base + pll->pllxfracr, value);
1660
1661 stm32mp1_pll_config_output(pll_id, pllcfg);
1662
1663 return 0;
1664 }
1665
stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id,uint32_t * csg)1666 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg)
1667 {
1668 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1669 uint32_t pllxcsg = 0;
1670
1671 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1672 RCC_PLLNCSGR_MOD_PER_MASK;
1673
1674 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1675 RCC_PLLNCSGR_INC_STEP_MASK;
1676
1677 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1678 RCC_PLLNCSGR_SSCG_MODE_MASK;
1679
1680 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
1681
1682 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr,
1683 RCC_PLLNCR_SSCG_CTRL);
1684 }
1685
stm32mp1_set_clksrc(unsigned int clksrc)1686 static int stm32mp1_set_clksrc(unsigned int clksrc)
1687 {
1688 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
1689 uint64_t timeout;
1690
1691 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK,
1692 clksrc & RCC_SELR_SRC_MASK);
1693
1694 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1695 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) {
1696 if (timeout_elapsed(timeout)) {
1697 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc,
1698 clksrc_address, mmio_read_32(clksrc_address));
1699 return -ETIMEDOUT;
1700 }
1701 }
1702
1703 return 0;
1704 }
1705
stm32mp1_set_clkdiv(unsigned int clkdiv,uintptr_t address)1706 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address)
1707 {
1708 uint64_t timeout;
1709
1710 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
1711 clkdiv & RCC_DIVR_DIV_MASK);
1712
1713 timeout = timeout_init_us(CLKDIV_TIMEOUT);
1714 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
1715 if (timeout_elapsed(timeout)) {
1716 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n",
1717 clkdiv, address, mmio_read_32(address));
1718 return -ETIMEDOUT;
1719 }
1720 }
1721
1722 return 0;
1723 }
1724
stm32mp1_mco_csg(uint32_t clksrc,uint32_t clkdiv)1725 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv)
1726 {
1727 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
1728
1729 /*
1730 * Binding clksrc :
1731 * bit15-4 offset
1732 * bit3: disable
1733 * bit2-0: MCOSEL[2:0]
1734 */
1735 if ((clksrc & 0x8U) != 0U) {
1736 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON);
1737 } else {
1738 mmio_clrsetbits_32(clksrc_address,
1739 RCC_MCOCFG_MCOSRC_MASK,
1740 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1741 mmio_clrsetbits_32(clksrc_address,
1742 RCC_MCOCFG_MCODIV_MASK,
1743 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1744 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON);
1745 }
1746 }
1747
stm32mp1_set_rtcsrc(unsigned int clksrc,bool lse_css)1748 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
1749 {
1750 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
1751
1752 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
1753 (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
1754 mmio_clrsetbits_32(address,
1755 RCC_BDCR_RTCSRC_MASK,
1756 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
1757
1758 mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
1759 }
1760
1761 if (lse_css) {
1762 mmio_setbits_32(address, RCC_BDCR_LSECSSON);
1763 }
1764 }
1765
stm32mp1_pkcs_config(uint32_t pkcs)1766 static void stm32mp1_pkcs_config(uint32_t pkcs)
1767 {
1768 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU);
1769 uint32_t value = pkcs & 0xFU;
1770 uint32_t mask = 0xFU;
1771
1772 if ((pkcs & BIT(31)) != 0U) {
1773 mask <<= 4;
1774 value <<= 4;
1775 }
1776
1777 mmio_clrsetbits_32(address, mask, value);
1778 }
1779
clk_get_pll_settings_from_dt(int plloff,unsigned int * pllcfg,uint32_t * fracv,uint32_t * csg,bool * csg_set)1780 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg,
1781 uint32_t *fracv, uint32_t *csg,
1782 bool *csg_set)
1783 {
1784 void *fdt;
1785 int ret;
1786
1787 if (fdt_get_address(&fdt) == 0) {
1788 return -FDT_ERR_NOTFOUND;
1789 }
1790
1791 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB,
1792 pllcfg);
1793 if (ret < 0) {
1794 return -FDT_ERR_NOTFOUND;
1795 }
1796
1797 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
1798
1799 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB,
1800 csg);
1801
1802 *csg_set = (ret == 0);
1803
1804 if (ret == -FDT_ERR_NOTFOUND) {
1805 ret = 0;
1806 }
1807
1808 return ret;
1809 }
1810
stm32mp1_clk_init(void)1811 int stm32mp1_clk_init(void)
1812 {
1813 uintptr_t rcc_base = stm32mp_rcc_base();
1814 uint32_t pllfracv[_PLL_NB];
1815 uint32_t pllcsg[_PLL_NB][PLLCSG_NB];
1816 unsigned int clksrc[CLKSRC_NB];
1817 unsigned int clkdiv[CLKDIV_NB];
1818 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1819 int plloff[_PLL_NB];
1820 int ret, len;
1821 enum stm32mp1_pll_id i;
1822 bool pllcsg_set[_PLL_NB];
1823 bool pllcfg_valid[_PLL_NB];
1824 bool lse_css = false;
1825 bool pll3_preserve = false;
1826 bool pll4_preserve = false;
1827 bool pll4_bootrom = false;
1828 const fdt32_t *pkcs_cell;
1829 void *fdt;
1830 int stgen_p = stm32mp1_clk_get_parent(STGEN_K);
1831 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K);
1832
1833 if (fdt_get_address(&fdt) == 0) {
1834 return -FDT_ERR_NOTFOUND;
1835 }
1836
1837 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
1838 clksrc);
1839 if (ret < 0) {
1840 return -FDT_ERR_NOTFOUND;
1841 }
1842
1843 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB,
1844 clkdiv);
1845 if (ret < 0) {
1846 return -FDT_ERR_NOTFOUND;
1847 }
1848
1849 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1850 char name[12];
1851
1852 snprintf(name, sizeof(name), "st,pll@%u", i);
1853 plloff[i] = fdt_rcc_subnode_offset(name);
1854
1855 pllcfg_valid[i] = fdt_check_node(plloff[i]);
1856 if (!pllcfg_valid[i]) {
1857 continue;
1858 }
1859
1860 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
1861 &pllfracv[i], pllcsg[i],
1862 &pllcsg_set[i]);
1863 if (ret != 0) {
1864 return ret;
1865 }
1866 }
1867
1868 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1869 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1870
1871 /*
1872 * Switch ON oscillator found in device-tree.
1873 * Note: HSI already ON after BootROM stage.
1874 */
1875 if (stm32mp1_osc[_LSI] != 0U) {
1876 stm32mp1_lsi_set(true);
1877 }
1878 if (stm32mp1_osc[_LSE] != 0U) {
1879 const char *name = stm32mp_osc_node_label[_LSE];
1880 bool bypass, digbyp;
1881 uint32_t lsedrv;
1882
1883 bypass = fdt_clk_read_bool(name, "st,bypass");
1884 digbyp = fdt_clk_read_bool(name, "st,digbypass");
1885 lse_css = fdt_clk_read_bool(name, "st,css");
1886 lsedrv = fdt_clk_read_uint32_default(name, "st,drive",
1887 LSEDRV_MEDIUM_HIGH);
1888 stm32mp1_lse_enable(bypass, digbyp, lsedrv);
1889 }
1890 if (stm32mp1_osc[_HSE] != 0U) {
1891 const char *name = stm32mp_osc_node_label[_HSE];
1892 bool bypass, digbyp, css;
1893
1894 bypass = fdt_clk_read_bool(name, "st,bypass");
1895 digbyp = fdt_clk_read_bool(name, "st,digbypass");
1896 css = fdt_clk_read_bool(name, "st,css");
1897 stm32mp1_hse_enable(bypass, digbyp, css);
1898 }
1899 /*
1900 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1901 * => switch on CSI even if node is not present in device tree
1902 */
1903 stm32mp1_csi_set(true);
1904
1905 /* Come back to HSI */
1906 ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
1907 if (ret != 0) {
1908 return ret;
1909 }
1910 ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
1911 if (ret != 0) {
1912 return ret;
1913 }
1914 ret = stm32mp1_set_clksrc(CLK_MCU_HSI);
1915 if (ret != 0) {
1916 return ret;
1917 }
1918
1919 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
1920 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
1921 if (pllcfg_valid[_PLL3]) {
1922 pll3_preserve =
1923 stm32mp1_check_pll_conf(_PLL3,
1924 clksrc[CLKSRC_PLL3],
1925 pllcfg[_PLL3],
1926 plloff[_PLL3]);
1927 }
1928
1929 if (pllcfg_valid[_PLL4]) {
1930 pll4_preserve =
1931 stm32mp1_check_pll_conf(_PLL4,
1932 clksrc[CLKSRC_PLL4],
1933 pllcfg[_PLL4],
1934 plloff[_PLL4]);
1935 }
1936 }
1937 /* Don't initialize PLL4, when used by BOOTROM */
1938 if ((stm32mp_get_boot_itf_selected() ==
1939 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) &&
1940 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) {
1941 pll4_bootrom = true;
1942 pll4_preserve = true;
1943 }
1944
1945 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1946 if (((i == _PLL3) && pll3_preserve) ||
1947 ((i == _PLL4) && pll4_preserve)) {
1948 continue;
1949 }
1950
1951 ret = stm32mp1_pll_stop(i);
1952 if (ret != 0) {
1953 return ret;
1954 }
1955 }
1956
1957 /* Configure HSIDIV */
1958 if (stm32mp1_osc[_HSI] != 0U) {
1959 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
1960 if (ret != 0) {
1961 return ret;
1962 }
1963
1964 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
1965 }
1966
1967 /* Select DIV */
1968 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1969 mmio_write_32(rcc_base + RCC_MPCKDIVR,
1970 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
1971 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
1972 if (ret != 0) {
1973 return ret;
1974 }
1975 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
1976 if (ret != 0) {
1977 return ret;
1978 }
1979 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
1980 if (ret != 0) {
1981 return ret;
1982 }
1983 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
1984 if (ret != 0) {
1985 return ret;
1986 }
1987 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
1988 if (ret != 0) {
1989 return ret;
1990 }
1991 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
1992 if (ret != 0) {
1993 return ret;
1994 }
1995 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
1996 if (ret != 0) {
1997 return ret;
1998 }
1999
2000 /* No ready bit for RTC */
2001 mmio_write_32(rcc_base + RCC_RTCDIVR,
2002 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
2003
2004 /* Configure PLLs source */
2005 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
2006 if (ret != 0) {
2007 return ret;
2008 }
2009
2010 if (!pll3_preserve) {
2011 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
2012 if (ret != 0) {
2013 return ret;
2014 }
2015 }
2016
2017 if (!pll4_preserve) {
2018 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
2019 if (ret != 0) {
2020 return ret;
2021 }
2022 }
2023
2024 /* Configure and start PLLs */
2025 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
2026 if (((i == _PLL3) && pll3_preserve) ||
2027 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
2028 continue;
2029 }
2030
2031 if (!pllcfg_valid[i]) {
2032 continue;
2033 }
2034
2035 if ((i == _PLL4) && pll4_bootrom) {
2036 /* Set output divider if not done by the Bootrom */
2037 stm32mp1_pll_config_output(i, pllcfg[i]);
2038 continue;
2039 }
2040
2041 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]);
2042 if (ret != 0) {
2043 return ret;
2044 }
2045
2046 if (pllcsg_set[i]) {
2047 stm32mp1_pll_csg(i, pllcsg[i]);
2048 }
2049
2050 stm32mp1_pll_start(i);
2051 }
2052 /* Wait and start PLLs output when ready */
2053 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
2054 if (!pllcfg_valid[i]) {
2055 continue;
2056 }
2057
2058 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
2059 if (ret != 0) {
2060 return ret;
2061 }
2062 }
2063 /* Wait LSE ready before to use it */
2064 if (stm32mp1_osc[_LSE] != 0U) {
2065 stm32mp1_lse_wait();
2066 }
2067
2068 /* Configure with expected clock source */
2069 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
2070 if (ret != 0) {
2071 return ret;
2072 }
2073 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
2074 if (ret != 0) {
2075 return ret;
2076 }
2077 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]);
2078 if (ret != 0) {
2079 return ret;
2080 }
2081 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css);
2082
2083 /* Configure PKCK */
2084 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
2085 if (pkcs_cell != NULL) {
2086 bool ckper_disabled = false;
2087 uint32_t j;
2088 uint32_t usbreg_bootrom = 0U;
2089
2090 if (pll4_bootrom) {
2091 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR);
2092 }
2093
2094 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
2095 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
2096
2097 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) {
2098 ckper_disabled = true;
2099 continue;
2100 }
2101 stm32mp1_pkcs_config(pkcs);
2102 }
2103
2104 /*
2105 * CKPER is source for some peripheral clocks
2106 * (FMC-NAND / QPSI-NOR) and switching source is allowed
2107 * only if previous clock is still ON
2108 * => deactivated CKPER only after switching clock
2109 */
2110 if (ckper_disabled) {
2111 stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
2112 }
2113
2114 if (pll4_bootrom) {
2115 uint32_t usbreg_value, usbreg_mask;
2116 const struct stm32mp1_clk_sel *sel;
2117
2118 sel = clk_sel_ref(_USBPHY_SEL);
2119 usbreg_mask = (uint32_t)sel->msk << sel->src;
2120 sel = clk_sel_ref(_USBO_SEL);
2121 usbreg_mask |= (uint32_t)sel->msk << sel->src;
2122
2123 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) &
2124 usbreg_mask;
2125 usbreg_bootrom &= usbreg_mask;
2126 if (usbreg_bootrom != usbreg_value) {
2127 VERBOSE("forbidden new USB clk path\n");
2128 VERBOSE("vs bootrom on USB boot\n");
2129 return -FDT_ERR_BADVALUE;
2130 }
2131 }
2132 }
2133
2134 /* Switch OFF HSI if not found in device-tree */
2135 if (stm32mp1_osc[_HSI] == 0U) {
2136 stm32mp1_hsi_set(false);
2137 }
2138
2139 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
2140
2141 /* Software Self-Refresh mode (SSR) during DDR initilialization */
2142 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
2143 RCC_DDRITFCR_DDRCKMOD_MASK,
2144 RCC_DDRITFCR_DDRCKMOD_SSR <<
2145 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2146
2147 return 0;
2148 }
2149
stm32mp1_osc_clk_init(const char * name,enum stm32mp_osc_id index)2150 static void stm32mp1_osc_clk_init(const char *name,
2151 enum stm32mp_osc_id index)
2152 {
2153 uint32_t frequency;
2154
2155 if (fdt_osc_read_freq(name, &frequency) == 0) {
2156 stm32mp1_osc[index] = frequency;
2157 }
2158 }
2159
stm32mp1_osc_init(void)2160 static void stm32mp1_osc_init(void)
2161 {
2162 enum stm32mp_osc_id i;
2163
2164 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
2165 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i);
2166 }
2167 }
2168
2169 #ifdef STM32MP_SHARED_RESOURCES
2170 /*
2171 * Get the parent ID of the target parent clock, for tagging as secure
2172 * shared clock dependencies.
2173 */
get_parent_id_parent(unsigned int parent_id)2174 static int get_parent_id_parent(unsigned int parent_id)
2175 {
2176 enum stm32mp1_parent_sel s = _UNKNOWN_SEL;
2177 enum stm32mp1_pll_id pll_id;
2178 uint32_t p_sel;
2179 uintptr_t rcc_base = stm32mp_rcc_base();
2180
2181 switch (parent_id) {
2182 case _ACLK:
2183 case _PCLK4:
2184 case _PCLK5:
2185 s = _AXIS_SEL;
2186 break;
2187 case _PLL1_P:
2188 case _PLL1_Q:
2189 case _PLL1_R:
2190 pll_id = _PLL1;
2191 break;
2192 case _PLL2_P:
2193 case _PLL2_Q:
2194 case _PLL2_R:
2195 pll_id = _PLL2;
2196 break;
2197 case _PLL3_P:
2198 case _PLL3_Q:
2199 case _PLL3_R:
2200 pll_id = _PLL3;
2201 break;
2202 case _PLL4_P:
2203 case _PLL4_Q:
2204 case _PLL4_R:
2205 pll_id = _PLL4;
2206 break;
2207 case _PCLK1:
2208 case _PCLK2:
2209 case _HCLK2:
2210 case _HCLK6:
2211 case _CK_PER:
2212 case _CK_MPU:
2213 case _CK_MCU:
2214 case _USB_PHY_48:
2215 /* We do not expect to access these */
2216 panic();
2217 break;
2218 default:
2219 /* Other parents have no parent */
2220 return -1;
2221 }
2222
2223 if (s != _UNKNOWN_SEL) {
2224 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s);
2225
2226 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &
2227 sel->msk;
2228
2229 if (p_sel < sel->nb_parent) {
2230 return (int)sel->parent[p_sel];
2231 }
2232 } else {
2233 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
2234
2235 p_sel = mmio_read_32(rcc_base + pll->rckxselr) &
2236 RCC_SELR_REFCLK_SRC_MASK;
2237
2238 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) {
2239 return (int)pll->refclk[p_sel];
2240 }
2241 }
2242
2243 VERBOSE("No parent selected for %s\n",
2244 stm32mp1_clk_parent_name[parent_id]);
2245
2246 return -1;
2247 }
2248
secure_parent_clocks(unsigned long parent_id)2249 static void secure_parent_clocks(unsigned long parent_id)
2250 {
2251 int grandparent_id;
2252
2253 switch (parent_id) {
2254 case _PLL3_P:
2255 case _PLL3_Q:
2256 case _PLL3_R:
2257 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2258 break;
2259
2260 /* These clocks are always secure when RCC is secure */
2261 case _ACLK:
2262 case _HCLK2:
2263 case _HCLK6:
2264 case _PCLK4:
2265 case _PCLK5:
2266 case _PLL1_P:
2267 case _PLL1_Q:
2268 case _PLL1_R:
2269 case _PLL2_P:
2270 case _PLL2_Q:
2271 case _PLL2_R:
2272 case _HSI:
2273 case _HSI_KER:
2274 case _LSI:
2275 case _CSI:
2276 case _CSI_KER:
2277 case _HSE:
2278 case _HSE_KER:
2279 case _HSE_KER_DIV2:
2280 case _HSE_RTC:
2281 case _LSE:
2282 break;
2283
2284 default:
2285 VERBOSE("Cannot secure parent clock %s\n",
2286 stm32mp1_clk_parent_name[parent_id]);
2287 panic();
2288 }
2289
2290 grandparent_id = get_parent_id_parent(parent_id);
2291 if (grandparent_id >= 0) {
2292 secure_parent_clocks(grandparent_id);
2293 }
2294 }
2295
stm32mp1_register_clock_parents_secure(unsigned long clock_id)2296 void stm32mp1_register_clock_parents_secure(unsigned long clock_id)
2297 {
2298 int parent_id;
2299
2300 if (!stm32mp1_rcc_is_secure()) {
2301 return;
2302 }
2303
2304 switch (clock_id) {
2305 case PLL1:
2306 case PLL2:
2307 /* PLL1/PLL2 are always secure: nothing to do */
2308 break;
2309 case PLL3:
2310 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2311 break;
2312 case PLL4:
2313 ERROR("PLL4 cannot be secured\n");
2314 panic();
2315 break;
2316 default:
2317 /* Others are expected gateable clock */
2318 parent_id = stm32mp1_clk_get_parent(clock_id);
2319 if (parent_id < 0) {
2320 INFO("No parent found for clock %lu\n", clock_id);
2321 } else {
2322 secure_parent_clocks(parent_id);
2323 }
2324 break;
2325 }
2326 }
2327 #endif /* STM32MP_SHARED_RESOURCES */
2328
sync_earlyboot_clocks_state(void)2329 static void sync_earlyboot_clocks_state(void)
2330 {
2331 unsigned int idx;
2332 const unsigned long secure_enable[] = {
2333 AXIDCG,
2334 BSEC,
2335 DDRC1, DDRC1LP,
2336 DDRC2, DDRC2LP,
2337 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP,
2338 DDRPHYC, DDRPHYCLP,
2339 RTCAPB,
2340 TZC1, TZC2,
2341 TZPC,
2342 STGEN_K,
2343 };
2344
2345 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) {
2346 stm32mp_clk_enable(secure_enable[idx]);
2347 }
2348 }
2349
2350 static const struct clk_ops stm32mp_clk_ops = {
2351 .enable = stm32mp_clk_enable,
2352 .disable = stm32mp_clk_disable,
2353 .is_enabled = stm32mp_clk_is_enabled,
2354 .get_rate = stm32mp_clk_get_rate,
2355 .get_parent = stm32mp1_clk_get_parent,
2356 };
2357
stm32mp1_clk_probe(void)2358 int stm32mp1_clk_probe(void)
2359 {
2360 #if defined(IMAGE_BL32)
2361 if (!fdt_get_rcc_secure_state()) {
2362 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U);
2363 }
2364 #endif
2365
2366 stm32mp1_osc_init();
2367
2368 sync_earlyboot_clocks_state();
2369
2370 clk_register(&stm32mp_clk_ops);
2371
2372 return 0;
2373 }
2374
