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/trusted-firmware-a-3.7.0/plat/st/common/
Dstm32mp_common.c39 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ argument
41 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ argument
43 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ argument
45 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ argument
47 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) argument
/trusted-firmware-a-3.7.0/plat/st/stm32mp1/
Dstm32mp1_scmi.c73 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ argument
110 #define RESET_CELL(_scmi_id, _id, _name) \ argument
/trusted-firmware-a-3.7.0/plat/mediatek/drivers/gpio/
Dmtgpio_common.h91 #define PIN(_id, _flag, _bit, _base, _offset) { \ argument
/trusted-firmware-a-3.7.0/plat/mediatek/mt8186/include/
Dplat_pm.h47 #define IS_SPM_LP_SMC(_type, _id) (_id == (SPM_LP_SMC_MAGIC | _type)) argument
/trusted-firmware-a-3.7.0/plat/mediatek/lib/pm/armv8_2/
Dpwr_ctrl.c449 #define CPM_PM_FN_CHECK(_fns, _ops, _id, _func, _result, _flag) ({ \ argument
/trusted-firmware-a-3.7.0/drivers/st/clk/
Dclk-stm32-core.h339 #define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \ argument