1/*
2 * Copyright (c) 2018-2022 ARM Limited
3 * Copyright (c) 2016-2021 Cypress Semiconductor Corp. All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 *     http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *
18 * This file is derivative of Cypress PDL 3.0 cy8c6xx7_cm4_dual.ld
19 */
20
21
22OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
23SEARCH_DIR(.)
24GROUP(-lgcc -lc -lnosys)
25ENTRY(Reset_Handler)
26
27#include "region_defs.h"
28
29__heap_size__  = NS_HEAP_SIZE;
30__stack_size__ = NS_STACK_SIZE;
31
32/* Force symbol to be entered in the output file as an undefined symbol. Doing
33* this may, for example, trigger linking of additional modules from standard
34* libraries. You may list several symbols for each EXTERN, and you may use
35* EXTERN multiple times. This command has the same effect as the -u command-line
36* option.
37*/
38EXTERN(Reset_Handler)
39
40/* The MEMORY section below describes the location and size of blocks of memory in the target.
41* Use this section to specify the memory regions available for allocation.
42*/
43MEMORY
44{
45    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
46     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
47     */
48    ram               (rwx)   : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
49    flash             (rx)    : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
50
51    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
52     * You can assign sections to this memory region for only one of the cores.
53     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
54     * Therefore, repurposing this memory region will prevent such middleware from operation.
55     */
56    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
57
58    /* The following regions define device specific memory regions and must not be changed. */
59    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
60    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
61    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
62    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
63    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
64    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
65    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
66}
67
68/* Library configurations */
69GROUP(libgcc.a libc.a libm.a libnosys.a)
70
71/* Linker script to place sections and symbol values. Should be used together
72 * with other linker script that defines memory regions FLASH and RAM.
73 * It references following symbols, which must be defined in code:
74 *   Reset_Handler : Entry of reset handler
75 *
76 * It defines following symbols, which code can use without definition:
77 *   __exidx_start
78 *   __exidx_end
79 *   __copy_table_start__
80 *   __copy_table_end__
81 *   __zero_table_start__
82 *   __zero_table_end__
83 *   __etext
84 *   __data_start__
85 *   __preinit_array_start
86 *   __preinit_array_end
87 *   __init_array_start
88 *   __init_array_end
89 *   __fini_array_start
90 *   __fini_array_end
91 *   __data_end__
92 *   __bss_start__
93 *   __bss_end__
94 *   __end__
95 *   end
96 *   __HeapLimit
97 *   __StackLimit
98 *   __StackTop
99 *   __stack
100 *   __Vectors_End
101 *   __Vectors_Size
102 */
103
104
105SECTIONS
106{
107    .text :
108    {
109        . = ALIGN(4);
110        __Vectors = . ;
111        KEEP(*(.vectors))
112        . = ALIGN(4);
113        __Vectors_End = .;
114        __Vectors_Size = __Vectors_End - __Vectors;
115        __end__ = .;
116
117        . = ALIGN(4);
118        *(.text*)
119
120        KEEP(*(.init))
121        KEEP(*(.fini))
122
123        /* .ctors */
124        *crtbegin.o(.ctors)
125        *crtbegin?.o(.ctors)
126        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
127        *(SORT(.ctors.*))
128        *(.ctors)
129
130        /* .dtors */
131        *crtbegin.o(.dtors)
132        *crtbegin?.o(.dtors)
133        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
134        *(SORT(.dtors.*))
135        *(.dtors)
136
137        /* Read-only code (constants). */
138        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
139
140        KEEP(*(.eh_frame*))
141    } > flash
142
143
144    .ARM.extab :
145    {
146        *(.ARM.extab* .gnu.linkonce.armextab.*)
147    } > flash
148
149    __exidx_start = .;
150
151    .ARM.exidx :
152    {
153        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
154    } > flash
155    __exidx_end = .;
156
157
158    /* To copy multiple ROM to RAM sections,
159     * uncomment .copy.table section and,
160     * define __STARTUP_COPY_MULTIPLE */
161    .copy.table :
162    {
163        . = ALIGN(4);
164        __copy_table_start__ = .;
165
166#ifdef RAM_VECTORS_SUPPORT
167        /* Copy interrupt vectors from flash to RAM */
168        LONG (__Vectors)                                    /* From */
169        LONG (__ram_vectors_start__)                        /* To   */
170        LONG ((__Vectors_End - __Vectors) / 4)              /* Size */
171#endif
172        /* Copy data section to RAM */
173        LONG (__etext)                                      /* From */
174        LONG (__data_start__)                               /* To   */
175        LONG ((__data_end__ - __data_start__) / 4)          /* Size */
176
177        __copy_table_end__ = .;
178    } > flash
179
180
181    /* To clear multiple BSS sections,
182     * uncomment .zero.table section and,
183     * define __STARTUP_CLEAR_BSS_MULTIPLE */
184    .zero.table :
185    {
186        . = ALIGN(4);
187        __zero_table_start__ = .;
188        LONG (__bss_start__)
189        LONG ((__bss_end__ - __bss_start__) / 4)
190        __zero_table_end__ = .;
191    } > flash
192
193    __etext =  ALIGN(4);
194
195
196#ifdef RAM_VECTORS_SUPPORT
197    .ramVectors (NOLOAD) : ALIGN(8)
198    {
199        __ram_vectors_start__ = .;
200        KEEP(*(.ram_vectors))
201        __ram_vectors_end__   = .;
202    } > ram
203
204    .data __ram_vectors_end__ : AT (__etext)
205#else
206    .data : AT (__etext)
207#endif
208    {
209        __data_start__ = .;
210
211        *(vtable)
212        *(.data*)
213
214        . = ALIGN(4);
215        /* preinit data */
216        PROVIDE_HIDDEN (__preinit_array_start = .);
217        KEEP(*(.preinit_array))
218        PROVIDE_HIDDEN (__preinit_array_end = .);
219
220        . = ALIGN(4);
221        /* init data */
222        PROVIDE_HIDDEN (__init_array_start = .);
223        KEEP(*(SORT(.init_array.*)))
224        KEEP(*(.init_array))
225        PROVIDE_HIDDEN (__init_array_end = .);
226
227        . = ALIGN(4);
228        /* finit data */
229        PROVIDE_HIDDEN (__fini_array_start = .);
230        KEEP(*(SORT(.fini_array.*)))
231        KEEP(*(.fini_array))
232        PROVIDE_HIDDEN (__fini_array_end = .);
233
234        KEEP(*(.jcr*))
235        . = ALIGN(4);
236
237        KEEP(*(.ramfunc))
238        . = ALIGN(4);
239
240        __data_end__ = .;
241
242    } > ram
243
244
245    /* Place variables in the section that should not be initialized during the
246    *  device startup.
247    */
248    .noinit (NOLOAD) : ALIGN(8)
249    {
250      KEEP(*(.noinit))
251    } > ram
252
253
254    /* The uninitialized global or static variables are placed in this section.
255    *
256    * The NOLOAD attribute tells linker that .bss section does not consume
257    * any space in the image. The NOLOAD attribute changes the .bss type to
258    * NOBITS, and that  makes linker to A) not allocate section in memory, and
259    * A) put information to clear the section with all zeros during application
260    * loading.
261    *
262    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
263    * This  makes linker to A) allocate zeroed section in memory, and B) copy
264    * this section to RAM during application loading.
265    */
266    .bss (NOLOAD):
267    {
268        . = ALIGN(4);
269        __bss_start__ = .;
270        *(.bss*)
271        *(COMMON)
272        . = ALIGN(4);
273        __bss_end__ = .;
274    } > ram
275
276
277    .heap (NOLOAD):
278    {
279        __HeapBase = .;
280        __end__ = .;
281        PROVIDE(end = .);
282        end = __end__;
283        . += __heap_size__;
284        __HeapLimit = .;
285        __heap_limit = .; /* Add for _sbrk */
286    } > ram
287
288    .stack : ALIGN(32)
289    {
290        . += __stack_size__;
291    } > ram
292    __StackLimit = ADDR(.stack);
293    __StackTop = ADDR(.stack) + SIZEOF(.stack);
294
295    PROVIDE(__stack = __StackTop);
296
297    Image$$ER_TFM_DATA$$RW$$Base = ADDR(.data);
298    Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.data) + SIZEOF(.data);
299
300    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.bss);
301    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.bss) + SIZEOF(.bss);
302
303    Image$$ER_TFM_DATA$$Base = ADDR(.data);
304    Image$$ER_TFM_DATA$$Limit = ADDR(.data) + SIZEOF(.data) + SIZEOF(.bss);
305
306#if defined(PSA_API_TEST_ENABLED)
307    .PSA_API_TEST_NVMEM PSA_API_TEST_NVMEM_START (NOLOAD) :
308    {
309        . += PSA_API_TEST_NVMEM_SIZE;
310    } > ram
311#endif
312
313#if defined (NS_DATA_SHARED_START)
314    .TFM_SHARED NS_DATA_SHARED_START (NOLOAD) :
315    {
316        . = ALIGN(4);
317        . += NS_DATA_SHARED_SIZE;
318    } > ram
319#endif
320
321    /* Used for the digital signature of the secure application and the Bootloader SDK appication.
322    * The size of the section depends on the required data size. */
323    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
324    {
325        KEEP(*(.cy_app_signature))
326    } > flash
327
328
329    /* Emulated EEPROM Flash area */
330    .cy_em_eeprom :
331    {
332        KEEP(*(.cy_em_eeprom))
333    } > em_eeprom
334
335
336    /* Supervisory Flash: User data */
337    .cy_sflash_user_data :
338    {
339        KEEP(*(.cy_sflash_user_data))
340    } > sflash_user_data
341
342
343    /* Supervisory Flash: Normal Access Restrictions (NAR) */
344    .cy_sflash_nar :
345    {
346        KEEP(*(.cy_sflash_nar))
347    } > sflash_nar
348
349
350    /* Supervisory Flash: Public Key */
351    .cy_sflash_public_key :
352    {
353        KEEP(*(.cy_sflash_public_key))
354    } > sflash_public_key
355
356
357    /* Supervisory Flash: Table of Content # 2 */
358    .cy_toc_part2 :
359    {
360        KEEP(*(.cy_toc_part2))
361    } > sflash_toc_2
362
363
364    /* Supervisory Flash: Table of Content # 2 Copy */
365    .cy_rtoc_part2 :
366    {
367        KEEP(*(.cy_rtoc_part2))
368    } > sflash_rtoc_2
369
370
371    /* Places the code in the Execute in Place (XIP) section. See the smif driver
372    *  documentation for details.
373    */
374    .cy_xip :
375    {
376        KEEP(*(.cy_xip))
377    } > xip
378
379
380    /* eFuse */
381    .cy_efuse :
382    {
383        KEEP(*(.cy_efuse))
384    } > efuse
385
386
387    /* These sections are used for additional metadata (silicon revision,
388    *  Silicon/JTAG ID, etc.) storage.
389    */
390    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
391}
392
393
394/* The following symbols used by the cymcuelftool. */
395/* Flash */
396__cy_memory_0_start    = 0x10000000;
397__cy_memory_0_length   = 0x00100000;
398__cy_memory_0_row_size = 0x200;
399
400/* Emulated EEPROM Flash area */
401__cy_memory_1_start    = 0x14000000;
402__cy_memory_1_length   = 0x8000;
403__cy_memory_1_row_size = 0x200;
404
405/* Supervisory Flash */
406__cy_memory_2_start    = 0x16000000;
407__cy_memory_2_length   = 0x8000;
408__cy_memory_2_row_size = 0x200;
409
410/* XIP */
411__cy_memory_3_start    = 0x18000000;
412__cy_memory_3_length   = 0x08000000;
413__cy_memory_3_row_size = 0x200;
414
415/* eFuse */
416__cy_memory_4_start    = 0x90700000;
417__cy_memory_4_length   = 0x100000;
418__cy_memory_4_row_size = 1;
419
420/* EOF */
421