1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L1xx_LL_SD_H 38 #define __STM32L1xx_LL_SD_H 39 40 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l1xx_hal_def.h" 48 49 /** @addtogroup STM32L1xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup SDMMC_LL 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief SDMMC Configuration Structure definition 64 */ 65 typedef struct 66 { 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 68 This parameter can be a value of @ref SDIO_Clock_Edge */ 69 70 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is 71 enabled or disabled. 72 This parameter can be a value of @ref SDIO_Clock_Bypass */ 73 74 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or 75 disabled when the bus is idle. 76 This parameter can be a value of @ref SDIO_Clock_Power_Save */ 77 78 uint32_t BusWide; /*!< Specifies the SDIO bus width. 79 This parameter can be a value of @ref SDIO_Bus_Wide */ 80 81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. 82 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ 83 84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. 85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 86 87 }SDIO_InitTypeDef; 88 89 90 /** 91 * @brief SDIO Command Control structure 92 */ 93 typedef struct 94 { 95 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent 96 to a card as part of a command message. If a command 97 contains an argument, it must be loaded into this register 98 before writing the command to the command register. */ 99 100 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and 101 Max_Data = 64 */ 102 103 uint32_t Response; /*!< Specifies the SDIO response type. 104 This parameter can be a value of @ref SDIO_Response_Type */ 105 106 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is 107 enabled or disabled. 108 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ 109 110 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) 111 is enabled or disabled. 112 This parameter can be a value of @ref SDIO_CPSM_State */ 113 }SDIO_CmdInitTypeDef; 114 115 116 /** 117 * @brief SDIO Data Control structure 118 */ 119 typedef struct 120 { 121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 122 123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 124 125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 126 This parameter can be a value of @ref SDIO_Data_Block_Size */ 127 128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 129 is a read or write. 130 This parameter can be a value of @ref SDIO_Transfer_Direction */ 131 132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 133 This parameter can be a value of @ref SDIO_Transfer_Type */ 134 135 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) 136 is enabled or disabled. 137 This parameter can be a value of @ref SDIO_DPSM_State */ 138 }SDIO_DataInitTypeDef; 139 140 /** 141 * @} 142 */ 143 144 /* Exported constants --------------------------------------------------------*/ 145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 146 * @{ 147 */ 148 149 /** @defgroup SDIO_Clock_Edge Clock Edge 150 * @{ 151 */ 152 #define SDIO_CLOCK_EDGE_RISING (0x00000000U) 153 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE 154 155 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ 156 ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) 157 /** 158 * @} 159 */ 160 161 /** @defgroup SDIO_Clock_Bypass Clock Bypass 162 * @{ 163 */ 164 #define SDIO_CLOCK_BYPASS_DISABLE (0x00000000U) 165 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS 166 167 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ 168 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) 169 /** 170 * @} 171 */ 172 173 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving 174 * @{ 175 */ 176 #define SDIO_CLOCK_POWER_SAVE_DISABLE (0x00000000U) 177 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV 178 179 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ 180 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) 181 /** 182 * @} 183 */ 184 185 /** @defgroup SDIO_Bus_Wide Bus Width 186 * @{ 187 */ 188 #define SDIO_BUS_WIDE_1B (0x00000000U) 189 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 190 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 191 192 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ 193 ((WIDE) == SDIO_BUS_WIDE_4B) || \ 194 ((WIDE) == SDIO_BUS_WIDE_8B)) 195 /** 196 * @} 197 */ 198 199 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control 200 * @{ 201 */ 202 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE (0x00000000U) 203 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN 204 205 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ 206 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) 207 /** 208 * @} 209 */ 210 211 /** @defgroup SDIO_Clock_Division Clock Division 212 * @{ 213 */ 214 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) 215 /** 216 * @} 217 */ 218 219 /** @defgroup SDIO_Command_Index Command Index 220 * @{ 221 */ 222 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) 223 /** 224 * @} 225 */ 226 227 /** @defgroup SDIO_Response_Type Response Type 228 * @{ 229 */ 230 #define SDIO_RESPONSE_NO (0x00000000U) 231 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 232 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP 233 234 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ 235 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ 236 ((RESPONSE) == SDIO_RESPONSE_LONG)) 237 /** 238 * @} 239 */ 240 241 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt 242 * @{ 243 */ 244 #define SDIO_WAIT_NO (0x00000000U) 245 #define SDIO_WAIT_IT SDIO_CMD_WAITINT 246 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND 247 248 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ 249 ((WAIT) == SDIO_WAIT_IT) || \ 250 ((WAIT) == SDIO_WAIT_PEND)) 251 /** 252 * @} 253 */ 254 255 /** @defgroup SDIO_CPSM_State CPSM State 256 * @{ 257 */ 258 #define SDIO_CPSM_DISABLE (0x00000000U) 259 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN 260 261 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ 262 ((CPSM) == SDIO_CPSM_ENABLE)) 263 /** 264 * @} 265 */ 266 267 /** @defgroup SDIO_Response_Registers Response Register 268 * @{ 269 */ 270 #define SDIO_RESP1 (0x00000000U) 271 #define SDIO_RESP2 (0x00000004U) 272 #define SDIO_RESP3 (0x00000008U) 273 #define SDIO_RESP4 (0x0000000CU) 274 275 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ 276 ((RESP) == SDIO_RESP2) || \ 277 ((RESP) == SDIO_RESP3) || \ 278 ((RESP) == SDIO_RESP4)) 279 /** 280 * @} 281 */ 282 283 /** @defgroup SDIO_Data_Length Data Lenght 284 * @{ 285 */ 286 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) 287 /** 288 * @} 289 */ 290 291 /** @defgroup SDIO_Data_Block_Size Data Block Size 292 * @{ 293 */ 294 #define SDIO_DATABLOCK_SIZE_1B (0x00000000U) 295 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 296 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 297 #define SDIO_DATABLOCK_SIZE_8B (0x00000030U) 298 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 299 #define SDIO_DATABLOCK_SIZE_32B (0x00000050U) 300 #define SDIO_DATABLOCK_SIZE_64B (0x00000060U) 301 #define SDIO_DATABLOCK_SIZE_128B (0x00000070U) 302 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 303 #define SDIO_DATABLOCK_SIZE_512B (0x00000090U) 304 #define SDIO_DATABLOCK_SIZE_1024B (0x000000A0U) 305 #define SDIO_DATABLOCK_SIZE_2048B (0x000000B0U) 306 #define SDIO_DATABLOCK_SIZE_4096B (0x000000C0U) 307 #define SDIO_DATABLOCK_SIZE_8192B (0x000000D0U) 308 #define SDIO_DATABLOCK_SIZE_16384B (0x000000E0U) 309 310 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ 311 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ 312 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ 313 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ 314 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ 315 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ 316 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ 317 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ 318 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ 319 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ 320 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ 321 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ 322 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ 323 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ 324 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 325 /** 326 * @} 327 */ 328 329 /** @defgroup SDIO_Transfer_Direction Transfer Direction 330 * @{ 331 */ 332 #define SDIO_TRANSFER_DIR_TO_CARD (0x00000000U) 333 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR 334 335 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ 336 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) 337 /** 338 * @} 339 */ 340 341 /** @defgroup SDIO_Transfer_Type Transfer Type 342 * @{ 343 */ 344 #define SDIO_TRANSFER_MODE_BLOCK (0x00000000U) 345 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE 346 347 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ 348 ((MODE) == SDIO_TRANSFER_MODE_STREAM)) 349 /** 350 * @} 351 */ 352 353 /** @defgroup SDIO_DPSM_State DPSM State 354 * @{ 355 */ 356 #define SDIO_DPSM_DISABLE (0x00000000U) 357 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN 358 359 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ 360 ((DPSM) == SDIO_DPSM_ENABLE)) 361 /** 362 * @} 363 */ 364 365 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode 366 * @{ 367 */ 368 #define SDIO_READ_WAIT_MODE_DATA2 (0x00000000U) 369 #define SDIO_READ_WAIT_MODE_CLK (0x00000001U) 370 371 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ 372 ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) 373 /** 374 * @} 375 */ 376 377 /** @defgroup SDIO_Interrupt_sources Interrupt Sources 378 * @{ 379 */ 380 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL 381 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL 382 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT 383 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT 384 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR 385 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR 386 #define SDIO_IT_CMDREND SDIO_STA_CMDREND 387 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT 388 #define SDIO_IT_DATAEND SDIO_STA_DATAEND 389 #define SDIO_IT_STBITERR SDIO_STA_STBITERR 390 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND 391 #define SDIO_IT_CMDACT SDIO_STA_CMDACT 392 #define SDIO_IT_TXACT SDIO_STA_TXACT 393 #define SDIO_IT_RXACT SDIO_STA_RXACT 394 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE 395 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF 396 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF 397 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF 398 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE 399 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE 400 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL 401 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL 402 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT 403 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND 404 /** 405 * @} 406 */ 407 408 /** @defgroup SDIO_Flags Flags 409 * @{ 410 */ 411 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL 412 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL 413 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT 414 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT 415 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR 416 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR 417 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND 418 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT 419 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND 420 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR 421 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND 422 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT 423 #define SDIO_FLAG_TXACT SDIO_STA_TXACT 424 #define SDIO_FLAG_RXACT SDIO_STA_RXACT 425 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE 426 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF 427 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF 428 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF 429 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE 430 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE 431 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL 432 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL 433 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT 434 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND 435 /** 436 * @} 437 */ 438 439 /** 440 * @} 441 */ 442 /* Exported macro ------------------------------------------------------------*/ 443 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 444 * @{ 445 */ 446 447 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region 448 * @{ 449 */ 450 /* ------------ SDIO registers bit address in the alias region -------------- */ 451 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) 452 453 /* --- CLKCR Register ---*/ 454 /* Alias word address of CLKEN bit */ 455 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04) 456 #define CLKEN_BITNUMBER 0x08 457 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4)) 458 459 /* --- CMD Register ---*/ 460 /* Alias word address of SDIOSUSPEND bit */ 461 #define CMD_OFFSET (SDIO_OFFSET + 0x0C) 462 #define SDIOSUSPEND_BITNUMBER 0x0B 463 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4)) 464 465 /* Alias word address of ENCMDCOMPL bit */ 466 #define ENCMDCOMPL_BITNUMBER 0x0C 467 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4)) 468 469 /* Alias word address of NIEN bit */ 470 #define NIEN_BITNUMBER 0x0D 471 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4)) 472 473 /* Alias word address of ATACMD bit */ 474 #define ATACMD_BITNUMBER 0x0E 475 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4)) 476 477 /* --- DCTRL Register ---*/ 478 /* Alias word address of DMAEN bit */ 479 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) 480 #define DMAEN_BITNUMBER 0x03 481 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4)) 482 483 /* Alias word address of RWSTART bit */ 484 #define RWSTART_BITNUMBER 0x08 485 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4)) 486 487 /* Alias word address of RWSTOP bit */ 488 #define RWSTOP_BITNUMBER 0x09 489 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4)) 490 491 /* Alias word address of RWMOD bit */ 492 #define RWMOD_BITNUMBER 0x0A 493 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4)) 494 495 /* Alias word address of SDIOEN bit */ 496 #define SDIOEN_BITNUMBER 0x0B 497 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4)) 498 /** 499 * @} 500 */ 501 502 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 503 * @brief SDMMC_LL registers bit address in the alias region 504 * @{ 505 */ 506 507 /* ---------------------- SDIO registers bit mask --------------------------- */ 508 /* --- CLKCR Register ---*/ 509 /* CLKCR register clear mask */ 510 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ 511 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ 512 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) 513 514 /* --- PWRCTRL Register ---*/ 515 /* --- DCTRL Register ---*/ 516 /* SDIO DCTRL Clear Mask */ 517 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ 518 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) 519 520 /* --- CMD Register ---*/ 521 /* CMD Register clear mask */ 522 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ 523 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ 524 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) 525 526 /* SDIO RESP Registers Address */ 527 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) 528 529 /* SDIO Initialization Frequency (400KHz max) */ 530 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) 531 532 /* SDIO Data Transfer Frequency */ 533 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4) 534 535 /** 536 * @} 537 */ 538 539 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 540 * @brief macros to handle interrupts and specific clock configurations 541 * @{ 542 */ 543 544 /** 545 * @brief Enable the SDIO device. 546 * @retval None 547 */ 548 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) 549 550 /** 551 * @brief Disable the SDIO device. 552 * @retval None 553 */ 554 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) 555 556 /** 557 * @brief Enable the SDIO DMA transfer. 558 * @retval None 559 */ 560 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) 561 562 /** 563 * @brief Disable the SDIO DMA transfer. 564 * @retval None 565 */ 566 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) 567 568 /** 569 * @brief Enable the SDIO device interrupt. 570 * @param __INSTANCE__ : Pointer to SDIO register base 571 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. 572 * This parameter can be one or a combination of the following values: 573 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 574 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 575 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 576 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 577 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 578 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 579 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 580 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 581 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 582 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 583 * bus mode interrupt 584 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 585 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 586 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 587 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 588 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 589 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 590 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 591 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 592 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 593 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 594 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 595 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 596 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 597 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt 598 * @retval None 599 */ 600 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 601 602 /** 603 * @brief Disable the SDIO device interrupt. 604 * @param __INSTANCE__ : Pointer to SDIO register base 605 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. 606 * This parameter can be one or a combination of the following values: 607 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 608 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 609 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 610 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 611 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 612 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 613 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 614 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 615 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 616 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 617 * bus mode interrupt 618 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 619 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 620 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 621 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 622 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 623 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 624 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 625 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 626 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 627 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 628 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 629 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 630 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 631 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt 632 * @retval None 633 */ 634 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 635 636 /** 637 * @brief Checks whether the specified SDIO flag is set or not. 638 * @param __INSTANCE__ : Pointer to SDIO register base 639 * @param __FLAG__: specifies the flag to check. 640 * This parameter can be one of the following values: 641 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) 642 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 643 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout 644 * @arg SDIO_FLAG_DTIMEOUT: Data timeout 645 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error 646 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error 647 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) 648 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) 649 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 650 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. 651 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) 652 * @arg SDIO_FLAG_CMDACT: Command transfer in progress 653 * @arg SDIO_FLAG_TXACT: Data transmit in progress 654 * @arg SDIO_FLAG_RXACT: Data receive in progress 655 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty 656 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full 657 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full 658 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full 659 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty 660 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty 661 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO 662 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO 663 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received 664 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 665 * @retval The new state of SDIO_FLAG (SET or RESET). 666 */ 667 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) 668 669 670 /** 671 * @brief Clears the SDIO pending flags. 672 * @param __INSTANCE__ : Pointer to SDIO register base 673 * @param __FLAG__: specifies the flag to clear. 674 * This parameter can be one or a combination of the following values: 675 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) 676 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 677 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout 678 * @arg SDIO_FLAG_DTIMEOUT: Data timeout 679 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error 680 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error 681 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) 682 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) 683 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 684 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode 685 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) 686 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received 687 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 688 * @retval None 689 */ 690 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 691 692 /** 693 * @brief Checks whether the specified SDIO interrupt has occurred or not. 694 * @param __INSTANCE__ : Pointer to SDIO register base 695 * @param __INTERRUPT__: specifies the SDIO interrupt source to check. 696 * This parameter can be one of the following values: 697 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 698 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 699 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 700 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 701 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 702 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 703 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 704 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 705 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 706 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 707 * bus mode interrupt 708 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 709 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 710 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 711 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 712 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 713 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 714 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 715 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 716 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 717 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 718 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 719 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 720 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 721 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt 722 * @retval The new state of SDIO_IT (SET or RESET). 723 */ 724 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 725 726 /** 727 * @brief Clears the SDIO's interrupt pending bits. 728 * @param __INSTANCE__ : Pointer to SDIO register base 729 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 730 * This parameter can be one or a combination of the following values: 731 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 732 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 733 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 734 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 735 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 736 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 737 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 738 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 739 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt 740 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 741 * bus mode interrupt 742 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt 743 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 744 * @retval None 745 */ 746 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 747 748 /** 749 * @brief Enable Start the SD I/O Read Wait operation. 750 * @retval None 751 */ 752 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) 753 754 /** 755 * @brief Disable Start the SD I/O Read Wait operations. 756 * @retval None 757 */ 758 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) 759 760 /** 761 * @brief Enable Start the SD I/O Read Wait operation. 762 * @retval None 763 */ 764 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) 765 766 /** 767 * @brief Disable Stop the SD I/O Read Wait operations. 768 * @retval None 769 */ 770 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) 771 772 /** 773 * @brief Enable the SD I/O Mode Operation. 774 * @retval None 775 */ 776 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) 777 778 /** 779 * @brief Disable the SD I/O Mode Operation. 780 * @retval None 781 */ 782 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) 783 784 /** 785 * @brief Enable the SD I/O Suspend command sending. 786 * @retval None 787 */ 788 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) 789 790 /** 791 * @brief Disable the SD I/O Suspend command sending. 792 * @retval None 793 */ 794 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) 795 796 /** 797 * @brief Enable the command completion signal. 798 * @retval None 799 */ 800 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) 801 802 /** 803 * @brief Disable the command completion signal. 804 * @retval None 805 */ 806 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) 807 808 /** 809 * @brief Enable the CE-ATA interrupt. 810 * @retval None 811 */ 812 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = 0U) 813 814 /** 815 * @brief Disable the CE-ATA interrupt. 816 * @retval None 817 */ 818 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = 1U) 819 820 /** 821 * @brief Enable send CE-ATA command (CMD61). 822 * @retval None 823 */ 824 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) 825 826 /** 827 * @brief Disable send CE-ATA command (CMD61). 828 * @retval None 829 */ 830 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) 831 832 /** 833 * @} 834 */ 835 836 /** 837 * @} 838 */ 839 840 /* Exported functions --------------------------------------------------------*/ 841 /** @addtogroup SDMMC_LL_Exported_Functions 842 * @{ 843 */ 844 845 /* Initialization/de-initialization functions **********************************/ 846 /** @addtogroup HAL_SDMMC_LL_Group1 847 * @{ 848 */ 849 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); 850 /** 851 * @} 852 */ 853 854 /* I/O operation functions *****************************************************/ 855 /** @addtogroup HAL_SDMMC_LL_Group2 856 * @{ 857 */ 858 /* Blocking mode: Polling */ 859 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); 860 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); 861 /** 862 * @} 863 */ 864 865 /* Peripheral Control functions ************************************************/ 866 /** @addtogroup HAL_SDMMC_LL_Group3 867 * @{ 868 */ 869 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); 870 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); 871 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); 872 873 /* Command path state machine (CPSM) management functions */ 874 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); 875 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); 876 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); 877 878 /* Data path state machine (DPSM) management functions */ 879 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct); 880 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); 881 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); 882 883 /* SDIO IO Cards mode management functions */ 884 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); 885 886 /** 887 * @} 888 */ 889 890 /** 891 * @} 892 */ 893 894 /** 895 * @} 896 */ 897 898 /** 899 * @} 900 */ 901 902 #ifdef __cplusplus 903 } 904 #endif 905 906 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 907 908 #endif /* __STM32L1xx_LL_SD_H */ 909 910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 911
