1 /*! 2 \file gd32vf103.h 3 \brief general definitions for GD32VF103 4 5 \version 2019-06-05, V1.0.0, firmware for GD32VF103 6 \version 2020-08-04, V1.1.0, firmware for GD32VF103 7 */ 8 9 /* 10 Copyright (c) 2020, GigaDevice Semiconductor Inc. 11 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 1. Redistributions of source code must retain the above copyright notice, this 16 list of conditions and the following disclaimer. 17 2. Redistributions in binary form must reproduce the above copyright notice, 18 this list of conditions and the following disclaimer in the documentation 19 and/or other materials provided with the distribution. 20 3. Neither the name of the copyright holder nor the names of its contributors 21 may be used to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 OF SUCH DAMAGE. 34 */ 35 36 #ifndef GD32VF103_H 37 #define GD32VF103_H 38 39 #ifdef cplusplus 40 extern "C" { 41 #endif 42 43 /* IO definitions (access restrictions to peripheral registers) */ 44 /** 45 46 <strong>IO Type Qualifiers</strong> are used 47 \li to specify the access to peripheral variables. 48 \li for automatic generation of peripheral register debug information. 49 */ 50 #ifdef __cplusplus 51 #define __I volatile /*!< Defines 'read only' permissions */ 52 #else 53 #define __I volatile const /*!< Defines 'read only' permissions */ 54 #endif 55 #define __O volatile /*!< Defines 'write only' permissions */ 56 #define __IO volatile /*!< Defines 'read / write' permissions */ 57 58 /* define value of high speed crystal oscillator (HXTAL) in Hz */ 59 #if !defined HXTAL_VALUE 60 #ifdef GD32VF103R_START 61 #define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ 62 #define HXTAL_VALUE_8M HXTAL_VALUE 63 #elif defined(GD32VF103V_EVAL) || defined(GD32VF103C_START) || defined(GD32VF103T_START) 64 #define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */ 65 #define HXTAL_VALUE_25M HXTAL_VALUE 66 #else 67 #error "Please select the target board type used in your application (in gd32vf103.h file)" 68 #endif 69 #endif /* high speed crystal oscillator value */ 70 71 /* define startup timeout value of high speed crystal oscillator (HXTAL) */ 72 #if !defined (HXTAL_STARTUP_TIMEOUT) 73 #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) 74 #endif /* high speed crystal oscillator startup timeout */ 75 76 /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ 77 #if !defined (IRC8M_VALUE) 78 #define IRC8M_VALUE ((uint32_t)8000000) 79 #endif /* internal 8MHz RC oscillator value */ 80 81 /* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ 82 #if !defined (IRC8M_STARTUP_TIMEOUT) 83 #define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) 84 #endif /* internal 8MHz RC oscillator startup timeout */ 85 86 /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ 87 #if !defined (IRC40K_VALUE) 88 #define IRC40K_VALUE ((uint32_t)40000) 89 #endif /* internal 40KHz RC oscillator value */ 90 91 /* define value of low speed crystal oscillator (LXTAL)in Hz */ 92 #if !defined (LXTAL_VALUE) 93 #define LXTAL_VALUE ((uint32_t)32768) 94 #endif /* low speed crystal oscillator value */ 95 96 /* define interrupt number */ 97 typedef enum IRQn 98 { 99 100 CLIC_INT_RESERVED = 0, /*!< RISC-V reserved */ 101 CLIC_INT_SFT = 3, /*!< Software interrupt */ 102 CLIC_INT_TMR = 7, /*!< CPU Timer interrupt */ 103 CLIC_INT_BWEI = 17, /*!< Bus Error interrupt */ 104 CLIC_INT_PMOVI = 18, /*!< Performance Monitor */ 105 106 /* interruput numbers */ 107 WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */ 108 LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */ 109 TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */ 110 RTC_IRQn = 22, /*!< RTC alarm interrupt */ 111 FMC_IRQn = 23, /*!< FMC interrupt */ 112 RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */ 113 EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */ 114 EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */ 115 EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */ 116 EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */ 117 EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */ 118 DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */ 119 DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */ 120 DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */ 121 DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */ 122 DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */ 123 DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */ 124 DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */ 125 ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */ 126 CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */ 127 CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */ 128 CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */ 129 CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */ 130 EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */ 131 TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */ 132 TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */ 133 TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */ 134 TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */ 135 TIMER1_IRQn = 47, /*!< TIMER1 interrupt */ 136 TIMER2_IRQn = 48, /*!< TIMER2 interrupt */ 137 TIMER3_IRQn = 49, /*!< TIMER3 interrupts */ 138 I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */ 139 I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */ 140 I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */ 141 I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */ 142 SPI0_IRQn = 54, /*!< SPI0 interrupt */ 143 SPI1_IRQn = 55, /*!< SPI1 interrupt */ 144 USART0_IRQn = 56, /*!< USART0 interrupt */ 145 USART1_IRQn = 57, /*!< USART1 interrupt */ 146 USART2_IRQn = 58, /*!< USART2 interrupt */ 147 EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */ 148 RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */ 149 USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */ 150 151 EXMC_IRQn = 67, /*!< EXMC global interrupt */ 152 153 TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */ 154 SPI2_IRQn = 70, /*!< SPI2 global interrupt */ 155 UART3_IRQn = 71, /*!< UART3 global interrupt */ 156 UART4_IRQn = 72, /*!< UART4 global interrupt */ 157 TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */ 158 TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */ 159 DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */ 160 DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */ 161 DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */ 162 DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */ 163 DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */ 164 165 CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */ 166 CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */ 167 CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */ 168 CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ 169 USBFS_IRQn = 86, /*!< USBFS global interrupt */ 170 171 ECLIC_NUM_INTERRUPTS 172 } IRQn_Type; 173 174 /* includes */ 175 #include "system_gd32vf103.h" 176 #include <stdint.h> 177 178 /* enum definitions */ 179 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; 180 typedef enum {RESET = 0, SET = !RESET} FlagStatus; 181 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; 182 183 /* bit operations */ 184 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) 185 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) 186 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) 187 #ifndef BIT 188 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) 189 #endif 190 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 191 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) 192 193 /* main flash and SRAM memory map */ 194 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ 195 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ 196 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ 197 #define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ 198 #define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ 199 200 /* peripheral memory map */ 201 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ 202 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ 203 #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ 204 #define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ 205 206 /* advanced peripheral bus 1 memory map */ 207 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ 208 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ 209 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ 210 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ 211 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ 212 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ 213 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ 214 #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ 215 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ 216 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ 217 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ 218 219 /* advanced peripheral bus 2 memory map */ 220 #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ 221 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ 222 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ 223 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ 224 225 /* advanced high performance bus 1 memory map */ 226 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ 227 #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ 228 #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ 229 #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ 230 #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ 231 232 /* define marco USE_STDPERIPH_DRIVER */ 233 #if !defined USE_STDPERIPH_DRIVER 234 #define USE_STDPERIPH_DRIVER 235 #endif 236 #ifdef USE_STDPERIPH_DRIVER 237 #include "gd32vf103_libopt.h" 238 #endif /* USE_STDPERIPH_DRIVER */ 239 240 #ifdef cplusplus 241 } 242 #endif 243 #endif 244
