1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2016 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F3xx_HAL_H 22 #define __STM32F3xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f3xx_hal_conf.h" 30 31 /** @addtogroup STM32F3xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Private macros ------------------------------------------------------------*/ 40 /** @addtogroup HAL_Private_Macros 41 * @{ 42 */ 43 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 44 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 45 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 46 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 47 /** 48 * @} 49 */ 50 51 /* Exported types ------------------------------------------------------------*/ 52 /* Exported constants --------------------------------------------------------*/ 53 /** @defgroup HAL_Exported_Constants HAL Exported Constants 54 * @{ 55 */ 56 57 /** @defgroup HAL_TICK_FREQ Tick Frequency 58 * @{ 59 */ 60 typedef enum 61 { 62 HAL_TICK_FREQ_10HZ = 100U, 63 HAL_TICK_FREQ_100HZ = 10U, 64 HAL_TICK_FREQ_1KHZ = 1U, 65 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 66 } HAL_TickFreqTypeDef; 67 /** 68 * @} 69 */ 70 71 /** 72 * @} 73 */ 74 /** @defgroup HAL_Exported_Constants HAL Exported Constants 75 * @{ 76 */ 77 /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region 78 * @brief SYSCFG registers bit address in the alias region 79 * @{ 80 */ 81 /* ------------ SYSCFG registers bit address in the alias region -------------*/ 82 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) 83 /* --- CFGR2 Register ---*/ 84 /* Alias word address of BYP_ADDR_PAR bit */ 85 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U) 86 #define BYPADDRPAR_BitNumber 0x04U 87 #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U)) 88 /** 89 * @} 90 */ 91 92 #if defined(SYSCFG_CFGR1_DMA_RMP) 93 /** @defgroup HAL_DMA_Remapping HAL DMA Remapping 94 * Elements values convention: 0xXXYYYYYY 95 * - YYYYYY : Position in the register 96 * - XX : Register index 97 * - 00: CFGR1 register in SYSCFG 98 * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices) 99 * @{ 100 */ 101 #define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 102 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */ 103 #define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap 104 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */ 105 #define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap 106 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */ 107 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 108 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */ 109 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 110 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */ 111 #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) 112 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ 113 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) 114 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ 115 #if defined(SYSCFG_CFGR3_DMA_RMP) 116 #if !defined(HAL_REMAP_CFGR3_MASK) 117 #define HAL_REMAP_CFGR3_MASK (0x01000000U) 118 #endif 119 120 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) 121 11: Map on DMA1 channel 2 */ 122 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) 123 01: Map on DMA1 channel 4 */ 124 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) 125 10: Map on DMA1 channel 6 */ 126 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) 127 11: Map on DMA1 channel 3 */ 128 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) 129 01: Map on DMA1 channel 5 */ 130 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) 131 10: Map on DMA1 channel 7 */ 132 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) 133 11: Map on DMA1 channel 7 */ 134 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) 135 01: Map on DMA1 channel 3 */ 136 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) 137 10: Map on DMA1 channel 5 */ 138 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) 139 11: Map on DMA1 channel 6 */ 140 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) 141 01: Map on DMA1 channel 2 */ 142 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) 143 10: Map on DMA1 channel 4 */ 144 #define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap 145 x0: No remap (ADC2 on DMA2) 146 10: Map on DMA1 channel 2 */ 147 #define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap 148 11: Map on DMA1 channel 4 */ 149 #endif /* SYSCFG_CFGR3_DMA_RMP */ 150 151 #if defined(SYSCFG_CFGR3_DMA_RMP) 152 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ 153 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ 154 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ 155 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ 156 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ 157 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ 158 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \ 159 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \ 160 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \ 161 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \ 162 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \ 163 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \ 164 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \ 165 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \ 166 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \ 167 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \ 168 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \ 169 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \ 170 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \ 171 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \ 172 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4)) 173 #else 174 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ 175 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ 176 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ 177 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ 178 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ 179 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ 180 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5)) 181 #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/ 182 /** 183 * @} 184 */ 185 #endif /* SYSCFG_CFGR1_DMA_RMP */ 186 187 /** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping 188 * Elements values convention: 0xXXYYYYYY 189 * - YYYYYY : Position in the register 190 * - XX : Register index 191 * - 00: CFGR1 register in SYSCFG 192 * - 01: CFGR3 register in SYSCFG 193 * @{ 194 */ 195 #define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices) 196 0: No remap (DAC trigger is TIM8_TRGO) 197 1: Remap (DAC trigger is TIM3_TRGO) */ 198 #define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap 199 0: No remap 200 1: Remap (TIM1_TRG3 = TIM17_OC) */ 201 #if defined(SYSCFG_CFGR3_TRIGGER_RMP) 202 #if !defined(HAL_REMAP_CFGR3_MASK) 203 #define HAL_REMAP_CFGR3_MASK (0x01000000U) 204 #endif 205 #define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap 206 0: Remap (DAC trigger is TIM15_TRGO) 207 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */ 208 #define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap 209 0: No remap 210 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */ 211 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ 212 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \ 213 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \ 214 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5)) 215 #else 216 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ 217 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3)) 218 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ 219 /** 220 * @} 221 */ 222 223 #if defined (STM32F302xE) 224 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping 225 * @{ 226 */ 227 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2 228 0: No remap (TIM1_CC3) 229 1: Remap (TIM20_TRGO) */ 230 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3 231 0: No remap (TIM2_CC2) 232 1: Remap (TIM20_TRGO2) */ 233 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5 234 0: No remap (TIM4_CC4) 235 1: Remap (TIM20_CC1) */ 236 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13 237 0: No remap (TIM6_TRGO) 238 1: Remap (TIM20_CC2) */ 239 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15 240 0: No remap (TIM3_CC4) 241 1: Remap (TIM20_CC3) */ 242 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3 243 0: No remap (TIM2_CC1) 244 1: Remap (TIM20_TRGO) */ 245 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 246 0: No remap (EXTI line 15) 247 1: Remap (TIM20_TRGO2) */ 248 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 249 0: No remap (TIM3_CC1) 250 1: Remap (TIM20_CC4) */ 251 252 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ 253 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ 254 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ 255 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \ 256 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \ 257 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ 258 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ 259 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13)) 260 /** 261 * @} 262 */ 263 #endif /* STM32F302xE */ 264 265 #if defined (STM32F303xE) || defined (STM32F398xx) 266 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping 267 * @{ 268 */ 269 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2 270 0: No remap (TIM1_CC3) 271 1: Remap (TIM20_TRGO) */ 272 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3 273 0: No remap (TIM2_CC2) 274 1: Remap (TIM20_TRGO2) */ 275 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5 276 0: No remap (TIM4_CC4) 277 1: Remap (TIM20_CC1) */ 278 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13 279 0: No remap (TIM6_TRGO) 280 1: Remap (TIM20_CC2) */ 281 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15 282 0: No remap (TIM3_CC4) 283 1: Remap (TIM20_CC3) */ 284 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3 285 0: No remap (TIM2_CC1) 286 1: Remap (TIM20_TRGO) */ 287 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 288 0: No remap (EXTI line 15) 289 1: Remap (TIM20_TRGO2) */ 290 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 291 0: No remap (TIM3_CC1) 292 1: Remap (TIM20_CC4) */ 293 #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5 294 0: No remap (EXTI line 2) 295 1: Remap (TIM20_TRGO) */ 296 #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6 297 0: No remap (TIM4_CC1) 298 1: Remap (TIM20_TRGO2) */ 299 #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15 300 0: No remap (TIM2_CC1) 301 1: Remap (TIM20_CC1) */ 302 #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5 303 0: No remap (TIM4_CC3) 304 1: Remap (TIM20_TRGO) */ 305 #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11 306 0: No remap (TIM1_CC3) 307 1: Remap (TIM20_TRGO2) */ 308 #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14 309 0: No remap (TIM7_TRGO) 310 1: Remap (TIM20_CC2) */ 311 312 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ 313 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ 314 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ 315 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \ 316 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \ 317 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ 318 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ 319 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \ 320 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \ 321 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \ 322 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \ 323 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \ 324 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \ 325 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14)) 326 /** 327 * @} 328 */ 329 #endif /* STM32F303xE || STM32F398xx */ 330 331 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 332 * @{ 333 */ 334 335 /** @brief Fast-mode Plus driving capability on a specific GPIO 336 */ 337 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP) 338 #define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */ 339 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */ 340 341 #if defined(SYSCFG_CFGR1_I2C_PB7_FMP) 342 #define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */ 343 #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */ 344 345 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 346 #define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */ 347 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 348 349 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 350 #define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */ 351 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 352 /** 353 * @} 354 */ 355 356 #if defined(SYSCFG_RCR_PAGE0) 357 /* CCM-SRAM defined */ 358 /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection 359 * @{ 360 */ 361 #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */ 362 #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */ 363 #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */ 364 #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */ 365 #if defined(SYSCFG_RCR_PAGE4) 366 /* More than 4KB CCM-SRAM defined */ 367 #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */ 368 #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */ 369 #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */ 370 #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */ 371 #endif /* SYSCFG_RCR_PAGE4 */ 372 #if defined(SYSCFG_RCR_PAGE8) 373 #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */ 374 #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */ 375 #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */ 376 #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */ 377 #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */ 378 #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */ 379 #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */ 380 #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */ 381 #endif /* SYSCFG_RCR_PAGE8 */ 382 383 #if defined(SYSCFG_RCR_PAGE8) 384 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU)) 385 #elif defined(SYSCFG_RCR_PAGE4) 386 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU)) 387 #else 388 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU)) 389 #endif /* SYSCFG_RCR_PAGE8 */ 390 /** 391 * @} 392 */ 393 #endif /* SYSCFG_RCR_PAGE0 */ 394 395 /** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts 396 * @{ 397 */ 398 #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */ 399 #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */ 400 #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */ 401 #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */ 402 #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */ 403 #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */ 404 405 #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \ 406 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \ 407 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \ 408 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \ 409 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \ 410 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5)) 411 412 /** 413 * @} 414 */ 415 416 /** 417 * @} 418 */ 419 420 /* Exported macros -----------------------------------------------------------*/ 421 /** @defgroup HAL_Exported_Macros HAL Exported Macros 422 * @{ 423 */ 424 425 /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode 426 * @{ 427 */ 428 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) 429 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) 430 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) 431 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ 432 433 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) 434 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) 435 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) 436 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ 437 438 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) 439 #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) 440 #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) 441 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */ 442 443 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP) 444 #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) 445 #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) 446 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */ 447 448 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) 449 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) 450 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) 451 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ 452 453 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) 454 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) 455 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) 456 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ 457 458 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) 459 #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) 460 #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) 461 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */ 462 463 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) 464 #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) 465 #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) 466 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */ 467 468 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) 469 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) 470 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) 471 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ 472 473 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP) 474 #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP)) 475 #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP)) 476 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ 477 478 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) 479 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) 480 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) 481 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ 482 483 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) 484 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) 485 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) 486 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ 487 488 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) 489 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) 490 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) 491 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ 492 493 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) 494 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) 495 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) 496 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ 497 498 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) 499 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) 500 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) 501 #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */ 502 503 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT) 504 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) 505 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) 506 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */ 507 508 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) 509 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) 510 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) 511 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ 512 /** 513 * @} 514 */ 515 516 /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode 517 * @{ 518 */ 519 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) 520 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) 521 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) 522 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ 523 524 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) 525 #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) 526 #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) 527 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */ 528 529 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) 530 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) 531 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) 532 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ 533 534 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) 535 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) 536 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) 537 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ 538 539 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) 540 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) 541 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) 542 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ 543 544 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP) 545 #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP)) 546 #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP)) 547 #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */ 548 549 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP) 550 #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP)) 551 #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP)) 552 #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */ 553 554 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP) 555 #define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)) 556 #define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)) 557 #endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */ 558 /** 559 * @} 560 */ 561 562 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection 563 * @{ 564 */ 565 #if defined(SYSCFG_CFGR1_MEM_MODE) 566 /** @brief Main Flash memory mapped at 0x00000000 567 */ 568 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) 569 #endif /* SYSCFG_CFGR1_MEM_MODE */ 570 571 #if defined(SYSCFG_CFGR1_MEM_MODE_0) 572 /** @brief System Flash memory mapped at 0x00000000 573 */ 574 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ 575 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ 576 }while(0U) 577 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ 578 579 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) 580 /** @brief Embedded SRAM mapped at 0x00000000 581 */ 582 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ 583 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ 584 }while(0U) 585 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ 586 587 #if defined(SYSCFG_CFGR1_MEM_MODE_2) 588 #define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ 589 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \ 590 }while(0U) 591 #endif /* SYSCFG_CFGR1_MEM_MODE_2 */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup Encoder_Mode Encoder Mode 597 * @{ 598 */ 599 #if defined(SYSCFG_CFGR1_ENCODER_MODE) 600 /** @brief No Encoder mode 601 */ 602 #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE)) 603 #endif /* SYSCFG_CFGR1_ENCODER_MODE */ 604 605 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) 606 /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 607 */ 608 #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ 609 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \ 610 }while(0U) 611 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */ 612 613 #if defined(SYSCFG_CFGR1_ENCODER_MODE_1) 614 /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 615 */ 616 #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ 617 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \ 618 }while(0U) 619 #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */ 620 621 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1) 622 /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices) 623 */ 624 #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ 625 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \ 626 }while(0U) 627 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup DMA_Remap_Enable DMA Remap Enable 633 * @{ 634 */ 635 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP) 636 /** @brief DMA remapping enable/disable macros 637 * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping 638 */ 639 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ 640 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ 641 (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ 642 (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \ 643 }while(0U) 644 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ 645 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ 646 (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ 647 (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \ 648 }while(0U) 649 #elif defined(SYSCFG_CFGR1_DMA_RMP) 650 /** @brief DMA remapping enable/disable macros 651 * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping 652 */ 653 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ 654 SYSCFG->CFGR1 |= (__DMA_REMAP__); \ 655 }while(0U) 656 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ 657 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ 658 }while(0U) 659 #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO 665 * @{ 666 */ 667 /** @brief Fast-mode Plus driving capability enable/disable macros 668 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. 669 * That you can find above these macros. 670 */ 671 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 672 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 673 }while(0U) 674 675 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 676 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 677 }while(0U) 678 /** 679 * @} 680 */ 681 682 /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable 683 * @{ 684 */ 685 /** @brief SYSCFG interrupt enable/disable macros 686 * @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts 687 */ 688 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ 689 SYSCFG->CFGR1 |= (__INTERRUPT__); \ 690 }while(0U) 691 692 #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ 693 SYSCFG->CFGR1 &= ~(__INTERRUPT__); \ 694 }while(0U) 695 /** 696 * @} 697 */ 698 699 #if defined(SYSCFG_CFGR1_USB_IT_RMP) 700 /** @defgroup USB_Interrupt_Remap USB Interrupt Remap 701 * @{ 702 */ 703 /** @brief USB interrupt remapping enable/disable macros 704 */ 705 #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP)) 706 #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP)) 707 /** 708 * @} 709 */ 710 #endif /* SYSCFG_CFGR1_USB_IT_RMP */ 711 712 #if defined(SYSCFG_CFGR1_VBAT) 713 /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable 714 * @{ 715 */ 716 /** @brief SYSCFG interrupt enable/disable macros 717 */ 718 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT)) 719 #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT)) 720 /** 721 * @} 722 */ 723 #endif /* SYSCFG_CFGR1_VBAT */ 724 725 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) 726 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable 727 * @{ 728 */ 729 /** @brief SYSCFG Break Lockup lock 730 * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input 731 * @note The selected configuration is locked and can be unlocked by system reset 732 */ 733 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ 734 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ 735 }while(0U) 736 /** 737 * @} 738 */ 739 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ 740 741 #if defined(SYSCFG_CFGR2_PVD_LOCK) 742 /** @defgroup PVD_Lock_Enable PVD Lock 743 * @{ 744 */ 745 /** @brief SYSCFG Break PVD lock 746 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register 747 * @note The selected configuration is locked and can be unlocked by system reset 748 */ 749 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ 750 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ 751 }while(0U) 752 /** 753 * @} 754 */ 755 #endif /* SYSCFG_CFGR2_PVD_LOCK */ 756 757 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) 758 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock 759 * @{ 760 */ 761 /** @brief SYSCFG Break SRAM PARITY lock 762 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 763 * @note The selected configuration is locked and can be unlocked by system reset 764 */ 765 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ 766 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ 767 }while(0U) 768 /** 769 * @} 770 */ 771 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ 772 773 /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable 774 * @{ 775 */ 776 #if defined(SYSCFG_CFGR3_TRIGGER_RMP) 777 /** @brief Trigger remapping enable/disable macros 778 * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping 779 */ 780 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ 781 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ 782 (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ 783 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \ 784 }while(0U) 785 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ 786 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ 787 (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ 788 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \ 789 }while(0U) 790 #else 791 /** @brief Trigger remapping enable/disable macros 792 * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping 793 */ 794 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ 795 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \ 796 }while(0U) 797 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ 798 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \ 799 }while(0U) 800 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ 801 /** 802 * @} 803 */ 804 805 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) 806 /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable 807 * @{ 808 */ 809 /** @brief ADC trigger remapping enable/disable macros 810 * @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping 811 */ 812 #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ 813 (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \ 814 }while(0U) 815 #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ 816 (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \ 817 }while(0U) 818 /** 819 * @} 820 */ 821 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 822 823 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR) 824 /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable 825 * @{ 826 */ 827 /** 828 * @brief Parity check on RAM disable macro 829 * @note Disabling the parity check on RAM locks the configuration bit. 830 * To re-enable the parity check on RAM perform a system reset. 831 */ 832 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U) 833 /** 834 * @} 835 */ 836 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */ 837 838 #if defined(SYSCFG_RCR_PAGE0) 839 /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable 840 * @{ 841 */ 842 /** @brief CCM RAM page write protection enable macro 843 * @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection 844 * @note write protection can only be disabled by a system reset 845 */ 846 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \ 847 SYSCFG->RCR |= (__PAGE_WP__); \ 848 }while(0U) 849 /** 850 * @} 851 */ 852 #endif /* SYSCFG_RCR_PAGE0 */ 853 854 /** 855 * @} 856 */ 857 /* Private macro -------------------------------------------------------------*/ 858 /** @defgroup HAL_Private_Macros HAL Private Macros 859 * @{ 860 */ 861 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 862 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 863 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 864 /** 865 * @} 866 */ 867 /* Exported functions --------------------------------------------------------*/ 868 /** @addtogroup HAL_Exported_Functions HAL Exported Functions 869 * @{ 870 */ 871 872 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 873 * @brief Initialization and de-initialization functions 874 * @{ 875 */ 876 /* Initialization and de-initialization functions ******************************/ 877 HAL_StatusTypeDef HAL_Init(void); 878 HAL_StatusTypeDef HAL_DeInit(void); 879 void HAL_MspInit(void); 880 void HAL_MspDeInit(void); 881 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 882 /** 883 * @} 884 */ 885 886 /* Exported variables ---------------------------------------------------------*/ 887 /** @addtogroup HAL_Exported_Variables 888 * @{ 889 */ 890 extern __IO uint32_t uwTick; 891 extern uint32_t uwTickPrio; 892 extern HAL_TickFreqTypeDef uwTickFreq; 893 /** 894 * @} 895 */ 896 897 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions 898 * @brief HAL Control functions 899 * @{ 900 */ 901 /* Peripheral Control functions ************************************************/ 902 void HAL_IncTick(void); 903 void HAL_Delay(uint32_t Delay); 904 void HAL_SuspendTick(void); 905 void HAL_ResumeTick(void); 906 uint32_t HAL_GetTick(void); 907 uint32_t HAL_GetTickPrio(void); 908 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 909 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 910 uint32_t HAL_GetHalVersion(void); 911 uint32_t HAL_GetREVID(void); 912 uint32_t HAL_GetDEVID(void); 913 uint32_t HAL_GetUIDw0(void); 914 uint32_t HAL_GetUIDw1(void); 915 uint32_t HAL_GetUIDw2(void); 916 void HAL_DBGMCU_EnableDBGSleepMode(void); 917 void HAL_DBGMCU_DisableDBGSleepMode(void); 918 void HAL_DBGMCU_EnableDBGStopMode(void); 919 void HAL_DBGMCU_DisableDBGStopMode(void); 920 void HAL_DBGMCU_EnableDBGStandbyMode(void); 921 void HAL_DBGMCU_DisableDBGStandbyMode(void); 922 /** 923 * @} 924 */ 925 926 /** 927 * @} 928 */ 929 930 /** 931 * @} 932 */ 933 934 /** 935 * @} 936 */ 937 938 #ifdef __cplusplus 939 } 940 #endif 941 942 #endif /* __STM32F3xx_HAL_H */ 943 944
