1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32H7xx_HAL_RCC_H 20 #define STM32H7xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32h7xx_hal_def.h" 28 29 /** @addtogroup STM32H7xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCC_Exported_Types RCC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLLState; /*!< The new state of the PLL. 49 This parameter can be a value of @ref RCC_PLL_Config */ 50 51 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 52 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 53 54 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 55 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 56 57 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 58 This parameter must be a number between Min_Data = 4 and Max_Data = 512 59 or between Min_Data = 8 and Max_Data = 420(*) 60 (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ 61 62 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 63 This parameter must be a number between Min_Data = 2 and Max_Data = 128 64 odd division factors are not allowed */ 65 66 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 67 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 68 69 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 70 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 71 uint32_t PLLRGE; /*!<PLLRGE: PLL1 clock Input range 72 This parameter must be a value of @ref RCC_PLL1_VCI_Range */ 73 uint32_t PLLVCOSEL; /*!<PLLVCOSEL: PLL1 clock Output range 74 This parameter must be a value of @ref RCC_PLL1_VCO_Range */ 75 76 uint32_t PLLFRACN; /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 77 PLL1 VCO It should be a value between 0 and 8191 */ 78 79 } RCC_PLLInitTypeDef; 80 81 /** 82 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 83 */ 84 typedef struct 85 { 86 uint32_t OscillatorType; /*!< The oscillators to be configured. 87 This parameter can be a value of @ref RCC_Oscillator_Type */ 88 89 uint32_t HSEState; /*!< The new state of the HSE. 90 This parameter can be a value of @ref RCC_HSE_Config */ 91 92 uint32_t LSEState; /*!< The new state of the LSE. 93 This parameter can be a value of @ref RCC_LSE_Config */ 94 95 uint32_t HSIState; /*!< The new state of the HSI. 96 This parameter can be a value of @ref RCC_HSI_Config */ 97 98 uint32_t HSICalibrationValue; /*!< The calibration trimming value. 99 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y 100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */ 101 102 uint32_t LSIState; /*!< The new state of the LSI. 103 This parameter can be a value of @ref RCC_LSI_Config */ 104 105 uint32_t HSI48State; /*!< The new state of the HSI48. 106 This parameter can be a value of @ref RCC_HSI48_Config */ 107 108 uint32_t CSIState; /*!< The new state of the CSI. 109 This parameter can be a value of @ref RCC_CSI_Config */ 110 111 uint32_t CSICalibrationValue; /*!< The calibration trimming value. 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y 113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */ 114 115 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 116 117 } RCC_OscInitTypeDef; 118 119 /** 120 * @brief RCC System, AHB and APB busses clock configuration structure definition 121 */ 122 typedef struct 123 { 124 uint32_t ClockType; /*!< The clock to be configured. 125 This parameter can be a value of @ref RCC_System_Clock_Type */ 126 127 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 128 This parameter can be a value of @ref RCC_System_Clock_Source */ 129 130 uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be 131 a value of @ref RCC_SYS_Clock_Source */ 132 133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 134 This parameter can be a value of @ref RCC_HCLK_Clock_Source */ 135 136 uint32_t APB3CLKDivider; /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK). 137 This parameter can be a value of @ref RCC_APB3_Clock_Source */ 138 139 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 140 This parameter can be a value of @ref RCC_APB1_Clock_Source */ 141 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 142 This parameter can be a value of @ref RCC_APB2_Clock_Source */ 143 uint32_t APB4CLKDivider; /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK). 144 This parameter can be a value of @ref RCC_APB4_Clock_Source */ 145 } RCC_ClkInitTypeDef; 146 147 /** 148 * @} 149 */ 150 151 /* Exported constants --------------------------------------------------------*/ 152 153 /** @defgroup RCC_Exported_Constants RCC Exported Constants 154 * @{ 155 */ 156 157 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type 158 * @{ 159 */ 160 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) 161 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) 162 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) 163 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) 164 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) 165 #define RCC_OSCILLATORTYPE_CSI (0x00000010U) 166 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) 167 168 /** 169 * @} 170 */ 171 172 /** @defgroup RCC_HSE_Config RCC HSE Config 173 * @{ 174 */ 175 #define RCC_HSE_OFF (0x00000000U) 176 #define RCC_HSE_ON RCC_CR_HSEON 177 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) 178 #if defined(RCC_CR_HSEEXT) 179 #define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)) 180 #endif /* RCC_CR_HSEEXT */ 181 182 /** 183 * @} 184 */ 185 186 /** @defgroup RCC_LSE_Config RCC LSE Config 187 * @{ 188 */ 189 #define RCC_LSE_OFF (0x00000000U) 190 #define RCC_LSE_ON RCC_BDCR_LSEON 191 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 192 #if defined(RCC_BDCR_LSEEXT) 193 #define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 194 #endif /* RCC_BDCR_LSEEXT */ 195 196 /** 197 * @} 198 */ 199 200 /** @defgroup RCC_HSI_Config RCC HSI Config 201 * @{ 202 */ 203 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ 204 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 205 206 #define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */ 207 #define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */ 208 #define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */ 209 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */ 210 211 212 #define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value for STM32H7 rev.V and above. (0x20 value for rev.Y handled within __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro ) */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup RCC_HSI48_Config RCC HSI48 Config 218 * @{ 219 */ 220 #define RCC_HSI48_OFF ((uint8_t)0x00) 221 #define RCC_HSI48_ON ((uint8_t)0x01) 222 223 /** 224 * @} 225 */ 226 227 /** @defgroup RCC_LSI_Config RCC LSI Config 228 * @{ 229 */ 230 #define RCC_LSI_OFF (0x00000000U) 231 #define RCC_LSI_ON RCC_CSR_LSION 232 233 /** 234 * @} 235 */ 236 237 /** @defgroup RCC_CSI_Config RCC CSI Config 238 * @{ 239 */ 240 #define RCC_CSI_OFF (0x00000000U) 241 #define RCC_CSI_ON RCC_CR_CSION 242 243 #define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value for STM32H7 rev.V and above. (0x10 value for rev.Y handled within __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro ) */ 244 /** 245 * @} 246 */ 247 248 /** @defgroup RCC_PLL_Config RCC PLL Config 249 * @{ 250 */ 251 #define RCC_PLL_NONE (0x00000000U) 252 #define RCC_PLL_OFF (0x00000001U) 253 #define RCC_PLL_ON (0x00000002U) 254 255 /** 256 * @} 257 */ 258 259 260 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source 261 * @{ 262 */ 263 #define RCC_PLLSOURCE_HSI (0x00000000U) 264 #define RCC_PLLSOURCE_CSI (0x00000001U) 265 #define RCC_PLLSOURCE_HSE (0x00000002U) 266 #define RCC_PLLSOURCE_NONE (0x00000003U) 267 /** 268 * @} 269 */ 270 271 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output 272 * @{ 273 */ 274 #define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN 275 #define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN 276 #define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN 277 278 /** 279 * @} 280 */ 281 282 283 284 /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range 285 * @{ 286 */ 287 #define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ 288 #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ 289 #define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ 290 #define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ 291 292 293 /** 294 * @} 295 */ 296 297 298 /** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range 299 * @{ 300 */ 301 #define RCC_PLL1VCOWIDE (0x00000000U) 302 #define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL 303 304 /** 305 * @} 306 */ 307 308 309 /** @defgroup RCC_System_Clock_Type RCC System Clock Type 310 * @{ 311 */ 312 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) 313 #define RCC_CLOCKTYPE_HCLK (0x00000002U) 314 #define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U) 315 #define RCC_CLOCKTYPE_PCLK1 (0x00000008U) 316 #define RCC_CLOCKTYPE_PCLK2 (0x00000010U) 317 #define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U) 318 319 /** 320 * @} 321 */ 322 323 /** @defgroup RCC_System_Clock_Source RCC System Clock Source 324 * @{ 325 */ 326 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI 327 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI 328 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE 329 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1 330 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 336 * @{ 337 */ 338 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */ 339 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 340 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 341 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source 347 * @{ 348 */ 349 #if defined(RCC_D1CFGR_D1CPRE_DIV1) 350 #define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1 351 #define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2 352 #define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4 353 #define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8 354 #define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16 355 #define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64 356 #define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128 357 #define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256 358 #define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512 359 #else 360 #define RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1 361 #define RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2 362 #define RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4 363 #define RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8 364 #define RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16 365 #define RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64 366 #define RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128 367 #define RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256 368 #define RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512 369 #endif 370 /** 371 * @} 372 */ 373 374 375 /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source 376 * @{ 377 */ 378 #if defined(RCC_D1CFGR_HPRE_DIV1) 379 #define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1 380 #define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2 381 #define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4 382 #define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8 383 #define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16 384 #define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64 385 #define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128 386 #define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256 387 #define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512 388 #else 389 #define RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1 390 #define RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2 391 #define RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4 392 #define RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8 393 #define RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16 394 #define RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64 395 #define RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128 396 #define RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256 397 #define RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512 398 #endif 399 /** 400 * @} 401 */ 402 403 /** @defgroup RCC_APB3_Clock_Source RCC APB3 Clock Source 404 * @{ 405 */ 406 #if defined (RCC_D1CFGR_D1PPRE_DIV1) 407 #define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1 408 #define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2 409 #define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4 410 #define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8 411 #define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16 412 #else 413 #define RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1 414 #define RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2 415 #define RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4 416 #define RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8 417 #define RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16 418 #endif 419 /** 420 * @} 421 */ 422 423 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source 424 * @{ 425 */ 426 #if defined (RCC_D2CFGR_D2PPRE1_DIV1) 427 #define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1 428 #define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2 429 #define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4 430 #define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8 431 #define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16 432 #else 433 #define RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1 434 #define RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2 435 #define RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4 436 #define RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8 437 #define RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16 438 #endif 439 440 /** 441 * @} 442 */ 443 444 /** @defgroup RCC_APB2_Clock_Source RCC APB2 Clock Source 445 * @{ 446 */ 447 #if defined (RCC_D2CFGR_D2PPRE2_DIV1) 448 #define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1 449 #define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2 450 #define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4 451 #define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8 452 #define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16 453 #else 454 #define RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1 455 #define RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2 456 #define RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4 457 #define RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8 458 #define RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16 459 #endif 460 /** 461 * @} 462 */ 463 464 /** @defgroup RCC_APB4_Clock_Source RCC APB4 Clock Source 465 * @{ 466 */ 467 #if defined(RCC_D3CFGR_D3PPRE_DIV1) 468 #define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1 469 #define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2 470 #define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4 471 #define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8 472 #define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16 473 #else 474 #define RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1 475 #define RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2 476 #define RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4 477 #define RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8 478 #define RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16 479 #endif 480 /** 481 * @} 482 */ 483 484 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source 485 * @{ 486 */ 487 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) 488 #define RCC_RTCCLKSOURCE_LSE (0x00000100U) 489 #define RCC_RTCCLKSOURCE_LSI (0x00000200U) 490 #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) 491 #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) 492 #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) 493 #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) 494 #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) 495 #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) 496 #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) 497 #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) 498 #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) 499 #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) 500 #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) 501 #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) 502 #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) 503 #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) 504 #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) 505 #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) 506 #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) 507 #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) 508 #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) 509 #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) 510 #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) 511 #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) 512 #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) 513 #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) 514 #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) 515 #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) 516 #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U) 517 #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) 518 #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) 519 #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) 520 #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) 521 #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) 522 #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) 523 #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) 524 #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) 525 #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) 526 #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) 527 #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) 528 #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) 529 #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) 530 #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) 531 #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) 532 #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) 533 #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) 534 #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) 535 #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) 536 #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) 537 #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) 538 #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) 539 #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) 540 #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) 541 #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) 542 #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) 543 #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) 544 #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) 545 #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) 546 #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) 547 #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) 548 #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) 549 #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) 550 #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) 551 #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) 552 553 554 /** 555 * @} 556 */ 557 558 559 /** @defgroup RCC_MCO_Index RCC MCO Index 560 * @{ 561 */ 562 #define RCC_MCO1 (0x00000000U) 563 #define RCC_MCO2 (0x00000001U) 564 565 /** 566 * @} 567 */ 568 569 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source 570 * @{ 571 */ 572 #define RCC_MCO1SOURCE_HSI (0x00000000U) 573 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 574 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 575 #define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1) 576 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2 577 578 /** 579 * @} 580 */ 581 582 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source 583 * @{ 584 */ 585 #define RCC_MCO2SOURCE_SYSCLK (0x00000000U) 586 #define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0 587 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 588 #define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1) 589 #define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2 590 #define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2) 591 592 /** 593 * @} 594 */ 595 596 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCOx Clock Prescaler 597 * @{ 598 */ 599 #define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0 600 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1 601 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) 602 #define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2 603 #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 604 #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 605 #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 606 #define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3 607 #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) 608 #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) 609 #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) 610 #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 611 #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 612 #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) 613 #define RCC_MCODIV_15 RCC_CFGR_MCO1PRE 614 615 616 /** 617 * @} 618 */ 619 620 /** @defgroup RCC_Interrupt RCC Interrupt 621 * @{ 622 */ 623 #define RCC_IT_LSIRDY (0x00000001U) 624 #define RCC_IT_LSERDY (0x00000002U) 625 #define RCC_IT_HSIRDY (0x00000004U) 626 #define RCC_IT_HSERDY (0x00000008U) 627 #define RCC_IT_CSIRDY (0x00000010U) 628 #define RCC_IT_HSI48RDY (0x00000020U) 629 #define RCC_IT_PLLRDY (0x00000040U) 630 #define RCC_IT_PLL2RDY (0x00000080U) 631 #define RCC_IT_PLL3RDY (0x00000100U) 632 #define RCC_IT_LSECSS (0x00000200U) 633 #define RCC_IT_CSS (0x00000400U) 634 /** 635 * @} 636 */ 637 638 /** @defgroup RCC_Flag RCC Flag 639 * Elements values convention: XXXYYYYYb 640 * - YYYYY : Flag position in the register 641 * - XXX : Register index 642 * - 001: CR register 643 * - 010: BDCR register 644 * - 011: CSR register 645 * - 100: RSR register 646 * @{ 647 */ 648 /* Flags in the CR register */ 649 #define RCC_FLAG_HSIRDY ((uint8_t)0x22) 650 #define RCC_FLAG_HSIDIV ((uint8_t)0x25) 651 #define RCC_FLAG_CSIRDY ((uint8_t)0x28) 652 #define RCC_FLAG_HSI48RDY ((uint8_t)0x2D) 653 #if defined(RCC_CR_D1CKRDY) 654 #define RCC_FLAG_D1CKRDY ((uint8_t)0x2E) 655 #else 656 #define RCC_FLAG_CPUCKRDY ((uint8_t)0x2E) 657 #define RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */ 658 #endif /* RCC_CR_D1CKRDY */ 659 #if defined(RCC_CR_D2CKRDY) 660 #define RCC_FLAG_D2CKRDY ((uint8_t)0x2F) 661 #else 662 #define RCC_FLAG_CDCKRDY ((uint8_t)0x2F) 663 #define RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */ 664 #endif /* RCC_CR_D2CKRDY */ 665 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 666 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 667 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) 668 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) 669 /* Flags in the BDCR register */ 670 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 671 672 /* Flags in the CSR register */ 673 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 674 675 /* Flags in the RSR register */ 676 #if defined(RCC_RSR_CPURSTF) 677 #define RCC_FLAG_CPURST ((uint8_t)0x91) 678 #endif /* RCC_RSR_CPURSTF */ 679 680 #if defined(RCC_RSR_D1RSTF) 681 #define RCC_FLAG_D1RST ((uint8_t)0x93) 682 #else 683 #define RCC_FLAG_CDRST ((uint8_t)0x93) 684 #endif /* RCC_RSR_D1RSTF */ 685 #if defined(RCC_RSR_D2RSTF) 686 #define RCC_FLAG_D2RST ((uint8_t)0x94) 687 #endif /* RCC_RSR_D2RSTF */ 688 #define RCC_FLAG_BORRST ((uint8_t)0x95) 689 #define RCC_FLAG_PINRST ((uint8_t)0x96) 690 #define RCC_FLAG_PORRST ((uint8_t)0x97) 691 #define RCC_FLAG_SFTRST ((uint8_t)0x98) 692 #define RCC_FLAG_IWDG1RST ((uint8_t)0x9A) 693 #define RCC_FLAG_WWDG1RST ((uint8_t)0x9C) 694 #define RCC_FLAG_LPWR1RST ((uint8_t)0x9E) 695 #define RCC_FLAG_LPWR2RST ((uint8_t)0x9F) 696 697 #if defined(DUAL_CORE) 698 #define RCC_FLAG_C1RST (RCC_FLAG_CPURST) 699 #define RCC_FLAG_C2RST ((uint8_t)0x92) 700 #define RCC_FLAG_SFTR1ST (RCC_FLAG_SFTRST) 701 #define RCC_FLAG_SFTR2ST ((uint8_t)0x99) 702 #define RCC_FLAG_WWDG2RST ((uint8_t)0x9D) 703 #define RCC_FLAG_IWDG2RST ((uint8_t)0x9B) 704 #endif /*DUAL_CORE*/ 705 706 707 /** 708 * @} 709 */ 710 711 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 712 * @{ 713 */ 714 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ 715 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 716 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 717 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 718 /** 719 * @} 720 */ 721 722 /** @defgroup RCC_Stop_WakeUpClock RCC Stop WakeUpClock 723 * @{ 724 */ 725 #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) 726 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK 727 728 /** 729 * @} 730 */ 731 732 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 733 * @{ 734 */ 735 #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) 736 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK 737 738 739 /** 740 * @} 741 */ 742 743 #if defined(RCC_VER_X) 744 #define HAL_RCC_REV_Y_HSITRIM_Pos (12U) 745 #define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U) 746 #define HAL_RCC_REV_Y_CSITRIM_Pos (26U) 747 #define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U) 748 #endif /* RCC_VER_X */ 749 750 /** 751 * @} 752 */ 753 754 /* Exported macros -----------------------------------------------------------*/ 755 756 /** @defgroup RCC_Exported_Macros RCC Exported Macros 757 * @{ 758 */ 759 760 /** @brief Enable or disable the AHB3 peripheral clock. 761 * @note After reset, the peripheral clock (used for registers read/write access) 762 * is disabled and the application software has to enable this clock before 763 * using it. 764 */ 765 #define __HAL_RCC_MDMA_CLK_ENABLE() do { \ 766 __IO uint32_t tmpreg; \ 767 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 768 /* Delay after an RCC peripheral clock enabling */ \ 769 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 770 UNUSED(tmpreg); \ 771 } while(0) 772 773 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 774 __IO uint32_t tmpreg; \ 775 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 776 /* Delay after an RCC peripheral clock enabling */ \ 777 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 778 UNUSED(tmpreg); \ 779 } while(0) 780 781 #if defined(JPEG) 782 #define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \ 783 __IO uint32_t tmpreg; \ 784 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 785 /* Delay after an RCC peripheral clock enabling */ \ 786 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 787 UNUSED(tmpreg); \ 788 } while(0) 789 #endif /* JPEG */ 790 791 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 792 __IO uint32_t tmpreg; \ 793 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 794 /* Delay after an RCC peripheral clock enabling */ \ 795 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 796 UNUSED(tmpreg); \ 797 } while(0) 798 799 #if defined(QUADSPI) 800 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 801 __IO uint32_t tmpreg; \ 802 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 803 /* Delay after an RCC peripheral clock enabling */ \ 804 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 805 UNUSED(tmpreg); \ 806 } while(0) 807 #endif /* QUADSPI */ 808 #if defined(OCTOSPI1) 809 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 810 __IO uint32_t tmpreg; \ 811 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ 812 /* Delay after an RCC peripheral clock enabling */ \ 813 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ 814 UNUSED(tmpreg); \ 815 } while(0) 816 #endif /* OCTOSPI1 */ 817 #if defined(OCTOSPI2) 818 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 819 __IO uint32_t tmpreg; \ 820 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ 821 /* Delay after an RCC peripheral clock enabling */ \ 822 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ 823 UNUSED(tmpreg); \ 824 } while(0) 825 #endif /* OCTOSPI2 */ 826 #if defined(OCTOSPIM) 827 #define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \ 828 __IO uint32_t tmpreg; \ 829 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ 830 /* Delay after an RCC peripheral clock enabling */ \ 831 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ 832 UNUSED(tmpreg); \ 833 } while(0) 834 #endif /* OCTOSPIM */ 835 #if defined(OTFDEC1) 836 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 837 __IO uint32_t tmpreg; \ 838 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ 839 /* Delay after an RCC peripheral clock enabling */ \ 840 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ 841 UNUSED(tmpreg); \ 842 } while(0) 843 #endif /* OTFDEC1 */ 844 #if defined(OTFDEC2) 845 #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ 846 __IO uint32_t tmpreg; \ 847 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ 848 /* Delay after an RCC peripheral clock enabling */ \ 849 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ 850 UNUSED(tmpreg); \ 851 } while(0) 852 #endif /* OTFDEC2 */ 853 #if defined(GFXMMU) 854 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 855 __IO uint32_t tmpreg; \ 856 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ 857 /* Delay after an RCC peripheral clock enabling */ \ 858 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ 859 UNUSED(tmpreg); \ 860 } while(0) 861 #endif /* GFXMMU */ 862 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 863 __IO uint32_t tmpreg; \ 864 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 865 /* Delay after an RCC peripheral clock enabling */ \ 866 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 867 UNUSED(tmpreg); \ 868 } while(0) 869 870 871 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) 872 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) 873 #if defined(JPEG) 874 #define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) 875 #endif /* JPEG */ 876 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) 877 878 #if defined(QUADSPI) 879 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) 880 #endif /* QUADSPI */ 881 #if defined(OCTOSPI1) 882 #define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN)) 883 #endif /* OCTOSPII */ 884 #if defined(OCTOSPI2) 885 #define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN)) 886 #endif /* OCTOSPI2 */ 887 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) 888 #if defined(OCTOSPIM) 889 #define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN)) 890 #endif /* OCTOSPIM */ 891 #if defined(OTFDEC1) 892 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN)) 893 #endif /* OTOFDEC1 */ 894 #if defined(OTFDEC2) 895 #define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN)) 896 #endif /* OTOFDEC2 */ 897 #if defined(GFXMMU) 898 #define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN)) 899 #endif /* GFXMMU */ 900 901 /** @brief Get the enable or disable status of the AHB3 peripheral clock 902 * @note After reset, the peripheral clock (used for registers read/write access) 903 * is disabled and the application software has to enable this clock before 904 * using it. 905 */ 906 907 #define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) 908 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) 909 #if defined(JPEG) 910 #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) 911 #endif /* JPEG */ 912 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) 913 #if defined (QUADSPI) 914 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) 915 #endif /* QUADSPI */ 916 #if defined(OCTOSPI1) 917 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U) 918 #endif /* OCTOSPII */ 919 #if defined(OCTOSPI2) 920 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U) 921 #endif /* OCTOSPI2 */ 922 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) 923 #if defined(OCTOSPIM) 924 #define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U) 925 #endif /* OCTOSPIM */ 926 #if defined(OTFDEC1) 927 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U) 928 #endif /* OTOFDEC1 */ 929 #if defined(OTFDEC2) 930 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U) 931 #endif /* OTOFDEC2 */ 932 #if defined(GFXMMU) 933 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U) 934 #endif /* GFXMMU */ 935 936 #define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) 937 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) 938 #if defined(JPEG) 939 #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) 940 #endif /* JPEG */ 941 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) 942 #if defined (QUADSPI) 943 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) 944 #endif /* QUADSPI */ 945 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) 946 #if defined(OCTOSPI1) 947 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U) 948 #endif 949 #if defined(OCTOSPI2) 950 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U) 951 #endif 952 #if defined(OCTOSPIM) 953 #define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U) 954 #endif 955 #if defined(OTFDEC1) 956 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U) 957 #endif 958 #if defined(OTFDEC2) 959 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U) 960 #endif 961 #if defined(GFXMMU) 962 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U) 963 #endif 964 /** @brief Enable or disable the AHB1 peripheral clock. 965 * @note After reset, the peripheral clock (used for registers read/write access) 966 * is disabled and the application software has to enable this clock before 967 * using it. 968 */ 969 970 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 971 __IO uint32_t tmpreg; \ 972 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 973 /* Delay after an RCC peripheral clock enabling */ \ 974 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 975 UNUSED(tmpreg); \ 976 } while(0) 977 978 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 979 __IO uint32_t tmpreg; \ 980 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 981 /* Delay after an RCC peripheral clock enabling */ \ 982 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 983 UNUSED(tmpreg); \ 984 } while(0) 985 986 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 987 __IO uint32_t tmpreg; \ 988 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 989 /* Delay after an RCC peripheral clock enabling */ \ 990 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 991 UNUSED(tmpreg); \ 992 } while(0) 993 994 #if defined(DUAL_CORE) 995 #define __HAL_RCC_ART_CLK_ENABLE() do { \ 996 __IO uint32_t tmpreg; \ 997 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 998 /* Delay after an RCC peripheral clock enabling */ \ 999 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 1000 UNUSED(tmpreg); \ 1001 } while(0) 1002 #endif /*DUAL_CORE*/ 1003 1004 #if defined(RCC_AHB1ENR_CRCEN) 1005 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 1006 __IO uint32_t tmpreg; \ 1007 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 1008 /* Delay after an RCC peripheral clock enabling */ \ 1009 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 1010 UNUSED(tmpreg); \ 1011 } while(0) 1012 #endif 1013 1014 #if defined(ETH) 1015 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ 1016 __IO uint32_t tmpreg; \ 1017 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 1018 /* Delay after an RCC peripheral clock enabling */ \ 1019 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 1020 UNUSED(tmpreg); \ 1021 } while(0) 1022 1023 #define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ 1024 __IO uint32_t tmpreg; \ 1025 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 1026 /* Delay after an RCC peripheral clock enabling */ \ 1027 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 1028 UNUSED(tmpreg); \ 1029 } while(0) 1030 1031 #define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ 1032 __IO uint32_t tmpreg; \ 1033 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 1034 /* Delay after an RCC peripheral clock enabling */ \ 1035 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 1036 UNUSED(tmpreg); \ 1037 } while(0) 1038 #endif 1039 1040 #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \ 1041 __IO uint32_t tmpreg; \ 1042 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 1043 /* Delay after an RCC peripheral clock enabling */ \ 1044 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 1045 UNUSED(tmpreg); \ 1046 } while(0) 1047 1048 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ 1049 __IO uint32_t tmpreg; \ 1050 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 1051 /* Delay after an RCC peripheral clock enabling */ \ 1052 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 1053 UNUSED(tmpreg); \ 1054 } while(0) 1055 1056 #if defined(USB2_OTG_FS) 1057 #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \ 1058 __IO uint32_t tmpreg; \ 1059 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 1060 /* Delay after an RCC peripheral clock enabling */ \ 1061 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 1062 UNUSED(tmpreg); \ 1063 } while(0) 1064 1065 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ 1066 __IO uint32_t tmpreg; \ 1067 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 1068 /* Delay after an RCC peripheral clock enabling */ \ 1069 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 1070 UNUSED(tmpreg); \ 1071 } while(0) 1072 #endif 1073 1074 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) 1075 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) 1076 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) 1077 #if defined(DUAL_CORE) 1078 #define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) 1079 #endif /*DUAL_CORE*/ 1080 #if defined(RCC_AHB1ENR_CRCEN) 1081 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN)) 1082 #endif 1083 #if defined(ETH) 1084 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) 1085 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) 1086 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) 1087 #endif 1088 #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) 1089 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) 1090 #if defined(USB2_OTG_FS) 1091 #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) 1092 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) 1093 #endif /* USB2_OTG_FS */ 1094 1095 /** @brief Get the enable or disable status of the AHB1 peripheral clock 1096 * @note After reset, the peripheral clock (used for registers read/write access) 1097 * is disabled and the application software has to enable this clock before 1098 * using it. 1099 */ 1100 1101 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U) 1102 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U) 1103 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U) 1104 #if defined(DUAL_CORE) 1105 #define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U) 1106 #endif /*DUAL_CORE*/ 1107 #if defined(RCC_AHB1ENR_CRCEN) 1108 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U) 1109 #endif 1110 #if defined(ETH) 1111 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) 1112 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) 1113 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) 1114 #endif 1115 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) 1116 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) 1117 #if defined(USB2_OTG_FS) 1118 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) 1119 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U) 1120 #endif /* USB2_OTG_FS */ 1121 1122 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) 1123 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) 1124 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U) 1125 #if defined(DUAL_CORE) 1126 #define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U) 1127 #endif /*DUAL_CORE*/ 1128 #if defined(RCC_AHB1ENR_CRCEN) 1129 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U) 1130 #endif 1131 #if defined(ETH) 1132 #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) 1133 #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) 1134 #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) 1135 #endif 1136 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) 1137 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) 1138 #if defined(USB2_OTG_FS) 1139 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) 1140 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U) 1141 #endif /* USB2_OTG_FS */ 1142 1143 /** @brief Enable or disable the AHB2 peripheral clock. 1144 * @note After reset, the peripheral clock (used for registers read/write access) 1145 * is disabled and the application software has to enable this clock before 1146 * using it. 1147 */ 1148 1149 #if defined(DCMI) && defined(PSSI) 1150 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 1151 __IO uint32_t tmpreg; \ 1152 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1153 /* Delay after an RCC peripheral clock enabling */ \ 1154 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1155 UNUSED(tmpreg); \ 1156 } while(0) 1157 1158 #define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/ 1159 #else 1160 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 1161 __IO uint32_t tmpreg; \ 1162 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1163 /* Delay after an RCC peripheral clock enabling */ \ 1164 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1165 UNUSED(tmpreg); \ 1166 } while(0) 1167 #endif /* DCMI && PSSI */ 1168 1169 #if defined(CRYP) 1170 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 1171 __IO uint32_t tmpreg; \ 1172 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1173 /* Delay after an RCC peripheral clock enabling */ \ 1174 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1175 UNUSED(tmpreg); \ 1176 } while(0) 1177 #endif /* CRYP */ 1178 1179 #if defined(HASH) 1180 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1181 __IO uint32_t tmpreg; \ 1182 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1183 /* Delay after an RCC peripheral clock enabling */ \ 1184 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1185 UNUSED(tmpreg); \ 1186 } while(0) 1187 #endif /* HASH */ 1188 1189 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1190 __IO uint32_t tmpreg; \ 1191 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1192 /* Delay after an RCC peripheral clock enabling */ \ 1193 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1194 UNUSED(tmpreg); \ 1195 } while(0) 1196 1197 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 1198 __IO uint32_t tmpreg; \ 1199 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 1200 /* Delay after an RCC peripheral clock enabling */ \ 1201 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 1202 UNUSED(tmpreg); \ 1203 } while(0) 1204 1205 #if defined(FMAC) 1206 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 1207 __IO uint32_t tmpreg; \ 1208 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ 1209 /* Delay after an RCC peripheral clock enabling */ \ 1210 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ 1211 UNUSED(tmpreg); \ 1212 } while(0) 1213 #endif /* FMAC */ 1214 1215 #if defined(CORDIC) 1216 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 1217 __IO uint32_t tmpreg; \ 1218 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ 1219 /* Delay after an RCC peripheral clock enabling */ \ 1220 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ 1221 UNUSED(tmpreg); \ 1222 } while(0) 1223 #endif /* CORDIC */ 1224 1225 #if defined(RCC_AHB2ENR_D2SRAM1EN) 1226 #define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \ 1227 __IO uint32_t tmpreg; \ 1228 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 1229 /* Delay after an RCC peripheral clock enabling */ \ 1230 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 1231 UNUSED(tmpreg); \ 1232 } while(0) 1233 #else 1234 #define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \ 1235 __IO uint32_t tmpreg; \ 1236 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ 1237 /* Delay after an RCC peripheral clock enabling */ \ 1238 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ 1239 UNUSED(tmpreg); \ 1240 } while(0) 1241 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 1242 1243 #if defined(RCC_AHB2ENR_D2SRAM2EN) 1244 #define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \ 1245 __IO uint32_t tmpreg; \ 1246 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 1247 /* Delay after an RCC peripheral clock enabling */ \ 1248 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 1249 UNUSED(tmpreg); \ 1250 } while(0) 1251 #else 1252 #define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \ 1253 __IO uint32_t tmpreg; \ 1254 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ 1255 /* Delay after an RCC peripheral clock enabling */ \ 1256 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ 1257 UNUSED(tmpreg); \ 1258 } while(0) 1259 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 1260 1261 #if defined(RCC_AHB2ENR_D2SRAM3EN) 1262 #define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \ 1263 __IO uint32_t tmpreg; \ 1264 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 1265 /* Delay after an RCC peripheral clock enabling */ \ 1266 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 1267 UNUSED(tmpreg); \ 1268 } while(0) 1269 #endif 1270 1271 #if defined(RCC_AHB2ENR_HSEMEN) 1272 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ 1273 __IO uint32_t tmpreg; \ 1274 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ 1275 /* Delay after an RCC peripheral clock enabling */ \ 1276 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ 1277 UNUSED(tmpreg); \ 1278 } while(0) 1279 #endif /* RCC_AHB2ENR_HSEMEN */ 1280 1281 #if defined(BDMA1) 1282 #define __HAL_RCC_BDMA1_CLK_ENABLE() do { \ 1283 __IO uint32_t tmpreg; \ 1284 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ 1285 /* Delay after an RCC peripheral clock enabling */ \ 1286 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ 1287 UNUSED(tmpreg); \ 1288 } while(0) 1289 #endif /* BDMA1 */ 1290 1291 #if defined(DCMI) && defined(PSSI) 1292 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN)) 1293 #define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ 1294 #else 1295 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) 1296 #endif /* DCMI && PSSI */ 1297 #if defined(CRYP) 1298 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) 1299 #endif /* CRYP */ 1300 #if defined(HASH) 1301 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) 1302 #endif /* HASH */ 1303 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) 1304 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) 1305 #if defined(FMAC) 1306 #define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN)) 1307 #endif /* FMAC */ 1308 #if defined(CORDIC) 1309 #define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN)) 1310 #endif /* CORDIC */ 1311 #if defined(RCC_AHB2ENR_D2SRAM1EN) 1312 #define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) 1313 #else 1314 #define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN)) 1315 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 1316 #if defined(RCC_AHB2ENR_D2SRAM2EN) 1317 #define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) 1318 #else 1319 #define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN)) 1320 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 1321 #if defined(RCC_AHB2ENR_D2SRAM3EN) 1322 #define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) 1323 #endif 1324 #if defined(RCC_AHB2ENR_HSEMEN) 1325 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN)) 1326 #endif 1327 #if defined(BDMA1) 1328 #define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN)) 1329 #endif 1330 1331 /** @brief Get the enable or disable status of the AHB2 peripheral clock 1332 * @note After reset, the peripheral clock (used for registers read/write access) 1333 * is disabled and the application software has to enable this clock before 1334 * using it. 1335 */ 1336 1337 #if defined(DCMI) && defined(PSSI) 1338 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U) 1339 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/ 1340 #else 1341 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) 1342 #endif /* DCMI && PSSI */ 1343 #if defined(CRYP) 1344 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) 1345 #endif /* CRYP */ 1346 #if defined(HASH) 1347 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) 1348 #endif /* HASH */ 1349 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) 1350 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) 1351 #if defined(FMAC) 1352 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U) 1353 #endif /* FMAC */ 1354 #if defined(CORDIC) 1355 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U) 1356 #endif /* CORDIC */ 1357 #if defined(RCC_AHB2ENR_D2SRAM1EN) 1358 #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) 1359 #else 1360 #define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U) 1361 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 1362 #if defined(RCC_AHB2ENR_D2SRAM2EN) 1363 #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) 1364 #else 1365 #define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U) 1366 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 1367 #if defined(RCC_AHB2ENR_D2SRAM3EN) 1368 #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) 1369 #endif 1370 #if defined(RCC_AHB2ENR_HSEMEN) 1371 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U) 1372 #endif 1373 #if defined(BDMA1) 1374 #define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U) 1375 #endif 1376 1377 #if defined(DCMI) && defined(PSSI) 1378 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U) 1379 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/ 1380 #else 1381 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) 1382 #endif /* DCMI && PSSI */ 1383 #if defined(CRYP) 1384 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) 1385 #endif /* CRYP */ 1386 #if defined(HASH) 1387 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) 1388 #endif /* HASH */ 1389 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) 1390 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) 1391 #if defined(FMAC) 1392 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U) 1393 #endif /* FMAC */ 1394 #if defined(CORDIC) 1395 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U) 1396 #endif /* CORDIC */ 1397 #if defined(RCC_AHB2ENR_D2SRAM1EN) 1398 #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) 1399 #else 1400 #define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U) 1401 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 1402 #if defined(RCC_AHB2ENR_D2SRAM2EN) 1403 #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) 1404 #else 1405 #define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U) 1406 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 1407 #if defined(RCC_AHB2ENR_D2SRAM3EN) 1408 #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) 1409 #endif 1410 #if defined(RCC_AHB2ENR_HSEMEN) 1411 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U) 1412 #endif 1413 #if defined(BDMA1) 1414 #define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U) 1415 #endif 1416 1417 /** @brief Enable or disable the AHB4 peripheral clock. 1418 * @note After reset, the peripheral clock (used for registers read/write access) 1419 * is disabled and the application software has to enable this clock before 1420 * using it. 1421 */ 1422 1423 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 1424 __IO uint32_t tmpreg; \ 1425 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 1426 /* Delay after an RCC peripheral clock enabling */ \ 1427 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 1428 UNUSED(tmpreg); \ 1429 } while(0) 1430 1431 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 1432 __IO uint32_t tmpreg; \ 1433 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 1434 /* Delay after an RCC peripheral clock enabling */ \ 1435 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 1436 UNUSED(tmpreg); \ 1437 } while(0) 1438 1439 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 1440 __IO uint32_t tmpreg; \ 1441 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 1442 /* Delay after an RCC peripheral clock enabling */ \ 1443 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 1444 UNUSED(tmpreg); \ 1445 } while(0) 1446 1447 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 1448 __IO uint32_t tmpreg; \ 1449 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 1450 /* Delay after an RCC peripheral clock enabling */ \ 1451 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 1452 UNUSED(tmpreg); \ 1453 } while(0) 1454 1455 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 1456 __IO uint32_t tmpreg; \ 1457 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 1458 /* Delay after an RCC peripheral clock enabling */ \ 1459 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 1460 UNUSED(tmpreg); \ 1461 } while(0) 1462 1463 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1464 __IO uint32_t tmpreg; \ 1465 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 1466 /* Delay after an RCC peripheral clock enabling */ \ 1467 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 1468 UNUSED(tmpreg); \ 1469 } while(0) 1470 1471 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1472 __IO uint32_t tmpreg; \ 1473 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 1474 /* Delay after an RCC peripheral clock enabling */ \ 1475 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 1476 UNUSED(tmpreg); \ 1477 } while(0) 1478 1479 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 1480 __IO uint32_t tmpreg; \ 1481 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 1482 /* Delay after an RCC peripheral clock enabling */ \ 1483 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 1484 UNUSED(tmpreg); \ 1485 } while(0) 1486 1487 #if defined(GPIOI) 1488 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 1489 __IO uint32_t tmpreg; \ 1490 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 1491 /* Delay after an RCC peripheral clock enabling */ \ 1492 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 1493 UNUSED(tmpreg); \ 1494 } while(0) 1495 #endif /* GPIOI */ 1496 1497 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 1498 __IO uint32_t tmpreg; \ 1499 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 1500 /* Delay after an RCC peripheral clock enabling */ \ 1501 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 1502 UNUSED(tmpreg); \ 1503 } while(0) 1504 1505 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 1506 __IO uint32_t tmpreg; \ 1507 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 1508 /* Delay after an RCC peripheral clock enabling */ \ 1509 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 1510 UNUSED(tmpreg); \ 1511 } while(0) 1512 1513 #if defined(RCC_AHB4ENR_CRCEN) 1514 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 1515 __IO uint32_t tmpreg; \ 1516 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 1517 /* Delay after an RCC peripheral clock enabling */ \ 1518 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 1519 UNUSED(tmpreg); \ 1520 } while(0) 1521 #endif 1522 1523 #if defined(BDMA2) 1524 #define __HAL_RCC_BDMA2_CLK_ENABLE() do { \ 1525 __IO uint32_t tmpreg; \ 1526 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ 1527 /* Delay after an RCC peripheral clock enabling */ \ 1528 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ 1529 UNUSED(tmpreg); \ 1530 } while(0) 1531 1532 #define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/ 1533 #else 1534 #define __HAL_RCC_BDMA_CLK_ENABLE() do { \ 1535 __IO uint32_t tmpreg; \ 1536 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 1537 /* Delay after an RCC peripheral clock enabling */ \ 1538 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 1539 UNUSED(tmpreg); \ 1540 } while(0) 1541 #endif 1542 1543 #if defined(ADC3) 1544 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 1545 __IO uint32_t tmpreg; \ 1546 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 1547 /* Delay after an RCC peripheral clock enabling */ \ 1548 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 1549 UNUSED(tmpreg); \ 1550 } while(0) 1551 #endif 1552 1553 #if defined(RCC_AHB4ENR_HSEMEN) 1554 #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ 1555 __IO uint32_t tmpreg; \ 1556 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 1557 /* Delay after an RCC peripheral clock enabling */ \ 1558 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 1559 UNUSED(tmpreg); \ 1560 } while(0) 1561 #endif 1562 1563 #if defined(RCC_AHB4ENR_SRDSRAMEN) 1564 #define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \ 1565 __IO uint32_t tmpreg; \ 1566 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ 1567 /* Delay after an RCC peripheral clock enabling */ \ 1568 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ 1569 UNUSED(tmpreg); \ 1570 } while(0) 1571 #endif 1572 1573 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ 1574 __IO uint32_t tmpreg; \ 1575 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 1576 /* Delay after an RCC peripheral clock enabling */ \ 1577 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 1578 UNUSED(tmpreg); \ 1579 } while(0) 1580 1581 1582 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) 1583 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) 1584 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) 1585 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) 1586 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) 1587 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) 1588 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) 1589 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) 1590 #if defined(GPIOI) 1591 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) 1592 #endif /* GPIOI */ 1593 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) 1594 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) 1595 #if defined(RCC_AHB4ENR_CRCEN) 1596 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) 1597 #endif 1598 #if defined(BDMA2) 1599 #define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN) 1600 #define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/ 1601 #else 1602 #define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) 1603 #endif 1604 #if defined(ADC3) 1605 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) 1606 #endif 1607 #if defined(RCC_AHB4ENR_HSEMEN) 1608 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) 1609 #endif 1610 #if defined(RCC_AHB4ENR_SRDSRAMEN) 1611 #define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN) 1612 #endif 1613 #define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) 1614 1615 1616 /** @brief Get the enable or disable status of the AHB4 peripheral clock 1617 * @note After reset, the peripheral clock (used for registers read/write access) 1618 * is disabled and the application software has to enable this clock before 1619 * using it. 1620 */ 1621 1622 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U) 1623 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U) 1624 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U) 1625 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U) 1626 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U) 1627 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) 1628 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) 1629 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) 1630 #if defined(GPIOI) 1631 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) 1632 #endif /* GPIOI */ 1633 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) 1634 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) 1635 #if defined(RCC_AHB4ENR_CRCEN) 1636 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) 1637 #endif 1638 #if defined(BDMA2) 1639 #define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U) 1640 #define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/ 1641 #else 1642 #define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) 1643 #endif 1644 #if defined(ADC3) 1645 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) 1646 #endif 1647 #if defined(RCC_AHB4ENR_HSEMEN) 1648 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) 1649 #endif 1650 #if defined(RCC_AHB4ENR_SRDSRAMEN) 1651 #define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U) 1652 #endif 1653 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) 1654 1655 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) 1656 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U) 1657 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U) 1658 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U) 1659 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U) 1660 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) 1661 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) 1662 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) 1663 #if defined(GPIOI) 1664 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) 1665 #endif /* GPIOI */ 1666 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) 1667 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) 1668 1669 #if defined(RCC_AHB4ENR_CRCEN) 1670 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) 1671 #endif 1672 #if defined(BDMA2) 1673 #define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U) 1674 #define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/ 1675 #else 1676 #define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) 1677 #endif 1678 #if defined(ADC3) 1679 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) 1680 #endif 1681 #if defined(RCC_AHB4ENR_HSEMEN) 1682 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) 1683 #endif 1684 #if defined(RCC_AHB4ENR_SRDSRAMEN) 1685 #define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U) 1686 #endif 1687 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) 1688 1689 1690 /** @brief Enable or disable the APB3 peripheral clock. 1691 * @note After reset, the peripheral clock (used for registers read/write access) 1692 * is disabled and the application software has to enable this clock before 1693 * using it. 1694 */ 1695 1696 #if defined(LTDC) 1697 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1698 __IO uint32_t tmpreg; \ 1699 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ 1700 /* Delay after an RCC peripheral clock enabling */ \ 1701 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ 1702 UNUSED(tmpreg); \ 1703 } while(0) 1704 #endif /* LTDC */ 1705 1706 #if defined(DSI) 1707 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1708 __IO uint32_t tmpreg; \ 1709 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ 1710 /* Delay after an RCC peripheral clock enabling */ \ 1711 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ 1712 UNUSED(tmpreg); \ 1713 } while(0) 1714 #endif /*DSI*/ 1715 1716 #define __HAL_RCC_WWDG1_CLK_ENABLE() do { \ 1717 __IO uint32_t tmpreg; \ 1718 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 1719 /* Delay after an RCC peripheral clock enabling */ \ 1720 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 1721 UNUSED(tmpreg); \ 1722 } while(0) 1723 1724 #if defined(LTDC) 1725 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) 1726 #endif /* LTDC */ 1727 #if defined(DSI) 1728 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) 1729 #endif /*DSI*/ 1730 #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) 1731 1732 /** @brief Get the enable or disable status of the APB3 peripheral clock 1733 * @note After reset, the peripheral clock (used for registers read/write access) 1734 * is disabled and the application software has to enable this clock before 1735 * using it. 1736 */ 1737 1738 #if defined(LTDC) 1739 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) 1740 #endif /* LTDC */ 1741 #if defined(DSI) 1742 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U) 1743 #endif /*DSI*/ 1744 #define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) 1745 #if defined(LTDC) 1746 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) 1747 #endif /* LTDC */ 1748 #if defined(DSI) 1749 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U) 1750 #endif /*DSI*/ 1751 #define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) 1752 1753 1754 /** @brief Enable or disable the APB1 peripheral clock. 1755 * @note After reset, the peripheral clock (used for registers read/write access) 1756 * is disabled and the application software has to enable this clock before 1757 * using it. 1758 */ 1759 1760 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1761 __IO uint32_t tmpreg; \ 1762 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ 1763 /* Delay after an RCC peripheral clock enabling */ \ 1764 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ 1765 UNUSED(tmpreg); \ 1766 } while(0) 1767 1768 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1769 __IO uint32_t tmpreg; \ 1770 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ 1771 /* Delay after an RCC peripheral clock enabling */ \ 1772 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ 1773 UNUSED(tmpreg); \ 1774 } while(0) 1775 1776 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1777 __IO uint32_t tmpreg; \ 1778 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ 1779 /* Delay after an RCC peripheral clock enabling */ \ 1780 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ 1781 UNUSED(tmpreg); \ 1782 } while(0) 1783 1784 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1785 __IO uint32_t tmpreg; \ 1786 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ 1787 /* Delay after an RCC peripheral clock enabling */ \ 1788 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ 1789 UNUSED(tmpreg); \ 1790 } while(0) 1791 1792 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1793 __IO uint32_t tmpreg; \ 1794 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ 1795 /* Delay after an RCC peripheral clock enabling */ \ 1796 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ 1797 UNUSED(tmpreg); \ 1798 } while(0) 1799 1800 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1801 __IO uint32_t tmpreg; \ 1802 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ 1803 /* Delay after an RCC peripheral clock enabling */ \ 1804 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ 1805 UNUSED(tmpreg); \ 1806 } while(0) 1807 1808 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1809 __IO uint32_t tmpreg; \ 1810 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ 1811 /* Delay after an RCC peripheral clock enabling */ \ 1812 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ 1813 UNUSED(tmpreg); \ 1814 } while(0) 1815 1816 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1817 __IO uint32_t tmpreg; \ 1818 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ 1819 /* Delay after an RCC peripheral clock enabling */ \ 1820 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ 1821 UNUSED(tmpreg); \ 1822 } while(0) 1823 1824 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1825 __IO uint32_t tmpreg; \ 1826 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ 1827 /* Delay after an RCC peripheral clock enabling */ \ 1828 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ 1829 UNUSED(tmpreg); \ 1830 } while(0) 1831 1832 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1833 __IO uint32_t tmpreg; \ 1834 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 1835 /* Delay after an RCC peripheral clock enabling */ \ 1836 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 1837 UNUSED(tmpreg); \ 1838 } while(0) 1839 1840 #if defined(DUAL_CORE) 1841 #define __HAL_RCC_WWDG2_CLK_ENABLE() do { \ 1842 __IO uint32_t tmpreg; \ 1843 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 1844 /* Delay after an RCC peripheral clock enabling */ \ 1845 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 1846 UNUSED(tmpreg); \ 1847 } while(0) 1848 #endif /*DUAL_CORE*/ 1849 1850 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1851 __IO uint32_t tmpreg; \ 1852 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ 1853 /* Delay after an RCC peripheral clock enabling */ \ 1854 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ 1855 UNUSED(tmpreg); \ 1856 } while(0) 1857 1858 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1859 __IO uint32_t tmpreg; \ 1860 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ 1861 /* Delay after an RCC peripheral clock enabling */ \ 1862 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ 1863 UNUSED(tmpreg); \ 1864 } while(0) 1865 1866 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 1867 __IO uint32_t tmpreg; \ 1868 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 1869 /* Delay after an RCC peripheral clock enabling */ \ 1870 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 1871 UNUSED(tmpreg); \ 1872 } while(0) 1873 1874 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1875 __IO uint32_t tmpreg; \ 1876 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ 1877 /* Delay after an RCC peripheral clock enabling */ \ 1878 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ 1879 UNUSED(tmpreg); \ 1880 } while(0) 1881 1882 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1883 __IO uint32_t tmpreg; \ 1884 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ 1885 /* Delay after an RCC peripheral clock enabling */ \ 1886 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ 1887 UNUSED(tmpreg); \ 1888 } while(0) 1889 1890 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1891 __IO uint32_t tmpreg; \ 1892 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ 1893 /* Delay after an RCC peripheral clock enabling */ \ 1894 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ 1895 UNUSED(tmpreg); \ 1896 } while(0) 1897 1898 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1899 __IO uint32_t tmpreg; \ 1900 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ 1901 /* Delay after an RCC peripheral clock enabling */ \ 1902 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ 1903 UNUSED(tmpreg); \ 1904 } while(0) 1905 1906 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1907 __IO uint32_t tmpreg; \ 1908 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ 1909 /* Delay after an RCC peripheral clock enabling */ \ 1910 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ 1911 UNUSED(tmpreg); \ 1912 } while(0) 1913 1914 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1915 __IO uint32_t tmpreg; \ 1916 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ 1917 /* Delay after an RCC peripheral clock enabling */ \ 1918 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ 1919 UNUSED(tmpreg); \ 1920 } while(0) 1921 1922 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1923 __IO uint32_t tmpreg; \ 1924 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ 1925 /* Delay after an RCC peripheral clock enabling */ \ 1926 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ 1927 UNUSED(tmpreg); \ 1928 } while(0) 1929 1930 #if defined(I2C5) 1931 #define __HAL_RCC_I2C5_CLK_ENABLE() do { \ 1932 __IO uint32_t tmpreg; \ 1933 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ 1934 /* Delay after an RCC peripheral clock enabling */ \ 1935 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ 1936 UNUSED(tmpreg); \ 1937 } while(0) 1938 #endif /* I2C5 */ 1939 1940 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1941 __IO uint32_t tmpreg; \ 1942 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ 1943 /* Delay after an RCC peripheral clock enabling */ \ 1944 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ 1945 UNUSED(tmpreg); \ 1946 } while(0) 1947 1948 #define __HAL_RCC_DAC12_CLK_ENABLE() do { \ 1949 __IO uint32_t tmpreg; \ 1950 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ 1951 /* Delay after an RCC peripheral clock enabling */ \ 1952 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ 1953 UNUSED(tmpreg); \ 1954 } while(0) 1955 1956 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1957 __IO uint32_t tmpreg; \ 1958 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ 1959 /* Delay after an RCC peripheral clock enabling */ \ 1960 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ 1961 UNUSED(tmpreg); \ 1962 } while(0) 1963 1964 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1965 __IO uint32_t tmpreg; \ 1966 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ 1967 /* Delay after an RCC peripheral clock enabling */ \ 1968 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ 1969 UNUSED(tmpreg); \ 1970 } while(0) 1971 1972 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1973 __IO uint32_t tmpreg; \ 1974 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ 1975 /* Delay after an RCC peripheral clock enabling */ \ 1976 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ 1977 UNUSED(tmpreg); \ 1978 } while(0) 1979 1980 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 1981 __IO uint32_t tmpreg; \ 1982 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 1983 /* Delay after an RCC peripheral clock enabling */ \ 1984 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 1985 UNUSED(tmpreg); \ 1986 } while(0) 1987 1988 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1989 __IO uint32_t tmpreg; \ 1990 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 1991 /* Delay after an RCC peripheral clock enabling */ \ 1992 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 1993 UNUSED(tmpreg); \ 1994 } while(0) 1995 1996 #define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ 1997 __IO uint32_t tmpreg; \ 1998 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 1999 /* Delay after an RCC peripheral clock enabling */ \ 2000 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 2001 UNUSED(tmpreg); \ 2002 } while(0) 2003 2004 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ 2005 __IO uint32_t tmpreg; \ 2006 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ 2007 /* Delay after an RCC peripheral clock enabling */ \ 2008 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ 2009 UNUSED(tmpreg); \ 2010 } while(0) 2011 2012 #if defined(TIM23) 2013 #define __HAL_RCC_TIM23_CLK_ENABLE() do { \ 2014 __IO uint32_t tmpreg; \ 2015 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ 2016 /* Delay after an RCC peripheral clock enabling */ \ 2017 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ 2018 UNUSED(tmpreg); \ 2019 } while(0) 2020 #endif /* TIM23 */ 2021 2022 #if defined(TIM24) 2023 #define __HAL_RCC_TIM24_CLK_ENABLE() do { \ 2024 __IO uint32_t tmpreg; \ 2025 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ 2026 /* Delay after an RCC peripheral clock enabling */ \ 2027 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ 2028 UNUSED(tmpreg); \ 2029 } while(0) 2030 #endif /* TIM24 */ 2031 2032 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) 2033 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) 2034 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) 2035 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) 2036 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) 2037 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) 2038 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) 2039 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) 2040 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) 2041 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) 2042 2043 #if defined(DUAL_CORE) 2044 #define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) 2045 #endif /*DUAL_CORE*/ 2046 2047 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) 2048 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) 2049 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) 2050 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) 2051 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) 2052 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) 2053 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) 2054 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) 2055 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) 2056 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) 2057 #if defined(I2C5) 2058 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN) 2059 #endif /* I2C5 */ 2060 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) 2061 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) 2062 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) 2063 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) 2064 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) 2065 #define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) 2066 #define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) 2067 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) 2068 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) 2069 #if defined(TIM23) 2070 #define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN) 2071 #endif /* TIM23 */ 2072 #if defined(TIM24) 2073 #define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN) 2074 #endif /* TIM24 */ 2075 2076 2077 /** @brief Get the enable or disable status of the APB1 peripheral clock 2078 * @note After reset, the peripheral clock (used for registers read/write access) 2079 * is disabled and the application software has to enable this clock before 2080 * using it. 2081 */ 2082 2083 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U) 2084 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U) 2085 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U) 2086 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U) 2087 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U) 2088 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U) 2089 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U) 2090 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U) 2091 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U) 2092 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U) 2093 #if defined(DUAL_CORE) 2094 #define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U) 2095 #endif /*DUAL_CORE*/ 2096 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U) 2097 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U) 2098 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U) 2099 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U) 2100 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U) 2101 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U) 2102 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U) 2103 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) 2104 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) 2105 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) 2106 #if defined(I2C5) 2107 #define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U) 2108 #endif /* I2C5 */ 2109 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) 2110 #define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) 2111 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) 2112 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U) 2113 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U) 2114 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U) 2115 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) 2116 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) 2117 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) 2118 #if defined(TIM23) 2119 #define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U) 2120 #endif /* TIM23 */ 2121 #if defined(TIM24) 2122 #define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U) 2123 #endif /* TIM24 */ 2124 2125 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) 2126 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) 2127 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U) 2128 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U) 2129 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U) 2130 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U) 2131 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U) 2132 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U) 2133 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U) 2134 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U) 2135 #if defined(DUAL_CORE) 2136 #define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U) 2137 #endif /*DUAL_CORE*/ 2138 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U) 2139 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U) 2140 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U) 2141 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U) 2142 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U) 2143 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U) 2144 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U) 2145 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) 2146 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) 2147 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) 2148 #if defined(I2C5) 2149 #define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U) 2150 #endif /* I2C5 */ 2151 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) 2152 #define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) 2153 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) 2154 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U) 2155 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U) 2156 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U) 2157 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) 2158 #define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) 2159 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) 2160 #if defined(TIM23) 2161 #define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U) 2162 #endif /* TIM23 */ 2163 #if defined(TIM24) 2164 #define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U) 2165 #endif /* TIM24 */ 2166 2167 2168 /** @brief Enable or disable the APB2 peripheral clock. 2169 * @note After reset, the peripheral clock (used for registers read/write access) 2170 * is disabled and the application software has to enable this clock before 2171 * using it. 2172 */ 2173 2174 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 2175 __IO uint32_t tmpreg; \ 2176 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 2177 /* Delay after an RCC peripheral clock enabling */ \ 2178 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 2179 UNUSED(tmpreg); \ 2180 } while(0) 2181 2182 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 2183 __IO uint32_t tmpreg; \ 2184 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2185 /* Delay after an RCC peripheral clock enabling */ \ 2186 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2187 UNUSED(tmpreg); \ 2188 } while(0) 2189 2190 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 2191 __IO uint32_t tmpreg; \ 2192 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 2193 /* Delay after an RCC peripheral clock enabling */ \ 2194 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 2195 UNUSED(tmpreg); \ 2196 } while(0) 2197 2198 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 2199 __IO uint32_t tmpreg; \ 2200 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 2201 /* Delay after an RCC peripheral clock enabling */ \ 2202 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 2203 UNUSED(tmpreg); \ 2204 } while(0) 2205 2206 #if defined(UART9) 2207 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 2208 __IO uint32_t tmpreg; \ 2209 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 2210 /* Delay after an RCC peripheral clock enabling */ \ 2211 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 2212 UNUSED(tmpreg); \ 2213 } while(0) 2214 #endif /*UART9*/ 2215 2216 #if defined(USART10) 2217 #define __HAL_RCC_USART10_CLK_ENABLE() do { \ 2218 __IO uint32_t tmpreg; \ 2219 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ 2220 /* Delay after an RCC peripheral clock enabling */ \ 2221 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ 2222 UNUSED(tmpreg); \ 2223 } while(0) 2224 #endif /*USART10*/ 2225 2226 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 2227 __IO uint32_t tmpreg; \ 2228 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2229 /* Delay after an RCC peripheral clock enabling */ \ 2230 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2231 UNUSED(tmpreg); \ 2232 } while(0) 2233 2234 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 2235 __IO uint32_t tmpreg; \ 2236 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2237 /* Delay after an RCC peripheral clock enabling */ \ 2238 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2239 UNUSED(tmpreg); \ 2240 } while(0) 2241 2242 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 2243 __IO uint32_t tmpreg; \ 2244 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 2245 /* Delay after an RCC peripheral clock enabling */ \ 2246 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 2247 UNUSED(tmpreg); \ 2248 } while(0) 2249 2250 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 2251 __IO uint32_t tmpreg; \ 2252 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 2253 /* Delay after an RCC peripheral clock enabling */ \ 2254 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 2255 UNUSED(tmpreg); \ 2256 } while(0) 2257 2258 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 2259 __IO uint32_t tmpreg; \ 2260 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 2261 /* Delay after an RCC peripheral clock enabling */ \ 2262 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 2263 UNUSED(tmpreg); \ 2264 } while(0) 2265 2266 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 2267 __IO uint32_t tmpreg; \ 2268 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 2269 /* Delay after an RCC peripheral clock enabling */ \ 2270 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 2271 UNUSED(tmpreg); \ 2272 } while(0) 2273 2274 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 2275 __IO uint32_t tmpreg; \ 2276 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 2277 /* Delay after an RCC peripheral clock enabling */ \ 2278 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 2279 UNUSED(tmpreg); \ 2280 } while(0) 2281 2282 #if defined(SAI2) 2283 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 2284 __IO uint32_t tmpreg; \ 2285 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 2286 /* Delay after an RCC peripheral clock enabling */ \ 2287 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 2288 UNUSED(tmpreg); \ 2289 } while(0) 2290 #endif /*SAI2*/ 2291 2292 #if defined(SAI3) 2293 #define __HAL_RCC_SAI3_CLK_ENABLE() do { \ 2294 __IO uint32_t tmpreg; \ 2295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ 2296 /* Delay after an RCC peripheral clock enabling */ \ 2297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ 2298 UNUSED(tmpreg); \ 2299 } while(0) 2300 #endif /*SAI3*/ 2301 2302 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 2303 __IO uint32_t tmpreg; \ 2304 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 2305 /* Delay after an RCC peripheral clock enabling */ \ 2306 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 2307 UNUSED(tmpreg); \ 2308 } while(0) 2309 2310 #if defined(HRTIM1) 2311 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ 2312 __IO uint32_t tmpreg; \ 2313 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 2314 /* Delay after an RCC peripheral clock enabling */ \ 2315 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 2316 UNUSED(tmpreg); \ 2317 } while(0) 2318 #endif /*HRTIM1*/ 2319 2320 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) 2321 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) 2322 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) 2323 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) 2324 #if defined(UART9) 2325 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN) 2326 #endif /*UART9*/ 2327 #if defined(USART10) 2328 #define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN) 2329 #endif /*USART10*/ 2330 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) 2331 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) 2332 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) 2333 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) 2334 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) 2335 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) 2336 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) 2337 #if defined(SAI2) 2338 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) 2339 #endif /*SAI2*/ 2340 #if defined(SAI3) 2341 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) 2342 #endif /*SAI3*/ 2343 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) 2344 #if defined(HRTIM1) 2345 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) 2346 #endif /*HRTIM*/ 2347 2348 /** @brief Get the enable or disable status of the APB2 peripheral clock 2349 * @note After reset, the peripheral clock (used for registers read/write access) 2350 * is disabled and the application software has to enable this clock before 2351 * using it. 2352 */ 2353 2354 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U) 2355 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) 2356 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) 2357 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) 2358 #if defined(UART9) 2359 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U) 2360 #endif /*UART9*/ 2361 #if defined(USART10) 2362 #define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U) 2363 #endif /*USART10*/ 2364 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) 2365 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) 2366 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) 2367 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U) 2368 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) 2369 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) 2370 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) 2371 #if defined(SAI2) 2372 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) 2373 #endif /*SAI2*/ 2374 #if defined(SAI3) 2375 #define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) 2376 #endif /* SAI3 */ 2377 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) 2378 #if defined(HRTIM1) 2379 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) 2380 #endif /*HRTIM1*/ 2381 2382 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) 2383 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) 2384 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) 2385 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) 2386 #if defined(UART9) 2387 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U) 2388 #endif /*UART9*/ 2389 #if defined(USART10) 2390 #define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U) 2391 #endif /*USART10*/ 2392 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) 2393 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) 2394 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) 2395 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U) 2396 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) 2397 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) 2398 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) 2399 #if defined(SAI2) 2400 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) 2401 #endif /*SAI2*/ 2402 #if defined(SAI3) 2403 #define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) 2404 #endif /*SAI3*/ 2405 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) 2406 #if defined(HRTIM1) 2407 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) 2408 #endif /*HRTIM1*/ 2409 2410 /** @brief Enable or disable the APB4 peripheral clock. 2411 * @note After reset, the peripheral clock (used for registers read/write access) 2412 * is disabled and the application software has to enable this clock before 2413 * using it. 2414 */ 2415 2416 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 2417 __IO uint32_t tmpreg; \ 2418 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 2419 /* Delay after an RCC peripheral clock enabling */ \ 2420 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 2421 UNUSED(tmpreg); \ 2422 } while(0) 2423 2424 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 2425 __IO uint32_t tmpreg; \ 2426 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 2427 /* Delay after an RCC peripheral clock enabling */ \ 2428 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 2429 UNUSED(tmpreg); \ 2430 } while(0) 2431 2432 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 2433 __IO uint32_t tmpreg; \ 2434 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ 2435 /* Delay after an RCC peripheral clock enabling */ \ 2436 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ 2437 UNUSED(tmpreg); \ 2438 } while(0) 2439 2440 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 2441 __IO uint32_t tmpreg; \ 2442 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ 2443 /* Delay after an RCC peripheral clock enabling */ \ 2444 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ 2445 UNUSED(tmpreg); \ 2446 } while(0) 2447 2448 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 2449 __IO uint32_t tmpreg; \ 2450 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 2451 /* Delay after an RCC peripheral clock enabling */ \ 2452 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 2453 UNUSED(tmpreg); \ 2454 } while(0) 2455 2456 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 2457 __IO uint32_t tmpreg; \ 2458 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 2459 /* Delay after an RCC peripheral clock enabling */ \ 2460 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 2461 UNUSED(tmpreg); \ 2462 } while(0) 2463 2464 #if defined(LPTIM4) 2465 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 2466 __IO uint32_t tmpreg; \ 2467 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 2468 /* Delay after an RCC peripheral clock enabling */ \ 2469 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 2470 UNUSED(tmpreg); \ 2471 } while(0) 2472 #endif /* LPTIM4 */ 2473 2474 #if defined(LPTIM5) 2475 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ 2476 __IO uint32_t tmpreg; \ 2477 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 2478 /* Delay after an RCC peripheral clock enabling */ \ 2479 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 2480 UNUSED(tmpreg); \ 2481 } while(0) 2482 #endif /* LPTIM5 */ 2483 2484 #if defined(DAC2) 2485 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ 2486 __IO uint32_t tmpreg; \ 2487 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ 2488 /* Delay after an RCC peripheral clock enabling */ \ 2489 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ 2490 UNUSED(tmpreg); \ 2491 } while(0) 2492 #endif /* DAC2 */ 2493 2494 #define __HAL_RCC_COMP12_CLK_ENABLE() do { \ 2495 __IO uint32_t tmpreg; \ 2496 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ 2497 /* Delay after an RCC peripheral clock enabling */ \ 2498 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ 2499 UNUSED(tmpreg); \ 2500 } while(0) 2501 2502 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 2503 __IO uint32_t tmpreg; \ 2504 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ 2505 /* Delay after an RCC peripheral clock enabling */ \ 2506 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ 2507 UNUSED(tmpreg); \ 2508 } while(0) 2509 2510 #if defined(SAI4) 2511 #define __HAL_RCC_SAI4_CLK_ENABLE() do { \ 2512 __IO uint32_t tmpreg; \ 2513 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ 2514 /* Delay after an RCC peripheral clock enabling */ \ 2515 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ 2516 UNUSED(tmpreg); \ 2517 } while(0) 2518 #endif /* SAI4 */ 2519 2520 #define __HAL_RCC_RTC_CLK_ENABLE() do { \ 2521 __IO uint32_t tmpreg; \ 2522 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 2523 /* Delay after an RCC peripheral clock enabling */ \ 2524 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 2525 UNUSED(tmpreg); \ 2526 } while(0) 2527 2528 #if defined(DTS) 2529 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 2530 __IO uint32_t tmpreg; \ 2531 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ 2532 /* Delay after an RCC peripheral clock enabling */ \ 2533 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ 2534 UNUSED(tmpreg); \ 2535 } while(0) 2536 #endif /*DTS*/ 2537 2538 #if defined(DFSDM2_BASE) 2539 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ 2540 __IO uint32_t tmpreg; \ 2541 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ 2542 /* Delay after an RCC peripheral clock enabling */ \ 2543 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ 2544 UNUSED(tmpreg); \ 2545 } while(0) 2546 #endif /*DFSDM2*/ 2547 2548 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) 2549 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) 2550 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) 2551 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) 2552 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) 2553 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) 2554 #if defined(LPTIM4) 2555 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) 2556 #endif /*LPTIM4*/ 2557 #if defined(LPTIM5) 2558 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) 2559 #endif /*LPTIM5*/ 2560 #if defined(DAC2) 2561 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN) 2562 #endif /*DAC2*/ 2563 #define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) 2564 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) 2565 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) 2566 #if defined(SAI4) 2567 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) 2568 #endif /*SAI4*/ 2569 #if defined(DTS) 2570 #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN) 2571 #endif /*DTS*/ 2572 #if defined(DFSDM2_BASE) 2573 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN) 2574 #endif /*DFSDM2*/ 2575 2576 /** @brief Get the enable or disable status of the APB4 peripheral clock 2577 * @note After reset, the peripheral clock (used for registers read/write access) 2578 * is disabled and the application software has to enable this clock before 2579 * using it. 2580 */ 2581 2582 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U) 2583 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U) 2584 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U) 2585 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) 2586 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) 2587 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) 2588 #if defined(LPTIM4) 2589 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) 2590 #endif /*LPTIM4*/ 2591 #if defined(LPTIM5) 2592 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) 2593 #endif /*LPTIM5*/ 2594 #if defined(DAC2) 2595 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U) 2596 #endif /*DAC2*/ 2597 #define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) 2598 #define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) 2599 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) 2600 #if defined(SAI4) 2601 #define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) 2602 #endif /*SAI4*/ 2603 #if defined(DTS) 2604 #define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U) 2605 #endif /*DTS*/ 2606 #if defined(DFSDM2_BASE) 2607 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U) 2608 #endif /*DFSDM2*/ 2609 2610 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) 2611 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) 2612 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U) 2613 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) 2614 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) 2615 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) 2616 #if defined(LPTIM4) 2617 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) 2618 #endif /*LPTIM4*/ 2619 #if defined(LPTIM5) 2620 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) 2621 #endif /*LPTIM5*/ 2622 #if defined(DAC2) 2623 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U) 2624 #endif /*DAC2*/ 2625 #define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) 2626 #define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) 2627 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) 2628 #if defined(SAI4) 2629 #define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) 2630 #endif /*SAI4*/ 2631 #if defined(DTS) 2632 #define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U) 2633 #endif /*DTS*/ 2634 #if defined(DFSDM2_BASE) 2635 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U) 2636 #endif /*DFSDM2*/ 2637 2638 #if defined(DUAL_CORE) 2639 2640 /* Exported macros for RCC_C1 -------------------------------------------------*/ 2641 2642 /** @brief Enable or disable the AHB3 peripheral clock. 2643 * @note After reset, the peripheral clock (used for registers read/write access) 2644 * is disabled and the application software has to enable this clock before 2645 * using it. 2646 */ 2647 2648 #define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \ 2649 __IO uint32_t tmpreg; \ 2650 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 2651 /* Delay after an RCC peripheral clock enabling */ \ 2652 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 2653 UNUSED(tmpreg); \ 2654 } while(0) 2655 2656 #define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \ 2657 __IO uint32_t tmpreg; \ 2658 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 2659 /* Delay after an RCC peripheral clock enabling */ \ 2660 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 2661 UNUSED(tmpreg); \ 2662 } while(0) 2663 2664 #define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \ 2665 __IO uint32_t tmpreg; \ 2666 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 2667 /* Delay after an RCC peripheral clock enabling */ \ 2668 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 2669 UNUSED(tmpreg); \ 2670 } while(0) 2671 2672 2673 #define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \ 2674 __IO uint32_t tmpreg; \ 2675 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 2676 /* Delay after an RCC peripheral clock enabling */ \ 2677 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 2678 UNUSED(tmpreg); \ 2679 } while(0) 2680 2681 #define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \ 2682 __IO uint32_t tmpreg; \ 2683 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 2684 /* Delay after an RCC peripheral clock enabling */ \ 2685 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 2686 UNUSED(tmpreg); \ 2687 } while(0) 2688 2689 #define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \ 2690 __IO uint32_t tmpreg; \ 2691 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 2692 /* Delay after an RCC peripheral clock enabling */ \ 2693 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 2694 UNUSED(tmpreg); \ 2695 } while(0) 2696 2697 2698 2699 2700 #define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) 2701 #define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) 2702 #define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) 2703 #define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) 2704 #define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) 2705 #define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) 2706 2707 2708 2709 2710 /** @brief Enable or disable the AHB1 peripheral clock. 2711 * @note After reset, the peripheral clock (used for registers read/write access) 2712 * is disabled and the application software has to enable this clock before 2713 * using it. 2714 */ 2715 2716 #define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \ 2717 __IO uint32_t tmpreg; \ 2718 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 2719 /* Delay after an RCC peripheral clock enabling */ \ 2720 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 2721 UNUSED(tmpreg); \ 2722 } while(0) 2723 2724 #define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \ 2725 __IO uint32_t tmpreg; \ 2726 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 2727 /* Delay after an RCC peripheral clock enabling */ \ 2728 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 2729 UNUSED(tmpreg); \ 2730 } while(0) 2731 2732 #define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \ 2733 __IO uint32_t tmpreg; \ 2734 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 2735 /* Delay after an RCC peripheral clock enabling */ \ 2736 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 2737 UNUSED(tmpreg); \ 2738 } while(0) 2739 2740 #define __HAL_RCC_C1_ART_CLK_ENABLE() do { \ 2741 __IO uint32_t tmpreg; \ 2742 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 2743 /* Delay after an RCC peripheral clock enabling */ \ 2744 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 2745 UNUSED(tmpreg); \ 2746 } while(0) 2747 2748 #define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \ 2749 __IO uint32_t tmpreg; \ 2750 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 2751 /* Delay after an RCC peripheral clock enabling */ \ 2752 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 2753 UNUSED(tmpreg); \ 2754 } while(0) 2755 2756 #define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \ 2757 __IO uint32_t tmpreg; \ 2758 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 2759 /* Delay after an RCC peripheral clock enabling */ \ 2760 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 2761 UNUSED(tmpreg); \ 2762 } while(0) 2763 2764 #define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \ 2765 __IO uint32_t tmpreg; \ 2766 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 2767 /* Delay after an RCC peripheral clock enabling */ \ 2768 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 2769 UNUSED(tmpreg); \ 2770 } while(0) 2771 2772 2773 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \ 2774 __IO uint32_t tmpreg; \ 2775 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 2776 /* Delay after an RCC peripheral clock enabling */ \ 2777 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 2778 UNUSED(tmpreg); \ 2779 } while(0) 2780 2781 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ 2782 __IO uint32_t tmpreg; \ 2783 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 2784 /* Delay after an RCC peripheral clock enabling */ \ 2785 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 2786 UNUSED(tmpreg); \ 2787 } while(0) 2788 2789 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \ 2790 __IO uint32_t tmpreg; \ 2791 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 2792 /* Delay after an RCC peripheral clock enabling */ \ 2793 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 2794 UNUSED(tmpreg); \ 2795 } while(0) 2796 2797 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ 2798 __IO uint32_t tmpreg; \ 2799 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 2800 /* Delay after an RCC peripheral clock enabling */ \ 2801 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 2802 UNUSED(tmpreg); \ 2803 } while(0) 2804 2805 #define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) 2806 #define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) 2807 #define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) 2808 #define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) 2809 #define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) 2810 #define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) 2811 #define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) 2812 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) 2813 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) 2814 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) 2815 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) 2816 2817 /** @brief Enable or disable the AHB2 peripheral clock. 2818 * @note After reset, the peripheral clock (used for registers read/write access) 2819 * is disabled and the application software has to enable this clock before 2820 * using it. 2821 */ 2822 2823 #define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \ 2824 __IO uint32_t tmpreg; \ 2825 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2826 /* Delay after an RCC peripheral clock enabling */ \ 2827 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2828 UNUSED(tmpreg); \ 2829 } while(0) 2830 #if defined(CRYP) 2831 #define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \ 2832 __IO uint32_t tmpreg; \ 2833 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2834 /* Delay after an RCC peripheral clock enabling */ \ 2835 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2836 UNUSED(tmpreg); \ 2837 } while(0) 2838 #endif /* CRYP */ 2839 2840 #if defined(HASH) 2841 #define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \ 2842 __IO uint32_t tmpreg; \ 2843 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2844 /* Delay after an RCC peripheral clock enabling */ \ 2845 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2846 UNUSED(tmpreg); \ 2847 } while(0) 2848 #endif /* HASH */ 2849 2850 #define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \ 2851 __IO uint32_t tmpreg; \ 2852 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2853 /* Delay after an RCC peripheral clock enabling */ \ 2854 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2855 UNUSED(tmpreg); \ 2856 } while(0) 2857 2858 #define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \ 2859 __IO uint32_t tmpreg; \ 2860 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 2861 /* Delay after an RCC peripheral clock enabling */ \ 2862 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 2863 UNUSED(tmpreg); \ 2864 } while(0) 2865 2866 #define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \ 2867 __IO uint32_t tmpreg; \ 2868 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 2869 /* Delay after an RCC peripheral clock enabling */ \ 2870 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 2871 UNUSED(tmpreg); \ 2872 } while(0) 2873 2874 #define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \ 2875 __IO uint32_t tmpreg; \ 2876 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 2877 /* Delay after an RCC peripheral clock enabling */ \ 2878 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 2879 UNUSED(tmpreg); \ 2880 } while(0) 2881 2882 #define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \ 2883 __IO uint32_t tmpreg; \ 2884 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 2885 /* Delay after an RCC peripheral clock enabling */ \ 2886 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 2887 UNUSED(tmpreg); \ 2888 } while(0) 2889 2890 #define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) 2891 #if defined(CRYP) 2892 #define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) 2893 #endif /* CRYP */ 2894 #if defined(HASH) 2895 #define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) 2896 #endif /* HASH */ 2897 #define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) 2898 #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) 2899 #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) 2900 #define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) 2901 #define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) 2902 2903 /** @brief Enable or disable the AHB4 peripheral clock. 2904 * @note After reset, the peripheral clock (used for registers read/write access) 2905 * is disabled and the application software has to enable this clock before 2906 * using it. 2907 */ 2908 2909 #define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \ 2910 __IO uint32_t tmpreg; \ 2911 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 2912 /* Delay after an RCC peripheral clock enabling */ \ 2913 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 2914 UNUSED(tmpreg); \ 2915 } while(0) 2916 2917 #define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \ 2918 __IO uint32_t tmpreg; \ 2919 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 2920 /* Delay after an RCC peripheral clock enabling */ \ 2921 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 2922 UNUSED(tmpreg); \ 2923 } while(0) 2924 2925 #define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \ 2926 __IO uint32_t tmpreg; \ 2927 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 2928 /* Delay after an RCC peripheral clock enabling */ \ 2929 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 2930 UNUSED(tmpreg); \ 2931 } while(0) 2932 2933 #define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \ 2934 __IO uint32_t tmpreg; \ 2935 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 2936 /* Delay after an RCC peripheral clock enabling */ \ 2937 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 2938 UNUSED(tmpreg); \ 2939 } while(0) 2940 2941 #define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \ 2942 __IO uint32_t tmpreg; \ 2943 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 2944 /* Delay after an RCC peripheral clock enabling */ \ 2945 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 2946 UNUSED(tmpreg); \ 2947 } while(0) 2948 2949 #define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \ 2950 __IO uint32_t tmpreg; \ 2951 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 2952 /* Delay after an RCC peripheral clock enabling */ \ 2953 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 2954 UNUSED(tmpreg); \ 2955 } while(0) 2956 2957 #define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \ 2958 __IO uint32_t tmpreg; \ 2959 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 2960 /* Delay after an RCC peripheral clock enabling */ \ 2961 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 2962 UNUSED(tmpreg); \ 2963 } while(0) 2964 2965 #define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \ 2966 __IO uint32_t tmpreg; \ 2967 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 2968 /* Delay after an RCC peripheral clock enabling */ \ 2969 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 2970 UNUSED(tmpreg); \ 2971 } while(0) 2972 2973 #define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \ 2974 __IO uint32_t tmpreg; \ 2975 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 2976 /* Delay after an RCC peripheral clock enabling */ \ 2977 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 2978 UNUSED(tmpreg); \ 2979 } while(0) 2980 2981 #define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \ 2982 __IO uint32_t tmpreg; \ 2983 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 2984 /* Delay after an RCC peripheral clock enabling */ \ 2985 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 2986 UNUSED(tmpreg); \ 2987 } while(0) 2988 2989 #define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \ 2990 __IO uint32_t tmpreg; \ 2991 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 2992 /* Delay after an RCC peripheral clock enabling */ \ 2993 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 2994 UNUSED(tmpreg); \ 2995 } while(0) 2996 2997 #define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \ 2998 __IO uint32_t tmpreg; \ 2999 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 3000 /* Delay after an RCC peripheral clock enabling */ \ 3001 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 3002 UNUSED(tmpreg); \ 3003 } while(0) 3004 3005 #define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \ 3006 __IO uint32_t tmpreg; \ 3007 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 3008 /* Delay after an RCC peripheral clock enabling */ \ 3009 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 3010 UNUSED(tmpreg); \ 3011 } while(0) 3012 3013 #define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \ 3014 __IO uint32_t tmpreg; \ 3015 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 3016 /* Delay after an RCC peripheral clock enabling */ \ 3017 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 3018 UNUSED(tmpreg); \ 3019 } while(0) 3020 3021 #define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \ 3022 __IO uint32_t tmpreg; \ 3023 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 3024 /* Delay after an RCC peripheral clock enabling */ \ 3025 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 3026 UNUSED(tmpreg); \ 3027 } while(0) 3028 3029 #define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \ 3030 __IO uint32_t tmpreg; \ 3031 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 3032 /* Delay after an RCC peripheral clock enabling */ \ 3033 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 3034 UNUSED(tmpreg); \ 3035 } while(0) 3036 3037 3038 #define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) 3039 #define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) 3040 #define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) 3041 #define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) 3042 #define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) 3043 #define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) 3044 #define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) 3045 #define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) 3046 #define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) 3047 #define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) 3048 #define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) 3049 #define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) 3050 #define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) 3051 #define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) 3052 #define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) 3053 #define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) 3054 3055 3056 /** @brief Enable or disable the APB3 peripheral clock. 3057 * @note After reset, the peripheral clock (used for registers read/write access) 3058 * is disabled and the application software has to enable this clock before 3059 * using it. 3060 */ 3061 3062 #define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \ 3063 __IO uint32_t tmpreg; \ 3064 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ 3065 /* Delay after an RCC peripheral clock enabling */ \ 3066 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ 3067 UNUSED(tmpreg); \ 3068 } while(0) 3069 3070 #define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \ 3071 __IO uint32_t tmpreg; \ 3072 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ 3073 /* Delay after an RCC peripheral clock enabling */ \ 3074 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ 3075 UNUSED(tmpreg); \ 3076 } while(0) 3077 3078 #define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \ 3079 __IO uint32_t tmpreg; \ 3080 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 3081 /* Delay after an RCC peripheral clock enabling */ \ 3082 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 3083 UNUSED(tmpreg); \ 3084 } while(0) 3085 3086 #define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) 3087 #define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) 3088 #define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) 3089 3090 /** @brief Enable or disable the APB1 peripheral clock. 3091 * @note After reset, the peripheral clock (used for registers read/write access) 3092 * is disabled and the application software has to enable this clock before 3093 * using it. 3094 */ 3095 3096 #define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \ 3097 __IO uint32_t tmpreg; \ 3098 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ 3099 /* Delay after an RCC peripheral clock enabling */ \ 3100 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ 3101 UNUSED(tmpreg); \ 3102 } while(0) 3103 3104 #define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \ 3105 __IO uint32_t tmpreg; \ 3106 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ 3107 /* Delay after an RCC peripheral clock enabling */ \ 3108 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ 3109 UNUSED(tmpreg); \ 3110 } while(0) 3111 3112 #define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \ 3113 __IO uint32_t tmpreg; \ 3114 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ 3115 /* Delay after an RCC peripheral clock enabling */ \ 3116 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ 3117 UNUSED(tmpreg); \ 3118 } while(0) 3119 3120 #define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \ 3121 __IO uint32_t tmpreg; \ 3122 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ 3123 /* Delay after an RCC peripheral clock enabling */ \ 3124 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ 3125 UNUSED(tmpreg); \ 3126 } while(0) 3127 3128 #define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \ 3129 __IO uint32_t tmpreg; \ 3130 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ 3131 /* Delay after an RCC peripheral clock enabling */ \ 3132 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ 3133 UNUSED(tmpreg); \ 3134 } while(0) 3135 3136 #define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \ 3137 __IO uint32_t tmpreg; \ 3138 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ 3139 /* Delay after an RCC peripheral clock enabling */ \ 3140 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ 3141 UNUSED(tmpreg); \ 3142 } while(0) 3143 3144 #define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \ 3145 __IO uint32_t tmpreg; \ 3146 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ 3147 /* Delay after an RCC peripheral clock enabling */ \ 3148 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ 3149 UNUSED(tmpreg); \ 3150 } while(0) 3151 3152 #define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \ 3153 __IO uint32_t tmpreg; \ 3154 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ 3155 /* Delay after an RCC peripheral clock enabling */ \ 3156 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ 3157 UNUSED(tmpreg); \ 3158 } while(0) 3159 3160 #define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \ 3161 __IO uint32_t tmpreg; \ 3162 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ 3163 /* Delay after an RCC peripheral clock enabling */ \ 3164 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ 3165 UNUSED(tmpreg); \ 3166 } while(0) 3167 3168 #define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \ 3169 __IO uint32_t tmpreg; \ 3170 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 3171 /* Delay after an RCC peripheral clock enabling */ \ 3172 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 3173 UNUSED(tmpreg); \ 3174 } while(0) 3175 3176 #define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \ 3177 __IO uint32_t tmpreg; \ 3178 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 3179 /* Delay after an RCC peripheral clock enabling */ \ 3180 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 3181 UNUSED(tmpreg); \ 3182 } while(0) 3183 3184 #define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \ 3185 __IO uint32_t tmpreg; \ 3186 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ 3187 /* Delay after an RCC peripheral clock enabling */ \ 3188 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ 3189 UNUSED(tmpreg); \ 3190 } while(0) 3191 3192 #define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \ 3193 __IO uint32_t tmpreg; \ 3194 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ 3195 /* Delay after an RCC peripheral clock enabling */ \ 3196 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ 3197 UNUSED(tmpreg); \ 3198 } while(0) 3199 3200 #define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \ 3201 __IO uint32_t tmpreg; \ 3202 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 3203 /* Delay after an RCC peripheral clock enabling */ \ 3204 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 3205 UNUSED(tmpreg); \ 3206 } while(0) 3207 3208 #define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \ 3209 __IO uint32_t tmpreg; \ 3210 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ 3211 /* Delay after an RCC peripheral clock enabling */ \ 3212 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ 3213 UNUSED(tmpreg); \ 3214 } while(0) 3215 3216 #define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \ 3217 __IO uint32_t tmpreg; \ 3218 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ 3219 /* Delay after an RCC peripheral clock enabling */ \ 3220 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ 3221 UNUSED(tmpreg); \ 3222 } while(0) 3223 3224 #define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \ 3225 __IO uint32_t tmpreg; \ 3226 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ 3227 /* Delay after an RCC peripheral clock enabling */ \ 3228 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ 3229 UNUSED(tmpreg); \ 3230 } while(0) 3231 3232 #define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \ 3233 __IO uint32_t tmpreg; \ 3234 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ 3235 /* Delay after an RCC peripheral clock enabling */ \ 3236 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ 3237 UNUSED(tmpreg); \ 3238 } while(0) 3239 3240 #define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \ 3241 __IO uint32_t tmpreg; \ 3242 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ 3243 /* Delay after an RCC peripheral clock enabling */ \ 3244 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ 3245 UNUSED(tmpreg); \ 3246 } while(0) 3247 3248 #define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \ 3249 __IO uint32_t tmpreg; \ 3250 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ 3251 /* Delay after an RCC peripheral clock enabling */ \ 3252 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ 3253 UNUSED(tmpreg); \ 3254 } while(0) 3255 3256 #define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \ 3257 __IO uint32_t tmpreg; \ 3258 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ 3259 /* Delay after an RCC peripheral clock enabling */ \ 3260 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ 3261 UNUSED(tmpreg); \ 3262 } while(0) 3263 3264 #define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \ 3265 __IO uint32_t tmpreg; \ 3266 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ 3267 /* Delay after an RCC peripheral clock enabling */ \ 3268 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ 3269 UNUSED(tmpreg); \ 3270 } while(0) 3271 3272 #define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \ 3273 __IO uint32_t tmpreg; \ 3274 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ 3275 /* Delay after an RCC peripheral clock enabling */ \ 3276 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ 3277 UNUSED(tmpreg); \ 3278 } while(0) 3279 3280 #define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \ 3281 __IO uint32_t tmpreg; \ 3282 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ 3283 /* Delay after an RCC peripheral clock enabling */ \ 3284 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ 3285 UNUSED(tmpreg); \ 3286 } while(0) 3287 3288 #define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \ 3289 __IO uint32_t tmpreg; \ 3290 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ 3291 /* Delay after an RCC peripheral clock enabling */ \ 3292 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ 3293 UNUSED(tmpreg); \ 3294 } while(0) 3295 3296 #define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \ 3297 __IO uint32_t tmpreg; \ 3298 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ 3299 /* Delay after an RCC peripheral clock enabling */ \ 3300 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ 3301 UNUSED(tmpreg); \ 3302 } while(0) 3303 3304 #define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \ 3305 __IO uint32_t tmpreg; \ 3306 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 3307 /* Delay after an RCC peripheral clock enabling */ \ 3308 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 3309 UNUSED(tmpreg); \ 3310 } while(0) 3311 3312 #define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \ 3313 __IO uint32_t tmpreg; \ 3314 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 3315 /* Delay after an RCC peripheral clock enabling */ \ 3316 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 3317 UNUSED(tmpreg); \ 3318 } while(0) 3319 3320 #define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \ 3321 __IO uint32_t tmpreg; \ 3322 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 3323 /* Delay after an RCC peripheral clock enabling */ \ 3324 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 3325 UNUSED(tmpreg); \ 3326 } while(0) 3327 3328 #define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \ 3329 __IO uint32_t tmpreg; \ 3330 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ 3331 /* Delay after an RCC peripheral clock enabling */ \ 3332 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ 3333 UNUSED(tmpreg); \ 3334 } while(0) 3335 3336 3337 #define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) 3338 #define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) 3339 #define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) 3340 #define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) 3341 #define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) 3342 #define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) 3343 #define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) 3344 #define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) 3345 #define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) 3346 #define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) 3347 #define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) 3348 #define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) 3349 #define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) 3350 #define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) 3351 #define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) 3352 #define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) 3353 #define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) 3354 #define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) 3355 #define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) 3356 #define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) 3357 #define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) 3358 #define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) 3359 #define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) 3360 #define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) 3361 #define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) 3362 #define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) 3363 #define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) 3364 #define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) 3365 #define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) 3366 #define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) 3367 3368 /** @brief Enable or disable the APB2 peripheral clock. 3369 * @note After reset, the peripheral clock (used for registers read/write access) 3370 * is disabled and the application software has to enable this clock before 3371 * using it. 3372 */ 3373 3374 #define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \ 3375 __IO uint32_t tmpreg; \ 3376 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ 3377 /* Delay after an RCC peripheral clock enabling */ \ 3378 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ 3379 UNUSED(tmpreg); \ 3380 } while(0) 3381 3382 #define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \ 3383 __IO uint32_t tmpreg; \ 3384 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ 3385 /* Delay after an RCC peripheral clock enabling */ \ 3386 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ 3387 UNUSED(tmpreg); \ 3388 } while(0) 3389 3390 #define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \ 3391 __IO uint32_t tmpreg; \ 3392 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ 3393 /* Delay after an RCC peripheral clock enabling */ \ 3394 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ 3395 UNUSED(tmpreg); \ 3396 } while(0) 3397 3398 #define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \ 3399 __IO uint32_t tmpreg; \ 3400 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ 3401 /* Delay after an RCC peripheral clock enabling */ \ 3402 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ 3403 UNUSED(tmpreg); \ 3404 } while(0) 3405 3406 #define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \ 3407 __IO uint32_t tmpreg; \ 3408 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ 3409 /* Delay after an RCC peripheral clock enabling */ \ 3410 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ 3411 UNUSED(tmpreg); \ 3412 } while(0) 3413 3414 #define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \ 3415 __IO uint32_t tmpreg; \ 3416 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3417 /* Delay after an RCC peripheral clock enabling */ \ 3418 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3419 UNUSED(tmpreg); \ 3420 } while(0) 3421 3422 #define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \ 3423 __IO uint32_t tmpreg; \ 3424 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ 3425 /* Delay after an RCC peripheral clock enabling */ \ 3426 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ 3427 UNUSED(tmpreg); \ 3428 } while(0) 3429 3430 #define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \ 3431 __IO uint32_t tmpreg; \ 3432 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ 3433 /* Delay after an RCC peripheral clock enabling */ \ 3434 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ 3435 UNUSED(tmpreg); \ 3436 } while(0) 3437 3438 #define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \ 3439 __IO uint32_t tmpreg; \ 3440 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ 3441 /* Delay after an RCC peripheral clock enabling */ \ 3442 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ 3443 UNUSED(tmpreg); \ 3444 } while(0) 3445 3446 #define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \ 3447 __IO uint32_t tmpreg; \ 3448 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3449 /* Delay after an RCC peripheral clock enabling */ \ 3450 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3451 UNUSED(tmpreg); \ 3452 } while(0) 3453 3454 #define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \ 3455 __IO uint32_t tmpreg; \ 3456 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ 3457 /* Delay after an RCC peripheral clock enabling */ \ 3458 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ 3459 UNUSED(tmpreg); \ 3460 } while(0) 3461 3462 #define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \ 3463 __IO uint32_t tmpreg; \ 3464 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ 3465 /* Delay after an RCC peripheral clock enabling */ \ 3466 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ 3467 UNUSED(tmpreg); \ 3468 } while(0) 3469 3470 #define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \ 3471 __IO uint32_t tmpreg; \ 3472 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ 3473 /* Delay after an RCC peripheral clock enabling */ \ 3474 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ 3475 UNUSED(tmpreg); \ 3476 } while(0) 3477 3478 #define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \ 3479 __IO uint32_t tmpreg; \ 3480 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 3481 /* Delay after an RCC peripheral clock enabling */ \ 3482 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 3483 UNUSED(tmpreg); \ 3484 } while(0) 3485 3486 #define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \ 3487 __IO uint32_t tmpreg; \ 3488 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 3489 /* Delay after an RCC peripheral clock enabling */ \ 3490 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 3491 UNUSED(tmpreg); \ 3492 } while(0) 3493 3494 #define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) 3495 #define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) 3496 #define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) 3497 #define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) 3498 #define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) 3499 #define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) 3500 #define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) 3501 #define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) 3502 #define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) 3503 #define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) 3504 #define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) 3505 #define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) 3506 #define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) 3507 #define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) 3508 #define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) 3509 3510 /** @brief Enable or disable the APB4 peripheral clock. 3511 * @note After reset, the peripheral clock (used for registers read/write access) 3512 * is disabled and the application software has to enable this clock before 3513 * using it. 3514 */ 3515 3516 #define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \ 3517 __IO uint32_t tmpreg; \ 3518 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 3519 /* Delay after an RCC peripheral clock enabling */ \ 3520 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 3521 UNUSED(tmpreg); \ 3522 } while(0) 3523 3524 #define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \ 3525 __IO uint32_t tmpreg; \ 3526 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 3527 /* Delay after an RCC peripheral clock enabling */ \ 3528 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 3529 UNUSED(tmpreg); \ 3530 } while(0) 3531 3532 #define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \ 3533 __IO uint32_t tmpreg; \ 3534 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ 3535 /* Delay after an RCC peripheral clock enabling */ \ 3536 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ 3537 UNUSED(tmpreg); \ 3538 } while(0) 3539 3540 #define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \ 3541 __IO uint32_t tmpreg; \ 3542 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ 3543 /* Delay after an RCC peripheral clock enabling */ \ 3544 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ 3545 UNUSED(tmpreg); \ 3546 } while(0) 3547 3548 #define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \ 3549 __IO uint32_t tmpreg; \ 3550 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 3551 /* Delay after an RCC peripheral clock enabling */ \ 3552 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 3553 UNUSED(tmpreg); \ 3554 } while(0) 3555 3556 #define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \ 3557 __IO uint32_t tmpreg; \ 3558 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 3559 /* Delay after an RCC peripheral clock enabling */ \ 3560 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 3561 UNUSED(tmpreg); \ 3562 } while(0) 3563 3564 #define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \ 3565 __IO uint32_t tmpreg; \ 3566 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 3567 /* Delay after an RCC peripheral clock enabling */ \ 3568 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 3569 UNUSED(tmpreg); \ 3570 } while(0) 3571 3572 #define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \ 3573 __IO uint32_t tmpreg; \ 3574 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 3575 /* Delay after an RCC peripheral clock enabling */ \ 3576 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 3577 UNUSED(tmpreg); \ 3578 } while(0) 3579 3580 #define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \ 3581 __IO uint32_t tmpreg; \ 3582 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ 3583 /* Delay after an RCC peripheral clock enabling */ \ 3584 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ 3585 UNUSED(tmpreg); \ 3586 } while(0) 3587 3588 3589 #define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \ 3590 __IO uint32_t tmpreg; \ 3591 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ 3592 /* Delay after an RCC peripheral clock enabling */ \ 3593 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ 3594 UNUSED(tmpreg); \ 3595 } while(0) 3596 3597 #define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \ 3598 __IO uint32_t tmpreg; \ 3599 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 3600 /* Delay after an RCC peripheral clock enabling */ \ 3601 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 3602 UNUSED(tmpreg); \ 3603 } while(0) 3604 3605 #define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \ 3606 __IO uint32_t tmpreg; \ 3607 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ 3608 /* Delay after an RCC peripheral clock enabling */ \ 3609 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ 3610 UNUSED(tmpreg); \ 3611 } while(0) 3612 3613 3614 #define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) 3615 #define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) 3616 #define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) 3617 #define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) 3618 #define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) 3619 #define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) 3620 #define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) 3621 #define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) 3622 #define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) 3623 #define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) 3624 #define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) 3625 #define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) 3626 3627 /* Exported macros for RCC_C2 -------------------------------------------------*/ 3628 3629 /** @brief Enable or disable the AHB3 peripheral clock. 3630 * @note After reset, the peripheral clock (used for registers read/write access) 3631 * is disabled and the application software has to enable this clock before 3632 * using it. 3633 */ 3634 3635 3636 #define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \ 3637 __IO uint32_t tmpreg; \ 3638 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 3639 /* Delay after an RCC peripheral clock enabling */ \ 3640 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 3641 UNUSED(tmpreg); \ 3642 } while(0) 3643 3644 #define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \ 3645 __IO uint32_t tmpreg; \ 3646 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 3647 /* Delay after an RCC peripheral clock enabling */ \ 3648 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 3649 UNUSED(tmpreg); \ 3650 } while(0) 3651 3652 #define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \ 3653 __IO uint32_t tmpreg; \ 3654 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 3655 /* Delay after an RCC peripheral clock enabling */ \ 3656 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 3657 UNUSED(tmpreg); \ 3658 } while(0) 3659 3660 #define __HAL_RCC_FLASH_C2_ALLOCATE() do { \ 3661 __IO uint32_t tmpreg; \ 3662 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ 3663 /* Delay after an RCC peripheral clock enabling */ \ 3664 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ 3665 UNUSED(tmpreg); \ 3666 } while(0) 3667 3668 #define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \ 3669 __IO uint32_t tmpreg; \ 3670 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ 3671 /* Delay after an RCC peripheral clock enabling */ \ 3672 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ 3673 UNUSED(tmpreg); \ 3674 } while(0) 3675 3676 #define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \ 3677 __IO uint32_t tmpreg; \ 3678 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ 3679 /* Delay after an RCC peripheral clock enabling */ \ 3680 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ 3681 UNUSED(tmpreg); \ 3682 } while(0) 3683 3684 #define __HAL_RCC_ITCM_C2_ALLOCATE() do { \ 3685 __IO uint32_t tmpreg; \ 3686 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ 3687 /* Delay after an RCC peripheral clock enabling */ \ 3688 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ 3689 UNUSED(tmpreg); \ 3690 } while(0) 3691 3692 #define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \ 3693 __IO uint32_t tmpreg; \ 3694 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ 3695 /* Delay after an RCC peripheral clock enabling */ \ 3696 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ 3697 UNUSED(tmpreg); \ 3698 } while(0) 3699 3700 #define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \ 3701 __IO uint32_t tmpreg; \ 3702 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 3703 /* Delay after an RCC peripheral clock enabling */ \ 3704 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 3705 UNUSED(tmpreg); \ 3706 } while(0) 3707 3708 #define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \ 3709 __IO uint32_t tmpreg; \ 3710 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 3711 /* Delay after an RCC peripheral clock enabling */ \ 3712 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 3713 UNUSED(tmpreg); \ 3714 } while(0) 3715 3716 #define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \ 3717 __IO uint32_t tmpreg; \ 3718 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 3719 /* Delay after an RCC peripheral clock enabling */ \ 3720 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ 3721 UNUSED(tmpreg); \ 3722 } while(0) 3723 3724 3725 3726 3727 #define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) 3728 #define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) 3729 #define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) 3730 #define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) 3731 #define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) 3732 #define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) 3733 #define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN)) 3734 #define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN)) 3735 #define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN)) 3736 #define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN)) 3737 #define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN)) 3738 3739 /** @brief Enable or disable the AHB1 peripheral clock. 3740 * @note After reset, the peripheral clock (used for registers read/write access) 3741 * is disabled and the application software has to enable this clock before 3742 * using it. 3743 */ 3744 3745 #define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \ 3746 __IO uint32_t tmpreg; \ 3747 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 3748 /* Delay after an RCC peripheral clock enabling */ \ 3749 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 3750 UNUSED(tmpreg); \ 3751 } while(0) 3752 3753 #define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \ 3754 __IO uint32_t tmpreg; \ 3755 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 3756 /* Delay after an RCC peripheral clock enabling */ \ 3757 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 3758 UNUSED(tmpreg); \ 3759 } while(0) 3760 3761 #define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \ 3762 __IO uint32_t tmpreg; \ 3763 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 3764 /* Delay after an RCC peripheral clock enabling */ \ 3765 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 3766 UNUSED(tmpreg); \ 3767 } while(0) 3768 3769 #define __HAL_RCC_C2_ART_CLK_ENABLE() do { \ 3770 __IO uint32_t tmpreg; \ 3771 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 3772 /* Delay after an RCC peripheral clock enabling */ \ 3773 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ 3774 UNUSED(tmpreg); \ 3775 } while(0) 3776 3777 #define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \ 3778 __IO uint32_t tmpreg; \ 3779 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 3780 /* Delay after an RCC peripheral clock enabling */ \ 3781 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 3782 UNUSED(tmpreg); \ 3783 } while(0) 3784 3785 #define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \ 3786 __IO uint32_t tmpreg; \ 3787 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 3788 /* Delay after an RCC peripheral clock enabling */ \ 3789 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 3790 UNUSED(tmpreg); \ 3791 } while(0) 3792 3793 #define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \ 3794 __IO uint32_t tmpreg; \ 3795 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 3796 /* Delay after an RCC peripheral clock enabling */ \ 3797 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 3798 UNUSED(tmpreg); \ 3799 } while(0) 3800 3801 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \ 3802 __IO uint32_t tmpreg; \ 3803 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 3804 /* Delay after an RCC peripheral clock enabling */ \ 3805 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ 3806 UNUSED(tmpreg); \ 3807 } while(0) 3808 3809 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ 3810 __IO uint32_t tmpreg; \ 3811 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 3812 /* Delay after an RCC peripheral clock enabling */ \ 3813 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ 3814 UNUSED(tmpreg); \ 3815 } while(0) 3816 3817 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \ 3818 __IO uint32_t tmpreg; \ 3819 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 3820 /* Delay after an RCC peripheral clock enabling */ \ 3821 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ 3822 UNUSED(tmpreg); \ 3823 } while(0) 3824 3825 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ 3826 __IO uint32_t tmpreg; \ 3827 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 3828 /* Delay after an RCC peripheral clock enabling */ \ 3829 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ 3830 UNUSED(tmpreg); \ 3831 } while(0) 3832 3833 3834 #define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) 3835 #define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) 3836 #define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) 3837 #define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) 3838 #define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) 3839 #define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) 3840 #define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) 3841 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) 3842 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) 3843 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) 3844 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) 3845 3846 /** @brief Enable or disable the AHB2 peripheral clock. 3847 * @note After reset, the peripheral clock (used for registers read/write access) 3848 * is disabled and the application software has to enable this clock before 3849 * using it. 3850 */ 3851 3852 #define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \ 3853 __IO uint32_t tmpreg; \ 3854 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 3855 /* Delay after an RCC peripheral clock enabling */ \ 3856 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 3857 UNUSED(tmpreg); \ 3858 } while(0) 3859 3860 #if defined(CRYP) 3861 #define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \ 3862 __IO uint32_t tmpreg; \ 3863 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 3864 /* Delay after an RCC peripheral clock enabling */ \ 3865 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 3866 UNUSED(tmpreg); \ 3867 } while(0) 3868 #endif /* CRYP */ 3869 3870 #if defined(HASH) 3871 #define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \ 3872 __IO uint32_t tmpreg; \ 3873 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 3874 /* Delay after an RCC peripheral clock enabling */ \ 3875 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 3876 UNUSED(tmpreg); \ 3877 } while(0) 3878 #endif /* HASH */ 3879 3880 #define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \ 3881 __IO uint32_t tmpreg; \ 3882 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 3883 /* Delay after an RCC peripheral clock enabling */ \ 3884 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 3885 UNUSED(tmpreg); \ 3886 } while(0) 3887 3888 #define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \ 3889 __IO uint32_t tmpreg; \ 3890 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 3891 /* Delay after an RCC peripheral clock enabling */ \ 3892 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 3893 UNUSED(tmpreg); \ 3894 } while(0) 3895 3896 #define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \ 3897 __IO uint32_t tmpreg; \ 3898 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 3899 /* Delay after an RCC peripheral clock enabling */ \ 3900 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ 3901 UNUSED(tmpreg); \ 3902 } while(0) 3903 3904 #define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \ 3905 __IO uint32_t tmpreg; \ 3906 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 3907 /* Delay after an RCC peripheral clock enabling */ \ 3908 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ 3909 UNUSED(tmpreg); \ 3910 } while(0) 3911 3912 #define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \ 3913 __IO uint32_t tmpreg; \ 3914 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 3915 /* Delay after an RCC peripheral clock enabling */ \ 3916 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ 3917 UNUSED(tmpreg); \ 3918 } while(0) 3919 3920 #define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) 3921 #if defined(CRYP) 3922 #define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) 3923 #endif /* CRYP */ 3924 #if defined(HASH) 3925 #define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) 3926 #endif /* HASH */ 3927 #define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) 3928 #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) 3929 #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) 3930 #define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) 3931 #define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) 3932 3933 /** @brief Enable or disable the AHB4 peripheral clock. 3934 * @note After reset, the peripheral clock (used for registers read/write access) 3935 * is disabled and the application software has to enable this clock before 3936 * using it. 3937 */ 3938 3939 #define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \ 3940 __IO uint32_t tmpreg; \ 3941 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 3942 /* Delay after an RCC peripheral clock enabling */ \ 3943 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 3944 UNUSED(tmpreg); \ 3945 } while(0) 3946 3947 #define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \ 3948 __IO uint32_t tmpreg; \ 3949 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 3950 /* Delay after an RCC peripheral clock enabling */ \ 3951 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 3952 UNUSED(tmpreg); \ 3953 } while(0) 3954 3955 #define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \ 3956 __IO uint32_t tmpreg; \ 3957 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 3958 /* Delay after an RCC peripheral clock enabling */ \ 3959 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 3960 UNUSED(tmpreg); \ 3961 } while(0) 3962 3963 #define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \ 3964 __IO uint32_t tmpreg; \ 3965 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 3966 /* Delay after an RCC peripheral clock enabling */ \ 3967 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 3968 UNUSED(tmpreg); \ 3969 } while(0) 3970 3971 #define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \ 3972 __IO uint32_t tmpreg; \ 3973 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 3974 /* Delay after an RCC peripheral clock enabling */ \ 3975 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 3976 UNUSED(tmpreg); \ 3977 } while(0) 3978 3979 #define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \ 3980 __IO uint32_t tmpreg; \ 3981 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 3982 /* Delay after an RCC peripheral clock enabling */ \ 3983 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 3984 UNUSED(tmpreg); \ 3985 } while(0) 3986 3987 #define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \ 3988 __IO uint32_t tmpreg; \ 3989 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 3990 /* Delay after an RCC peripheral clock enabling */ \ 3991 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 3992 UNUSED(tmpreg); \ 3993 } while(0) 3994 3995 #define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \ 3996 __IO uint32_t tmpreg; \ 3997 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 3998 /* Delay after an RCC peripheral clock enabling */ \ 3999 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 4000 UNUSED(tmpreg); \ 4001 } while(0) 4002 4003 #define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \ 4004 __IO uint32_t tmpreg; \ 4005 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 4006 /* Delay after an RCC peripheral clock enabling */ \ 4007 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ 4008 UNUSED(tmpreg); \ 4009 } while(0) 4010 4011 #define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \ 4012 __IO uint32_t tmpreg; \ 4013 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 4014 /* Delay after an RCC peripheral clock enabling */ \ 4015 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ 4016 UNUSED(tmpreg); \ 4017 } while(0) 4018 4019 #define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \ 4020 __IO uint32_t tmpreg; \ 4021 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 4022 /* Delay after an RCC peripheral clock enabling */ \ 4023 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ 4024 UNUSED(tmpreg); \ 4025 } while(0) 4026 4027 #define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \ 4028 __IO uint32_t tmpreg; \ 4029 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 4030 /* Delay after an RCC peripheral clock enabling */ \ 4031 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 4032 UNUSED(tmpreg); \ 4033 } while(0) 4034 4035 #define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \ 4036 __IO uint32_t tmpreg; \ 4037 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 4038 /* Delay after an RCC peripheral clock enabling */ \ 4039 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ 4040 UNUSED(tmpreg); \ 4041 } while(0) 4042 4043 #define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \ 4044 __IO uint32_t tmpreg; \ 4045 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 4046 /* Delay after an RCC peripheral clock enabling */ \ 4047 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ 4048 UNUSED(tmpreg); \ 4049 } while(0) 4050 4051 #define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \ 4052 __IO uint32_t tmpreg; \ 4053 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 4054 /* Delay after an RCC peripheral clock enabling */ \ 4055 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ 4056 UNUSED(tmpreg); \ 4057 } while(0) 4058 4059 #define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \ 4060 __IO uint32_t tmpreg; \ 4061 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 4062 /* Delay after an RCC peripheral clock enabling */ \ 4063 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 4064 UNUSED(tmpreg); \ 4065 } while(0) 4066 4067 4068 #define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) 4069 #define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) 4070 #define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) 4071 #define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) 4072 #define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) 4073 #define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) 4074 #define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) 4075 #define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) 4076 #define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) 4077 #define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) 4078 #define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) 4079 #define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) 4080 #define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) 4081 #define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) 4082 #define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) 4083 #define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) 4084 4085 4086 /** @brief Enable or disable the APB3 peripheral clock. 4087 * @note After reset, the peripheral clock (used for registers read/write access) 4088 * is disabled and the application software has to enable this clock before 4089 * using it. 4090 */ 4091 4092 #define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \ 4093 __IO uint32_t tmpreg; \ 4094 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ 4095 /* Delay after an RCC peripheral clock enabling */ \ 4096 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ 4097 UNUSED(tmpreg); \ 4098 } while(0) 4099 4100 #define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \ 4101 __IO uint32_t tmpreg; \ 4102 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ 4103 /* Delay after an RCC peripheral clock enabling */ \ 4104 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ 4105 UNUSED(tmpreg); \ 4106 } while(0) 4107 4108 #define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \ 4109 __IO uint32_t tmpreg; \ 4110 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 4111 /* Delay after an RCC peripheral clock enabling */ \ 4112 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ 4113 UNUSED(tmpreg); \ 4114 } while(0) 4115 4116 #define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) 4117 #define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) 4118 #define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) 4119 4120 /** @brief Enable or disable the APB1 peripheral clock. 4121 * @note After reset, the peripheral clock (used for registers read/write access) 4122 * is disabled and the application software has to enable this clock before 4123 * using it. 4124 */ 4125 4126 #define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \ 4127 __IO uint32_t tmpreg; \ 4128 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ 4129 /* Delay after an RCC peripheral clock enabling */ \ 4130 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ 4131 UNUSED(tmpreg); \ 4132 } while(0) 4133 4134 #define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \ 4135 __IO uint32_t tmpreg; \ 4136 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ 4137 /* Delay after an RCC peripheral clock enabling */ \ 4138 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ 4139 UNUSED(tmpreg); \ 4140 } while(0) 4141 4142 #define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \ 4143 __IO uint32_t tmpreg; \ 4144 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ 4145 /* Delay after an RCC peripheral clock enabling */ \ 4146 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ 4147 UNUSED(tmpreg); \ 4148 } while(0) 4149 4150 #define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \ 4151 __IO uint32_t tmpreg; \ 4152 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ 4153 /* Delay after an RCC peripheral clock enabling */ \ 4154 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ 4155 UNUSED(tmpreg); \ 4156 } while(0) 4157 4158 #define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \ 4159 __IO uint32_t tmpreg; \ 4160 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ 4161 /* Delay after an RCC peripheral clock enabling */ \ 4162 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ 4163 UNUSED(tmpreg); \ 4164 } while(0) 4165 4166 #define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \ 4167 __IO uint32_t tmpreg; \ 4168 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ 4169 /* Delay after an RCC peripheral clock enabling */ \ 4170 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ 4171 UNUSED(tmpreg); \ 4172 } while(0) 4173 4174 #define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \ 4175 __IO uint32_t tmpreg; \ 4176 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ 4177 /* Delay after an RCC peripheral clock enabling */ \ 4178 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ 4179 UNUSED(tmpreg); \ 4180 } while(0) 4181 4182 #define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \ 4183 __IO uint32_t tmpreg; \ 4184 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ 4185 /* Delay after an RCC peripheral clock enabling */ \ 4186 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ 4187 UNUSED(tmpreg); \ 4188 } while(0) 4189 4190 #define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \ 4191 __IO uint32_t tmpreg; \ 4192 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ 4193 /* Delay after an RCC peripheral clock enabling */ \ 4194 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ 4195 UNUSED(tmpreg); \ 4196 } while(0) 4197 4198 #define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \ 4199 __IO uint32_t tmpreg; \ 4200 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 4201 /* Delay after an RCC peripheral clock enabling */ \ 4202 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ 4203 UNUSED(tmpreg); \ 4204 } while(0) 4205 4206 #define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \ 4207 __IO uint32_t tmpreg; \ 4208 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 4209 /* Delay after an RCC peripheral clock enabling */ \ 4210 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ 4211 UNUSED(tmpreg); \ 4212 } while(0) 4213 4214 #define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \ 4215 __IO uint32_t tmpreg; \ 4216 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ 4217 /* Delay after an RCC peripheral clock enabling */ \ 4218 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ 4219 UNUSED(tmpreg); \ 4220 } while(0) 4221 4222 #define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \ 4223 __IO uint32_t tmpreg; \ 4224 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ 4225 /* Delay after an RCC peripheral clock enabling */ \ 4226 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ 4227 UNUSED(tmpreg); \ 4228 } while(0) 4229 4230 #define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \ 4231 __IO uint32_t tmpreg; \ 4232 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 4233 /* Delay after an RCC peripheral clock enabling */ \ 4234 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ 4235 UNUSED(tmpreg); \ 4236 } while(0) 4237 4238 #define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \ 4239 __IO uint32_t tmpreg; \ 4240 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ 4241 /* Delay after an RCC peripheral clock enabling */ \ 4242 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ 4243 UNUSED(tmpreg); \ 4244 } while(0) 4245 4246 #define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \ 4247 __IO uint32_t tmpreg; \ 4248 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ 4249 /* Delay after an RCC peripheral clock enabling */ \ 4250 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ 4251 UNUSED(tmpreg); \ 4252 } while(0) 4253 4254 #define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \ 4255 __IO uint32_t tmpreg; \ 4256 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ 4257 /* Delay after an RCC peripheral clock enabling */ \ 4258 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ 4259 UNUSED(tmpreg); \ 4260 } while(0) 4261 4262 #define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \ 4263 __IO uint32_t tmpreg; \ 4264 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ 4265 /* Delay after an RCC peripheral clock enabling */ \ 4266 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ 4267 UNUSED(tmpreg); \ 4268 } while(0) 4269 4270 #define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \ 4271 __IO uint32_t tmpreg; \ 4272 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ 4273 /* Delay after an RCC peripheral clock enabling */ \ 4274 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ 4275 UNUSED(tmpreg); \ 4276 } while(0) 4277 4278 #define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \ 4279 __IO uint32_t tmpreg; \ 4280 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ 4281 /* Delay after an RCC peripheral clock enabling */ \ 4282 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ 4283 UNUSED(tmpreg); \ 4284 } while(0) 4285 4286 #define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \ 4287 __IO uint32_t tmpreg; \ 4288 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ 4289 /* Delay after an RCC peripheral clock enabling */ \ 4290 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ 4291 UNUSED(tmpreg); \ 4292 } while(0) 4293 4294 #define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \ 4295 __IO uint32_t tmpreg; \ 4296 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ 4297 /* Delay after an RCC peripheral clock enabling */ \ 4298 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ 4299 UNUSED(tmpreg); \ 4300 } while(0) 4301 4302 #define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \ 4303 __IO uint32_t tmpreg; \ 4304 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ 4305 /* Delay after an RCC peripheral clock enabling */ \ 4306 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ 4307 UNUSED(tmpreg); \ 4308 } while(0) 4309 4310 #define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \ 4311 __IO uint32_t tmpreg; \ 4312 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ 4313 /* Delay after an RCC peripheral clock enabling */ \ 4314 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ 4315 UNUSED(tmpreg); \ 4316 } while(0) 4317 4318 #define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \ 4319 __IO uint32_t tmpreg; \ 4320 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ 4321 /* Delay after an RCC peripheral clock enabling */ \ 4322 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ 4323 UNUSED(tmpreg); \ 4324 } while(0) 4325 4326 #define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \ 4327 __IO uint32_t tmpreg; \ 4328 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ 4329 /* Delay after an RCC peripheral clock enabling */ \ 4330 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ 4331 UNUSED(tmpreg); \ 4332 } while(0) 4333 4334 #define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \ 4335 __IO uint32_t tmpreg; \ 4336 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 4337 /* Delay after an RCC peripheral clock enabling */ \ 4338 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ 4339 UNUSED(tmpreg); \ 4340 } while(0) 4341 4342 #define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \ 4343 __IO uint32_t tmpreg; \ 4344 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 4345 /* Delay after an RCC peripheral clock enabling */ \ 4346 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ 4347 UNUSED(tmpreg); \ 4348 } while(0) 4349 4350 #define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \ 4351 __IO uint32_t tmpreg; \ 4352 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 4353 /* Delay after an RCC peripheral clock enabling */ \ 4354 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ 4355 UNUSED(tmpreg); \ 4356 } while(0) 4357 4358 #define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \ 4359 __IO uint32_t tmpreg; \ 4360 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ 4361 /* Delay after an RCC peripheral clock enabling */ \ 4362 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ 4363 UNUSED(tmpreg); \ 4364 } while(0) 4365 4366 4367 #define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) 4368 #define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) 4369 #define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) 4370 #define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) 4371 #define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) 4372 #define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) 4373 #define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) 4374 #define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) 4375 #define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) 4376 #define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) 4377 #define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) 4378 #define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) 4379 #define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) 4380 #define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) 4381 #define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) 4382 #define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) 4383 #define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) 4384 #define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) 4385 #define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) 4386 #define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) 4387 #define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) 4388 #define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) 4389 #define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) 4390 #define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) 4391 #define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) 4392 #define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) 4393 #define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) 4394 #define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) 4395 #define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) 4396 #define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) 4397 4398 /** @brief Enable or disable the APB2 peripheral clock. 4399 * @note After reset, the peripheral clock (used for registers read/write access) 4400 * is disabled and the application software has to enable this clock before 4401 * using it. 4402 */ 4403 4404 #define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \ 4405 __IO uint32_t tmpreg; \ 4406 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ 4407 /* Delay after an RCC peripheral clock enabling */ \ 4408 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ 4409 UNUSED(tmpreg); \ 4410 } while(0) 4411 4412 #define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \ 4413 __IO uint32_t tmpreg; \ 4414 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4415 /* Delay after an RCC peripheral clock enabling */ \ 4416 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4417 UNUSED(tmpreg); \ 4418 } while(0) 4419 4420 #define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \ 4421 __IO uint32_t tmpreg; \ 4422 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ 4423 /* Delay after an RCC peripheral clock enabling */ \ 4424 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ 4425 UNUSED(tmpreg); \ 4426 } while(0) 4427 4428 #define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \ 4429 __IO uint32_t tmpreg; \ 4430 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ 4431 /* Delay after an RCC peripheral clock enabling */ \ 4432 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ 4433 UNUSED(tmpreg); \ 4434 } while(0) 4435 4436 #define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \ 4437 __IO uint32_t tmpreg; \ 4438 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ 4439 /* Delay after an RCC peripheral clock enabling */ \ 4440 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ 4441 UNUSED(tmpreg); \ 4442 } while(0) 4443 4444 #define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \ 4445 __IO uint32_t tmpreg; \ 4446 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4447 /* Delay after an RCC peripheral clock enabling */ \ 4448 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4449 UNUSED(tmpreg); \ 4450 } while(0) 4451 4452 #define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \ 4453 __IO uint32_t tmpreg; \ 4454 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ 4455 /* Delay after an RCC peripheral clock enabling */ \ 4456 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ 4457 UNUSED(tmpreg); \ 4458 } while(0) 4459 4460 #define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \ 4461 __IO uint32_t tmpreg; \ 4462 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ 4463 /* Delay after an RCC peripheral clock enabling */ \ 4464 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ 4465 UNUSED(tmpreg); \ 4466 } while(0) 4467 4468 #define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \ 4469 __IO uint32_t tmpreg; \ 4470 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ 4471 /* Delay after an RCC peripheral clock enabling */ \ 4472 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ 4473 UNUSED(tmpreg); \ 4474 } while(0) 4475 4476 #define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \ 4477 __IO uint32_t tmpreg; \ 4478 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ 4479 /* Delay after an RCC peripheral clock enabling */ \ 4480 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ 4481 UNUSED(tmpreg); \ 4482 } while(0) 4483 4484 #define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \ 4485 __IO uint32_t tmpreg; \ 4486 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4487 /* Delay after an RCC peripheral clock enabling */ \ 4488 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4489 UNUSED(tmpreg); \ 4490 } while(0) 4491 4492 #define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \ 4493 __IO uint32_t tmpreg; \ 4494 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4495 /* Delay after an RCC peripheral clock enabling */ \ 4496 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4497 UNUSED(tmpreg); \ 4498 } while(0) 4499 4500 #define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \ 4501 __IO uint32_t tmpreg; \ 4502 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ 4503 /* Delay after an RCC peripheral clock enabling */ \ 4504 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ 4505 UNUSED(tmpreg); \ 4506 } while(0) 4507 4508 #define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \ 4509 __IO uint32_t tmpreg; \ 4510 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 4511 /* Delay after an RCC peripheral clock enabling */ \ 4512 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 4513 UNUSED(tmpreg); \ 4514 } while(0) 4515 4516 #define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \ 4517 __IO uint32_t tmpreg; \ 4518 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 4519 /* Delay after an RCC peripheral clock enabling */ \ 4520 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ 4521 UNUSED(tmpreg); \ 4522 } while(0) 4523 4524 #define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) 4525 #define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) 4526 #define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) 4527 #define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) 4528 #define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) 4529 #define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) 4530 #define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) 4531 #define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) 4532 #define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) 4533 #define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) 4534 #define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) 4535 #define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) 4536 #define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) 4537 #define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) 4538 #define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) 4539 4540 /** @brief Enable or disable the APB4 peripheral clock. 4541 * @note After reset, the peripheral clock (used for registers read/write access) 4542 * is disabled and the application software has to enable this clock before 4543 * using it. 4544 */ 4545 4546 #define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \ 4547 __IO uint32_t tmpreg; \ 4548 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 4549 /* Delay after an RCC peripheral clock enabling */ \ 4550 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ 4551 UNUSED(tmpreg); \ 4552 } while(0) 4553 4554 #define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \ 4555 __IO uint32_t tmpreg; \ 4556 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 4557 /* Delay after an RCC peripheral clock enabling */ \ 4558 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 4559 UNUSED(tmpreg); \ 4560 } while(0) 4561 4562 #define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \ 4563 __IO uint32_t tmpreg; \ 4564 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ 4565 /* Delay after an RCC peripheral clock enabling */ \ 4566 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ 4567 UNUSED(tmpreg); \ 4568 } while(0) 4569 4570 #define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \ 4571 __IO uint32_t tmpreg; \ 4572 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ 4573 /* Delay after an RCC peripheral clock enabling */ \ 4574 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ 4575 UNUSED(tmpreg); \ 4576 } while(0) 4577 4578 #define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \ 4579 __IO uint32_t tmpreg; \ 4580 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 4581 /* Delay after an RCC peripheral clock enabling */ \ 4582 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 4583 UNUSED(tmpreg); \ 4584 } while(0) 4585 4586 #define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \ 4587 __IO uint32_t tmpreg; \ 4588 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 4589 /* Delay after an RCC peripheral clock enabling */ \ 4590 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 4591 UNUSED(tmpreg); \ 4592 } while(0) 4593 4594 #define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \ 4595 __IO uint32_t tmpreg; \ 4596 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 4597 /* Delay after an RCC peripheral clock enabling */ \ 4598 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 4599 UNUSED(tmpreg); \ 4600 } while(0) 4601 4602 #define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \ 4603 __IO uint32_t tmpreg; \ 4604 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 4605 /* Delay after an RCC peripheral clock enabling */ \ 4606 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 4607 UNUSED(tmpreg); \ 4608 } while(0) 4609 4610 #define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \ 4611 __IO uint32_t tmpreg; \ 4612 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ 4613 /* Delay after an RCC peripheral clock enabling */ \ 4614 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ 4615 UNUSED(tmpreg); \ 4616 } while(0) 4617 4618 #define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \ 4619 __IO uint32_t tmpreg; \ 4620 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ 4621 /* Delay after an RCC peripheral clock enabling */ \ 4622 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ 4623 UNUSED(tmpreg); \ 4624 } while(0) 4625 4626 #define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \ 4627 __IO uint32_t tmpreg; \ 4628 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 4629 /* Delay after an RCC peripheral clock enabling */ \ 4630 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 4631 UNUSED(tmpreg); \ 4632 } while(0) 4633 4634 #define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \ 4635 __IO uint32_t tmpreg; \ 4636 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ 4637 /* Delay after an RCC peripheral clock enabling */ \ 4638 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ 4639 UNUSED(tmpreg); \ 4640 } while(0) 4641 4642 4643 4644 #define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) 4645 #define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) 4646 #define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) 4647 #define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) 4648 #define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) 4649 #define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) 4650 #define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) 4651 #define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) 4652 #define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) 4653 #define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) 4654 #define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) 4655 #define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) 4656 4657 #endif /*DUAL_CORE*/ 4658 4659 /** @brief Enable or disable the AHB3 peripheral reset. 4660 */ 4661 4662 #if (STM32H7_DEV_ID == 0x450UL) 4663 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */ 4664 #elif (STM32H7_DEV_ID == 0x480UL) 4665 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */ 4666 #else 4667 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */ 4668 #endif /* STM32H7_DEV_ID == 0x450UL */ 4669 #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) 4670 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) 4671 #if defined(JPEG) 4672 #define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) 4673 #endif /* JPEG */ 4674 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 4675 #if defined(QUADSPI) 4676 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 4677 #endif /*QUADSPI*/ 4678 #if defined(OCTOSPI1) 4679 #define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST)) 4680 #endif /*OCTOSPI1*/ 4681 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) 4682 #if defined(OCTOSPI2) 4683 #define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST)) 4684 #endif /*OCTOSPI2*/ 4685 #if defined(OCTOSPIM) 4686 #define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST)) 4687 #endif /*OCTOSPIM*/ 4688 #if defined(OTFDEC1) 4689 #define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST)) 4690 #endif /*OTFDEC1*/ 4691 #if defined(OTFDEC2) 4692 #define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST)) 4693 #endif /*OTFDEC2*/ 4694 #if defined(GFXMMU) 4695 #define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST)) 4696 #endif /*GFXMMU*/ 4697 4698 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) 4699 #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) 4700 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) 4701 #if defined(JPEG) 4702 #define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) 4703 #endif /* JPEG */ 4704 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) 4705 #if defined(QUADSPI) 4706 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) 4707 #endif /*QUADSPI*/ 4708 #if defined(OCTOSPI1) 4709 #define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST)) 4710 #endif /*OCTOSPI1*/ 4711 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) 4712 #if defined(OCTOSPI2) 4713 #define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST)) 4714 #endif /*OCTOSPI2*/ 4715 #if defined(OCTOSPIM) 4716 #define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST)) 4717 #endif /*OCTOSPIM*/ 4718 #if defined(OTFDEC1) 4719 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST)) 4720 #endif /*OTFDEC1*/ 4721 #if defined(OTFDEC2) 4722 #define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST)) 4723 #endif /*OTFDEC2*/ 4724 #if defined(GFXMMU) 4725 #define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST)) 4726 #endif /*GFXMMU*/ 4727 4728 4729 4730 /** @brief Force or release the AHB1 peripheral reset. 4731 */ 4732 #if (STM32H7_DEV_ID == 0x450UL) 4733 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */ 4734 #elif (STM32H7_DEV_ID == 0x480UL) 4735 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */ 4736 #else 4737 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */ 4738 #endif /* STM32H7_DEV_ID == 0x450UL */ 4739 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) 4740 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) 4741 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) 4742 #if defined(DUAL_CORE) 4743 #define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST)) 4744 #endif /*DUAL_CORE*/ 4745 #if defined(RCC_AHB1RSTR_CRCRST) 4746 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 4747 #endif 4748 #if defined(ETH) 4749 #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) 4750 #endif /*ETH*/ 4751 #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) 4752 #if defined(USB2_OTG_FS) 4753 #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) 4754 #endif /*USB2_OTG_FS*/ 4755 4756 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 4757 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) 4758 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST)) 4759 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST)) 4760 #if defined(DUAL_CORE) 4761 #define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST)) 4762 #endif /*DUAL_CORE*/ 4763 #if defined(RCC_AHB1RSTR_CRCRST) 4764 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST)) 4765 #endif 4766 #if defined(ETH) 4767 #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) 4768 #endif /*ETH*/ 4769 #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) 4770 #if defined(USB2_OTG_FS) 4771 #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) 4772 #endif /*USB2_OTG_FS*/ 4773 4774 /** @brief Force or release the AHB2 peripheral reset. 4775 */ 4776 #if (STM32H7_DEV_ID == 0x450UL) 4777 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */ 4778 #elif (STM32H7_DEV_ID == 0x480UL) 4779 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */ 4780 #else 4781 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */ 4782 #endif /* STM32H7_DEV_ID == 0x450UL */ 4783 #if defined(DCMI) && defined(PSSI) 4784 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST)) 4785 #define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/ 4786 #else 4787 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 4788 #endif /* DCMI && PSSI */ 4789 #if defined(CRYP) 4790 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 4791 #endif /* CRYP */ 4792 #if defined(HASH) 4793 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 4794 #endif /* HASH */ 4795 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 4796 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) 4797 #if defined(FMAC) 4798 #define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST)) 4799 #endif /*FMAC*/ 4800 #if defined(CORDIC) 4801 #define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST)) 4802 #endif /*CORDIC*/ 4803 #if defined(RCC_AHB2RSTR_HSEMRST) 4804 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST)) 4805 #endif 4806 #if defined(BDMA1) 4807 #define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST)) 4808 #endif /*BDMA1*/ 4809 4810 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 4811 #if defined(DCMI) && defined(PSSI) 4812 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST)) 4813 #define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/ 4814 #else 4815 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) 4816 #endif /* DCMI && PSSI */ 4817 #if defined(CRYP) 4818 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) 4819 #endif /* CRYP */ 4820 #if defined(HASH) 4821 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) 4822 #endif /* HASH */ 4823 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) 4824 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) 4825 #if defined(FMAC) 4826 #define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST)) 4827 #endif /*FMAC*/ 4828 #if defined(CORDIC) 4829 #define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST)) 4830 #endif /*CORDIC*/ 4831 #if defined(RCC_AHB2RSTR_HSEMRST) 4832 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST)) 4833 #endif 4834 #if defined(BDMA1) 4835 #define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST)) 4836 #endif /*BDMA1*/ 4837 4838 4839 /** @brief Force or release the AHB4 peripheral reset. 4840 */ 4841 4842 #if (STM32H7_DEV_ID == 0x450UL) 4843 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */ 4844 #elif (STM32H7_DEV_ID == 0x480UL) 4845 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */ 4846 #else 4847 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */ 4848 #endif /* STM32H7_DEV_ID == 0x450UL */ 4849 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) 4850 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) 4851 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) 4852 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST) 4853 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST) 4854 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) 4855 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) 4856 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) 4857 #if defined(GPIOI) 4858 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) 4859 #endif /* GPIOI */ 4860 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) 4861 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) 4862 #if defined(RCC_AHB4RSTR_CRCRST) 4863 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST) 4864 #endif 4865 #if defined(BDMA2) 4866 #define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST) 4867 #define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/ 4868 #else 4869 #define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) 4870 #endif /*BDMA2*/ 4871 #if defined(ADC3) 4872 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) 4873 #endif /*ADC3*/ 4874 #if defined(RCC_AHB4RSTR_HSEMRST) 4875 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) 4876 #endif 4877 4878 #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) 4879 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) 4880 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST) 4881 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST) 4882 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST) 4883 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST) 4884 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) 4885 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) 4886 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) 4887 #if defined(GPIOI) 4888 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) 4889 #endif /* GPIOI */ 4890 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) 4891 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) 4892 #if defined(RCC_AHB4RSTR_CRCRST) 4893 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) 4894 #endif 4895 #if defined(BDMA2) 4896 #define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST) 4897 #define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/ 4898 #else 4899 #define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) 4900 #endif /*BDMA2*/ 4901 #if defined(ADC3) 4902 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) 4903 #endif /*ADC3*/ 4904 #if defined(RCC_AHB4RSTR_HSEMRST) 4905 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) 4906 #endif 4907 4908 /** @brief Force or release the APB3 peripheral reset. 4909 */ 4910 #if (STM32H7_DEV_ID == 0x450UL) 4911 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */ 4912 #else 4913 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */ 4914 #endif /* STM32H7_DEV_ID == 0x450UL */ 4915 #if defined(LTDC) 4916 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) 4917 #endif /* LTDC */ 4918 #if defined(DSI) 4919 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST) 4920 #endif /*DSI*/ 4921 4922 #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) 4923 #if defined(LTDC) 4924 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) 4925 #endif /* LTDC */ 4926 #if defined(DSI) 4927 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST) 4928 #endif /*DSI*/ 4929 4930 /** @brief Force or release the APB1 peripheral reset. 4931 */ 4932 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) 4933 #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */ 4934 #else 4935 #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */ 4936 #endif /* STM32H7_DEV_ID == 0x450UL */ 4937 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) 4938 #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */ 4939 #else 4940 #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */ 4941 #endif /* STM32H7_DEV_ID == 0x450UL */ 4942 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) 4943 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) 4944 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) 4945 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST) 4946 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST) 4947 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST) 4948 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST) 4949 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST) 4950 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST) 4951 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST) 4952 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST) 4953 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST) 4954 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST) 4955 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST) 4956 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST) 4957 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST) 4958 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST) 4959 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) 4960 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) 4961 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) 4962 #if defined(I2C5) 4963 #define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST) 4964 #endif /* I2C5 */ 4965 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) 4966 #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) 4967 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) 4968 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST) 4969 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST) 4970 #define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST) 4971 #define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) 4972 #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) 4973 #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) 4974 #if defined(TIM23) 4975 #define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST) 4976 #endif /* TIM23 */ 4977 #if defined(TIM24) 4978 #define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST) 4979 #endif /* TIM24 */ 4980 4981 #define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) 4982 #define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) 4983 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST) 4984 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST) 4985 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST) 4986 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST) 4987 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST) 4988 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST) 4989 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST) 4990 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST) 4991 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST) 4992 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST) 4993 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST) 4994 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST) 4995 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST) 4996 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST) 4997 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST) 4998 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST) 4999 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST) 5000 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) 5001 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) 5002 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) 5003 #if defined(I2C5) 5004 #define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST) 5005 #endif /* I2C5 */ 5006 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) 5007 #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) 5008 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) 5009 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST) 5010 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST) 5011 #define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST) 5012 #define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) 5013 #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) 5014 #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) 5015 #if defined(TIM23) 5016 #define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST) 5017 #endif /* TIM23 */ 5018 #if defined(TIM24) 5019 #define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST) 5020 #endif /* TIM24 */ 5021 5022 /** @brief Force or release the APB2 peripheral reset. 5023 */ 5024 #if (STM32H7_DEV_ID == 0x450UL) 5025 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */ 5026 #elif (STM32H7_DEV_ID == 0x480UL) 5027 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */ 5028 #else 5029 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */ 5030 #endif /* STM32H7_DEV_ID == 0x450UL */ 5031 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) 5032 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) 5033 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) 5034 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) 5035 #if defined(UART9) 5036 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST) 5037 #endif /*UART9*/ 5038 #if defined(USART10) 5039 #define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST) 5040 #endif /*USART10*/ 5041 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) 5042 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) 5043 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) 5044 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST) 5045 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) 5046 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) 5047 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) 5048 #if defined(SAI2) 5049 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) 5050 #endif /* SAI2 */ 5051 #if defined(SAI3) 5052 #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) 5053 #endif /*SAI3*/ 5054 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) 5055 #if defined(HRTIM1) 5056 #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) 5057 #endif /*HRTIM1*/ 5058 5059 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 5060 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) 5061 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) 5062 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) 5063 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) 5064 #if defined(UART9) 5065 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST) 5066 #endif /*UART9*/ 5067 #if defined(USART10) 5068 #define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST) 5069 #endif /*USART10*/ 5070 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) 5071 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) 5072 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) 5073 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST) 5074 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) 5075 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) 5076 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) 5077 #if defined(SAI2) 5078 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) 5079 #endif /* SAI2 */ 5080 #if defined(SAI3) 5081 #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) 5082 #endif /*SAI3*/ 5083 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) 5084 #if defined(HRTIM1) 5085 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) 5086 #endif /*HRTIM1*/ 5087 5088 /** @brief Force or release the APB4 peripheral reset. 5089 */ 5090 5091 #if (STM32H7_DEV_ID == 0x450UL) 5092 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */ 5093 #elif (STM32H7_DEV_ID == 0x480UL) 5094 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */ 5095 #else 5096 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */ 5097 #endif /* STM32H7_DEV_ID == 0x450UL */ 5098 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) 5099 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) 5100 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) 5101 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) 5102 #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) 5103 #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) 5104 #if defined(LPTIM4) 5105 #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) 5106 #endif /*LPTIM4*/ 5107 #if defined(LPTIM5) 5108 #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) 5109 #endif /*LPTIM5*/ 5110 #if defined(DAC2) 5111 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST) 5112 #endif /*DAC2*/ 5113 #define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) 5114 #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) 5115 #if defined(SAI4) 5116 #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST) 5117 #endif /*SAI4*/ 5118 #if defined(DTS) 5119 #define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST) 5120 #endif /*DTS*/ 5121 #if defined(DFSDM2_BASE) 5122 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST) 5123 #endif /*DFSDM2*/ 5124 5125 #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) 5126 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) 5127 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST) 5128 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST) 5129 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) 5130 #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) 5131 #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) 5132 #if defined(LPTIM4) 5133 #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) 5134 #endif /*LPTIM4*/ 5135 #if defined(LPTIM5) 5136 #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) 5137 #endif /*LPTIM5*/ 5138 #if defined(RCC_APB4RSTR_DAC2RST) 5139 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST) 5140 #endif 5141 #define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) 5142 #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) 5143 #if defined(SAI4) 5144 #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) 5145 #endif /*SAI4*/ 5146 #if defined(DTS) 5147 #define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST) 5148 #endif /*DTS*/ 5149 #if defined(DFSDM2_BASE) 5150 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST) 5151 #endif /*DFSDM2*/ 5152 5153 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 5154 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5155 * power consumption. 5156 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5157 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5158 */ 5159 5160 5161 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) 5162 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) 5163 #if defined(JPEG) 5164 #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) 5165 #endif /* JPEG */ 5166 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) 5167 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 5168 #if defined(QUADSPI) 5169 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 5170 #endif /*QUADSPI*/ 5171 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) 5172 #if defined(OCTOSPI1) 5173 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN)) 5174 #endif /*OCTOSPI1*/ 5175 #if defined(OCTOSPI2) 5176 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN)) 5177 #endif /*OCTOSPI2*/ 5178 #if defined(OCTOSPIM) 5179 #define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN)) 5180 #endif /*OCTOSPIM*/ 5181 #if defined(OTFDEC1) 5182 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN)) 5183 #endif /*OTFDEC1*/ 5184 #if defined(OTFDEC2) 5185 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN)) 5186 #endif /*OTFDEC2*/ 5187 #if defined(GFXMMU) 5188 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN)) 5189 #endif /*GFXMMU*/ 5190 #if defined(CD_AXISRAM2_BASE) 5191 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN)) 5192 #endif 5193 #if defined(CD_AXISRAM3_BASE) 5194 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN)) 5195 #endif 5196 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) 5197 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) 5198 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) 5199 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 5200 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) 5201 #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE 5202 #else 5203 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN)) 5204 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */ 5205 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 5206 5207 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) 5208 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) 5209 #if defined(JPEG) 5210 #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) 5211 #endif /* JPEG */ 5212 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) 5213 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) 5214 #if defined(QUADSPI) 5215 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) 5216 #endif /*QUADSPI*/ 5217 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) 5218 #if defined(OCTOSPI1) 5219 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN)) 5220 #endif /*OCTOSPI1*/ 5221 #if defined(OCTOSPI2) 5222 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN)) 5223 #endif /*OCTOSPI2*/ 5224 #if defined(OCTOSPIM) 5225 #define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN)) 5226 #endif /*OCTOSPIM*/ 5227 #if defined(OTFDEC1) 5228 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN)) 5229 #endif /*OTFDEC1*/ 5230 #if defined(OTFDEC2) 5231 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN)) 5232 #endif /*OTFDEC2*/ 5233 #if defined(GFXMMU) 5234 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN)) 5235 #endif /*GFXMMU*/ 5236 #if defined(CD_AXISRAM2_BASE) 5237 #define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN)) 5238 #endif 5239 #if defined(CD_AXISRAM3_BASE) 5240 #define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN)) 5241 #endif 5242 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) 5243 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) 5244 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) 5245 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 5246 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) 5247 #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE 5248 #else 5249 #define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN)) 5250 #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */ 5251 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 5252 5253 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. 5254 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5255 * power consumption. 5256 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5257 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5258 */ 5259 5260 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) 5261 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) 5262 #if defined(JPEG) 5263 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) 5264 #endif /* JPEG */ 5265 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) 5266 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) 5267 #if defined(QUADSPI) 5268 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) 5269 #endif /*QUADSPI*/ 5270 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) 5271 #if defined(OCTOSPI1) 5272 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U) 5273 #endif /*OCTOSPI1*/ 5274 #if defined(OCTOSPI2) 5275 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U) 5276 #endif /*OCTOSPI2*/ 5277 #if defined(OCTOSPIM) 5278 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U) 5279 #endif /*OCTOSPIM*/ 5280 #if defined(OTFDEC1) 5281 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U) 5282 #endif /*OTFDEC1*/ 5283 #if defined(OTFDEC2) 5284 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U) 5285 #endif /*OTFDEC2*/ 5286 #if defined(GFXMMU) 5287 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U) 5288 #endif /*GFXMMU*/ 5289 #if defined(CD_AXISRAM2_BASE) 5290 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U) 5291 #endif 5292 #if defined(CD_AXISRAM3_BASE) 5293 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U) 5294 #endif 5295 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) 5296 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) 5297 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) 5298 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 5299 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) 5300 #else 5301 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U) 5302 #endif 5303 5304 #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) 5305 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) 5306 #if defined(JPEG) 5307 #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) 5308 #endif /* JPEG */ 5309 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) 5310 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) 5311 #if defined(QUADSPI) 5312 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) 5313 #endif /*QUADSPI*/ 5314 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) 5315 #if defined(OCTOSPI1) 5316 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U) 5317 #endif /*OCTOSPI1*/ 5318 #if defined(OCTOSPI2) 5319 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U) 5320 #endif /*OCTOSPI2*/ 5321 #if defined(OCTOSPIM) 5322 #define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U) 5323 #endif /*OCTOSPIM*/ 5324 #if defined(OTFDEC1) 5325 #define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U) 5326 #endif /*OTFDEC1*/ 5327 #if defined(OTFDEC2) 5328 #define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U) 5329 #endif /*OTFDEC2*/ 5330 #if defined(GFXMMU) 5331 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U) 5332 #endif /*GFXMMU*/ 5333 #if defined(CD_AXISRAM2_BASE) 5334 #define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U) 5335 #endif 5336 #if defined(CD_AXISRAM3_BASE) 5337 #define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U) 5338 #endif 5339 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) 5340 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) 5341 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) 5342 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 5343 #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) 5344 #else 5345 #define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U) 5346 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 5347 5348 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 5349 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5350 * power consumption. 5351 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 5352 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 5353 */ 5354 5355 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 5356 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 5357 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) 5358 #if defined(RCC_AHB1LPENR_CRCLPEN) 5359 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 5360 #endif 5361 #if defined(ETH) 5362 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) 5363 #endif /*ETH*/ 5364 #if defined(DUAL_CORE) 5365 #define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN)) 5366 #endif /*DUAL_CORE*/ 5367 #if defined(ETH) 5368 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) 5369 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) 5370 #endif /*ETH*/ 5371 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) 5372 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 5373 #if defined(USB2_OTG_FS) 5374 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) 5375 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 5376 #endif /* USB2_OTG_FS */ 5377 5378 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) 5379 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) 5380 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) 5381 #if defined(RCC_AHB1LPENR_CRCLPEN) 5382 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN)) 5383 #endif 5384 #if defined(ETH) 5385 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) 5386 #endif /*ETH*/ 5387 #if defined(DUAL_CORE) 5388 #define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN)) 5389 #endif /*DUAL_CORE*/ 5390 #if defined(ETH) 5391 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) 5392 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) 5393 #endif /*ETH*/ 5394 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) 5395 #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 5396 #if defined(USB2_OTG_FS) 5397 #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) 5398 #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 5399 #endif /* USB2_OTG_FS */ 5400 5401 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. 5402 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5403 * power consumption. 5404 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5405 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5406 */ 5407 5408 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) 5409 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) 5410 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) 5411 #if defined(RCC_AHB1LPENR_CRCLPEN) 5412 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U) 5413 #endif 5414 #if defined(ETH) 5415 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) 5416 #endif /*ETH*/ 5417 #if defined(DUAL_CORE) 5418 #define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U) 5419 #endif /*DUAL_CORE*/ 5420 #if defined(ETH) 5421 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) 5422 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) 5423 #endif /*ETH*/ 5424 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) 5425 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) 5426 #if defined(USB2_OTG_FS) 5427 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) 5428 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U) 5429 #endif /* USB2_OTG_FS */ 5430 5431 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) 5432 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) 5433 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) 5434 #if defined(RCC_AHB1LPENR_CRCLPEN) 5435 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U) 5436 #endif 5437 #if defined(ETH) 5438 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) 5439 #endif /* ETH */ 5440 #if defined(DUAL_CORE) 5441 #define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U) 5442 #endif /*DUAL_CORE*/ 5443 #if defined(ETH) 5444 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) 5445 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) 5446 #endif /* ETH */ 5447 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) 5448 #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) 5449 #if defined(USB2_OTG_FS) 5450 #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) 5451 #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U) 5452 #endif /* USB2_OTG_FS */ 5453 5454 5455 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 5456 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5457 * power consumption. 5458 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 5459 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 5460 */ 5461 5462 #if defined(DCMI) && defined(PSSI) 5463 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN)) 5464 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/ 5465 #else 5466 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 5467 #endif /* DCMI && PSSI */ 5468 #if defined(CRYP) 5469 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 5470 #endif /* CRYP */ 5471 #if defined(HASH) 5472 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 5473 #endif /* HASH */ 5474 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 5475 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) 5476 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 5477 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN)) 5478 #endif 5479 #if defined(FMAC) 5480 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN)) 5481 #endif /* FMAC */ 5482 #if defined(CORDIC) 5483 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN)) 5484 #endif /* CORDIC */ 5485 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 5486 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) 5487 #else 5488 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN)) 5489 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 5490 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 5491 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) 5492 #else 5493 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN)) 5494 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 5495 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 5496 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) 5497 #endif 5498 5499 #if defined(DCMI) && defined(PSSI) 5500 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN)) 5501 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/ 5502 #else 5503 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) 5504 #endif /* DCMI && PSSI */ 5505 #if defined(CRYP) 5506 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) 5507 #endif /* CRYP */ 5508 #if defined(HASH) 5509 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) 5510 #endif /* HASH */ 5511 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) 5512 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) 5513 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 5514 #define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN)) 5515 #endif 5516 #if defined(FMAC) 5517 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN)) 5518 #endif /* FMAC */ 5519 #if defined(CORDIC) 5520 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN)) 5521 #endif /* CORDIC */ 5522 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 5523 #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) 5524 #else 5525 #define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN)) 5526 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 5527 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 5528 #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) 5529 #else 5530 #define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN)) 5531 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 5532 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 5533 #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) 5534 #endif 5535 5536 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. 5537 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5538 * power consumption. 5539 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5540 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5541 */ 5542 5543 #if defined(DCMI) && defined(PSSI) 5544 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U) 5545 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/ 5546 #else 5547 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) 5548 #endif /* DCMI && PSSI */ 5549 #if defined(CRYP) 5550 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) 5551 #endif /* CRYP */ 5552 #if defined(HASH) 5553 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) 5554 #endif /* HASH */ 5555 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) 5556 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) 5557 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 5558 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U) 5559 #endif 5560 #if defined(FMAC) 5561 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U) 5562 #endif /* FMAC */ 5563 #if defined(CORDIC) 5564 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U) 5565 #endif /* CORDIC */ 5566 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 5567 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) 5568 #else 5569 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U) 5570 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 5571 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 5572 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) 5573 #else 5574 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U) 5575 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 5576 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 5577 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) 5578 #endif /* RCC_AHB2LPENR_D2SRAM3LPEN */ 5579 5580 #if defined(DCMI) && defined(PSSI) 5581 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U) 5582 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/ 5583 #else 5584 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) 5585 #endif /* DCMI && PSSI */ 5586 #if defined(CRYP) 5587 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) 5588 #endif /* CRYP */ 5589 #if defined(HASH) 5590 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) 5591 #endif /* HASH */ 5592 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) 5593 #if defined(RCC_AHB2LPENR_DFSDMDMALPEN) 5594 #define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U) 5595 #endif 5596 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) 5597 #if defined(FMAC) 5598 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U) 5599 #endif /* FMAC */ 5600 #if defined(CORDIC) 5601 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U) 5602 #endif /* CORDIC */ 5603 #if defined(RCC_AHB2LPENR_D2SRAM1LPEN) 5604 #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) 5605 #else 5606 #define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U) 5607 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ 5608 #if defined(RCC_AHB2LPENR_D2SRAM2LPEN) 5609 #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) 5610 #else 5611 #define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U) 5612 #endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ 5613 #if defined(RCC_AHB2LPENR_D2SRAM3LPEN) 5614 #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) 5615 #endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/ 5616 5617 5618 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 5619 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5620 * power consumption. 5621 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 5622 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 5623 */ 5624 5625 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) 5626 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) 5627 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) 5628 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) 5629 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) 5630 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) 5631 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) 5632 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) 5633 #if defined(GPIOI) 5634 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) 5635 #endif /* GPIOI */ 5636 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) 5637 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) 5638 #if defined(RCC_AHB4LPENR_CRCLPEN) 5639 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) 5640 #endif 5641 #if defined(BDMA2) 5642 #define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN) 5643 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/ 5644 #else 5645 #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) 5646 #endif /* BDMA2 */ 5647 #if defined(ADC3) 5648 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) 5649 #endif /* ADC3 */ 5650 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) 5651 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 5652 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN)) 5653 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/ 5654 #else 5655 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) 5656 #endif /* RCC_AHB4LPENR_SRDSRAMLPEN */ 5657 5658 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) 5659 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) 5660 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) 5661 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) 5662 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) 5663 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) 5664 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) 5665 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) 5666 #if defined(GPIOI) 5667 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) 5668 #endif /* GPIOI */ 5669 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) 5670 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) 5671 #if defined(RCC_AHB4LPENR_CRCLPEN) 5672 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) 5673 #endif 5674 #if defined(BDMA2) 5675 #define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN) 5676 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/ 5677 #else 5678 #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) 5679 #endif /*BDMA2*/ 5680 #if defined(ADC3) 5681 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) 5682 #endif /*ADC3*/ 5683 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) 5684 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 5685 #define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN)) 5686 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE 5687 #else 5688 #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) 5689 #endif 5690 5691 5692 /** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. 5693 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5694 * power consumption. 5695 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5696 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5697 */ 5698 5699 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U) 5700 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U) 5701 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U) 5702 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U) 5703 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U) 5704 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) 5705 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) 5706 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) 5707 #if defined(GPIOI) 5708 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) 5709 #endif /* GPIOI */ 5710 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) 5711 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) 5712 #if defined(RCC_AHB4LPENR_CRCLPEN) 5713 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) 5714 #endif 5715 #if defined(BDMA2) 5716 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U) 5717 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ 5718 #else 5719 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) 5720 #endif /*BDMA2*/ 5721 #if defined(ADC3) 5722 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) 5723 #endif /*ADC3*/ 5724 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) 5725 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 5726 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U) 5727 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ 5728 #else 5729 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) 5730 #endif 5731 5732 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) 5733 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) 5734 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U) 5735 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U) 5736 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U) 5737 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) 5738 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) 5739 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) 5740 #if defined(GPIOI) 5741 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) 5742 #endif /* GPIOI */ 5743 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) 5744 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) 5745 #if defined(RCC_AHB4LPENR_CRCLPEN) 5746 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) 5747 #endif 5748 #if defined(BDMA2) 5749 #define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U) 5750 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ 5751 #else 5752 #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) 5753 #endif /*BDMA2*/ 5754 #if defined(ADC3) 5755 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) 5756 #endif /*ADC3*/ 5757 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) 5758 #if defined(RCC_AHB4LPENR_SRDSRAMLPEN) 5759 #define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U) 5760 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ 5761 #else 5762 #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) 5763 #endif 5764 5765 5766 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. 5767 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5768 * power consumption. 5769 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 5770 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 5771 */ 5772 5773 #if defined(LTDC) 5774 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) 5775 #endif /* LTDC */ 5776 #if defined(DSI) 5777 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) 5778 #endif /*DSI*/ 5779 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) 5780 5781 #if defined(LTDC) 5782 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) 5783 #endif /* LTDC */ 5784 #if defined(DSI) 5785 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) 5786 #endif /*DSI*/ 5787 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) 5788 5789 5790 /** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode. 5791 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5792 * power consumption. 5793 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5794 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5795 */ 5796 5797 #if defined(LTDC) 5798 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) 5799 #endif /* LTDC */ 5800 #if defined(DSI) 5801 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U) 5802 #endif /*DSI*/ 5803 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U) 5804 5805 #if defined(LTDC) 5806 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) 5807 #endif /* LTDC */ 5808 #if defined(DSI) 5809 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U) 5810 #endif /*DSI*/ 5811 #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U) 5812 5813 5814 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. 5815 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5816 * power consumption. 5817 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 5818 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 5819 */ 5820 5821 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) 5822 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) 5823 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) 5824 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) 5825 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) 5826 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) 5827 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) 5828 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) 5829 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) 5830 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) 5831 5832 #if defined(DUAL_CORE) 5833 #define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) 5834 #endif /*DUAL_CORE*/ 5835 5836 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) 5837 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) 5838 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) 5839 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) 5840 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) 5841 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) 5842 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) 5843 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) 5844 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) 5845 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) 5846 #if defined(I2C5) 5847 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN) 5848 #endif /* I2C5 */ 5849 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) 5850 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) 5851 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) 5852 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) 5853 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) 5854 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) 5855 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) 5856 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) 5857 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) 5858 #if defined(TIM23) 5859 #define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN) 5860 #endif /* TIM23 */ 5861 #if defined(TIM24) 5862 #define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN) 5863 #endif /* TIM24 */ 5864 5865 5866 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) 5867 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) 5868 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) 5869 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) 5870 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) 5871 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) 5872 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) 5873 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) 5874 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) 5875 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) 5876 5877 #if defined(DUAL_CORE) 5878 #define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) 5879 #endif /*DUAL_CORE*/ 5880 5881 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) 5882 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) 5883 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) 5884 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) 5885 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) 5886 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) 5887 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) 5888 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) 5889 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) 5890 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) 5891 #if defined(I2C5) 5892 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN) 5893 #endif /* I2C5 */ 5894 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) 5895 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) 5896 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) 5897 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) 5898 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) 5899 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) 5900 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) 5901 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) 5902 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) 5903 #if defined(TIM23) 5904 #define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN) 5905 #endif /* TIM23 */ 5906 #if defined(TIM24) 5907 #define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN) 5908 #endif /* TIM24 */ 5909 5910 5911 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. 5912 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5913 * power consumption. 5914 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5915 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5916 */ 5917 5918 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U) 5919 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U) 5920 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U) 5921 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U) 5922 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U) 5923 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U) 5924 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U) 5925 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U) 5926 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U) 5927 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U) 5928 #if defined(DUAL_CORE) 5929 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U) 5930 #endif /*DUAL_CORE*/ 5931 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U) 5932 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U) 5933 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U) 5934 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U) 5935 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U) 5936 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U) 5937 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U) 5938 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) 5939 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) 5940 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) 5941 #if defined(I2C5) 5942 #define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U) 5943 #endif /* I2C5 */ 5944 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) 5945 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) 5946 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) 5947 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U) 5948 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U) 5949 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U) 5950 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) 5951 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) 5952 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) 5953 #if defined(TIM23) 5954 #define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U) 5955 #endif /* TIM23 */ 5956 #if defined(TIM24) 5957 #define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U) 5958 #endif /* TIM24 */ 5959 5960 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) 5961 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) 5962 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U) 5963 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U) 5964 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U) 5965 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U) 5966 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U) 5967 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U) 5968 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U) 5969 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U) 5970 #if defined(DUAL_CORE) 5971 #define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U) 5972 #endif /*DUAL_CORE*/ 5973 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U) 5974 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U) 5975 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U) 5976 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U) 5977 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U) 5978 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U) 5979 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U) 5980 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) 5981 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) 5982 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) 5983 #if defined(I2C5) 5984 #define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U) 5985 #endif /* I2C5 */ 5986 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) 5987 #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) 5988 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) 5989 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U) 5990 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U) 5991 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U) 5992 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) 5993 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) 5994 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) 5995 #if defined(TIM23) 5996 #define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U) 5997 #endif /* TIM23 */ 5998 #if defined(TIM24) 5999 #define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U) 6000 #endif /* TIM24 */ 6001 6002 6003 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. 6004 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6005 * power consumption. 6006 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6007 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6008 */ 6009 6010 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) 6011 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) 6012 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) 6013 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) 6014 #if defined(UART9) 6015 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN) 6016 #endif /*UART9*/ 6017 #if defined(USART10) 6018 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN) 6019 #endif /*USART10*/ 6020 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) 6021 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) 6022 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) 6023 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) 6024 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) 6025 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) 6026 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) 6027 #if defined(SAI2) 6028 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) 6029 #endif /* SAI2 */ 6030 #if defined(SAI3) 6031 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) 6032 #endif /*SAI3*/ 6033 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) 6034 #if defined(HRTIM1) 6035 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) 6036 #endif /*HRTIM1*/ 6037 6038 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) 6039 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) 6040 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) 6041 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) 6042 #if defined(UART9) 6043 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN) 6044 #endif /*UART9*/ 6045 #if defined(USART10) 6046 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN) 6047 #endif /*USART10*/ 6048 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) 6049 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) 6050 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) 6051 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) 6052 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) 6053 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) 6054 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) 6055 #if defined(SAI2) 6056 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) 6057 #endif /* SAI2 */ 6058 #if defined(SAI3) 6059 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) 6060 #endif /*SAI3*/ 6061 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) 6062 #if defined(HRTIM1) 6063 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) 6064 #endif /*HRTIM1*/ 6065 6066 6067 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. 6068 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6069 * power consumption. 6070 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 6071 * @note By default, all peripheral clocks are enabled during SLEEP mode. 6072 */ 6073 6074 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U) 6075 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) 6076 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) 6077 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) 6078 #if defined(UART9) 6079 #define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U) 6080 #endif /*UART9*/ 6081 #if defined(USART10) 6082 #define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U) 6083 #endif /*USART10*/ 6084 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) 6085 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) 6086 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) 6087 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U) 6088 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) 6089 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) 6090 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) 6091 #if defined(SAI2) 6092 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) 6093 #endif /* SAI2 */ 6094 #if defined(SAI3) 6095 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) 6096 #endif /*SAI3*/ 6097 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) 6098 #if defined(HRTIM1) 6099 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) 6100 #endif /*HRTIM1*/ 6101 6102 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) 6103 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) 6104 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) 6105 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) 6106 #if defined(UART9) 6107 #define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U) 6108 #endif /*UART9*/ 6109 #if defined(USART10) 6110 #define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U) 6111 #endif /*USART10*/ 6112 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) 6113 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) 6114 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) 6115 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U) 6116 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) 6117 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) 6118 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) 6119 #if defined(SAI2) 6120 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) 6121 #endif /* SAI2 */ 6122 #if defined(SAI3) 6123 #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) 6124 #endif /*SAI3*/ 6125 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) 6126 #if defined(HRTIM1) 6127 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) 6128 #endif /*HRTIM1*/ 6129 6130 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. 6131 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6132 * power consumption. 6133 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6134 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6135 */ 6136 6137 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) 6138 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) 6139 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) 6140 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) 6141 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) 6142 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) 6143 #if defined(LPTIM4) 6144 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) 6145 #endif /*LPTIM4*/ 6146 #if defined(LPTIM5) 6147 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) 6148 #endif /*LPTIM5*/ 6149 #if defined(DAC2) 6150 #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN) 6151 #endif /*DAC2*/ 6152 #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) 6153 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) 6154 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) 6155 #if defined(SAI4) 6156 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) 6157 #endif /*SAI4*/ 6158 #if defined(DTS) 6159 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN) 6160 #endif /*DTS*/ 6161 #if defined(DFSDM2_BASE) 6162 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN) 6163 #endif /*DFSDM2*/ 6164 6165 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) 6166 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) 6167 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) 6168 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) 6169 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) 6170 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) 6171 #if defined(LPTIM4) 6172 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) 6173 #endif /*LPTIM4*/ 6174 #if defined(LPTIM5) 6175 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) 6176 #endif /*LPTIM5*/ 6177 #if defined(DAC2) 6178 #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN) 6179 #endif /*DAC2*/ 6180 #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) 6181 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) 6182 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) 6183 #if defined(SAI4) 6184 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) 6185 #endif /*SAI4*/ 6186 #if defined(DTS) 6187 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN) 6188 #endif /*DTS*/ 6189 #if defined(DFSDM2_BASE) 6190 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN) 6191 #endif /*DFSDM2*/ 6192 6193 6194 /** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. 6195 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6196 * power consumption. 6197 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 6198 * @note By default, all peripheral clocks are enabled during SLEEP mode. 6199 */ 6200 6201 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U) 6202 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U) 6203 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U) 6204 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) 6205 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) 6206 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) 6207 #if defined(LPTIM4) 6208 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) 6209 #endif /*LPTIM4*/ 6210 #if defined(LPTIM5) 6211 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) 6212 #endif /*LPTIM5*/ 6213 #if defined(DAC2) 6214 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U) 6215 #endif /*DAC2*/ 6216 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) 6217 #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) 6218 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) 6219 #if defined(SAI4) 6220 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) 6221 #endif /*SAI4*/ 6222 #if defined(DTS) 6223 #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U) 6224 #endif /*DTS*/ 6225 #if defined(DFSDM2_BASE) 6226 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U) 6227 #endif /*DFSDM2*/ 6228 6229 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) 6230 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) 6231 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U) 6232 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) 6233 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) 6234 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) 6235 #if defined(LPTIM4) 6236 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) 6237 #endif /*LPTIM4*/ 6238 #if defined(LPTIM5) 6239 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) 6240 #endif /*LPTIM5*/ 6241 #if defined(DAC2) 6242 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U) 6243 #endif /*DAC2*/ 6244 #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) 6245 #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) 6246 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) 6247 #if defined(SAI4) 6248 #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) 6249 #endif /*SAI4*/ 6250 #if defined(DTS) 6251 #define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U) 6252 #endif /*DTS*/ 6253 #if defined(DFSDM2_BASE) 6254 #define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U) 6255 #endif /*DFSDM2*/ 6256 6257 6258 #if defined(DUAL_CORE) 6259 6260 /** @brief Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode. 6261 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6262 * power consumption. 6263 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 6264 * @note By default, all peripheral clocks are enabled during SLEEP mode. 6265 */ 6266 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) 6267 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) 6268 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) 6269 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) 6270 #define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 6271 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 6272 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) 6273 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) 6274 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) 6275 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) 6276 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) 6277 6278 6279 #define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) 6280 #define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) 6281 #define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) 6282 #define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) 6283 #define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) 6284 #define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) 6285 #define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) 6286 #define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) 6287 #define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) 6288 #define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) 6289 #define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) 6290 6291 6292 6293 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 6294 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6295 * power consumption. 6296 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6297 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6298 */ 6299 6300 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 6301 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 6302 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) 6303 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) 6304 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) 6305 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) 6306 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) 6307 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 6308 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) 6309 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 6310 6311 #define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) 6312 #define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) 6313 #define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) 6314 #define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) 6315 #define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) 6316 #define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) 6317 #define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) 6318 #define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 6319 #define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) 6320 #define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 6321 6322 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 6323 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6324 * power consumption. 6325 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6326 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6327 */ 6328 6329 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 6330 #if defined(CRYP) 6331 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 6332 #endif /* CRYP */ 6333 #if defined(HASH) 6334 #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 6335 #endif /* HASH */ 6336 #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 6337 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) 6338 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) 6339 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) 6340 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) 6341 6342 #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) 6343 #if defined(CRYP) 6344 #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) 6345 #endif /* CRYP */ 6346 #if defined(HASH) 6347 #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) 6348 #endif /* HASH */ 6349 #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) 6350 #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) 6351 #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) 6352 #define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) 6353 #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) 6354 6355 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 6356 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6357 * power consumption. 6358 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6359 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6360 */ 6361 6362 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) 6363 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) 6364 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) 6365 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) 6366 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) 6367 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) 6368 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) 6369 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) 6370 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) 6371 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) 6372 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) 6373 #define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) 6374 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) 6375 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) 6376 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) 6377 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) 6378 6379 #define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) 6380 #define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) 6381 #define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) 6382 #define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) 6383 #define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) 6384 #define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) 6385 #define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) 6386 #define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) 6387 #define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) 6388 #define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) 6389 #define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) 6390 #define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) 6391 #define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) 6392 #define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) 6393 #define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) 6394 #define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) 6395 6396 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. 6397 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6398 * power consumption. 6399 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6400 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6401 */ 6402 6403 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) 6404 #define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) 6405 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) 6406 6407 #define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) 6408 #define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) 6409 #define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) 6410 6411 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. 6412 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6413 * power consumption. 6414 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6415 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6416 */ 6417 6418 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) 6419 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) 6420 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) 6421 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) 6422 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) 6423 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) 6424 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) 6425 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) 6426 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) 6427 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) 6428 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) 6429 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) 6430 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) 6431 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) 6432 #define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) 6433 #define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) 6434 #define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) 6435 #define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) 6436 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) 6437 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) 6438 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) 6439 #define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) 6440 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) 6441 #define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) 6442 #define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) 6443 #define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) 6444 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) 6445 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) 6446 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) 6447 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) 6448 6449 6450 #define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) 6451 #define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) 6452 #define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) 6453 #define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) 6454 #define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) 6455 #define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) 6456 #define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) 6457 #define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) 6458 #define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) 6459 #define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) 6460 #define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) 6461 #define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) 6462 #define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) 6463 #define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) 6464 #define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) 6465 #define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) 6466 #define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) 6467 #define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) 6468 #define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) 6469 #define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) 6470 #define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) 6471 #define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) 6472 #define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) 6473 #define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) 6474 #define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) 6475 #define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) 6476 #define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) 6477 #define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) 6478 #define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) 6479 #define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) 6480 6481 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. 6482 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6483 * power consumption. 6484 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6485 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6486 */ 6487 6488 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) 6489 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) 6490 #define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) 6491 #define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) 6492 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) 6493 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) 6494 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) 6495 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) 6496 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) 6497 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) 6498 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) 6499 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) 6500 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) 6501 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) 6502 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) 6503 6504 #define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) 6505 #define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) 6506 #define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) 6507 #define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) 6508 #define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) 6509 #define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) 6510 #define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) 6511 #define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) 6512 #define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) 6513 #define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) 6514 #define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) 6515 #define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) 6516 #define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) 6517 #define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) 6518 #define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) 6519 6520 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. 6521 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6522 * power consumption. 6523 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6524 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6525 */ 6526 6527 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) 6528 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) 6529 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) 6530 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) 6531 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) 6532 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) 6533 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) 6534 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) 6535 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) 6536 #define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) 6537 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) 6538 #define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) 6539 6540 6541 #define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) 6542 #define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) 6543 #define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) 6544 #define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) 6545 #define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) 6546 #define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) 6547 #define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) 6548 #define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) 6549 #define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) 6550 #define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) 6551 #define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) 6552 #define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) 6553 6554 /** @brief Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode. 6555 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6556 * power consumption. 6557 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 6558 * @note By default, all peripheral clocks are enabled during SLEEP mode. 6559 */ 6560 6561 6562 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) 6563 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) 6564 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) 6565 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) 6566 #define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 6567 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 6568 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) 6569 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) 6570 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) 6571 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) 6572 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) 6573 6574 6575 #define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) 6576 #define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) 6577 #define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) 6578 #define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) 6579 #define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) 6580 #define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) 6581 #define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) 6582 #define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) 6583 #define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) 6584 #define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) 6585 #define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) 6586 6587 6588 6589 /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 6590 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6591 * power consumption. 6592 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6593 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6594 */ 6595 6596 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 6597 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 6598 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) 6599 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) 6600 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) 6601 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) 6602 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) 6603 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 6604 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) 6605 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 6606 6607 #define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) 6608 #define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) 6609 #define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) 6610 #define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) 6611 #define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) 6612 #define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) 6613 #define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) 6614 #define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) 6615 #define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) 6616 #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) 6617 6618 /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 6619 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6620 * power consumption. 6621 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6622 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6623 */ 6624 6625 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 6626 #if defined(CRYP) 6627 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 6628 #endif /* CRYP */ 6629 #if defined(HASH) 6630 #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 6631 #endif /* HASH */ 6632 #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 6633 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) 6634 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) 6635 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) 6636 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) 6637 6638 #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) 6639 #if defined(CRYP) 6640 #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) 6641 #endif /* CRYP */ 6642 #if defined(HASH) 6643 #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) 6644 #endif /* HASH */ 6645 #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) 6646 #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) 6647 #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) 6648 #define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) 6649 #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) 6650 6651 /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 6652 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6653 * power consumption. 6654 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6655 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6656 */ 6657 6658 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) 6659 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) 6660 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) 6661 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) 6662 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) 6663 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) 6664 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) 6665 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) 6666 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) 6667 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) 6668 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) 6669 #define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) 6670 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) 6671 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) 6672 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) 6673 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) 6674 6675 #define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) 6676 #define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) 6677 #define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) 6678 #define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) 6679 #define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) 6680 #define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) 6681 #define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) 6682 #define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) 6683 #define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) 6684 #define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) 6685 #define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) 6686 #define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) 6687 #define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) 6688 #define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) 6689 #define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) 6690 #define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) 6691 6692 /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. 6693 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6694 * power consumption. 6695 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6696 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6697 */ 6698 6699 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) 6700 #define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) 6701 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) 6702 6703 #define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) 6704 #define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) 6705 #define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) 6706 6707 /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. 6708 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6709 * power consumption. 6710 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6711 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6712 */ 6713 6714 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) 6715 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) 6716 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) 6717 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) 6718 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) 6719 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) 6720 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) 6721 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) 6722 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) 6723 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) 6724 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) 6725 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) 6726 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) 6727 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) 6728 #define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) 6729 #define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) 6730 #define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) 6731 #define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) 6732 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) 6733 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) 6734 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) 6735 #define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) 6736 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) 6737 #define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) 6738 #define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) 6739 #define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) 6740 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) 6741 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) 6742 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) 6743 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) 6744 6745 6746 #define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) 6747 #define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) 6748 #define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) 6749 #define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) 6750 #define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) 6751 #define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) 6752 #define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) 6753 #define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) 6754 #define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) 6755 #define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) 6756 #define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) 6757 #define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) 6758 #define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) 6759 #define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) 6760 #define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) 6761 #define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) 6762 #define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) 6763 #define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) 6764 #define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) 6765 #define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) 6766 #define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) 6767 #define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) 6768 #define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) 6769 #define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) 6770 #define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) 6771 #define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) 6772 #define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) 6773 #define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) 6774 #define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) 6775 #define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) 6776 6777 /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. 6778 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6779 * power consumption. 6780 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6781 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6782 */ 6783 6784 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) 6785 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) 6786 #define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) 6787 #define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) 6788 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) 6789 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) 6790 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) 6791 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) 6792 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) 6793 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) 6794 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) 6795 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) 6796 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) 6797 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) 6798 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) 6799 6800 #define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) 6801 #define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) 6802 #define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) 6803 #define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) 6804 #define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) 6805 #define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) 6806 #define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) 6807 #define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) 6808 #define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) 6809 #define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) 6810 #define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) 6811 #define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) 6812 #define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) 6813 #define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) 6814 #define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) 6815 6816 /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. 6817 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 6818 * power consumption. 6819 * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. 6820 * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. 6821 */ 6822 6823 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) 6824 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) 6825 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) 6826 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) 6827 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) 6828 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) 6829 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) 6830 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) 6831 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) 6832 #define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) 6833 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) 6834 #define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) 6835 6836 #define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) 6837 #define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) 6838 #define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) 6839 #define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) 6840 #define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) 6841 #define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) 6842 #define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) 6843 #define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) 6844 #define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) 6845 #define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) 6846 #define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) 6847 #define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) 6848 6849 #endif /*DUAL_CORE*/ 6850 6851 #if defined(DUAL_CORE) 6852 /** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN 6853 * @note After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP 6854 */ 6855 #else 6856 /** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN 6857 * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP 6858 */ 6859 #endif /*DUAL_CORE*/ 6860 6861 #if defined(RCC_D3AMR_BDMAAMEN) 6862 #define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) 6863 #endif 6864 #if defined(RCC_D3AMR_LPUART1AMEN) 6865 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) 6866 #endif 6867 #if defined(RCC_D3AMR_SPI6AMEN) 6868 #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) 6869 #endif 6870 #if defined(RCC_D3AMR_I2C4AMEN) 6871 #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) 6872 #endif 6873 #if defined(RCC_D3AMR_LPTIM2AMEN) 6874 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) 6875 #endif 6876 #if defined(RCC_D3AMR_LPTIM3AMEN) 6877 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) 6878 #endif 6879 #if defined(LPTIM4) 6880 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) 6881 #endif 6882 #if defined(LPTIM5) 6883 #define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) 6884 #endif 6885 #if defined(RCC_D3AMR_COMP12AMEN) 6886 #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) 6887 #endif 6888 #if defined(RCC_D3AMR_VREFAMEN) 6889 #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) 6890 #endif 6891 #if defined(RCC_D3AMR_RTCAMEN) 6892 #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) 6893 #endif 6894 #if defined(RCC_D3AMR_CRCAMEN) 6895 #define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) 6896 #endif 6897 #if defined(SAI4) 6898 #define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) 6899 #endif 6900 #if defined(ADC3) 6901 #define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) 6902 #endif 6903 #if defined(RCC_D3AMR_DTSAMEN) 6904 #define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN) 6905 #endif 6906 #if defined(RCC_D3AMR_BKPRAMAMEN) 6907 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) 6908 #endif 6909 #if defined(RCC_D3AMR_SRAM4AMEN) 6910 #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) 6911 #endif 6912 6913 #if defined(BDMA2) 6914 #define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN) 6915 #endif 6916 #if defined(RCC_SRDAMR_GPIOAMEN) 6917 #define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN) 6918 #endif 6919 #if defined(RCC_SRDAMR_LPUART1AMEN) 6920 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN) 6921 #endif 6922 #if defined(RCC_SRDAMR_SPI6AMEN) 6923 #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN) 6924 #endif 6925 #if defined(RCC_SRDAMR_I2C4AMEN) 6926 #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN) 6927 #endif 6928 #if defined(RCC_SRDAMR_LPTIM2AMEN) 6929 #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN) 6930 #endif 6931 #if defined(RCC_SRDAMR_LPTIM3AMEN) 6932 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN) 6933 #endif 6934 #if defined(DAC2) 6935 #define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN) 6936 #endif 6937 #if defined(RCC_SRDAMR_COMP12AMEN) 6938 #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN) 6939 #endif 6940 #if defined(RCC_SRDAMR_VREFAMEN) 6941 #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN) 6942 #endif 6943 #if defined(RCC_SRDAMR_RTCAMEN) 6944 #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN) 6945 #endif 6946 #if defined(RCC_SRDAMR_DTSAMEN) 6947 #define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN) 6948 #endif 6949 #if defined(DFSDM2_BASE) 6950 #define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN) 6951 #endif 6952 #if defined(RCC_SRDAMR_BKPRAMAMEN) 6953 #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN) 6954 #endif 6955 #if defined(RCC_SRDAMR_SRDSRAMAMEN) 6956 #define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN) 6957 #endif 6958 6959 #if defined(RCC_D3AMR_BDMAAMEN) 6960 #define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) 6961 #endif 6962 #if defined(RCC_D3AMR_LPUART1AMEN) 6963 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) 6964 #endif 6965 #if defined(RCC_D3AMR_SPI6AMEN) 6966 #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) 6967 #endif 6968 #if defined(RCC_D3AMR_I2C4AMEN) 6969 #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) 6970 #endif 6971 #if defined(RCC_D3AMR_LPTIM2AMEN) 6972 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) 6973 #endif 6974 #if defined(RCC_D3AMR_LPTIM3AMEN) 6975 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) 6976 #endif 6977 #if defined(LPTIM4) 6978 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) 6979 #endif 6980 #if defined(LPTIM5) 6981 #define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) 6982 #endif 6983 #if defined(RCC_D3AMR_COMP12AMEN) 6984 #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) 6985 #endif 6986 #if defined(RCC_D3AMR_VREFAMEN) 6987 #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) 6988 #endif 6989 #if defined(RCC_D3AMR_RTCAMEN) 6990 #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN) 6991 #endif 6992 #if defined(RCC_D3AMR_CRCAMEN) 6993 #define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN) 6994 #endif 6995 #if defined(SAI4) 6996 #define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN) 6997 #endif 6998 #if defined(ADC3) 6999 #define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN) 7000 #endif 7001 #if defined(RCC_D3AMR_DTSAMEN) 7002 #define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN) 7003 #endif 7004 #if defined(RCC_D3AMR_BKPRAMAMEN) 7005 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) 7006 #endif 7007 #if defined(RCC_D3AMR_SRAM4AMEN) 7008 #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) 7009 #endif 7010 7011 #if defined(BDMA2) 7012 #define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN) 7013 #endif 7014 #if defined(RCC_SRDAMR_GPIOAMEN) 7015 #define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN) 7016 #endif 7017 #if defined(RCC_SRDAMR_LPUART1AMEN) 7018 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN) 7019 #endif 7020 #if defined(RCC_SRDAMR_SPI6AMEN) 7021 #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN) 7022 #endif 7023 #if defined(RCC_SRDAMR_I2C4AMEN) 7024 #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN) 7025 #endif 7026 #if defined(RCC_SRDAMR_LPTIM2AMEN) 7027 #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN) 7028 #endif 7029 #if defined(RCC_SRDAMR_LPTIM3AMEN) 7030 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN) 7031 #endif 7032 #if defined(RCC_SRDAMR_DAC2AMEN) 7033 #define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN) 7034 #endif 7035 #if defined(RCC_SRDAMR_COMP12AMEN) 7036 #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN) 7037 #endif 7038 #if defined(RCC_SRDAMR_VREFAMEN) 7039 #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN) 7040 #endif 7041 #if defined(RCC_SRDAMR_RTCAMEN) 7042 #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN) 7043 #endif 7044 #if defined(RCC_SRDAMR_DTSAMEN) 7045 #define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN) 7046 #endif 7047 #if defined(DFSDM2_BASE) 7048 #define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN) 7049 #endif 7050 #if defined(RCC_SRDAMR_BKPRAMAMEN) 7051 #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN) 7052 #endif 7053 #if defined(RCC_SRDAMR_SRDSRAMAMEN) 7054 #define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN) 7055 #endif 7056 7057 7058 #if defined(RCC_CKGAENR_AXICKG) 7059 /** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register). 7060 */ 7061 7062 #define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG) 7063 #define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG) 7064 #define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG) 7065 #define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG) 7066 #define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG) 7067 #define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG) 7068 #define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG) 7069 #define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG) 7070 #define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG) 7071 #define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG) 7072 #define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG) 7073 #define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG) 7074 #define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG) 7075 #define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG) 7076 #define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG) 7077 #define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG) 7078 #define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG) 7079 #define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG) 7080 #define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG) 7081 #define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG) 7082 #define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG) 7083 7084 7085 #define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG) 7086 #define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG) 7087 #define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG) 7088 #define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG) 7089 #define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG) 7090 #define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG) 7091 #define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG) 7092 #define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG) 7093 #define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG) 7094 #define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG) 7095 #define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG) 7096 #define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG) 7097 #define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG) 7098 #define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG) 7099 #define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG) 7100 #define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG) 7101 #define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG) 7102 #define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG) 7103 #define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG) 7104 #define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG) 7105 #define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG) 7106 7107 #endif /* RCC_CKGAENR_AXICKG */ 7108 7109 7110 7111 7112 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). 7113 * @note After enabling the HSI, the application software should wait on 7114 * HSIRDY flag to be set indicating that HSI clock is stable and can 7115 * be used to clock the PLL and/or system clock. 7116 * @note HSI can not be stopped if it is used directly or through the PLL 7117 * as system clock. In this case, you have to select another source 7118 * of the system clock then stop the HSI. 7119 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 7120 * @param __STATE__ specifies the new state of the HSI. 7121 * This parameter can be one of the following values: 7122 * @arg RCC_HSI_OFF turn OFF the HSI oscillator 7123 * @arg RCC_HSI_ON turn ON the HSI oscillator 7124 * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset) 7125 * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 7126 * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 7127 * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 7128 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 7129 * clock cycles. 7130 */ 7131 #define __HAL_RCC_HSI_CONFIG(__STATE__) \ 7132 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) 7133 7134 7135 /** @brief Macro to get the HSI divider. 7136 * @retval The HSI divider. The returned value can be one 7137 * of the following: 7138 * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) 7139 * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 7140 * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 7141 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 7142 */ 7143 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 7144 7145 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 7146 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 7147 * It is used (enabled by hardware) as system clock source after start-up 7148 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 7149 * of the HSE used directly or indirectly as system clock (if the Clock 7150 * Security System CSS is enabled). 7151 * @note HSI can not be stopped if it is used as system clock source. In this case, 7152 * you have to select another source of the system clock then stop the HSI. 7153 * @note After enabling the HSI, the application software should wait on HSIRDY 7154 * flag to be set indicating that HSI clock is stable and can be used as 7155 * system clock source. 7156 * This parameter can be: ENABLE or DISABLE. 7157 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 7158 * clock cycles. 7159 */ 7160 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 7161 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 7162 7163 7164 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 7165 * @note The calibration is used to compensate for the variations in voltage 7166 * and temperature that influence the frequency of the internal HSI RC. 7167 * @param __HSICalibrationValue__: specifies the calibration trimming value. 7168 * This parameter must be a number between 0 and 0x7F (3F for Rev Y device). 7169 */ 7170 #if defined(RCC_VER_X) 7171 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ 7172 do { \ 7173 if(HAL_GetREVID() <= REV_ID_Y) \ 7174 { \ 7175 if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \ 7176 { \ 7177 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \ 7178 } \ 7179 else \ 7180 { \ 7181 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \ 7182 } \ 7183 } \ 7184 else \ 7185 { \ 7186 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \ 7187 } \ 7188 } while(0) 7189 7190 #else 7191 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ 7192 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); 7193 #endif /*RCC_VER_X*/ 7194 /** 7195 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 7196 * in STOP mode to be quickly available as kernel clock for some peripherals. 7197 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 7198 * speed because of the HSI start-up time. 7199 * @note The enable of this function has not effect on the HSION bit. 7200 * This parameter can be: ENABLE or DISABLE. 7201 * @retval None 7202 */ 7203 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 7204 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 7205 7206 7207 /** 7208 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). 7209 * @note After enabling the HSI48, the application software should wait on 7210 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can 7211 * be used to clock the USB. 7212 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 7213 */ 7214 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); 7215 7216 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); 7217 7218 /** 7219 * @brief Macros to enable or disable the Internal oscillator (CSI). 7220 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 7221 * It is used (enabled by hardware) as system clock source after 7222 * start-up from Reset, wakeup from STOP and STANDBY mode, or in case 7223 * of failure of the HSE used directly or indirectly as system clock 7224 * (if the Clock Security System CSS is enabled). 7225 * @note CSI can not be stopped if it is used as system clock source. 7226 * In this case, you have to select another source of the system 7227 * clock then stop the CSI. 7228 * @note After enabling the CSI, the application software should wait on 7229 * CSIRDY flag to be set indicating that CSI clock is stable and can 7230 * be used as system clock source. 7231 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 7232 * clock cycles. 7233 */ 7234 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) 7235 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) 7236 7237 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. 7238 * @note The calibration is used to compensate for the variations in voltage 7239 * and temperature that influence the frequency of the internal CSI RC. 7240 * @param __CSICalibrationValue__: specifies the calibration trimming value. 7241 * This parameter must be a number between 0 and 0x1F. 7242 */ 7243 #if defined(RCC_VER_X) 7244 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 7245 do { \ 7246 if(HAL_GetREVID() <= REV_ID_Y) \ 7247 { \ 7248 if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \ 7249 { \ 7250 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \ 7251 } \ 7252 else \ 7253 { \ 7254 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \ 7255 } \ 7256 } \ 7257 else \ 7258 { \ 7259 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ 7260 } \ 7261 } while(0) 7262 7263 #else 7264 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 7265 do { \ 7266 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ 7267 } while(0) 7268 7269 #endif /*RCC_VER_X*/ 7270 /** 7271 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) 7272 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 7273 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 7274 * speed because of the CSI start-up time. 7275 * @note The enable of this function has not effect on the CSION bit. 7276 * This parameter can be: ENABLE or DISABLE. 7277 * @retval None 7278 */ 7279 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) 7280 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) 7281 7282 7283 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 7284 * @note After enabling the LSI, the application software should wait on 7285 * LSIRDY flag to be set indicating that LSI clock is stable and can 7286 * be used to clock the IWDG and/or the RTC. 7287 * @note LSI can not be disabled if the IWDG is running. 7288 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 7289 * clock cycles. 7290 */ 7291 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 7292 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 7293 7294 /** 7295 * @brief Macro to configure the External High Speed oscillator (__HSE__). 7296 * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), 7297 * the application software should wait on HSERDY flag to be set indicating 7298 * that HSE clock is stable and can be used to clock the PLL and/or system clock. 7299 * @note HSE state can not be changed if it is used directly or through the 7300 * PLL as system clock. In this case, you have to select another source 7301 * of the system clock then change the HSE state (ex. disable it). 7302 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 7303 * @note This function reset the CSSON bit, so if the clock security system(CSS) 7304 * was previously enabled you have to enable it again after calling this 7305 * function. 7306 * @param __STATE__: specifies the new state of the HSE. 7307 * This parameter can be one of the following values: 7308 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 7309 * 6 HSE oscillator clock cycles. 7310 * @arg RCC_HSE_ON: turn ON the HSE oscillator. 7311 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. 7312 * @arg RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*) 7313 * 7314 * (*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 7315 */ 7316 #if defined(RCC_CR_HSEEXT) 7317 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 7318 do { \ 7319 if ((__STATE__) == RCC_HSE_ON) \ 7320 { \ 7321 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 7322 } \ 7323 else if ((__STATE__) == RCC_HSE_OFF) \ 7324 { \ 7325 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 7326 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 7327 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 7328 } \ 7329 else if ((__STATE__) == RCC_HSE_BYPASS) \ 7330 { \ 7331 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 7332 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 7333 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 7334 } \ 7335 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 7336 { \ 7337 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 7338 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 7339 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 7340 } \ 7341 else \ 7342 { \ 7343 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 7344 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 7345 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 7346 } \ 7347 } while(0) 7348 #else 7349 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 7350 do { \ 7351 if ((__STATE__) == RCC_HSE_ON) \ 7352 { \ 7353 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 7354 } \ 7355 else if ((__STATE__) == RCC_HSE_OFF) \ 7356 { \ 7357 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 7358 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 7359 } \ 7360 else if ((__STATE__) == RCC_HSE_BYPASS) \ 7361 { \ 7362 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 7363 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 7364 } \ 7365 else \ 7366 { \ 7367 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 7368 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 7369 } \ 7370 } while(0) 7371 #endif /* RCC_CR_HSEEXT */ 7372 7373 /** @defgroup RCC_LSE_Configuration LSE Configuration 7374 * @{ 7375 */ 7376 7377 /** 7378 * @brief Macro to configure the External Low Speed oscillator (LSE). 7379 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 7380 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 7381 * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). 7382 A duty cycle close to 50% is recommended. 7383 * @note As the LSE is in the Backup domain and write access is denied to 7384 * this domain after reset, you have to enable write access using 7385 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 7386 * (to be done once after reset). 7387 * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application 7388 * software should wait on LSERDY flag to be set indicating that LSE clock 7389 * is stable and can be used to clock the RTC. 7390 * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) 7391 * @param __STATE__: specifies the new state of the LSE. 7392 * This parameter can be one of the following values: 7393 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 7394 * 6 LSE oscillator clock cycles. 7395 * @arg RCC_LSE_ON: turn ON the LSE oscillator. 7396 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. 7397 * @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*) 7398 * 7399 * (*) Available on some STM32H7 lines only. 7400 */ 7401 #if defined(RCC_BDCR_LSEEXT) 7402 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 7403 do { \ 7404 if((__STATE__) == RCC_LSE_ON) \ 7405 { \ 7406 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7407 } \ 7408 else if((__STATE__) == RCC_LSE_OFF) \ 7409 { \ 7410 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7411 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 7412 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 7413 } \ 7414 else if((__STATE__) == RCC_LSE_BYPASS) \ 7415 { \ 7416 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 7417 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 7418 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7419 } \ 7420 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ 7421 { \ 7422 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 7423 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 7424 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7425 } \ 7426 else \ 7427 { \ 7428 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7429 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 7430 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 7431 } \ 7432 } while(0) 7433 #else 7434 7435 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 7436 do { \ 7437 if((__STATE__) == RCC_LSE_ON) \ 7438 { \ 7439 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7440 } \ 7441 else if((__STATE__) == RCC_LSE_OFF) \ 7442 { \ 7443 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7444 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 7445 } \ 7446 else if((__STATE__) == RCC_LSE_BYPASS) \ 7447 { \ 7448 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 7449 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7450 } \ 7451 else \ 7452 { \ 7453 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 7454 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 7455 } \ 7456 } while(0) 7457 7458 #endif /* RCC_BDCR_LSEEXT */ 7459 /** 7460 * @} 7461 */ 7462 7463 /** @brief Macros to enable or disable the the RTC clock. 7464 * @note These macros must be used only after the RTC clock source was selected. 7465 */ 7466 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 7467 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 7468 7469 /** @brief Macros to configure the RTC clock (RTCCLK). 7470 * @note As the RTC clock configuration bits are in the Backup domain and write 7471 * access is denied to this domain after reset, you have to enable write 7472 * access using the Power Backup Access macro before to configure 7473 * the RTC clock source (to be done once after reset). 7474 * @note Once the RTC clock is configured it can't be changed unless the 7475 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 7476 * a Power On Reset (POR). 7477 * @param __RTCCLKSource__: specifies the RTC clock source. 7478 * This parameter can be one of the following values: 7479 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 7480 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 7481 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected 7482 * as RTC clock, where x:[2,31] 7483 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 7484 * work in STOP and STANDBY modes, and can be used as wakeup source. 7485 * However, when the HSE clock is used as RTC clock source, the RTC 7486 * cannot be used in STOP and STANDBY modes. 7487 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 7488 * RTC clock source). 7489 */ 7490 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 7491 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) 7492 7493 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 7494 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 7495 } while (0) 7496 7497 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 7498 7499 7500 /** @brief Macros to force or release the Backup domain reset. 7501 * @note This function resets the RTC peripheral (including the backup registers) 7502 * and the RTC clock source selection in RCC_BDCR register. 7503 * @note The BKPSRAM is not affected by this reset. 7504 */ 7505 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 7506 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 7507 7508 /** @brief Macros to enable or disable the main PLL. 7509 * @note After enabling the main PLL, the application software should wait on 7510 * PLLRDY flag to be set indicating that PLL clock is stable and can 7511 * be used as system clock source. 7512 * @note The main PLL can not be disabled if it is used as system clock source 7513 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 7514 */ 7515 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 7516 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 7517 7518 /** 7519 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) 7520 * @note Enabling/disabling those Clocks can be done only when the PLL is disabled. 7521 * This is mainly used to save Power. 7522 * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock). 7523 * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted 7524 * This parameter can be one of the following values: 7525 * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 7526 * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 7527 * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) 7528 * 7529 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. 7530 * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. 7531 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. 7532 * 7533 * @retval None 7534 */ 7535 #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) 7536 7537 #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) 7538 7539 7540 /** 7541 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 7542 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 7543 * @retval None 7544 */ 7545 #define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) 7546 7547 #define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) 7548 7549 7550 /** 7551 * @brief Macro to configures the main PLL clock source, multiplication and division factors. 7552 * @note This function must be used only when the main PLL is disabled. 7553 * 7554 * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. 7555 * This parameter can be one of the following values: 7556 * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry 7557 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 7558 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 7559 * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . 7560 * 7561 * @param __PLLM1__: specifies the division factor for PLL VCO input clock 7562 * This parameter must be a number between 1 and 63. 7563 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 7564 * frequency ranges from 1 to 16 MHz. 7565 * 7566 * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock 7567 * This parameter must be a number between 4 and 512 or between 8 and 420(*). 7568 * @note You have to set the PLLN parameter correctly to ensure that the VCO 7569 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 7570 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 7571 * 7572 * @param __PLLP1__: specifies the division factor for system clock. 7573 * This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed) 7574 * 7575 * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks 7576 * This parameter must be a number between 1 and 128 7577 * 7578 * @param __PLLR1__: specifies the division factor for peripheral kernel clocks 7579 * This parameter must be a number between 1 and 128 7580 * 7581 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) 7582 * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 7583 * value to __PLL1P__, __PLL1Q__ or __PLL1R__ parameters. 7584 * @retval None 7585 * 7586 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 7587 * (**): For stm32h72xxx and stm32h73xxx family lines. 7588 */ 7589 7590 7591 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ 7592 do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \ 7593 WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \ 7594 ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \ 7595 } while(0) 7596 7597 7598 /** @brief Macro to configure the PLLs clock source. 7599 * @note This function must be used only when all PLLs are disabled. 7600 * @param __PLLSOURCE__: specifies the PLLs entry clock source. 7601 * This parameter can be one of the following values: 7602 * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry 7603 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 7604 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 7605 * 7606 */ 7607 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) 7608 7609 7610 /** 7611 * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor 7612 * 7613 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 7614 * 7615 * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 7616 * It should be a value between 0 and 8191 7617 * @note Warning: The software has to set correctly these bits to insure that the VCO 7618 * output frequency is between its valid frequency range, which is: 7619 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 7620 * 150 to 420 MHz if PLL1VCOSEL = 1. 7621 * 7622 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 7623 * 7624 * @retval None 7625 */ 7626 #define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) 7627 7628 7629 /** @brief Macro to select the PLL1 reference frequency range. 7630 * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range 7631 * This parameter can be one of the following values: 7632 * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz 7633 * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz 7634 * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz 7635 * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz 7636 * @retval None 7637 */ 7638 #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \ 7639 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__)) 7640 7641 7642 /** @brief Macro to select the PLL1 reference frequency range. 7643 * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range 7644 * This parameter can be one of the following values: 7645 * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 7646 * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz 7647 * 7648 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 7649 * 7650 * @retval None 7651 */ 7652 #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \ 7653 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) 7654 7655 7656 7657 /** @brief Macro to get the clock source used as system clock. 7658 * @retval The clock source used as system clock. The returned value can be one 7659 * of the following: 7660 * - RCC_CFGR_SWS_CSI: CSI used as system clock. 7661 * - RCC_CFGR_SWS_HSI: HSI used as system clock. 7662 * - RCC_CFGR_SWS_HSE: HSE used as system clock. 7663 * - RCC_CFGR_SWS_PLL: PLL used as system clock. 7664 */ 7665 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 7666 7667 7668 /** 7669 * @brief Macro to configure the system clock source. 7670 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. 7671 * This parameter can be one of the following values: 7672 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 7673 * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. 7674 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 7675 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 7676 */ 7677 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) 7678 7679 /** @brief Macro to get the oscillator used as PLL clock source. 7680 * @retval The oscillator used as PLL clock source. The returned value can be one 7681 * of the following: 7682 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 7683 * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source. 7684 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 7685 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 7686 */ 7687 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC)) 7688 7689 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 7690 * @{ 7691 */ 7692 7693 /** @brief Macro to configure the MCO1 clock. 7694 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 7695 * This parameter can be one of the following values: 7696 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 7697 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 7698 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 7699 * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source 7700 * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source 7701 * @param __MCODIV__ specifies the MCO clock prescaler. 7702 * This parameter can be one of the following values: 7703 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock 7704 */ 7705 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 7706 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 7707 7708 /** @brief Macro to configure the MCO2 clock. 7709 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 7710 * This parameter can be one of the following values: 7711 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 7712 * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source 7713 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 7714 * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source 7715 * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source 7716 * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source 7717 * @param __MCODIV__ specifies the MCO clock prescaler. 7718 * This parameter can be one of the following values: 7719 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock 7720 */ 7721 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 7722 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); 7723 7724 /** 7725 * @} 7726 */ 7727 7728 /** 7729 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 7730 * @note As the LSE is in the Backup domain and write access is denied to 7731 * this domain after reset, you have to enable write access using 7732 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 7733 * (to be done once after reset). 7734 * @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON. 7735 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 7736 * This parameter can be one of the following values: 7737 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. 7738 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. 7739 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. 7740 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. 7741 * @retval None 7742 */ 7743 #if defined(RCC_VER_X) 7744 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 7745 do{ \ 7746 if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \ 7747 { \ 7748 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \ 7749 } \ 7750 else \ 7751 { \ 7752 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \ 7753 } \ 7754 } while(0) 7755 #else 7756 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 7757 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); 7758 #endif /*RCC_VER_X*/ 7759 /** 7760 * @brief Macro to configure the wake up from stop clock. 7761 * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop 7762 * This parameter can be one of the following values: 7763 * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source 7764 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source 7765 * @retval None 7766 */ 7767 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \ 7768 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__)) 7769 7770 /** 7771 * @brief Macro to configure the Kernel wake up from stop clock. 7772 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 7773 * This parameter can be one of the following values: 7774 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source 7775 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 7776 * @retval None 7777 */ 7778 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 7779 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 7780 7781 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 7782 * @brief macros to manage the specified RCC Flags and interrupts. 7783 * @{ 7784 */ 7785 /** @brief Enable RCC interrupt. 7786 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 7787 * This parameter can be any combination of the following values: 7788 * @arg RCC_IT_LSIRDY: LSI ready interrupt 7789 * @arg RCC_IT_LSERDY: LSE ready interrupt 7790 * @arg RCC_IT_CSIRDY: HSI ready interrupt 7791 * @arg RCC_IT_HSIRDY: HSI ready interrupt 7792 * @arg RCC_IT_HSERDY: HSE ready interrupt 7793 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 7794 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 7795 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 7796 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 7797 * @arg RCC_IT_LSECSS: Clock security system interrupt 7798 */ 7799 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 7800 7801 /** @brief Disable RCC interrupt 7802 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 7803 * This parameter can be any combination of the following values: 7804 * @arg RCC_IT_LSIRDY: LSI ready interrupt 7805 * @arg RCC_IT_LSERDY: LSE ready interrupt 7806 * @arg RCC_IT_CSIRDY: HSI ready interrupt 7807 * @arg RCC_IT_HSIRDY: HSI ready interrupt 7808 * @arg RCC_IT_HSERDY: HSE ready interrupt 7809 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 7810 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 7811 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 7812 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 7813 * @arg RCC_IT_LSECSS: Clock security system interrupt 7814 */ 7815 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 7816 7817 /** @brief Clear the RCC's interrupt pending bits 7818 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 7819 * This parameter can be any combination of the following values: 7820 * @arg RCC_IT_LSIRDY: LSI ready interrupt 7821 * @arg RCC_IT_LSERDY: LSE ready interrupt 7822 * @arg RCC_IT_CSIRDY: CSI ready interrupt 7823 * @arg RCC_IT_HSIRDY: HSI ready interrupt 7824 * @arg RCC_IT_HSERDY: HSE ready interrupt 7825 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 7826 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 7827 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 7828 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 7829 * @arg RCC_IT_HSECSS: HSE Clock Security interrupt 7830 * @arg RCC_IT_LSECSS: Clock security system interrupt 7831 */ 7832 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 7833 7834 /** @brief Check the RCC's interrupt has occurred or not. 7835 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 7836 * This parameter can be any combination of the following values: 7837 * @arg RCC_IT_LSIRDY: LSI ready interrupt 7838 * @arg RCC_IT_LSERDY: LSE ready interrupt 7839 * @arg RCC_IT_CSIRDY: CSI ready interrupt 7840 * @arg RCC_IT_HSIRDY: HSI ready interrupt 7841 * @arg RCC_IT_HSERDY: HSE ready interrupt 7842 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt 7843 * @arg RCC_IT_PLLRDY: main PLL ready interrupt 7844 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 7845 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt 7846 * @arg RCC_IT_HSECSS: HSE Clock Security interrupt 7847 * @arg RCC_IT_LSECSS: Clock security system interrupt 7848 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 7849 */ 7850 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 7851 7852 /** @brief Set RMVF bit to clear the reset flags. 7853 */ 7854 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) 7855 7856 #if defined(DUAL_CORE) 7857 #define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF) 7858 7859 #define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF) 7860 #endif /*DUAL_CORE*/ 7861 7862 #if defined(DUAL_CORE) 7863 /** @brief Check RCC flag is set or not. 7864 * @param __FLAG__: specifies the flag to check. 7865 * This parameter can be one of the following values: 7866 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready 7867 * @arg RCC_FLAG_HSIDIV: HSI divider flag 7868 * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready 7869 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready 7870 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready 7871 * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready 7872 * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready 7873 * @arg RCC_FLAG_PLLRDY: PLL1 clock ready 7874 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready 7875 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready 7876 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready 7877 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready 7878 * @arg RCC_FLAG_C1RST: CPU reset flag 7879 * @arg RCC_FLAG_C2RST: CPU2 reset flag 7880 * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag 7881 * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag 7882 * @arg RCC_FLAG_BORRST: BOR reset flag 7883 * @arg RCC_FLAG_PINRST: Pin reset 7884 * @arg RCC_FLAG_PORRST: POR/PDR reset 7885 * @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag 7886 * @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag 7887 * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag 7888 * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset 7889 * @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset 7890 * @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset 7891 * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset 7892 * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag 7893 * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag 7894 * @retval The new state of __FLAG__ (TRUE or FALSE). 7895 */ 7896 #define RCC_FLAG_MASK ((uint8_t)0x1F) 7897 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 7898 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 7899 7900 #define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 7901 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 7902 7903 #define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 7904 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 7905 7906 #else 7907 7908 /** @brief Check RCC flag is set or not. 7909 * @param __FLAG__: specifies the flag to check. 7910 * This parameter can be one of the following values: 7911 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready 7912 * @arg RCC_FLAG_HSIDIV: HSI divider flag 7913 * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready 7914 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready 7915 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready 7916 * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready (*) 7917 * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready (*) 7918 * @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*) 7919 * @arg RCC_FLAG_CDCKRDY: CPU Domain clock ready (*) 7920 * @arg RCC_FLAG_PLLRDY: PLL1 clock ready 7921 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready 7922 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready 7923 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready 7924 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready 7925 * @arg RCC_FLAG_CPURST: CPU reset flag 7926 * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag (*) 7927 * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag (*) 7928 * @arg RCC_FLAG_CDRST: CD domain power switch reset flag (*) 7929 * @arg RCC_FLAG_BORRST: BOR reset flag 7930 * @arg RCC_FLAG_PINRST: Pin reset 7931 * @arg RCC_FLAG_PORRST: POR/PDR reset 7932 * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag 7933 * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag 7934 * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset 7935 * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset 7936 * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag 7937 * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag 7938 * @retval The new state of __FLAG__ (TRUE or FALSE). 7939 * 7940 * (*) Available on some STM32H7 lines only. 7941 */ 7942 #define RCC_FLAG_MASK ((uint8_t)0x1F) 7943 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 7944 ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 7945 #endif /*DUAL_CORE*/ 7946 7947 /** 7948 * @} 7949 */ 7950 7951 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos) 7952 7953 /** 7954 * @} 7955 */ 7956 7957 /* Include RCC HAL Extension module */ 7958 #include "stm32h7xx_hal_rcc_ex.h" 7959 7960 /* Exported functions --------------------------------------------------------*/ 7961 /** @addtogroup RCC_Exported_Functions 7962 * @{ 7963 */ 7964 7965 /** @addtogroup RCC_Exported_Functions_Group1 7966 * @{ 7967 */ 7968 /* Initialization and de-initialization functions ******************************/ 7969 HAL_StatusTypeDef HAL_RCC_DeInit(void); 7970 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 7971 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 7972 7973 /** 7974 * @} 7975 */ 7976 7977 /** @addtogroup RCC_Exported_Functions_Group2 7978 * @{ 7979 */ 7980 /* Peripheral Control functions ************************************************/ 7981 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 7982 void HAL_RCC_EnableCSS(void); 7983 void HAL_RCC_DisableCSS(void); 7984 uint32_t HAL_RCC_GetSysClockFreq(void); 7985 uint32_t HAL_RCC_GetHCLKFreq(void); 7986 uint32_t HAL_RCC_GetPCLK1Freq(void); 7987 uint32_t HAL_RCC_GetPCLK2Freq(void); 7988 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 7989 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 7990 /* CSS NMI IRQ handler */ 7991 void HAL_RCC_NMI_IRQHandler(void); 7992 /* User Callbacks in non blocking mode (IT mode) */ 7993 void HAL_RCC_CSSCallback(void); 7994 7995 /** 7996 * @} 7997 */ 7998 7999 /** 8000 * @} 8001 */ 8002 8003 /* Private types -------------------------------------------------------------*/ 8004 /* Private variables ---------------------------------------------------------*/ 8005 /* Private constants ---------------------------------------------------------*/ 8006 /** @defgroup RCC_Private_Constants RCC Private Constants 8007 * @{ 8008 */ 8009 8010 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 8011 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms */ 8012 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */ 8013 #define CSI_TIMEOUT_VALUE (2U) /* 2 ms */ 8014 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms */ 8015 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms */ 8016 #define PLL_FRAC_TIMEOUT_VALUE (1U) /* PLL Fractional part waiting time before new latch enable : 1 ms */ 8017 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ 8018 #define RCC_DBP_TIMEOUT_VALUE (100U) 8019 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 8020 8021 /** 8022 * @} 8023 */ 8024 8025 /* Private macros ------------------------------------------------------------*/ 8026 /** @addtogroup RCC_Private_Macros RCC Private Macros 8027 * @{ 8028 */ 8029 8030 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 8031 * @{ 8032 */ 8033 8034 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ 8035 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 8036 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 8037 (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ 8038 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 8039 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 8040 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) 8041 8042 #if defined(RCC_CR_HSEEXT) 8043 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 8044 ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL)) 8045 #else 8046 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 8047 ((HSE) == RCC_HSE_BYPASS)) 8048 #endif /* RCC_CR_HSEEXT */ 8049 8050 #if defined(RCC_BDCR_LSEEXT) 8051 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 8052 ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL)) 8053 #else 8054 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 8055 ((LSE) == RCC_LSE_BYPASS)) 8056 #endif /* RCC_BDCR_LSEEXT */ 8057 8058 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ 8059 ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \ 8060 ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8)) 8061 8062 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) 8063 8064 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 8065 8066 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) 8067 8068 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 8069 ((PLL) == RCC_PLL_ON)) 8070 8071 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \ 8072 ((SOURCE) == RCC_PLLSOURCE_HSI) || \ 8073 ((SOURCE) == RCC_PLLSOURCE_NONE) || \ 8074 ((SOURCE) == RCC_PLLSOURCE_HSE)) 8075 8076 #define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \ 8077 ((VALUE) == RCC_PLL1VCIRANGE_1) || \ 8078 ((VALUE) == RCC_PLL1VCIRANGE_2) || \ 8079 ((VALUE) == RCC_PLL1VCIRANGE_3)) 8080 8081 #define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM)) 8082 8083 #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) 8084 8085 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 8086 #if !defined(RCC_VER_2_0) 8087 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 8088 #else 8089 #define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U)) 8090 #endif /* !RCC_VER_2_0 */ 8091 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 8092 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 8093 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 8094 8095 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ 8096 ((VALUE) == RCC_PLL1_DIVQ) || \ 8097 ((VALUE) == RCC_PLL1_DIVR)) 8098 8099 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU)) 8100 8101 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \ 8102 ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 8103 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 8104 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) 8105 8106 #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ 8107 ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \ 8108 ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \ 8109 ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \ 8110 ((SYSCLK) == RCC_SYSCLK_DIV512)) 8111 8112 8113 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ 8114 ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ 8115 ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ 8116 ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ 8117 ((HCLK) == RCC_HCLK_DIV512)) 8118 8119 #define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \ 8120 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \ 8121 ((CDPCLK1) == RCC_APB3_DIV16)) 8122 8123 #define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */ 8124 8125 #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \ 8126 ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \ 8127 ((PCLK1) == RCC_APB1_DIV16)) 8128 8129 #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \ 8130 ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \ 8131 ((PCLK2) == RCC_APB2_DIV16)) 8132 8133 #define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \ 8134 ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \ 8135 ((SRDPCLK1) == RCC_APB4_DIV16)) 8136 8137 #define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/ 8138 8139 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ 8140 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 8141 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 8142 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 8143 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 8144 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 8145 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 8146 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 8147 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 8148 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 8149 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 8150 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 8151 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 8152 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 8153 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 8154 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ 8155 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ 8156 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ 8157 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ 8158 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ 8159 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ 8160 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ 8161 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ 8162 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ 8163 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ 8164 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ 8165 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ 8166 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ 8167 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ 8168 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ 8169 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ 8170 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63)) 8171 8172 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 8173 8174 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 8175 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \ 8176 ((SOURCE) == RCC_MCO1SOURCE_HSI48)) 8177 8178 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \ 8179 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \ 8180 ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK)) 8181 8182 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 8183 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 8184 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ 8185 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ 8186 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ 8187 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ 8188 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ 8189 ((DIV) == RCC_MCODIV_15)) 8190 8191 #if defined(DUAL_CORE) 8192 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ 8193 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 8194 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ 8195 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ 8196 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 8197 ((FLAG) == RCC_FLAG_LSIRDY) || \ 8198 ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \ 8199 ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \ 8200 ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \ 8201 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ 8202 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 8203 ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ 8204 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ 8205 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV)) 8206 8207 #else 8208 8209 #if defined(RCC_CR_D2CKRDY) 8210 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ 8211 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 8212 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ 8213 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ 8214 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 8215 ((FLAG) == RCC_FLAG_LSIRDY) || \ 8216 ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \ 8217 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ 8218 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 8219 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ 8220 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ 8221 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) 8222 #else 8223 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ 8224 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 8225 ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \ 8226 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ 8227 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 8228 ((FLAG) == RCC_FLAG_LSIRDY) || \ 8229 ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \ 8230 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 8231 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ 8232 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ 8233 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) 8234 #endif /* RCC_CR_D2CKRDY */ 8235 8236 #endif /*DUAL_CORE*/ 8237 8238 #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU) 8239 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) 8240 8241 #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \ 8242 ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) 8243 8244 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ 8245 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 8246 /** 8247 * @} 8248 */ 8249 8250 /** 8251 * @} 8252 */ 8253 8254 /** 8255 * @} 8256 */ 8257 8258 /** 8259 * @} 8260 */ 8261 #ifdef __cplusplus 8262 } 8263 #endif 8264 8265 #endif /* STM32H7xx_HAL_RCC_H */ 8266 8267
