1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32L0xx_HAL_RCC_EX_H 20 #define __STM32L0xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l0xx_hal_def.h" 28 29 /** @addtogroup STM32L0xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /** @addtogroup RCCEx_Private_Constants 38 * @{ 39 */ 40 41 42 #if defined(CRS) 43 /* CRS IT Error Mask */ 44 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 45 46 /* CRS Flag Error Mask */ 47 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 48 49 #endif /* CRS */ 50 /** 51 * @} 52 */ 53 54 /** @addtogroup RCCEx_Private_Macros 55 * @{ 56 */ 57 #if defined (STM32L052xx) || defined(STM32L062xx) 58 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 59 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 60 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1)) 61 #elif defined (STM32L053xx) || defined(STM32L063xx) 62 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 63 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 64 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD)) 65 #elif defined (STM32L072xx) || defined(STM32L082xx) 66 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 67 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 68 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 )) 69 #elif defined (STM32L073xx) || defined(STM32L083xx) 70 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 71 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 72 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \ 73 RCC_PERIPHCLK_LCD)) 74 #endif 75 76 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 77 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 78 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 79 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | \ 80 RCC_PERIPHCLK_LPTIM1)) 81 #elif defined(STM32L051xx) 82 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 83 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 84 RCC_PERIPHCLK_LPTIM1)) 85 #elif defined(STM32L071xx) || defined(STM32L081xx) 86 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 87 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 88 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3)) 89 #endif 90 91 #if defined (RCC_CCIPR_USART1SEL) 92 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 93 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 94 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 95 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 96 #endif /* RCC_CCIPR_USART1SEL */ 97 98 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 99 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 100 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 101 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 102 103 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 104 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 105 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 106 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 107 108 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 109 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 110 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 111 112 #if defined(RCC_CCIPR_I2C3SEL) 113 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 114 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 115 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 116 #endif /* RCC_CCIPR_I2C3SEL */ 117 118 #if defined(USB) 119 #define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 120 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) 121 #endif /* USB */ 122 123 #if defined(RNG) 124 #define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \ 125 ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK)) 126 #endif /* RNG */ 127 128 #if defined(RCC_CCIPR_HSI48SEL) 129 #define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48)) 130 #endif /* RCC_CCIPR_HSI48SEL */ 131 132 #define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 133 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \ 134 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \ 135 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE)) 136 137 #define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 138 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 139 140 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 141 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH)) 142 143 #if defined(CRS) 144 145 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 146 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ 147 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) 148 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ 149 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ 150 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ 151 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) 152 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ 153 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) 154 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) 155 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) 156 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) 157 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ 158 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) 159 #endif /* CRS */ 160 /** 161 * @} 162 */ 163 164 /* Exported types ------------------------------------------------------------*/ 165 166 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 167 * @{ 168 */ 169 170 /** 171 * @brief RCC extended clocks structure definition 172 */ 173 typedef struct 174 { 175 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 176 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 177 178 uint32_t RTCClockSelection; /*!< specifies the RTC clock source. 179 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ 180 181 #if defined(LCD) 182 183 uint32_t LCDClockSelection; /*!< specifies the LCD clock source. 184 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ 185 186 #endif /* LCD */ 187 #if defined(RCC_CCIPR_USART1SEL) 188 uint32_t Usart1ClockSelection; /*!< USART1 clock source 189 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 190 #endif /* RCC_CCIPR_USART1SEL */ 191 uint32_t Usart2ClockSelection; /*!< USART2 clock source 192 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 193 194 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source 195 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 196 197 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 198 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 199 200 #if defined(RCC_CCIPR_I2C3SEL) 201 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 202 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 203 #endif /* RCC_CCIPR_I2C3SEL */ 204 uint32_t LptimClockSelection; /*!< LPTIM1 clock source 205 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 206 #if defined(USB) 207 uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection 208 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 209 #endif /* USB */ 210 } RCC_PeriphCLKInitTypeDef; 211 212 #if defined (CRS) 213 /** 214 * @brief RCC_CRS Init structure definition 215 */ 216 typedef struct 217 { 218 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 219 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 220 221 uint32_t Source; /*!< Specifies the SYNC signal source. 222 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 223 224 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 225 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 226 227 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 228 It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 229 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 230 231 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 232 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 233 234 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 235 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 236 237 }RCC_CRSInitTypeDef; 238 239 /** 240 * @brief RCC_CRS Synchronization structure definition 241 */ 242 typedef struct 243 { 244 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 245 This parameter must be a number between 0 and 0xFFFF */ 246 247 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 248 This parameter must be a number between 0 and 0x3F */ 249 250 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 251 value latched in the time of the last SYNC event. 252 This parameter must be a number between 0 and 0xFFFF */ 253 254 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 255 frequency error counter latched in the time of the last SYNC event. 256 It shows whether the actual frequency is below or above the target. 257 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 258 259 }RCC_CRSSynchroInfoTypeDef; 260 261 #endif /* CRS */ 262 263 /** 264 * @} 265 */ 266 267 /* Exported constants --------------------------------------------------------*/ 268 269 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 270 * @{ 271 */ 272 273 274 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 275 * @{ 276 */ 277 #define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 278 /** 279 * @} 280 */ 281 282 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 283 * @{ 284 */ 285 #if defined(RCC_CCIPR_USART1SEL) 286 #define RCC_PERIPHCLK_USART1 (0x00000001U) 287 #endif /* RCC_CCIPR_USART1SEL */ 288 #define RCC_PERIPHCLK_USART2 (0x00000002U) 289 #define RCC_PERIPHCLK_LPUART1 (0x00000004U) 290 #define RCC_PERIPHCLK_I2C1 (0x00000008U) 291 #define RCC_PERIPHCLK_I2C2 (0x00000010U) 292 #define RCC_PERIPHCLK_RTC (0x00000020U) 293 #if defined(USB) 294 #define RCC_PERIPHCLK_USB (0x00000040U) 295 #endif /* USB */ 296 #define RCC_PERIPHCLK_LPTIM1 (0x00000080U) 297 #if defined(LCD) 298 #define RCC_PERIPHCLK_LCD (0x00000800U) 299 #endif /* LCD */ 300 #if defined(RCC_CCIPR_I2C3SEL) 301 #define RCC_PERIPHCLK_I2C3 (0x00000100U) 302 #endif /* RCC_CCIPR_I2C3SEL */ 303 304 /** 305 * @} 306 */ 307 308 #if defined (RCC_CCIPR_USART1SEL) 309 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source 310 * @{ 311 */ 312 #define RCC_USART1CLKSOURCE_PCLK2 (0x00000000U) 313 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 314 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 315 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 316 /** 317 * @} 318 */ 319 #endif /* RCC_CCIPR_USART1SEL */ 320 321 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 322 * @{ 323 */ 324 #define RCC_USART2CLKSOURCE_PCLK1 (0x00000000U) 325 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 326 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 327 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 328 /** 329 * @} 330 */ 331 332 /** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source 333 * @{ 334 */ 335 #define RCC_LPUART1CLKSOURCE_PCLK1 (0x00000000U) 336 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 337 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 338 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 339 /** 340 * @} 341 */ 342 343 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source 344 * @{ 345 */ 346 #define RCC_I2C1CLKSOURCE_PCLK1 (0x00000000U) 347 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 348 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 349 /** 350 * @} 351 */ 352 353 #if defined(RCC_CCIPR_I2C3SEL) 354 355 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source 356 * @{ 357 */ 358 #define RCC_I2C3CLKSOURCE_PCLK1 (0x00000000U) 359 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 360 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 361 /** 362 * @} 363 */ 364 #endif /* RCC_CCIPR_I2C3SEL */ 365 366 /** @defgroup RCCEx_TIM_PRescaler_Selection RCCEx TIM Prescaler Selection 367 * @{ 368 */ 369 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 370 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 371 /** 372 * @} 373 */ 374 375 #if defined(USB) 376 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 377 * @{ 378 */ 379 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL 380 #define RCC_USBCLKSOURCE_PLL (0x00000000U) 381 /** 382 * @} 383 */ 384 #endif /* USB */ 385 386 #if defined(RNG) 387 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 388 * @{ 389 */ 390 #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL 391 #define RCC_RNGCLKSOURCE_PLLCLK (0x00000000U) 392 /** 393 * @} 394 */ 395 #endif /* RNG */ 396 397 #if defined(RCC_CCIPR_HSI48SEL) 398 /** @defgroup RCCEx_HSI48M_Clock_Source RCCEx HSI48M Clock Source 399 * @{ 400 */ 401 #define RCC_FLAG_HSI48 SYSCFG_CFGR3_VREFINT_RDYF 402 403 #define RCC_HSI48M_PLL (0x00000000U) 404 #define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL 405 406 /** 407 * @} 408 */ 409 #endif /* RCC_CCIPR_HSI48SEL */ 410 411 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source 412 * @{ 413 */ 414 #define RCC_LPTIM1CLKSOURCE_PCLK1 (0x00000000U) 415 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 416 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 417 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 418 /** 419 * @} 420 */ 421 422 /** @defgroup RCCEx_StopWakeUp_Clock RCCEx StopWakeUp Clock 423 * @{ 424 */ 425 426 #define RCC_STOP_WAKEUPCLOCK_MSI (0x00000000U) 427 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK 428 /** 429 * @} 430 */ 431 432 /** @defgroup RCCEx_LSEDrive_Configuration RCCEx LSE Drive Configuration 433 * @{ 434 */ 435 436 #define RCC_LSEDRIVE_LOW (0x00000000U) 437 #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 438 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 439 #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV 440 /** 441 * @} 442 */ 443 444 #if defined(CRS) 445 446 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 447 * @{ 448 */ 449 #define RCC_CRS_NONE (0x00000000U) 450 #define RCC_CRS_TIMEOUT (0x00000001U) 451 #define RCC_CRS_SYNCOK (0x00000002U) 452 #define RCC_CRS_SYNCWARN (0x00000004U) 453 #define RCC_CRS_SYNCERR (0x00000008U) 454 #define RCC_CRS_SYNCMISS (0x00000010U) 455 #define RCC_CRS_TRIMOVF (0x00000020U) 456 457 /** 458 * @} 459 */ 460 461 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source 462 * @{ 463 */ 464 #define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ 465 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 466 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 467 /** 468 * @} 469 */ 470 471 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider 472 * @{ 473 */ 474 #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ 475 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 476 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 477 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 478 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 479 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 480 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 481 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity 487 * @{ 488 */ 489 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ 490 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 491 /** 492 * @} 493 */ 494 495 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value 496 * @{ 497 */ 498 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 499 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 500 /** 501 * @} 502 */ 503 504 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value 505 * @{ 506 */ 507 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ 508 /** 509 * @} 510 */ 511 512 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye 513 * @{ 514 */ 515 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 516 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 517 corresponds to a higher output frequency */ 518 /** 519 * @} 520 */ 521 522 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction 523 * @{ 524 */ 525 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 526 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 527 /** 528 * @} 529 */ 530 531 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 532 * @{ 533 */ 534 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 535 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 536 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 537 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 538 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 539 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 540 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 541 542 /** 543 * @} 544 */ 545 546 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 547 * @{ 548 */ 549 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 550 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 551 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 552 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 553 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 554 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 555 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 556 557 /** 558 * @} 559 */ 560 561 #endif /* CRS */ 562 563 /** 564 * @} 565 */ 566 567 /* Exported macro ------------------------------------------------------------*/ 568 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 569 * @{ 570 */ 571 572 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 573 * @brief Enable or disable the AHB peripheral clock. 574 * @note After reset, the peripheral clock (used for registers read/write access) 575 * is disabled and the application software has to enable this clock before 576 * using it. 577 * @{ 578 */ 579 580 #if defined(STM32L062xx) || defined(STM32L063xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx) 581 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 582 __IO uint32_t tmpreg; \ 583 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\ 584 /* Delay after an RCC peripheral clock enabling */ \ 585 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\ 586 UNUSED(tmpreg); \ 587 } while(0) 588 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN)) 589 590 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != 0U) 591 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == 0U) 592 593 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx */ 594 595 #if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 596 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 597 __IO uint32_t tmpreg; \ 598 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 599 /* Delay after an RCC peripheral clock enabling */ \ 600 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 601 UNUSED(tmpreg); \ 602 } while(0) 603 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN)) 604 605 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U) 606 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U) 607 608 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 609 __IO uint32_t tmpreg; \ 610 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\ 611 /* Delay after an RCC peripheral clock enabling */ \ 612 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\ 613 UNUSED(tmpreg); \ 614 } while(0) 615 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN)) 616 617 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != 0U) 618 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == 0U) 619 #endif /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 620 621 /** 622 * @} 623 */ 624 625 /** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable 626 * @brief Enable or disable the IOPORT peripheral clock. 627 * @note After reset, the peripheral clock (used for registers read/write access) 628 * is disabled and the application software has to enable this clock before 629 * using it. 630 * @{ 631 */ 632 #if defined(GPIOE) 633 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 634 __IO uint32_t tmpreg; \ 635 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\ 636 /* Delay after an RCC peripheral clock enabling */ \ 637 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\ 638 UNUSED(tmpreg); \ 639 } while(0) 640 641 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN)) 642 643 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != 0U) 644 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == 0U) 645 646 #endif /* GPIOE */ 647 #if defined(GPIOD) 648 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 649 __IO uint32_t tmpreg; \ 650 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\ 651 /* Delay after an RCC peripheral clock enabling */ \ 652 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\ 653 UNUSED(tmpreg); \ 654 } while(0) 655 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN)) 656 657 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != 0U) 658 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == 0U) 659 660 #endif /* GPIOD */ 661 /** 662 * @} 663 */ 664 665 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 666 * @brief Enable or disable the APB1 peripheral clock. 667 * @note After reset, the peripheral clock (used for registers read/write access) 668 * is disabled and the application software has to enable this clock before 669 * using it. 670 * @{ 671 */ 672 673 #if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 674 #define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN)) 675 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN)) 676 677 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) != 0U) 678 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) == 0U) 679 680 #define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN)) 681 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN)) 682 683 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) != 0U) 684 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) == 0U) 685 686 #endif /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 687 688 689 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) 690 #define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN)) 691 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN)) 692 693 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) != 0U) 694 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) == 0U) 695 696 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ 697 698 #if defined(STM32L053xx) || defined(STM32L063xx) \ 699 || defined(STM32L052xx) || defined(STM32L062xx) \ 700 || defined(STM32L051xx) 701 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 702 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 703 #define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 704 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 705 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 706 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 707 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 708 #define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 709 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 710 711 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 712 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 713 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 714 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 715 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 716 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 717 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 718 #define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 719 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 720 721 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U) 722 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U) 723 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U) 724 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U) 725 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U) 726 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U) 727 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U) 728 #define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U) 729 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U) 730 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U) 731 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U) 732 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U) 733 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U) 734 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U) 735 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U) 736 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U) 737 #define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U) 738 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U) 739 740 #endif /* STM32L053xx || STM32L063xx || */ 741 /* STM32L052xx || STM32L062xx || */ 742 /* STM32L051xx */ 743 744 #if defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) || \ 745 defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) 746 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 747 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 748 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 749 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 750 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 751 752 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 753 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 754 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 755 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 756 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 757 758 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U) 759 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U) 760 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U) 761 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U) 762 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U) 763 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U) 764 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U) 765 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U) 766 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U) 767 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U) 768 769 #endif /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 || */ 770 /* STM32L011xx || STM32L021xx || STM32L031xx || STM32L041xx */ 771 772 773 #if defined(STM32L073xx) || defined(STM32L083xx) \ 774 || defined(STM32L072xx) || defined(STM32L082xx) \ 775 || defined(STM32L071xx) || defined(STM32L081xx) 776 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 777 #define __HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN)) 778 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 779 #define __HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN)) 780 #define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 781 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 782 #define __HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN)) 783 #define __HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN)) 784 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 785 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 786 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 787 #define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN)) 788 #define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 789 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 790 791 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 792 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN)) 793 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 794 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN)) 795 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 796 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 797 #define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN)) 798 #define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN)) 799 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 800 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 801 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 802 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN)) 803 #define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 804 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 805 806 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U) 807 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) != 0U) 808 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U) 809 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) != 0U) 810 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U) 811 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U) 812 #define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) != 0U) 813 #define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) != 0U) 814 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U) 815 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U) 816 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U) 817 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != 0U) 818 #define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U) 819 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U) 820 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U) 821 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) == 0U) 822 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U) 823 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) == 0U) 824 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U) 825 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U) 826 #define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) == 0U) 827 #define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) == 0U) 828 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U) 829 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U) 830 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U) 831 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == 0U) 832 #define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U) 833 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U) 834 835 #endif /* STM32L071xx || STM32L081xx || */ 836 /* STM32L072xx || STM32L082xx || */ 837 /* STM32L073xx || STM32L083xx */ 838 839 /** 840 * @} 841 */ 842 843 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 844 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \ 845 || defined(STM32L051xx) || defined(STM32L071xx) || defined(STM32L081xx) || defined(STM32L031xx) \ 846 || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L010xB) \ 847 || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 848 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 849 * @brief Enable or disable the APB2 peripheral clock. 850 * @note After reset, the peripheral clock (used for registers read/write access) 851 * is disabled and the application software has to enable this clock before 852 * using it. 853 * @{ 854 */ 855 #define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN)) 856 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 857 #define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN)) 858 #endif 859 #define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN)) 860 #define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN)) 861 #define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN)) 862 863 #define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN)) 864 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 865 #define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN)) 866 #endif 867 #define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN)) 868 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN)) 869 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN)) 870 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 871 #define __HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN)) 872 #define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN)) 873 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */ 874 875 #define __HAL_RCC_TIM21_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM21EN) != 0U) 876 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 877 #define __HAL_RCC_TIM22_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM22EN) != 0U) 878 #endif 879 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != 0U) 880 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 881 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 882 883 #define __HAL_RCC_TIM21_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN) == 0U) 884 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 885 #define __HAL_RCC_TIM22_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN) == 0U) 886 #endif 887 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN) == 0U) 888 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN) == 0U) 889 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN) == 0U) 890 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 891 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MIFIEN) != 0U) 892 #define __HAL_RCC_FIREWALL_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN) == 0U) 893 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */ 894 895 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */ 896 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ 897 /* STM32L051xx || STM32L071xx || STM32L081xx || STM32L031xx || */ 898 /* STM32L041xx || STM32L011xx || STM32L021xx || STM32L010xB || */ 899 /* STM32L010x8 || STM32L010x6 || STM32L010x4 */ 900 /** 901 * @} 902 */ 903 904 /** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 905 * @brief Force or release AHB peripheral reset. 906 * @{ 907 */ 908 #if defined(STM32L062xx) || defined(STM32L063xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx) 909 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST)) 910 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST)) 911 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx*/ 912 913 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 914 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST)) 915 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST)) 916 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST)) 917 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST)) 918 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 919 920 /** 921 * @} 922 */ 923 924 /** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset 925 * @brief Force or release IOPORT peripheral reset. 926 * @{ 927 */ 928 #if defined(STM32L073xx) || defined(STM32L083xx) \ 929 || defined(STM32L072xx) || defined(STM32L082xx) \ 930 || defined(STM32L071xx) || defined(STM32L081xx) \ 931 || defined(STM32L010xB) 932 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST)) 933 934 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST)) 935 936 #endif /* STM32L071xx || STM32L081xx || */ 937 /* STM32L072xx || STM32L082xx || */ 938 /* STM32L073xx || STM32L083xx || */ 939 /* STM32L010xB */ 940 #if !defined(STM32L010x4) && !defined(STM32L010x6) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 941 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST)) 942 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST)) 943 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */ 944 /** 945 * @} 946 */ 947 948 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 949 * @brief Force or release APB1 peripheral reset. 950 * @{ 951 */ 952 953 #if defined(STM32L053xx) || defined(STM32L063xx) \ 954 || defined(STM32L052xx) || defined(STM32L062xx) \ 955 || defined(STM32L051xx) 956 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 957 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 958 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 959 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 960 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 961 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 962 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 963 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 964 #define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 965 966 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 967 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 968 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 969 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 970 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 971 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 972 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 973 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 974 #define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 975 #endif /* STM32L053xx || STM32L063xx || */ 976 /* STM32L052xx || STM32L062xx || */ 977 /* STM32L051xx */ 978 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 979 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 980 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 981 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 982 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 983 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 984 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 985 986 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 987 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 988 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 989 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 990 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 991 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */ 992 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 993 994 #if defined(STM32L073xx) || defined(STM32L083xx) \ 995 || defined(STM32L072xx) || defined(STM32L082xx) \ 996 || defined(STM32L071xx) || defined(STM32L081xx) 997 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 998 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST)) 999 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 1000 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST)) 1001 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 1002 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 1003 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 1004 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST)) 1005 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 1006 #define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST)) 1007 #define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST)) 1008 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 1009 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 1010 #define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 1011 1012 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 1013 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST)) 1014 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 1015 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST)) 1016 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 1017 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 1018 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 1019 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST)) 1020 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 1021 #define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST)) 1022 #define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST)) 1023 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 1024 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 1025 #define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 1026 #endif /* STM32L071xx || STM32L081xx || */ 1027 /* STM32L072xx || STM32L082xx || */ 1028 /* STM32L073xx || STM32L083xx || */ 1029 1030 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \ 1031 !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ 1032 !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) 1033 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST)) 1034 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST)) 1035 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST)) 1036 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST)) 1037 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */ 1038 /* !(STM32L051xx) && !(STM32L071xx) && !(STM32L081xx) && !(STM32L010xB) && */ 1039 /* !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && */ 1040 1041 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) 1042 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST)) 1043 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST)) 1044 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ 1045 1046 /** 1047 * @} 1048 */ 1049 1050 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 1051 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \ 1052 || defined(STM32L051xx) || defined(STM32L071xx) || defined(STM32L081xx) 1053 1054 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1055 * @brief Force or release APB2 peripheral reset. 1056 * @{ 1057 */ 1058 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST)) 1059 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1060 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1061 #define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1062 #define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1063 1064 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST)) 1065 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1066 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1067 #define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1068 #define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1069 1070 #endif /* STM32L051xx || STM32L071xx || STM32L081xx || STM32L052xx || */ 1071 /* STM32L062xx || STM32L072xx || STM32L082xx || STM32L053xx || */ 1072 /* STM32L063xx || STM32L073xx || STM32L083xx */ 1073 1074 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 1075 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 1076 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1077 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1078 #define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1079 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1080 #define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1081 #endif 1082 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1083 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1084 #define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1085 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1086 #define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1087 #endif 1088 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */ 1089 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 1090 1091 /** 1092 * @} 1093 */ 1094 1095 /** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable 1096 * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. 1097 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1098 * power consumption. 1099 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1100 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1101 * @{ 1102 */ 1103 1104 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \ 1105 !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && !defined(STM32L010xB) && \ 1106 !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) 1107 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN)) 1108 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN)) 1109 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN)) 1110 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN)) 1111 1112 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) != 0U) 1113 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != 0U) 1114 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) == 0U) 1115 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == 0U) 1116 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */ 1117 /* !(STM32L051xx) && !(STM32L071xx) && !(STM32L081xx) &&!(STM32L010xB) && */ 1118 /* !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && */ 1119 1120 #if defined(STM32L062xx) || defined(STM32L063xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) 1121 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN)) 1122 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN)) 1123 1124 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) != 0U) 1125 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) == 0U) 1126 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx || STM32L041xx */ 1127 1128 /** 1129 * @} 1130 */ 1131 1132 /** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable 1133 * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode. 1134 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1135 * power consumption. 1136 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1137 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1138 * @{ 1139 */ 1140 #if defined(STM32L073xx) || defined(STM32L083xx) \ 1141 || defined(STM32L072xx) || defined(STM32L082xx) \ 1142 || defined(STM32L071xx) || defined(STM32L081xx) \ 1143 || defined(STM32L010xB) 1144 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN)) 1145 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN)) 1146 1147 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) != 0U) 1148 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == 0U) 1149 #endif /* STM32L071xx || STM32L081xx || */ 1150 /* STM32L072xx || STM32L082xx || */ 1151 /* STM32L073xx || STM32L083xx || */ 1152 /* STM32L010xB */ 1153 #if !defined(STM32L010x4) && !defined(STM32L010x6) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 1154 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN)) 1155 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN)) 1156 1157 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) != 0U) 1158 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == 0U) 1159 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */ 1160 /** 1161 * @} 1162 */ 1163 1164 1165 /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 1166 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1167 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1168 * power consumption. 1169 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1170 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1171 * @{ 1172 */ 1173 1174 #if defined(STM32L053xx) || defined(STM32L063xx) \ 1175 || defined(STM32L052xx) || defined(STM32L062xx) \ 1176 || defined(STM32L051xx) 1177 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1178 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1179 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1180 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1181 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1182 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1183 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1184 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1185 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1186 1187 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1188 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1189 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1190 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1191 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1192 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1193 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1194 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1195 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1196 1197 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U) 1198 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U) 1199 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U) 1200 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U) 1201 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U) 1202 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U) 1203 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U) 1204 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U) 1205 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U) 1206 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U) 1207 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U) 1208 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U) 1209 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U) 1210 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U) 1211 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U) 1212 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U) 1213 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U) 1214 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U) 1215 #endif /* STM32L053xx || STM32L063xx || */ 1216 /* STM32L052xx || STM32L062xx || */ 1217 /* STM32L051xx */ 1218 1219 #if defined(STM32L073xx) || defined(STM32L083xx) \ 1220 || defined(STM32L072xx) || defined(STM32L082xx) \ 1221 || defined(STM32L071xx) || defined(STM32L081xx) 1222 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1223 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN)) 1224 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1225 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN)) 1226 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1227 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1228 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN)) 1229 #define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN)) 1230 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1231 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1232 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1233 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN)) 1234 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1235 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1236 1237 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1238 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN)) 1239 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1240 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN)) 1241 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1242 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1243 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN)) 1244 #define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN)) 1245 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1246 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1247 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1248 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN)) 1249 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1250 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1251 1252 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U) 1253 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) != 0U) 1254 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U) 1255 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) != 0U) 1256 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U) 1257 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U) 1258 #define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) != 0U) 1259 #define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) != 0U) 1260 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U) 1261 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U) 1262 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U) 1263 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) != 0U) 1264 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U) 1265 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U) 1266 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U) 1267 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) == 0U) 1268 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U) 1269 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) == 0U) 1270 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U) 1271 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U) 1272 #define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) == 0U) 1273 #define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) == 0U) 1274 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U) 1275 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U) 1276 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U) 1277 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) == 0U) 1278 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U) 1279 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U) 1280 #endif /* STM32L071xx || STM32L081xx || */ 1281 /* STM32L072xx || STM32L082xx || */ 1282 /* STM32L073xx || STM32L083xx */ 1283 1284 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 1285 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 1286 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1287 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1288 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1289 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1290 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1291 1292 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1293 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1294 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1295 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1296 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1297 1298 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U) 1299 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U) 1300 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U) 1301 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U) 1302 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U) 1303 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U) 1304 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U) 1305 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U) 1306 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U) 1307 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U) 1308 1309 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */ 1310 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 1311 1312 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \ 1313 !defined(STM32L051xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ 1314 !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) 1315 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN)) 1316 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN)) 1317 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN)) 1318 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN)) 1319 1320 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) != 0U) 1321 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) == 0U) 1322 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) != 0U) 1323 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) == 0U) 1324 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */ 1325 /* !(STM32L051xx) && !(STM32L071xx) && !(STM32L081xx) && !(STM32L010xB) && */ 1326 /* !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) */ 1327 1328 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) 1329 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN)) 1330 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN)) 1331 1332 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) != 0U) 1333 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) == 0U) 1334 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ 1335 1336 /** 1337 * @} 1338 */ 1339 1340 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 1341 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \ 1342 || defined(STM32L051xx) || defined(STM32L071xx) || defined(STM32L081xx) || defined(STM32L031xx) \ 1343 || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L010xB) \ 1344 || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 1345 1346 /** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 1347 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1348 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1349 * power consumption. 1350 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1351 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1352 * @{ 1353 */ 1354 #define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN)) 1355 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1356 #define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN)) 1357 #endif 1358 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN)) 1359 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN)) 1360 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN)) 1361 1362 #define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN)) 1363 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1364 #define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN)) 1365 #endif 1366 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN)) 1367 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN)) 1368 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN)) 1369 1370 #define __HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM21SMEN) != 0U) 1371 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1372 #define __HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM22SMEN) != 0U) 1373 #endif 1374 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADC1SMEN) != 0U) 1375 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 1376 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 1377 1378 #define __HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN) == 0U) 1379 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1380 #define __HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN) == 0U) 1381 #endif 1382 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN) == 0U) 1383 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN) == 0U) 1384 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN) == 0U) 1385 1386 /** 1387 * @} 1388 */ 1389 1390 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */ 1391 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ 1392 /* STM32L051xx || STM32L071xx || STM32L081xx || STM32L031xx || */ 1393 /* STM32L041xx || STM32L011xx || STM32L021xx || STM32L010xB || */ 1394 /* STM32L010x8 || STM32L010x6 || STM32L010x4 */ 1395 1396 1397 /** 1398 * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. 1399 * @retval None 1400 */ 1401 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) 1402 1403 /** 1404 * @brief Disable interrupt on RCC LSE CSS EXTI Line 19. 1405 * @retval None 1406 */ 1407 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) 1408 1409 /** 1410 * @brief Enable event on RCC LSE CSS EXTI Line 19. 1411 * @retval None. 1412 */ 1413 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) 1414 1415 /** 1416 * @brief Disable event on RCC LSE CSS EXTI Line 19. 1417 * @retval None. 1418 */ 1419 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) 1420 1421 1422 /** 1423 * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger. 1424 * @retval None. 1425 */ 1426 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) 1427 1428 1429 /** 1430 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1431 * @retval None. 1432 */ 1433 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) 1434 1435 1436 /** 1437 * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger. 1438 * @retval None. 1439 */ 1440 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) 1441 1442 /** 1443 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1444 * @retval None. 1445 */ 1446 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) 1447 1448 /** 1449 * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger. 1450 * @retval None. 1451 */ 1452 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1453 do { \ 1454 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1455 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1456 } while(0) 1457 1458 /** 1459 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1460 * @retval None. 1461 */ 1462 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1463 do { \ 1464 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1465 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1466 } while(0) 1467 1468 /** 1469 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1470 * @retval EXTI RCC LSE CSS Line Status. 1471 */ 1472 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS)) 1473 1474 /** 1475 * @brief Clear the RCC LSE CSS EXTI flag. 1476 * @retval None. 1477 */ 1478 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS)) 1479 1480 /** 1481 * @brief Generate a Software interrupt on selected EXTI line. 1482 * @retval None. 1483 */ 1484 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) 1485 1486 1487 #if defined(LCD) 1488 1489 /** @defgroup RCCEx_LCD_Configuration LCD Configuration 1490 * @brief Macros to configure clock source of LCD peripherals. 1491 * @{ 1492 */ 1493 1494 /** @brief Macro to configures LCD clock (LCDCLK). 1495 * @note LCD and RTC use the same configuration 1496 * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the 1497 * LCD clock source. 1498 * 1499 * @param __LCD_CLKSOURCE__ specifies the LCD clock source. 1500 * This parameter can be one of the following values: 1501 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock 1502 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock 1503 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock 1504 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock 1505 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock 1506 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock 1507 */ 1508 #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) 1509 1510 /** @brief Macro to get the LCD clock source. 1511 */ 1512 #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() 1513 1514 /** @brief Macro to get the LCD clock pre-scaler. 1515 */ 1516 #define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER() 1517 1518 /** 1519 * @} 1520 */ 1521 1522 #endif /* LCD */ 1523 1524 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1525 * 1526 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1527 * This parameter can be one of the following values: 1528 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1529 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1530 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1531 */ 1532 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1533 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1534 1535 /** @brief Macro to get the I2C1 clock source. 1536 * @retval The clock source can be one of the following values: 1537 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1538 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1539 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1540 */ 1541 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) 1542 1543 #if defined(RCC_CCIPR_I2C3SEL) 1544 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1545 * 1546 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1547 * This parameter can be one of the following values: 1548 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1549 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1550 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1551 */ 1552 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1553 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 1554 1555 /** @brief Macro to get the I2C3 clock source. 1556 * @retval The clock source can be one of the following values: 1557 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1558 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1559 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1560 */ 1561 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) 1562 1563 #endif /* RCC_CCIPR_I2C3SEL */ 1564 1565 #if defined (RCC_CCIPR_USART1SEL) 1566 /** @brief Macro to configure the USART1 clock (USART1CLK). 1567 * 1568 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1569 * This parameter can be one of the following values: 1570 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1571 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1572 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1573 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1574 */ 1575 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1576 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 1577 1578 /** @brief Macro to get the USART1 clock source. 1579 * @retval The clock source can be one of the following values: 1580 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1581 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1582 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1583 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1584 */ 1585 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) 1586 #endif /* RCC_CCIPR_USART1SEL */ 1587 1588 /** @brief Macro to configure the USART2 clock (USART2CLK). 1589 * 1590 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1591 * This parameter can be one of the following values: 1592 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1593 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1594 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1595 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1596 */ 1597 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1598 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 1599 1600 /** @brief Macro to get the USART2 clock source. 1601 * @retval The clock source can be one of the following values: 1602 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1603 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1604 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1605 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1606 */ 1607 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) 1608 1609 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1610 * 1611 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1612 * This parameter can be one of the following values: 1613 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1614 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1615 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1616 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1617 */ 1618 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1619 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 1620 1621 /** @brief Macro to get the LPUART1 clock source. 1622 * @retval The clock source can be one of the following values: 1623 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1624 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1625 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1626 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1627 */ 1628 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) 1629 1630 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1631 * 1632 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1633 * This parameter can be one of the following values: 1634 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1635 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1636 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 1637 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1638 */ 1639 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1640 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1641 1642 /** @brief Macro to get the LPTIM1 clock source. 1643 * @retval The clock source can be one of the following values: 1644 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1645 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 1646 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 1647 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 1648 */ 1649 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) 1650 1651 #if defined(USB) 1652 /** @brief Macro to configure the USB clock (USBCLK). 1653 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1654 * This parameter can be one of the following values: 1655 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 1656 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock 1657 */ 1658 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 1659 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USB_CLKSOURCE__)) 1660 1661 /** @brief Macro to get the USB clock source. 1662 * @retval The clock source can be one of the following values: 1663 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 1664 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock 1665 */ 1666 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) 1667 #endif /* USB */ 1668 1669 #if defined(RNG) 1670 /** @brief Macro to configure the RNG clock (RNGCLK). 1671 * @param __RNG_CLKSOURCE__ specifies the USB clock source. 1672 * This parameter can be one of the following values: 1673 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1674 * @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock 1675 */ 1676 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1677 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNG_CLKSOURCE__)) 1678 1679 /** @brief Macro to get the RNG clock source. 1680 * @retval The clock source can be one of the following values: 1681 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1682 * @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock 1683 */ 1684 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) 1685 #endif /* RNG */ 1686 1687 #if defined(RCC_CCIPR_HSI48SEL) 1688 /** @brief Macro to select the HSI48M clock source 1689 * @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or 1690 * __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources. 1691 * 1692 * @param __HSI48M_CLKSOURCE__ specifies the HSI48M clock source dedicated for 1693 * USB an RNG peripherals. 1694 * This parameter can be one of the following values: 1695 * @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output. 1696 * @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator. 1697 */ 1698 #define __HAL_RCC_HSI48M_CONFIG(__HSI48M_CLKSOURCE__) \ 1699 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48M_CLKSOURCE__)) 1700 1701 /** @brief Macro to get the HSI48M clock source. 1702 * @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or 1703 * __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources. 1704 * @retval The clock source can be one of the following values: 1705 * @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output. 1706 * @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator. 1707 */ 1708 #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) 1709 #endif /* RCC_CCIPR_HSI48SEL */ 1710 1711 /** 1712 * @brief Macro to enable the force of the Internal High Speed oscillator (HSI) 1713 * in STOP mode to be quickly available as kernel clock for USART and I2C. 1714 * @note The Enable of this function has not effect on the HSION bit. 1715 */ 1716 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 1717 1718 /** 1719 * @brief Macro to disable the force of the Internal High Speed oscillator (HSI) 1720 * in STOP mode to be quickly available as kernel clock for USART and I2C. 1721 * @retval None 1722 */ 1723 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 1724 1725 /** 1726 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. 1727 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. 1728 * This parameter can be one of the following values: 1729 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 1730 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 1731 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 1732 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 1733 * @retval None 1734 */ 1735 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->CSR,\ 1736 RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) 1737 1738 /** 1739 * @brief Macro to configures the wake up from stop clock. 1740 * @param __RCC_STOPWUCLK__ specifies the clock source used after wake up from stop 1741 * This parameter can be one of the following values: 1742 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 1743 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 1744 * @retval None 1745 */ 1746 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\ 1747 RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) )) 1748 1749 #if defined(CRS) 1750 /** 1751 * @brief Enables the specified CRS interrupts. 1752 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1753 * This parameter can be any combination of the following values: 1754 * @arg @ref RCC_CRS_IT_SYNCOK 1755 * @arg @ref RCC_CRS_IT_SYNCWARN 1756 * @arg @ref RCC_CRS_IT_ERR 1757 * @arg @ref RCC_CRS_IT_ESYNC 1758 * @retval None 1759 */ 1760 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1761 1762 /** 1763 * @brief Disables the specified CRS interrupts. 1764 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1765 * This parameter can be any combination of the following values: 1766 * @arg @ref RCC_CRS_IT_SYNCOK 1767 * @arg @ref RCC_CRS_IT_SYNCWARN 1768 * @arg @ref RCC_CRS_IT_ERR 1769 * @arg @ref RCC_CRS_IT_ESYNC 1770 * @retval None 1771 */ 1772 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR,(__INTERRUPT__)) 1773 1774 /** @brief Check the CRS interrupt has occurred or not. 1775 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1776 * This parameter can be one of the following values: 1777 * @arg @ref RCC_CRS_IT_SYNCOK 1778 * @arg @ref RCC_CRS_IT_SYNCWARN 1779 * @arg @ref RCC_CRS_IT_ERR 1780 * @arg @ref RCC_CRS_IT_ESYNC 1781 * @retval The new state of __INTERRUPT__ (SET or RESET). 1782 */ 1783 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET) 1784 1785 /** @brief Clear the CRS interrupt pending bits 1786 * bits to clear the selected interrupt pending bits. 1787 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1788 * This parameter can be any combination of the following values: 1789 * @arg @ref RCC_CRS_IT_SYNCOK 1790 * @arg @ref RCC_CRS_IT_SYNCWARN 1791 * @arg @ref RCC_CRS_IT_ERR 1792 * @arg @ref RCC_CRS_IT_ESYNC 1793 * @arg @ref RCC_CRS_IT_TRIMOVF 1794 * @arg @ref RCC_CRS_IT_SYNCERR 1795 * @arg @ref RCC_CRS_IT_SYNCMISS 1796 */ 1797 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1798 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1799 { \ 1800 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1801 } \ 1802 else \ 1803 { \ 1804 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1805 } \ 1806 } while(0) 1807 1808 /** 1809 * @brief Checks whether the specified CRS flag is set or not. 1810 * @param __FLAG__ specifies the flag to check. 1811 * This parameter can be one of the following values: 1812 * @arg @ref RCC_CRS_FLAG_SYNCOK 1813 * @arg @ref RCC_CRS_FLAG_SYNCWARN 1814 * @arg @ref RCC_CRS_FLAG_ERR 1815 * @arg @ref RCC_CRS_FLAG_ESYNC 1816 * @arg @ref RCC_CRS_FLAG_TRIMOVF 1817 * @arg @ref RCC_CRS_FLAG_SYNCERR 1818 * @arg @ref RCC_CRS_FLAG_SYNCMISS 1819 * @retval The new state of __FLAG__ (TRUE or FALSE). 1820 */ 1821 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__)) 1822 1823 /** 1824 * @brief Clears the CRS specified FLAG. 1825 * @param __FLAG__ specifies the flag to clear. 1826 * This parameter can be one of the following values: 1827 * @arg @ref RCC_CRS_FLAG_SYNCOK 1828 * @arg @ref RCC_CRS_FLAG_SYNCWARN 1829 * @arg @ref RCC_CRS_FLAG_ERR 1830 * @arg @ref RCC_CRS_FLAG_ESYNC 1831 * @arg @ref RCC_CRS_FLAG_TRIMOVF 1832 * @arg @ref RCC_CRS_FLAG_SYNCERR 1833 * @arg @ref RCC_CRS_FLAG_SYNCMISS 1834 * @retval None 1835 */ 1836 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1837 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1838 { \ 1839 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1840 } \ 1841 else \ 1842 { \ 1843 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1844 } \ 1845 } while(0) 1846 1847 /** 1848 * @brief Enables the oscillator clock for frequency error counter. 1849 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1850 * @retval None 1851 */ 1852 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1853 1854 /** 1855 * @brief Disables the oscillator clock for frequency error counter. 1856 * @retval None 1857 */ 1858 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1859 1860 /** 1861 * @brief Enables the automatic hardware adjustment of TRIM bits. 1862 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1863 * @retval None 1864 */ 1865 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1866 1867 /** 1868 * @brief Enables or disables the automatic hardware adjustment of TRIM bits. 1869 * @retval None 1870 */ 1871 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1872 1873 /** 1874 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1875 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1876 * of the synchronization source after prescaling. It is then decreased by one in order to 1877 * reach the expected synchronization on the zero value. The formula is the following: 1878 * RELOAD = (fTARGET / fSYNC) -1 1879 * @param __FTARGET__ Target frequency (value in Hz) 1880 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1881 * @retval None 1882 */ 1883 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1) 1884 1885 #endif /* CRS */ 1886 1887 1888 #if defined(RCC_CR_HSIOUTEN) 1889 /** @brief Enable he HSI OUT . 1890 * @note After reset, the HSI output is not available 1891 */ 1892 1893 #define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN) 1894 1895 /** @brief Disable the HSI OUT . 1896 * @note After reset, the HSI output is not available 1897 */ 1898 1899 #define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN) 1900 1901 #endif /* RCC_CR_HSIOUTEN */ 1902 1903 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)\ 1904 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) 1905 1906 /** 1907 * @brief Enable the Internal High Speed oscillator for USB (HSI48). 1908 * @note After enabling the HSI48, the application software should wait on 1909 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can 1910 * be used to clock the USB. 1911 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 1912 */ 1913 #define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ 1914 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1915 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \ 1916 } while (0) 1917 /** 1918 * @brief Disable the Internal High Speed oscillator for USB (HSI48). 1919 */ 1920 #define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ 1921 CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \ 1922 } while (0) 1923 1924 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. 1925 * @retval The clock source can be one of the following values: 1926 * @arg @ref RCC_HSI48_ON HSI48 enabled 1927 * @arg @ref RCC_HSI48_OFF HSI48 disabled 1928 */ 1929 #define __HAL_RCC_GET_HSI48_STATE() \ 1930 (((uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)) != 0U) ? RCC_HSI48_ON : RCC_HSI48_OFF) 1931 1932 /** @brief Enable or disable the HSI48M DIV6 OUT . 1933 * @note After reset, the HSI48Mhz (divided by 6) output is not available 1934 */ 1935 1936 #define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN) 1937 #define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN) 1938 1939 #endif /* STM32L071xx || STM32L081xx || */ 1940 /* STM32L072xx || STM32L082xx || */ 1941 /* STM32L073xx || STM32L083xx */ 1942 1943 1944 /** 1945 * @} 1946 */ 1947 1948 /* Exported functions --------------------------------------------------------*/ 1949 /** @addtogroup RCCEx_Exported_Functions 1950 * @{ 1951 */ 1952 1953 /** @addtogroup RCCEx_Exported_Functions_Group1 1954 * @{ 1955 */ 1956 1957 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1958 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1959 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1960 1961 1962 void HAL_RCCEx_EnableLSECSS(void); 1963 void HAL_RCCEx_DisableLSECSS(void); 1964 void HAL_RCCEx_EnableLSECSS_IT(void); 1965 void HAL_RCCEx_LSECSS_IRQHandler(void); 1966 void HAL_RCCEx_LSECSS_Callback(void); 1967 1968 1969 #if defined(SYSCFG_CFGR3_ENREF_HSI48) 1970 void HAL_RCCEx_EnableHSI48_VREFINT(void); 1971 void HAL_RCCEx_DisableHSI48_VREFINT(void); 1972 #endif /* SYSCFG_CFGR3_ENREF_HSI48 */ 1973 1974 /** 1975 * @} 1976 */ 1977 1978 #if defined(CRS) 1979 1980 /** @addtogroup RCCEx_Exported_Functions_Group3 1981 * @{ 1982 */ 1983 1984 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1985 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1986 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1987 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1988 void HAL_RCCEx_CRS_IRQHandler(void); 1989 void HAL_RCCEx_CRS_SyncOkCallback(void); 1990 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1991 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1992 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1993 1994 /** 1995 * @} 1996 */ 1997 1998 #endif /* CRS */ 1999 2000 /** 2001 * @} 2002 */ 2003 2004 /** 2005 * @} 2006 */ 2007 2008 /** 2009 * @} 2010 */ 2011 2012 #ifdef __cplusplus 2013 } 2014 #endif 2015 2016 #endif /* __STM32L0xx_HAL_RCC_EX_H */ 2017 2018 2019
