1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F3xx_HAL_RCC_EX_H 20 #define __STM32F3xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f3xx_hal_def.h" 28 29 /** @addtogroup STM32F3xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /** @addtogroup RCCEx_Private_Macros 38 * @{ 39 */ 40 41 #if defined(RCC_CFGR_PLLNODIV) 42 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ 43 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ 44 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 45 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ 46 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ 47 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ 48 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ 49 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2)) 50 #else 51 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ 52 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ 53 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 54 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ 55 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ 56 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ 57 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2)) 58 #endif /* RCC_CFGR_PLLNODIV */ 59 60 #if defined(STM32F301x8) || defined(STM32F318xx) 61 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ 62 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 63 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ 64 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ 65 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ 66 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC)) 67 #endif /* STM32F301x8 || STM32F318xx */ 68 #if defined(STM32F302x8) 69 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ 70 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 71 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ 72 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ 73 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ 74 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ 75 RCC_PERIPHCLK_TIM17)) 76 #endif /* STM32F302x8 */ 77 #if defined(STM32F302xC) 78 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 79 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 80 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 81 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ 82 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ 83 RCC_PERIPHCLK_USB)) 84 #endif /* STM32F302xC */ 85 #if defined(STM32F303xC) 86 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 87 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 88 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 89 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ 90 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ 91 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ 92 RCC_PERIPHCLK_USB)) 93 #endif /* STM32F303xC */ 94 #if defined(STM32F302xE) 95 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 96 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 97 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 98 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ 99 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ 100 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ 101 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ 102 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ 103 RCC_PERIPHCLK_TIM17)) 104 #endif /* STM32F302xE */ 105 #if defined(STM32F303xE) 106 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 107 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 108 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 109 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ 110 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ 111 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ 112 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ 113 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ 114 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ 115 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20)) 116 #endif /* STM32F303xE */ 117 #if defined(STM32F398xx) 118 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 119 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 120 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 121 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ 122 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ 123 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ 124 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \ 125 RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \ 126 RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \ 127 RCC_PERIPHCLK_TIM20)) 128 #endif /* STM32F398xx */ 129 #if defined(STM32F358xx) 130 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 131 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 132 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 133 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ 134 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ 135 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC)) 136 #endif /* STM32F358xx */ 137 #if defined(STM32F303x8) 138 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ 139 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ 140 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) 141 #endif /* STM32F303x8 */ 142 #if defined(STM32F334x8) 143 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ 144 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ 145 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \ 146 RCC_PERIPHCLK_RTC)) 147 #endif /* STM32F334x8 */ 148 #if defined(STM32F328xx) 149 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ 150 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ 151 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) 152 #endif /* STM32F328xx */ 153 #if defined(STM32F373xC) 154 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 155 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 156 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ 157 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ 158 RCC_PERIPHCLK_USB)) 159 #endif /* STM32F373xC */ 160 #if defined(STM32F378xx) 161 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 162 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 163 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ 164 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) 165 #endif /* STM32F378xx */ 166 167 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 168 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ 169 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ 170 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 171 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 172 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 173 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) 174 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ 175 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) 176 #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \ 177 ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \ 178 ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \ 179 ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \ 180 ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \ 181 ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \ 182 ((ADCCLK) == RCC_ADC1PLLCLK_DIV256)) 183 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ 184 ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) 185 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ 186 ((SOURCE) == RCC_TIM1CLK_PLLCLK)) 187 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ 188 ((SOURCE) == RCC_TIM15CLK_PLLCLK)) 189 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ 190 ((SOURCE) == RCC_TIM16CLK_PLLCLK)) 191 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ 192 ((SOURCE) == RCC_TIM17CLK_PLLCLK)) 193 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 194 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 195 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ 196 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ 197 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 198 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 199 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 200 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) 201 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ 202 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ 203 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ 204 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ 205 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ 206 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ 207 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) 208 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ 209 ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) 210 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ 211 ((SOURCE) == RCC_TIM1CLK_PLLCLK)) 212 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ 213 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ 214 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ 215 ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 216 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ 217 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ 218 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ 219 ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 220 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */ 221 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 222 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ 223 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ 224 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 225 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 226 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 227 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) 228 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ 229 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) 230 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ 231 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ 232 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ 233 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ 234 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ 235 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ 236 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) 237 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ 238 ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) 239 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ 240 ((SOURCE) == RCC_TIM1CLK_PLLCLK)) 241 #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \ 242 ((SOURCE) == RCC_TIM2CLK_PLLCLK)) 243 #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \ 244 ((SOURCE) == RCC_TIM34CLK_PLLCLK)) 245 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ 246 ((SOURCE) == RCC_TIM15CLK_PLLCLK)) 247 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ 248 ((SOURCE) == RCC_TIM16CLK_PLLCLK)) 249 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ 250 ((SOURCE) == RCC_TIM17CLK_PLLCLK)) 251 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ 252 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ 253 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ 254 ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 255 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ 256 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ 257 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ 258 ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 259 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 260 #if defined(STM32F303xE) || defined(STM32F398xx) 261 #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \ 262 ((SOURCE) == RCC_TIM20CLK_PLLCLK)) 263 #endif /* STM32F303xE || STM32F398xx */ 264 #if defined(STM32F303xE) || defined(STM32F398xx)\ 265 || defined(STM32F303xC) || defined(STM32F358xx) 266 #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \ 267 ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \ 268 ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \ 269 ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \ 270 ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \ 271 ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \ 272 ((ADCCLK) == RCC_ADC34PLLCLK_DIV256)) 273 #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \ 274 ((SOURCE) == RCC_TIM8CLK_PLLCLK)) 275 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ 276 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 277 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ 278 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ 279 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 280 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 281 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ 282 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ 283 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ 284 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ 285 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ 286 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ 287 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) 288 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ 289 ((SOURCE) == RCC_TIM1CLK_PLLCLK)) 290 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 291 #if defined(STM32F334x8) 292 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \ 293 ((SOURCE) == RCC_HRTIM1CLK_PLLCLK)) 294 #endif /* STM32F334x8 */ 295 #if defined(STM32F373xC) || defined(STM32F378xx) 296 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ 297 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ 298 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 299 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 300 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ 301 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) 302 #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \ 303 ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8)) 304 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ 305 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 306 #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \ 307 ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \ 308 ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \ 309 ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \ 310 ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \ 311 ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \ 312 ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \ 313 ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \ 314 ((DIV) == RCC_SDADCSYSCLK_DIV48)) 315 #endif /* STM32F373xC || STM32F378xx */ 316 #if defined(STM32F302xE) || defined(STM32F303xE)\ 317 || defined(STM32F302xC) || defined(STM32F303xC)\ 318 || defined(STM32F302x8) \ 319 || defined(STM32F373xC) 320 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ 321 ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5)) 322 #endif /* STM32F302xE || STM32F303xE || */ 323 /* STM32F302xC || STM32F303xC || */ 324 /* STM32F302x8 || */ 325 /* STM32F373xC */ 326 #if defined(RCC_CFGR_MCOPRE) 327 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 328 ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ 329 ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ 330 ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) 331 #else 332 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) 333 #endif /* RCC_CFGR_MCOPRE */ 334 335 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 336 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 337 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 338 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 339 340 /** 341 * @} 342 */ 343 344 /* Exported types ------------------------------------------------------------*/ 345 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 346 * @{ 347 */ 348 349 /** 350 * @brief RCC extended clocks structure definition 351 */ 352 #if defined(STM32F301x8) || defined(STM32F318xx) 353 typedef struct 354 { 355 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 356 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 357 358 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 359 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 360 361 uint32_t Usart1ClockSelection; /*!< USART1 clock source 362 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 363 364 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 365 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 366 367 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 368 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 369 370 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 371 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 372 373 uint32_t Adc1ClockSelection; /*!< ADC1 clock source 374 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ 375 376 uint32_t I2sClockSelection; /*!< I2S clock source 377 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 378 379 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 380 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 381 382 uint32_t Tim15ClockSelection; /*!< TIM15 clock source 383 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ 384 385 uint32_t Tim16ClockSelection; /*!< TIM16 clock source 386 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ 387 388 uint32_t Tim17ClockSelection; /*!< TIM17 clock source 389 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ 390 }RCC_PeriphCLKInitTypeDef; 391 #endif /* STM32F301x8 || STM32F318xx */ 392 393 #if defined(STM32F302x8) 394 typedef struct 395 { 396 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 397 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 398 399 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 400 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 401 402 uint32_t Usart1ClockSelection; /*!< USART1 clock source 403 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 404 405 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 406 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 407 408 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 409 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 410 411 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 412 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 413 414 uint32_t Adc1ClockSelection; /*!< ADC1 clock source 415 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ 416 417 uint32_t I2sClockSelection; /*!< I2S clock source 418 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 419 420 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 421 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 422 423 uint32_t Tim15ClockSelection; /*!< TIM15 clock source 424 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ 425 426 uint32_t Tim16ClockSelection; /*!< TIM16 clock source 427 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ 428 429 uint32_t Tim17ClockSelection; /*!< TIM17 clock source 430 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ 431 432 uint32_t USBClockSelection; /*!< USB clock source 433 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 434 435 }RCC_PeriphCLKInitTypeDef; 436 #endif /* STM32F302x8 */ 437 438 #if defined(STM32F302xC) 439 typedef struct 440 { 441 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 442 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 443 444 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 445 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 446 447 uint32_t Usart1ClockSelection; /*!< USART1 clock source 448 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 449 450 uint32_t Usart2ClockSelection; /*!< USART2 clock source 451 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 452 453 uint32_t Usart3ClockSelection; /*!< USART3 clock source 454 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 455 456 uint32_t Uart4ClockSelection; /*!< UART4 clock source 457 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 458 459 uint32_t Uart5ClockSelection; /*!< UART5 clock source 460 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 461 462 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 463 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 464 465 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 466 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 467 468 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 469 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 470 471 uint32_t I2sClockSelection; /*!< I2S clock source 472 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 473 474 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 475 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 476 477 uint32_t USBClockSelection; /*!< USB clock source 478 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 479 480 }RCC_PeriphCLKInitTypeDef; 481 #endif /* STM32F302xC */ 482 483 #if defined(STM32F303xC) 484 typedef struct 485 { 486 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 487 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 488 489 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 490 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 491 492 uint32_t Usart1ClockSelection; /*!< USART1 clock source 493 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 494 495 uint32_t Usart2ClockSelection; /*!< USART2 clock source 496 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 497 498 uint32_t Usart3ClockSelection; /*!< USART3 clock source 499 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 500 501 uint32_t Uart4ClockSelection; /*!< UART4 clock source 502 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 503 504 uint32_t Uart5ClockSelection; /*!< UART5 clock source 505 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 506 507 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 508 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 509 510 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 511 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 512 513 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 514 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 515 516 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source 517 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ 518 519 uint32_t I2sClockSelection; /*!< I2S clock source 520 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 521 522 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 523 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 524 525 uint32_t Tim8ClockSelection; /*!< TIM8 clock source 526 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ 527 528 uint32_t USBClockSelection; /*!< USB clock source 529 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 530 531 }RCC_PeriphCLKInitTypeDef; 532 #endif /* STM32F303xC */ 533 534 #if defined(STM32F302xE) 535 typedef struct 536 { 537 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 538 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 539 540 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 541 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 542 543 uint32_t Usart1ClockSelection; /*!< USART1 clock source 544 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 545 546 uint32_t Usart2ClockSelection; /*!< USART2 clock source 547 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 548 549 uint32_t Usart3ClockSelection; /*!< USART3 clock source 550 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 551 552 uint32_t Uart4ClockSelection; /*!< UART4 clock source 553 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 554 555 uint32_t Uart5ClockSelection; /*!< UART5 clock source 556 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 557 558 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 559 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 560 561 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 562 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 563 564 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 565 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 566 567 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 568 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 569 570 uint32_t I2sClockSelection; /*!< I2S clock source 571 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 572 573 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 574 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 575 576 uint32_t Tim2ClockSelection; /*!< TIM2 clock source 577 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ 578 579 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source 580 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ 581 582 uint32_t Tim15ClockSelection; /*!< TIM15 clock source 583 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ 584 585 uint32_t Tim16ClockSelection; /*!< TIM16 clock source 586 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ 587 588 uint32_t Tim17ClockSelection; /*!< TIM17 clock source 589 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ 590 591 uint32_t USBClockSelection; /*!< USB clock source 592 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 593 594 }RCC_PeriphCLKInitTypeDef; 595 #endif /* STM32F302xE */ 596 597 #if defined(STM32F303xE) 598 typedef struct 599 { 600 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 601 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 602 603 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 604 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 605 606 uint32_t Usart1ClockSelection; /*!< USART1 clock source 607 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 608 609 uint32_t Usart2ClockSelection; /*!< USART2 clock source 610 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 611 612 uint32_t Usart3ClockSelection; /*!< USART3 clock source 613 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 614 615 uint32_t Uart4ClockSelection; /*!< UART4 clock source 616 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 617 618 uint32_t Uart5ClockSelection; /*!< UART5 clock source 619 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 620 621 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 622 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 623 624 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 625 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 626 627 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 628 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 629 630 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 631 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 632 633 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source 634 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ 635 636 uint32_t I2sClockSelection; /*!< I2S clock source 637 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 638 639 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 640 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 641 642 uint32_t Tim2ClockSelection; /*!< TIM2 clock source 643 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ 644 645 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source 646 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ 647 648 uint32_t Tim8ClockSelection; /*!< TIM8 clock source 649 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ 650 651 uint32_t Tim15ClockSelection; /*!< TIM15 clock source 652 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ 653 654 uint32_t Tim16ClockSelection; /*!< TIM16 clock source 655 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ 656 657 uint32_t Tim17ClockSelection; /*!< TIM17 clock source 658 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ 659 660 uint32_t Tim20ClockSelection; /*!< TIM20 clock source 661 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ 662 663 uint32_t USBClockSelection; /*!< USB clock source 664 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 665 666 }RCC_PeriphCLKInitTypeDef; 667 #endif /* STM32F303xE */ 668 669 #if defined(STM32F398xx) 670 typedef struct 671 { 672 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 673 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 674 675 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 676 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 677 678 uint32_t Usart1ClockSelection; /*!< USART1 clock source 679 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 680 681 uint32_t Usart2ClockSelection; /*!< USART2 clock source 682 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 683 684 uint32_t Usart3ClockSelection; /*!< USART3 clock source 685 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 686 687 uint32_t Uart4ClockSelection; /*!< UART4 clock source 688 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 689 690 uint32_t Uart5ClockSelection; /*!< UART5 clock source 691 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 692 693 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 694 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 695 696 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 697 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 698 699 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 700 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 701 702 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 703 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 704 705 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source 706 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ 707 708 uint32_t I2sClockSelection; /*!< I2S clock source 709 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 710 711 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 712 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 713 714 uint32_t Tim2ClockSelection; /*!< TIM2 clock source 715 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ 716 717 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source 718 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ 719 720 uint32_t Tim8ClockSelection; /*!< TIM8 clock source 721 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ 722 723 uint32_t Tim15ClockSelection; /*!< TIM15 clock source 724 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ 725 726 uint32_t Tim16ClockSelection; /*!< TIM16 clock source 727 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ 728 729 uint32_t Tim17ClockSelection; /*!< TIM17 clock source 730 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ 731 732 uint32_t Tim20ClockSelection; /*!< TIM20 clock source 733 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ 734 735 }RCC_PeriphCLKInitTypeDef; 736 #endif /* STM32F398xx */ 737 738 #if defined(STM32F358xx) 739 typedef struct 740 { 741 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 742 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 743 744 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 745 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 746 747 uint32_t Usart1ClockSelection; /*!< USART1 clock source 748 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 749 750 uint32_t Usart2ClockSelection; /*!< USART2 clock source 751 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 752 753 uint32_t Usart3ClockSelection; /*!< USART3 clock source 754 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 755 756 uint32_t Uart4ClockSelection; /*!< UART4 clock source 757 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 758 759 uint32_t Uart5ClockSelection; /*!< UART5 clock source 760 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 761 762 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 763 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 764 765 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 766 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 767 768 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 769 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 770 771 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source 772 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ 773 774 uint32_t I2sClockSelection; /*!< I2S clock source 775 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 776 777 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 778 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 779 780 uint32_t Tim8ClockSelection; /*!< TIM8 clock source 781 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ 782 783 }RCC_PeriphCLKInitTypeDef; 784 #endif /* STM32F358xx */ 785 786 #if defined(STM32F303x8) 787 typedef struct 788 { 789 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 790 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 791 792 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 793 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 794 795 uint32_t Usart1ClockSelection; /*!< USART1 clock source 796 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 797 798 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 799 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 800 801 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 802 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 803 804 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 805 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 806 807 }RCC_PeriphCLKInitTypeDef; 808 #endif /* STM32F303x8 */ 809 810 #if defined(STM32F334x8) 811 typedef struct 812 { 813 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 814 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 815 816 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 817 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 818 819 uint32_t Usart1ClockSelection; /*!< USART1 clock source 820 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 821 822 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 823 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 824 825 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 826 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 827 828 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 829 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 830 831 uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source 832 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ 833 834 }RCC_PeriphCLKInitTypeDef; 835 #endif /* STM32F334x8 */ 836 837 #if defined(STM32F328xx) 838 typedef struct 839 { 840 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 841 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 842 843 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 844 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 845 846 uint32_t Usart1ClockSelection; /*!< USART1 clock source 847 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 848 849 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 850 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 851 852 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source 853 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 854 855 uint32_t Tim1ClockSelection; /*!< TIM1 clock source 856 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ 857 858 }RCC_PeriphCLKInitTypeDef; 859 #endif /* STM32F328xx */ 860 861 #if defined(STM32F373xC) 862 typedef struct 863 { 864 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 865 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 866 867 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 868 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 869 870 uint32_t Usart1ClockSelection; /*!< USART1 clock source 871 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 872 873 uint32_t Usart2ClockSelection; /*!< USART2 clock source 874 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 875 876 uint32_t Usart3ClockSelection; /*!< USART3 clock source 877 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 878 879 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 880 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 881 882 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 883 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 884 885 uint32_t Adc1ClockSelection; /*!< ADC1 clock source 886 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ 887 888 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler 889 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ 890 891 uint32_t CecClockSelection; /*!< HDMI CEC clock source 892 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 893 894 uint32_t USBClockSelection; /*!< USB clock source 895 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 896 897 }RCC_PeriphCLKInitTypeDef; 898 #endif /* STM32F373xC */ 899 900 #if defined(STM32F378xx) 901 typedef struct 902 { 903 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 904 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 905 906 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 907 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 908 909 uint32_t Usart1ClockSelection; /*!< USART1 clock source 910 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 911 912 uint32_t Usart2ClockSelection; /*!< USART2 clock source 913 This parameter can be a value of @ref RCC_USART2_Clock_Source */ 914 915 uint32_t Usart3ClockSelection; /*!< USART3 clock source 916 This parameter can be a value of @ref RCC_USART3_Clock_Source */ 917 918 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 919 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 920 921 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 922 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 923 924 uint32_t Adc1ClockSelection; /*!< ADC1 clock source 925 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ 926 927 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler 928 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ 929 930 uint32_t CecClockSelection; /*!< HDMI CEC clock source 931 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 932 933 }RCC_PeriphCLKInitTypeDef; 934 #endif /* STM32F378xx */ 935 936 /** 937 * @} 938 */ 939 940 /* Exported constants --------------------------------------------------------*/ 941 /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants 942 * @{ 943 */ 944 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source 945 * @{ 946 */ 947 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK 948 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI 949 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE 950 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK 951 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI 952 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE 953 #if defined(RCC_CFGR_PLLNODIV) 954 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL) 955 #endif /* RCC_CFGR_PLLNODIV */ 956 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL 957 958 /** 959 * @} 960 */ 961 962 /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection 963 * @{ 964 */ 965 #if defined(STM32F301x8) || defined(STM32F318xx) 966 #define RCC_PERIPHCLK_USART1 (0x00000001U) 967 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 968 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 969 #define RCC_PERIPHCLK_ADC1 (0x00000080U) 970 #define RCC_PERIPHCLK_I2S (0x00000200U) 971 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 972 #define RCC_PERIPHCLK_I2C3 (0x00008000U) 973 #define RCC_PERIPHCLK_RTC (0x00010000U) 974 #define RCC_PERIPHCLK_TIM15 (0x00040000U) 975 #define RCC_PERIPHCLK_TIM16 (0x00080000U) 976 #define RCC_PERIPHCLK_TIM17 (0x00100000U) 977 978 #endif /* STM32F301x8 || STM32F318xx */ 979 980 #if defined(STM32F302x8) 981 #define RCC_PERIPHCLK_USART1 (0x00000001U) 982 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 983 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 984 #define RCC_PERIPHCLK_ADC1 (0x00000080U) 985 #define RCC_PERIPHCLK_I2S (0x00000200U) 986 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 987 #define RCC_PERIPHCLK_I2C3 (0x00008000U) 988 #define RCC_PERIPHCLK_RTC (0x00010000U) 989 #define RCC_PERIPHCLK_USB (0x00020000U) 990 #define RCC_PERIPHCLK_TIM15 (0x00040000U) 991 #define RCC_PERIPHCLK_TIM16 (0x00080000U) 992 #define RCC_PERIPHCLK_TIM17 (0x00100000U) 993 994 995 #endif /* STM32F302x8 */ 996 997 #if defined(STM32F302xC) 998 #define RCC_PERIPHCLK_USART1 (0x00000001U) 999 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1000 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1001 #define RCC_PERIPHCLK_UART4 (0x00000008U) 1002 #define RCC_PERIPHCLK_UART5 (0x00000010U) 1003 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1004 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1005 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1006 #define RCC_PERIPHCLK_I2S (0x00000200U) 1007 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1008 #define RCC_PERIPHCLK_RTC (0x00010000U) 1009 #define RCC_PERIPHCLK_USB (0x00020000U) 1010 1011 #endif /* STM32F302xC */ 1012 1013 #if defined(STM32F303xC) 1014 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1015 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1016 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1017 #define RCC_PERIPHCLK_UART4 (0x00000008U) 1018 #define RCC_PERIPHCLK_UART5 (0x00000010U) 1019 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1020 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1021 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1022 #define RCC_PERIPHCLK_ADC34 (0x00000100U) 1023 #define RCC_PERIPHCLK_I2S (0x00000200U) 1024 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1025 #define RCC_PERIPHCLK_TIM8 (0x00002000U) 1026 #define RCC_PERIPHCLK_RTC (0x00010000U) 1027 #define RCC_PERIPHCLK_USB (0x00020000U) 1028 1029 #endif /* STM32F303xC */ 1030 1031 #if defined(STM32F302xE) 1032 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1033 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1034 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1035 #define RCC_PERIPHCLK_UART4 (0x00000008U) 1036 #define RCC_PERIPHCLK_UART5 (0x00000010U) 1037 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1038 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1039 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1040 #define RCC_PERIPHCLK_I2S (0x00000200U) 1041 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1042 #define RCC_PERIPHCLK_RTC (0x00010000U) 1043 #define RCC_PERIPHCLK_USB (0x00020000U) 1044 #define RCC_PERIPHCLK_I2C3 (0x00040000U) 1045 #define RCC_PERIPHCLK_TIM2 (0x00100000U) 1046 #define RCC_PERIPHCLK_TIM34 (0x00200000U) 1047 #define RCC_PERIPHCLK_TIM15 (0x00400000U) 1048 #define RCC_PERIPHCLK_TIM16 (0x00800000U) 1049 #define RCC_PERIPHCLK_TIM17 (0x01000000U) 1050 1051 #endif /* STM32F302xE */ 1052 1053 #if defined(STM32F303xE) 1054 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1055 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1056 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1057 #define RCC_PERIPHCLK_UART4 (0x00000008U) 1058 #define RCC_PERIPHCLK_UART5 (0x00000010U) 1059 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1060 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1061 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1062 #define RCC_PERIPHCLK_ADC34 (0x00000100U) 1063 #define RCC_PERIPHCLK_I2S (0x00000200U) 1064 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1065 #define RCC_PERIPHCLK_TIM8 (0x00002000U) 1066 #define RCC_PERIPHCLK_RTC (0x00010000U) 1067 #define RCC_PERIPHCLK_USB (0x00020000U) 1068 #define RCC_PERIPHCLK_I2C3 (0x00040000U) 1069 #define RCC_PERIPHCLK_TIM2 (0x00100000U) 1070 #define RCC_PERIPHCLK_TIM34 (0x00200000U) 1071 #define RCC_PERIPHCLK_TIM15 (0x00400000U) 1072 #define RCC_PERIPHCLK_TIM16 (0x00800000U) 1073 #define RCC_PERIPHCLK_TIM17 (0x01000000U) 1074 #define RCC_PERIPHCLK_TIM20 (0x02000000U) 1075 1076 #endif /* STM32F303xE */ 1077 1078 #if defined(STM32F398xx) 1079 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1080 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1081 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1082 #define RCC_PERIPHCLK_UART4 (0x00000008U) 1083 #define RCC_PERIPHCLK_UART5 (0x00000010U) 1084 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1085 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1086 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1087 #define RCC_PERIPHCLK_ADC34 (0x00000100U) 1088 #define RCC_PERIPHCLK_I2S (0x00000200U) 1089 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1090 #define RCC_PERIPHCLK_TIM8 (0x00002000U) 1091 #define RCC_PERIPHCLK_RTC (0x00010000U) 1092 #define RCC_PERIPHCLK_I2C3 (0x00040000U) 1093 #define RCC_PERIPHCLK_TIM2 (0x00100000U) 1094 #define RCC_PERIPHCLK_TIM34 (0x00200000U) 1095 #define RCC_PERIPHCLK_TIM15 (0x00400000U) 1096 #define RCC_PERIPHCLK_TIM16 (0x00800000U) 1097 #define RCC_PERIPHCLK_TIM17 (0x01000000U) 1098 #define RCC_PERIPHCLK_TIM20 (0x02000000U) 1099 1100 1101 #endif /* STM32F398xx */ 1102 1103 #if defined(STM32F358xx) 1104 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1105 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1106 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1107 #define RCC_PERIPHCLK_UART4 (0x00000008U) 1108 #define RCC_PERIPHCLK_UART5 (0x00000010U) 1109 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1110 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1111 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1112 #define RCC_PERIPHCLK_ADC34 (0x00000100U) 1113 #define RCC_PERIPHCLK_I2S (0x00000200U) 1114 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1115 #define RCC_PERIPHCLK_TIM8 (0x00002000U) 1116 #define RCC_PERIPHCLK_RTC (0x00010000U) 1117 1118 #endif /* STM32F358xx */ 1119 1120 #if defined(STM32F303x8) 1121 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1122 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1123 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1124 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1125 #define RCC_PERIPHCLK_RTC (0x00010000U) 1126 1127 #endif /* STM32F303x8 */ 1128 1129 #if defined(STM32F334x8) 1130 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1131 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1132 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1133 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1134 #define RCC_PERIPHCLK_HRTIM1 (0x00004000U) 1135 #define RCC_PERIPHCLK_RTC (0x00010000U) 1136 1137 1138 #endif /* STM32F334x8 */ 1139 1140 #if defined(STM32F328xx) 1141 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1142 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1143 #define RCC_PERIPHCLK_ADC12 (0x00000080U) 1144 #define RCC_PERIPHCLK_TIM1 (0x00001000U) 1145 #define RCC_PERIPHCLK_RTC (0x00010000U) 1146 1147 #endif /* STM32F328xx */ 1148 1149 #if defined(STM32F373xC) 1150 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1151 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1152 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1153 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1154 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1155 #define RCC_PERIPHCLK_ADC1 (0x00000080U) 1156 #define RCC_PERIPHCLK_CEC (0x00000400U) 1157 #define RCC_PERIPHCLK_SDADC (0x00000800U) 1158 #define RCC_PERIPHCLK_RTC (0x00010000U) 1159 #define RCC_PERIPHCLK_USB (0x00020000U) 1160 1161 #endif /* STM32F373xC */ 1162 1163 #if defined(STM32F378xx) 1164 #define RCC_PERIPHCLK_USART1 (0x00000001U) 1165 #define RCC_PERIPHCLK_USART2 (0x00000002U) 1166 #define RCC_PERIPHCLK_USART3 (0x00000004U) 1167 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 1168 #define RCC_PERIPHCLK_I2C2 (0x00000040U) 1169 #define RCC_PERIPHCLK_ADC1 (0x00000080U) 1170 #define RCC_PERIPHCLK_CEC (0x00000400U) 1171 #define RCC_PERIPHCLK_SDADC (0x00000800U) 1172 #define RCC_PERIPHCLK_RTC (0x00010000U) 1173 1174 #endif /* STM32F378xx */ 1175 /** 1176 * @} 1177 */ 1178 1179 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 1180 1181 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source 1182 * @{ 1183 */ 1184 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1 1185 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK 1186 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE 1187 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI 1188 1189 /** 1190 * @} 1191 */ 1192 1193 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source 1194 * @{ 1195 */ 1196 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI 1197 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK 1198 1199 /** 1200 * @} 1201 */ 1202 1203 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source 1204 * @{ 1205 */ 1206 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI 1207 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK 1208 1209 /** 1210 * @} 1211 */ 1212 1213 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source 1214 * @{ 1215 */ 1216 #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO 1217 #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1 1218 #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2 1219 #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4 1220 #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6 1221 #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8 1222 #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10 1223 #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12 1224 #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16 1225 #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32 1226 #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64 1227 #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128 1228 #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256 1229 1230 /** 1231 * @} 1232 */ 1233 1234 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source 1235 * @{ 1236 */ 1237 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK 1238 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT 1239 1240 /** 1241 * @} 1242 */ 1243 1244 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source 1245 * @{ 1246 */ 1247 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK 1248 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL 1249 1250 /** 1251 * @} 1252 */ 1253 1254 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source 1255 * @{ 1256 */ 1257 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK 1258 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL 1259 1260 /** 1261 * @} 1262 */ 1263 1264 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source 1265 * @{ 1266 */ 1267 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK 1268 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL 1269 1270 /** 1271 * @} 1272 */ 1273 1274 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source 1275 * @{ 1276 */ 1277 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK 1278 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL 1279 1280 /** 1281 * @} 1282 */ 1283 1284 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1285 1286 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 1287 1288 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source 1289 * @{ 1290 */ 1291 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 1292 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK 1293 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE 1294 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI 1295 1296 /** 1297 * @} 1298 */ 1299 1300 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source 1301 * @{ 1302 */ 1303 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI 1304 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK 1305 1306 /** 1307 * @} 1308 */ 1309 1310 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source 1311 * @{ 1312 */ 1313 1314 /* ADC1 & ADC2 */ 1315 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO 1316 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 1317 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 1318 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 1319 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 1320 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 1321 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 1322 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 1323 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 1324 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 1325 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 1326 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 1327 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 1328 1329 /** 1330 * @} 1331 */ 1332 1333 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source 1334 * @{ 1335 */ 1336 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK 1337 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT 1338 1339 /** 1340 * @} 1341 */ 1342 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source 1343 * @{ 1344 */ 1345 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK 1346 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL 1347 1348 /** 1349 * @} 1350 */ 1351 1352 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source 1353 * @{ 1354 */ 1355 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK 1356 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK 1357 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE 1358 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI 1359 1360 /** 1361 * @} 1362 */ 1363 1364 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source 1365 * @{ 1366 */ 1367 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK 1368 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK 1369 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE 1370 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI 1371 1372 /** 1373 * @} 1374 */ 1375 1376 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */ 1377 1378 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 1379 1380 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source 1381 * @{ 1382 */ 1383 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 1384 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK 1385 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE 1386 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI 1387 1388 /** 1389 * @} 1390 */ 1391 1392 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source 1393 * @{ 1394 */ 1395 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI 1396 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK 1397 1398 /** 1399 * @} 1400 */ 1401 1402 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source 1403 * @{ 1404 */ 1405 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI 1406 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK 1407 1408 /** 1409 * @} 1410 */ 1411 1412 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source 1413 * @{ 1414 */ 1415 1416 /* ADC1 & ADC2 */ 1417 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO 1418 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 1419 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 1420 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 1421 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 1422 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 1423 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 1424 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 1425 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 1426 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 1427 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 1428 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 1429 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 1430 1431 /** 1432 * @} 1433 */ 1434 1435 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source 1436 * @{ 1437 */ 1438 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK 1439 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT 1440 1441 /** 1442 * @} 1443 */ 1444 1445 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source 1446 * @{ 1447 */ 1448 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK 1449 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL 1450 1451 /** 1452 * @} 1453 */ 1454 1455 /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source 1456 * @{ 1457 */ 1458 #define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK 1459 #define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL 1460 1461 /** 1462 * @} 1463 */ 1464 1465 /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source 1466 * @{ 1467 */ 1468 #define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK 1469 #define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL 1470 1471 /** 1472 * @} 1473 */ 1474 1475 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source 1476 * @{ 1477 */ 1478 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK 1479 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL 1480 1481 /** 1482 * @} 1483 */ 1484 1485 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source 1486 * @{ 1487 */ 1488 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK 1489 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL 1490 1491 /** 1492 * @} 1493 */ 1494 1495 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source 1496 * @{ 1497 */ 1498 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK 1499 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL 1500 1501 /** 1502 * @} 1503 */ 1504 1505 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source 1506 * @{ 1507 */ 1508 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK 1509 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK 1510 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE 1511 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI 1512 1513 /** 1514 * @} 1515 */ 1516 1517 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source 1518 * @{ 1519 */ 1520 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK 1521 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK 1522 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE 1523 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI 1524 1525 /** 1526 * @} 1527 */ 1528 1529 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 1530 1531 #if defined(STM32F303xE) || defined(STM32F398xx) 1532 /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source 1533 * @{ 1534 */ 1535 #define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK 1536 #define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL 1537 1538 /** 1539 * @} 1540 */ 1541 #endif /* STM32F303xE || STM32F398xx */ 1542 1543 #if defined(STM32F303xE) || defined(STM32F398xx)\ 1544 || defined(STM32F303xC) || defined(STM32F358xx) 1545 1546 /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source 1547 * @{ 1548 */ 1549 1550 /* ADC3 & ADC4 */ 1551 #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO 1552 #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1 1553 #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2 1554 #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4 1555 #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6 1556 #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8 1557 #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10 1558 #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12 1559 #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16 1560 #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32 1561 #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64 1562 #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128 1563 #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256 1564 1565 /** 1566 * @} 1567 */ 1568 1569 /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source 1570 * @{ 1571 */ 1572 #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK 1573 #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL 1574 1575 /** 1576 * @} 1577 */ 1578 1579 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ 1580 1581 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 1582 1583 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source 1584 * @{ 1585 */ 1586 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1 1587 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK 1588 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE 1589 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI 1590 1591 /** 1592 * @} 1593 */ 1594 1595 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source 1596 * @{ 1597 */ 1598 /* ADC1 & ADC2 */ 1599 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO 1600 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 1601 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 1602 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 1603 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 1604 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 1605 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 1606 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 1607 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 1608 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 1609 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 1610 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 1611 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 1612 1613 /** 1614 * @} 1615 */ 1616 1617 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source 1618 * @{ 1619 */ 1620 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK 1621 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL 1622 1623 /** 1624 * @} 1625 */ 1626 1627 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 1628 1629 #if defined(STM32F334x8) 1630 1631 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source 1632 * @{ 1633 */ 1634 #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK 1635 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL 1636 1637 /** 1638 * @} 1639 */ 1640 1641 #endif /* STM32F334x8 */ 1642 1643 #if defined(STM32F373xC) || defined(STM32F378xx) 1644 1645 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source 1646 * @{ 1647 */ 1648 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 1649 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK 1650 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE 1651 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI 1652 1653 /** 1654 * @} 1655 */ 1656 1657 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source 1658 * @{ 1659 */ 1660 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI 1661 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK 1662 1663 /** 1664 * @} 1665 */ 1666 1667 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source 1668 * @{ 1669 */ 1670 1671 /* ADC1 */ 1672 #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 1673 #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 1674 #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 1675 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 1676 1677 /** 1678 * @} 1679 */ 1680 1681 /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source 1682 * @{ 1683 */ 1684 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 1685 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE 1686 1687 /** 1688 * @} 1689 */ 1690 1691 /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler 1692 * @{ 1693 */ 1694 #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1 1695 #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2 1696 #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4 1697 #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6 1698 #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8 1699 #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10 1700 #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12 1701 #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14 1702 #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16 1703 #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20 1704 #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24 1705 #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28 1706 #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32 1707 #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36 1708 #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40 1709 #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44 1710 #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48 1711 1712 /** 1713 * @} 1714 */ 1715 1716 #endif /* STM32F373xC || STM32F378xx */ 1717 1718 #if defined(STM32F302xE) || defined(STM32F303xE)\ 1719 || defined(STM32F302xC) || defined(STM32F303xC)\ 1720 || defined(STM32F302x8) \ 1721 || defined(STM32F373xC) 1722 /** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source 1723 * @{ 1724 */ 1725 1726 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 1727 #define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5 1728 1729 /** 1730 * @} 1731 */ 1732 1733 #endif /* STM32F302xE || STM32F303xE || */ 1734 /* STM32F302xC || STM32F303xC || */ 1735 /* STM32F302x8 || */ 1736 /* STM32F373xC */ 1737 1738 1739 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler 1740 * @{ 1741 */ 1742 #if defined(RCC_CFGR_MCOPRE) 1743 1744 #define RCC_MCODIV_1 (0x00000000U) 1745 #define RCC_MCODIV_2 (0x10000000U) 1746 #define RCC_MCODIV_4 (0x20000000U) 1747 #define RCC_MCODIV_8 (0x30000000U) 1748 #define RCC_MCODIV_16 (0x40000000U) 1749 #define RCC_MCODIV_32 (0x50000000U) 1750 #define RCC_MCODIV_64 (0x60000000U) 1751 #define RCC_MCODIV_128 (0x70000000U) 1752 1753 #else 1754 1755 #define RCC_MCODIV_1 (0x00000000U) 1756 1757 #endif /* RCC_CFGR_MCOPRE */ 1758 1759 /** 1760 * @} 1761 */ 1762 1763 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration 1764 * @{ 1765 */ 1766 1767 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ 1768 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ 1769 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ 1770 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ 1771 1772 /** 1773 * @} 1774 */ 1775 1776 /** 1777 * @} 1778 */ 1779 1780 /* Exported macro ------------------------------------------------------------*/ 1781 /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros 1782 * @{ 1783 */ 1784 1785 /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration 1786 * @{ 1787 */ 1788 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 1789 /** @brief Macro to configure the PLL clock source, multiplication and division factors. 1790 * @note This macro must be used only when the PLL is disabled. 1791 * 1792 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 1793 * This parameter can be one of the following values: 1794 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 1795 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 1796 * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock 1797 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. 1798 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock 1799 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. 1800 * 1801 */ 1802 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ 1803 do { \ 1804 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ 1805 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ 1806 } while(0U) 1807 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 1808 1809 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ 1810 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 1811 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ 1812 || defined(STM32F373xC) || defined(STM32F378xx) 1813 /** @brief Macro to configure the PLL clock source and multiplication factor. 1814 * @note This macro must be used only when the PLL is disabled. 1815 * 1816 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 1817 * This parameter can be one of the following values: 1818 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 1819 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 1820 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock 1821 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. 1822 * 1823 */ 1824 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \ 1825 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))) 1826 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ 1827 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 1828 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1829 /* STM32F373xC || STM32F378xx */ 1830 /** 1831 * @} 1832 */ 1833 1834 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ 1835 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 1836 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ 1837 || defined(STM32F373xC) || defined(STM32F378xx) 1838 /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration 1839 * @{ 1840 */ 1841 1842 /** 1843 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 1844 * @note Predivision factor can not be changed if PLL is used as system clock 1845 * In this case, you have to select another source of the system clock, disable the PLL and 1846 * then change the HSE predivision factor. 1847 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 1848 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. 1849 */ 1850 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ 1851 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) 1852 1853 /** 1854 * @brief Macro to get prediv1 factor for PLL. 1855 */ 1856 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV) 1857 1858 /** 1859 * @} 1860 */ 1861 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ 1862 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 1863 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1864 /* STM32F373xC || STM32F378xx */ 1865 1866 /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable 1867 * @brief Enable or disable the AHB peripheral clock. 1868 * @note After reset, the peripheral clock (used for registers read/write access) 1869 * is disabled and the application software has to enable this clock before 1870 * using it. 1871 * @{ 1872 */ 1873 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 1874 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 1875 __IO uint32_t tmpreg; \ 1876 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ 1877 /* Delay after an RCC peripheral clock enabling */ \ 1878 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ 1879 UNUSED(tmpreg); \ 1880 } while(0U) 1881 1882 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN)) 1883 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1884 1885 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 1886 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 1887 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 1888 __IO uint32_t tmpreg; \ 1889 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 1890 /* Delay after an RCC peripheral clock enabling */ \ 1891 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 1892 UNUSED(tmpreg); \ 1893 } while(0U) 1894 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 1895 __IO uint32_t tmpreg; \ 1896 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 1897 /* Delay after an RCC peripheral clock enabling */ \ 1898 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 1899 UNUSED(tmpreg); \ 1900 } while(0U) 1901 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 1902 __IO uint32_t tmpreg; \ 1903 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ 1904 /* Delay after an RCC peripheral clock enabling */ \ 1905 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ 1906 UNUSED(tmpreg); \ 1907 } while(0U) 1908 /* Aliases for STM32 F3 compatibility */ 1909 #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() 1910 #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() 1911 1912 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 1913 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) 1914 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) 1915 /* Aliases for STM32 F3 compatibility */ 1916 #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() 1917 #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() 1918 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 1919 /* STM32F302xC || STM32F303xC || STM32F358xx */ 1920 1921 #if defined(STM32F303xE) || defined(STM32F398xx)\ 1922 || defined(STM32F303xC) || defined(STM32F358xx) 1923 #define __HAL_RCC_ADC34_CLK_ENABLE() do { \ 1924 __IO uint32_t tmpreg; \ 1925 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\ 1926 /* Delay after an RCC peripheral clock enabling */ \ 1927 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\ 1928 UNUSED(tmpreg); \ 1929 } while(0U) 1930 #define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN)) 1931 #endif /* STM32F303xE || STM32F398xx || */ 1932 /* STM32F303xC || STM32F358xx */ 1933 1934 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 1935 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 1936 __IO uint32_t tmpreg; \ 1937 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ 1938 /* Delay after an RCC peripheral clock enabling */ \ 1939 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ 1940 UNUSED(tmpreg); \ 1941 } while(0U) 1942 /* Aliases for STM32 F3 compatibility */ 1943 #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() 1944 #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() 1945 1946 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) 1947 /* Aliases for STM32 F3 compatibility */ 1948 #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() 1949 #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() 1950 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 1951 1952 #if defined(STM32F373xC) || defined(STM32F378xx) 1953 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 1954 __IO uint32_t tmpreg; \ 1955 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 1956 /* Delay after an RCC peripheral clock enabling */ \ 1957 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 1958 UNUSED(tmpreg); \ 1959 } while(0U) 1960 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 1961 __IO uint32_t tmpreg; \ 1962 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 1963 /* Delay after an RCC peripheral clock enabling */ \ 1964 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 1965 UNUSED(tmpreg); \ 1966 } while(0U) 1967 1968 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 1969 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) 1970 #endif /* STM32F373xC || STM32F378xx */ 1971 1972 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 1973 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1974 __IO uint32_t tmpreg; \ 1975 SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\ 1976 /* Delay after an RCC peripheral clock enabling */ \ 1977 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\ 1978 UNUSED(tmpreg); \ 1979 } while(0U) 1980 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1981 __IO uint32_t tmpreg; \ 1982 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ 1983 /* Delay after an RCC peripheral clock enabling */ \ 1984 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ 1985 UNUSED(tmpreg); \ 1986 } while(0U) 1987 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 1988 __IO uint32_t tmpreg; \ 1989 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ 1990 /* Delay after an RCC peripheral clock enabling */ \ 1991 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ 1992 UNUSED(tmpreg); \ 1993 } while(0U) 1994 1995 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN)) 1996 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) 1997 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) 1998 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 1999 /** 2000 * @} 2001 */ 2002 2003 /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable 2004 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 2005 * @note After reset, the peripheral clock (used for registers read/write access) 2006 * is disabled and the application software has to enable this clock before 2007 * using it. 2008 * @{ 2009 */ 2010 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2011 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 2012 __IO uint32_t tmpreg; \ 2013 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 2014 /* Delay after an RCC peripheral clock enabling */ \ 2015 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 2016 UNUSED(tmpreg); \ 2017 } while(0U) 2018 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 2019 __IO uint32_t tmpreg; \ 2020 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2021 /* Delay after an RCC peripheral clock enabling */ \ 2022 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2023 UNUSED(tmpreg); \ 2024 } while(0U) 2025 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 2026 __IO uint32_t tmpreg; \ 2027 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 2028 /* Delay after an RCC peripheral clock enabling */ \ 2029 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 2030 UNUSED(tmpreg); \ 2031 } while(0U) 2032 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 2033 __IO uint32_t tmpreg; \ 2034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2035 /* Delay after an RCC peripheral clock enabling */ \ 2036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2037 UNUSED(tmpreg); \ 2038 } while(0U) 2039 2040 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 2041 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 2042 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 2043 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 2044 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2045 2046 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2047 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2048 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2049 __IO uint32_t tmpreg; \ 2050 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2051 /* Delay after an RCC peripheral clock enabling */ \ 2052 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2053 UNUSED(tmpreg); \ 2054 } while(0U) 2055 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 2056 __IO uint32_t tmpreg; \ 2057 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2058 /* Delay after an RCC peripheral clock enabling */ \ 2059 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2060 UNUSED(tmpreg); \ 2061 } while(0U) 2062 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 2063 __IO uint32_t tmpreg; \ 2064 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 2065 /* Delay after an RCC peripheral clock enabling */ \ 2066 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 2067 UNUSED(tmpreg); \ 2068 } while(0U) 2069 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 2070 __IO uint32_t tmpreg; \ 2071 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2072 /* Delay after an RCC peripheral clock enabling */ \ 2073 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2074 UNUSED(tmpreg); \ 2075 } while(0U) 2076 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 2077 __IO uint32_t tmpreg; \ 2078 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2079 /* Delay after an RCC peripheral clock enabling */ \ 2080 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2081 UNUSED(tmpreg); \ 2082 } while(0U) 2083 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 2084 __IO uint32_t tmpreg; \ 2085 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2086 /* Delay after an RCC peripheral clock enabling */ \ 2087 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2088 UNUSED(tmpreg); \ 2089 } while(0U) 2090 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 2091 __IO uint32_t tmpreg; \ 2092 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 2093 /* Delay after an RCC peripheral clock enabling */ \ 2094 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 2095 UNUSED(tmpreg); \ 2096 } while(0U) 2097 2098 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 2099 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 2100 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 2101 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 2102 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 2103 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 2104 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 2105 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2106 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2107 2108 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2109 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2110 __IO uint32_t tmpreg; \ 2111 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2112 /* Delay after an RCC peripheral clock enabling */ \ 2113 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2114 UNUSED(tmpreg); \ 2115 } while(0U) 2116 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ 2117 __IO uint32_t tmpreg; \ 2118 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ 2119 /* Delay after an RCC peripheral clock enabling */ \ 2120 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ 2121 UNUSED(tmpreg); \ 2122 } while(0U) 2123 2124 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 2125 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) 2126 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2127 2128 #if defined(STM32F373xC) || defined(STM32F378xx) 2129 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2130 __IO uint32_t tmpreg; \ 2131 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2132 /* Delay after an RCC peripheral clock enabling */ \ 2133 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2134 UNUSED(tmpreg); \ 2135 } while(0U) 2136 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 2137 __IO uint32_t tmpreg; \ 2138 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2139 /* Delay after an RCC peripheral clock enabling */ \ 2140 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2141 UNUSED(tmpreg); \ 2142 } while(0U) 2143 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 2144 __IO uint32_t tmpreg; \ 2145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 2146 /* Delay after an RCC peripheral clock enabling */ \ 2147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 2148 UNUSED(tmpreg); \ 2149 } while(0U) 2150 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 2151 __IO uint32_t tmpreg; \ 2152 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2153 /* Delay after an RCC peripheral clock enabling */ \ 2154 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2155 UNUSED(tmpreg); \ 2156 } while(0U) 2157 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 2158 __IO uint32_t tmpreg; \ 2159 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2160 /* Delay after an RCC peripheral clock enabling */ \ 2161 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2162 UNUSED(tmpreg); \ 2163 } while(0U) 2164 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 2165 __IO uint32_t tmpreg; \ 2166 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2167 /* Delay after an RCC peripheral clock enabling */ \ 2168 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2169 UNUSED(tmpreg); \ 2170 } while(0U) 2171 #define __HAL_RCC_TIM18_CLK_ENABLE() do { \ 2172 __IO uint32_t tmpreg; \ 2173 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ 2174 /* Delay after an RCC peripheral clock enabling */ \ 2175 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ 2176 UNUSED(tmpreg); \ 2177 } while(0U) 2178 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 2179 __IO uint32_t tmpreg; \ 2180 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 2181 /* Delay after an RCC peripheral clock enabling */ \ 2182 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 2183 UNUSED(tmpreg); \ 2184 } while(0U) 2185 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 2186 __IO uint32_t tmpreg; \ 2187 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2188 /* Delay after an RCC peripheral clock enabling */ \ 2189 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2190 UNUSED(tmpreg); \ 2191 } while(0U) 2192 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 2193 __IO uint32_t tmpreg; \ 2194 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 2195 /* Delay after an RCC peripheral clock enabling */ \ 2196 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 2197 UNUSED(tmpreg); \ 2198 } while(0U) 2199 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ 2200 __IO uint32_t tmpreg; \ 2201 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ 2202 /* Delay after an RCC peripheral clock enabling */ \ 2203 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ 2204 UNUSED(tmpreg); \ 2205 } while(0U) 2206 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 2207 __IO uint32_t tmpreg; \ 2208 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 2209 /* Delay after an RCC peripheral clock enabling */ \ 2210 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 2211 UNUSED(tmpreg); \ 2212 } while(0U) 2213 2214 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 2215 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 2216 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 2217 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 2218 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 2219 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 2220 #define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN)) 2221 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 2222 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 2223 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 2224 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) 2225 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 2226 #endif /* STM32F373xC || STM32F378xx */ 2227 2228 #if defined(STM32F303xE) || defined(STM32F398xx) \ 2229 || defined(STM32F303xC) || defined(STM32F358xx) \ 2230 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 2231 || defined(STM32F373xC) || defined(STM32F378xx) 2232 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 2233 __IO uint32_t tmpreg; \ 2234 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2235 /* Delay after an RCC peripheral clock enabling */ \ 2236 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2237 UNUSED(tmpreg); \ 2238 } while(0U) 2239 2240 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 2241 #endif /* STM32F303xE || STM32F398xx || */ 2242 /* STM32F303xC || STM32F358xx || */ 2243 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 2244 /* STM32F373xC || STM32F378xx */ 2245 2246 #if defined(STM32F302xE) || defined(STM32F303xE)\ 2247 || defined(STM32F302xC) || defined(STM32F303xC)\ 2248 || defined(STM32F302x8) \ 2249 || defined(STM32F373xC) 2250 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 2251 __IO uint32_t tmpreg; \ 2252 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 2253 /* Delay after an RCC peripheral clock enabling */ \ 2254 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 2255 UNUSED(tmpreg); \ 2256 } while(0U) 2257 2258 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) 2259 #endif /* STM32F302xE || STM32F303xE || */ 2260 /* STM32F302xC || STM32F303xC || */ 2261 /* STM32F302x8 || */ 2262 /* STM32F373xC */ 2263 2264 #if !defined(STM32F301x8) 2265 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 2266 __IO uint32_t tmpreg; \ 2267 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ 2268 /* Delay after an RCC peripheral clock enabling */ \ 2269 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ 2270 UNUSED(tmpreg); \ 2271 } while(0U) 2272 2273 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) 2274 #endif /* STM32F301x8*/ 2275 2276 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2277 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 2278 __IO uint32_t tmpreg; \ 2279 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2280 /* Delay after an RCC peripheral clock enabling */ \ 2281 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2282 UNUSED(tmpreg); \ 2283 } while(0U) 2284 2285 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 2286 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2287 /** 2288 * @} 2289 */ 2290 2291 /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable 2292 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 2293 * @note After reset, the peripheral clock (used for registers read/write access) 2294 * is disabled and the application software has to enable this clock before 2295 * using it. 2296 * @{ 2297 */ 2298 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2299 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2300 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 2301 __IO uint32_t tmpreg; \ 2302 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2303 /* Delay after an RCC peripheral clock enabling */ \ 2304 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2305 UNUSED(tmpreg); \ 2306 } while(0U) 2307 2308 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 2309 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2310 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2311 2312 #if defined(STM32F303xE) || defined(STM32F398xx)\ 2313 || defined(STM32F303xC) || defined(STM32F358xx) 2314 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 2315 __IO uint32_t tmpreg; \ 2316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2317 /* Delay after an RCC peripheral clock enabling */ \ 2318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2319 UNUSED(tmpreg); \ 2320 } while(0U) 2321 2322 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 2323 #endif /* STM32F303xE || STM32F398xx || */ 2324 /* STM32F303xC || STM32F358xx */ 2325 2326 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2327 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 2328 __IO uint32_t tmpreg; \ 2329 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2330 /* Delay after an RCC peripheral clock enabling */ \ 2331 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2332 UNUSED(tmpreg); \ 2333 } while(0U) 2334 2335 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 2336 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2337 2338 #if defined(STM32F334x8) 2339 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ 2340 __IO uint32_t tmpreg; \ 2341 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\ 2342 /* Delay after an RCC peripheral clock enabling */ \ 2343 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\ 2344 UNUSED(tmpreg); \ 2345 } while(0U) 2346 2347 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN)) 2348 #endif /* STM32F334x8 */ 2349 2350 #if defined(STM32F373xC) || defined(STM32F378xx) 2351 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 2352 __IO uint32_t tmpreg; \ 2353 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 2354 /* Delay after an RCC peripheral clock enabling */ \ 2355 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 2356 UNUSED(tmpreg); \ 2357 } while(0U) 2358 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 2359 __IO uint32_t tmpreg; \ 2360 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2361 /* Delay after an RCC peripheral clock enabling */ \ 2362 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 2363 UNUSED(tmpreg); \ 2364 } while(0U) 2365 #define __HAL_RCC_TIM19_CLK_ENABLE() do { \ 2366 __IO uint32_t tmpreg; \ 2367 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ 2368 /* Delay after an RCC peripheral clock enabling */ \ 2369 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ 2370 UNUSED(tmpreg); \ 2371 } while(0U) 2372 #define __HAL_RCC_SDADC1_CLK_ENABLE() do { \ 2373 __IO uint32_t tmpreg; \ 2374 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ 2375 /* Delay after an RCC peripheral clock enabling */ \ 2376 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ 2377 UNUSED(tmpreg); \ 2378 } while(0U) 2379 #define __HAL_RCC_SDADC2_CLK_ENABLE() do { \ 2380 __IO uint32_t tmpreg; \ 2381 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ 2382 /* Delay after an RCC peripheral clock enabling */ \ 2383 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ 2384 UNUSED(tmpreg); \ 2385 } while(0U) 2386 #define __HAL_RCC_SDADC3_CLK_ENABLE() do { \ 2387 __IO uint32_t tmpreg; \ 2388 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ 2389 /* Delay after an RCC peripheral clock enabling */ \ 2390 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ 2391 UNUSED(tmpreg); \ 2392 } while(0U) 2393 2394 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 2395 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 2396 #define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN)) 2397 #define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN)) 2398 #define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN)) 2399 #define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN)) 2400 #endif /* STM32F373xC || STM32F378xx */ 2401 2402 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2403 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ 2404 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 2405 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2406 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 2407 __IO uint32_t tmpreg; \ 2408 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 2409 /* Delay after an RCC peripheral clock enabling */ \ 2410 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 2411 UNUSED(tmpreg); \ 2412 } while(0U) 2413 2414 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 2415 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2416 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 2417 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 2418 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2419 2420 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2421 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 2422 __IO uint32_t tmpreg; \ 2423 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2424 /* Delay after an RCC peripheral clock enabling */ \ 2425 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2426 UNUSED(tmpreg); \ 2427 } while(0U) 2428 2429 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 2430 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2431 2432 #if defined(STM32F303xE) || defined(STM32F398xx) 2433 #define __HAL_RCC_TIM20_CLK_ENABLE() do { \ 2434 __IO uint32_t tmpreg; \ 2435 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\ 2436 /* Delay after an RCC peripheral clock enabling */ \ 2437 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\ 2438 UNUSED(tmpreg); \ 2439 } while(0U) 2440 #define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN)) 2441 #endif /* STM32F303xE || STM32F398xx */ 2442 2443 /** 2444 * @} 2445 */ 2446 2447 /** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status 2448 * @brief Get the enable or disable status of the AHB peripheral clock. 2449 * @note After reset, the peripheral clock (used for registers read/write access) 2450 * is disabled and the application software has to enable this clock before 2451 * using it. 2452 * @{ 2453 */ 2454 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2455 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET) 2456 2457 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET) 2458 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2459 2460 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2461 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2462 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) 2463 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) 2464 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET) 2465 2466 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) 2467 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) 2468 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET) 2469 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2470 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2471 2472 #if defined(STM32F303xE) || defined(STM32F398xx)\ 2473 || defined(STM32F303xC) || defined(STM32F358xx) 2474 #define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET) 2475 2476 #define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET) 2477 #endif /* STM32F303xE || STM32F398xx || */ 2478 /* STM32F303xC || STM32F358xx */ 2479 2480 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2481 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET) 2482 2483 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET) 2484 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2485 2486 #if defined(STM32F373xC) || defined(STM32F378xx) 2487 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) 2488 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) 2489 2490 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) 2491 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) 2492 #endif /* STM32F373xC || STM32F378xx */ 2493 2494 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2495 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET) 2496 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET) 2497 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET) 2498 2499 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET) 2500 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET) 2501 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET) 2502 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2503 /** 2504 * @} 2505 */ 2506 2507 /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status 2508 * @brief Get the enable or disable status of the APB1 peripheral clock. 2509 * @note After reset, the peripheral clock (used for registers read/write access) 2510 * is disabled and the application software has to enable this clock before 2511 * using it. 2512 * @{ 2513 */ 2514 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2515 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 2516 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 2517 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 2518 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 2519 2520 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 2521 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 2522 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 2523 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 2524 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2525 2526 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2527 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2528 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 2529 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 2530 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 2531 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 2532 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 2533 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 2534 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 2535 2536 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 2537 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 2538 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 2539 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 2540 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 2541 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 2542 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 2543 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2544 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2545 2546 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2547 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 2548 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET) 2549 2550 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 2551 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET) 2552 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2553 2554 #if defined(STM32F373xC) || defined(STM32F378xx) 2555 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 2556 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 2557 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 2558 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 2559 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 2560 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 2561 #define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET) 2562 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 2563 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 2564 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 2565 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET) 2566 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 2567 2568 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 2569 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 2570 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 2571 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 2572 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 2573 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 2574 #define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET) 2575 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 2576 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 2577 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 2578 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET) 2579 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 2580 #endif /* STM32F373xC || STM32F378xx */ 2581 2582 #if defined(STM32F303xE) || defined(STM32F398xx) \ 2583 || defined(STM32F303xC) || defined(STM32F358xx) \ 2584 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 2585 || defined(STM32F373xC) || defined(STM32F378xx) 2586 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 2587 2588 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 2589 #endif /* STM32F303xE || STM32F398xx || */ 2590 /* STM32F303xC || STM32F358xx || */ 2591 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 2592 /* STM32F373xC || STM32F378xx */ 2593 2594 #if defined(STM32F302xE) || defined(STM32F303xE)\ 2595 || defined(STM32F302xC) || defined(STM32F303xC)\ 2596 || defined(STM32F302x8) \ 2597 || defined(STM32F373xC) 2598 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) 2599 2600 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) 2601 #endif /* STM32F302xE || STM32F303xE || */ 2602 /* STM32F302xC || STM32F303xC || */ 2603 /* STM32F302x8 || */ 2604 /* STM32F373xC */ 2605 2606 #if !defined(STM32F301x8) 2607 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET) 2608 2609 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET) 2610 #endif /* STM32F301x8*/ 2611 2612 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2613 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 2614 2615 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 2616 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2617 /** 2618 * @} 2619 */ 2620 2621 /** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status 2622 * @brief Get the enable or disable status of the APB2 peripheral clock. 2623 * @note After reset, the peripheral clock (used for registers read/write access) 2624 * is disabled and the application software has to enable this clock before 2625 * using it. 2626 * @{ 2627 */ 2628 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2629 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2630 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 2631 2632 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 2633 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2634 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2635 2636 #if defined(STM32F303xE) || defined(STM32F398xx)\ 2637 || defined(STM32F303xC) || defined(STM32F358xx) 2638 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 2639 2640 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 2641 #endif /* STM32F303xE || STM32F398xx || */ 2642 /* STM32F303xC || STM32F358xx */ 2643 2644 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2645 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 2646 2647 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 2648 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2649 2650 #if defined(STM32F334x8) 2651 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET) 2652 2653 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET) 2654 #endif /* STM32F334x8 */ 2655 2656 #if defined(STM32F373xC) || defined(STM32F378xx) 2657 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 2658 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 2659 #define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET) 2660 #define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET) 2661 #define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET) 2662 #define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET) 2663 2664 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 2665 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 2666 #define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET) 2667 #define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET) 2668 #define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET) 2669 #define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET) 2670 #endif /* STM32F373xC || STM32F378xx */ 2671 2672 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2673 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ 2674 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 2675 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2676 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 2677 2678 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 2679 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2680 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 2681 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 2682 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2683 2684 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2685 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 2686 2687 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 2688 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2689 2690 #if defined(STM32F303xE) || defined(STM32F398xx) 2691 #define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET) 2692 2693 #define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET) 2694 #endif /* STM32F303xE || STM32F398xx */ 2695 /** 2696 * @} 2697 */ 2698 2699 /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset 2700 * @brief Force or release AHB peripheral reset. 2701 * @{ 2702 */ 2703 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2704 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST)) 2705 2706 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST)) 2707 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2708 2709 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2710 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2711 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) 2712 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) 2713 /* Aliases for STM32 F3 compatibility */ 2714 #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() 2715 #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() 2716 2717 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) 2718 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) 2719 /* Aliases for STM32 F3 compatibility */ 2720 #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() 2721 #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() 2722 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2723 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2724 2725 #if defined(STM32F303xE) || defined(STM32F398xx)\ 2726 || defined(STM32F303xC) || defined(STM32F358xx) 2727 #define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST)) 2728 2729 #define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST)) 2730 #endif /* STM32F303xE || STM32F398xx || */ 2731 /* STM32F303xC || STM32F358xx */ 2732 2733 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2734 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) 2735 /* Aliases for STM32 F3 compatibility */ 2736 #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() 2737 #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() 2738 2739 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) 2740 /* Aliases for STM32 F3 compatibility */ 2741 #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() 2742 #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() 2743 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2744 2745 #if defined(STM32F373xC) || defined(STM32F378xx) 2746 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) 2747 2748 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) 2749 #endif /* STM32F373xC || STM32F378xx */ 2750 2751 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2752 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST)) 2753 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) 2754 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) 2755 2756 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST)) 2757 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) 2758 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) 2759 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2760 /** 2761 * @} 2762 */ 2763 2764 /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset 2765 * @brief Force or release APB1 peripheral reset. 2766 * @{ 2767 */ 2768 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2769 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 2770 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 2771 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 2772 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 2773 2774 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 2775 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 2776 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 2777 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 2778 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2779 2780 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2781 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2782 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 2783 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 2784 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 2785 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 2786 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 2787 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 2788 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 2789 2790 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 2791 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 2792 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 2793 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 2794 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 2795 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 2796 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 2797 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2798 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2799 2800 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2801 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 2802 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) 2803 2804 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 2805 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) 2806 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2807 2808 #if defined(STM32F373xC) || defined(STM32F378xx) 2809 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 2810 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 2811 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 2812 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 2813 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 2814 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 2815 #define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST)) 2816 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 2817 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 2818 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 2819 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) 2820 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 2821 2822 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 2823 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 2824 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 2825 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 2826 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 2827 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 2828 #define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST)) 2829 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 2830 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 2831 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 2832 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) 2833 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 2834 #endif /* STM32F373xC || STM32F378xx */ 2835 2836 #if defined(STM32F303xE) || defined(STM32F398xx)\ 2837 || defined(STM32F303xC) || defined(STM32F358xx)\ 2838 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 2839 || defined(STM32F373xC) || defined(STM32F378xx) 2840 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 2841 2842 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 2843 #endif /* STM32F303xE || STM32F398xx || */ 2844 /* STM32F303xC || STM32F358xx || */ 2845 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 2846 /* STM32F373xC || STM32F378xx */ 2847 2848 #if defined(STM32F302xE) || defined(STM32F303xE)\ 2849 || defined(STM32F302xC) || defined(STM32F303xC)\ 2850 || defined(STM32F302x8) \ 2851 || defined(STM32F373xC) 2852 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) 2853 2854 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) 2855 #endif /* STM32F302xE || STM32F303xE || */ 2856 /* STM32F302xC || STM32F303xC || */ 2857 /* STM32F302x8 || */ 2858 /* STM32F373xC */ 2859 2860 #if !defined(STM32F301x8) 2861 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) 2862 2863 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) 2864 #endif /* STM32F301x8*/ 2865 2866 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2867 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 2868 2869 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 2870 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2871 /** 2872 * @} 2873 */ 2874 2875 /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset 2876 * @brief Force or release APB2 peripheral reset. 2877 * @{ 2878 */ 2879 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2880 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 2881 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 2882 2883 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 2884 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2885 /* STM32F302xC || STM32F303xC || STM32F358xx */ 2886 2887 #if defined(STM32F303xE) || defined(STM32F398xx)\ 2888 || defined(STM32F303xC) || defined(STM32F358xx) 2889 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 2890 2891 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 2892 #endif /* STM32F303xE || STM32F398xx || */ 2893 /* STM32F303xC || STM32F358xx */ 2894 2895 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2896 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 2897 2898 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 2899 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2900 2901 #if defined(STM32F334x8) 2902 #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST)) 2903 2904 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST)) 2905 #endif /* STM32F334x8 */ 2906 2907 #if defined(STM32F373xC) || defined(STM32F378xx) 2908 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) 2909 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 2910 #define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST)) 2911 #define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST)) 2912 #define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST)) 2913 #define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST)) 2914 2915 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) 2916 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 2917 #define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST)) 2918 #define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST)) 2919 #define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST)) 2920 #define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST)) 2921 #endif /* STM32F373xC || STM32F378xx */ 2922 2923 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 2924 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ 2925 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ 2926 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2927 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 2928 2929 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 2930 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2931 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 2932 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 2933 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2934 2935 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 2936 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 2937 2938 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 2939 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 2940 2941 #if defined(STM32F303xE) || defined(STM32F398xx) 2942 #define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST)) 2943 2944 #define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST)) 2945 #endif /* STM32F303xE || STM32F398xx */ 2946 2947 /** 2948 * @} 2949 */ 2950 2951 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2952 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config 2953 * @{ 2954 */ 2955 2956 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 2957 * @param __I2C2CLKSource__ specifies the I2C2 clock source. 2958 * This parameter can be one of the following values: 2959 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2960 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 2961 */ 2962 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ 2963 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) 2964 2965 /** @brief Macro to get the I2C2 clock source. 2966 * @retval The clock source can be one of the following values: 2967 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2968 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 2969 */ 2970 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) 2971 2972 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 2973 * @param __I2C3CLKSource__ specifies the I2C3 clock source. 2974 * This parameter can be one of the following values: 2975 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2976 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 2977 */ 2978 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ 2979 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) 2980 2981 /** @brief Macro to get the I2C3 clock source. 2982 * @retval The clock source can be one of the following values: 2983 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2984 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 2985 */ 2986 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) 2987 2988 /** 2989 * @} 2990 */ 2991 2992 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config 2993 * @{ 2994 */ 2995 /** @brief Macro to configure the TIM1 clock (TIM1CLK). 2996 * @param __TIM1CLKSource__ specifies the TIM1 clock source. 2997 * This parameter can be one of the following values: 2998 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock 2999 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock 3000 */ 3001 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ 3002 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) 3003 3004 /** @brief Macro to get the TIM1 clock (TIM1CLK). 3005 * @retval The clock source can be one of the following values: 3006 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock 3007 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock 3008 */ 3009 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) 3010 3011 /** @brief Macro to configure the TIM15 clock (TIM15CLK). 3012 * @param __TIM15CLKSource__ specifies the TIM15 clock source. 3013 * This parameter can be one of the following values: 3014 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock 3015 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock 3016 */ 3017 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ 3018 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) 3019 3020 /** @brief Macro to get the TIM15 clock (TIM15CLK). 3021 * @retval The clock source can be one of the following values: 3022 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock 3023 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock 3024 */ 3025 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) 3026 3027 /** @brief Macro to configure the TIM16 clock (TIM16CLK). 3028 * @param __TIM16CLKSource__ specifies the TIM16 clock source. 3029 * This parameter can be one of the following values: 3030 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock 3031 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock 3032 */ 3033 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ 3034 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) 3035 3036 /** @brief Macro to get the TIM16 clock (TIM16CLK). 3037 * @retval The clock source can be one of the following values: 3038 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock 3039 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock 3040 */ 3041 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) 3042 3043 /** @brief Macro to configure the TIM17 clock (TIM17CLK). 3044 * @param __TIM17CLKSource__ specifies the TIM17 clock source. 3045 * This parameter can be one of the following values: 3046 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock 3047 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock 3048 */ 3049 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ 3050 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) 3051 3052 /** @brief Macro to get the TIM17 clock (TIM17CLK). 3053 * @retval The clock source can be one of the following values: 3054 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock 3055 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock 3056 */ 3057 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) 3058 3059 /** 3060 * @} 3061 */ 3062 3063 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config 3064 * @{ 3065 */ 3066 /** @brief Macro to configure the I2S clock source (I2SCLK). 3067 * @note This function must be called before enabling the I2S APB clock. 3068 * @param __I2SCLKSource__ specifies the I2S clock source. 3069 * This parameter can be one of the following values: 3070 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source 3071 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 3072 * used as I2S clock source 3073 */ 3074 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ 3075 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) 3076 3077 /** @brief Macro to get the I2S clock source (I2SCLK). 3078 * @retval The clock source can be one of the following values: 3079 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source 3080 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 3081 * used as I2S clock source 3082 */ 3083 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) 3084 /** 3085 * @} 3086 */ 3087 3088 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config 3089 * @{ 3090 */ 3091 3092 /** @brief Macro to configure the ADC1 clock (ADC1CLK). 3093 * @param __ADC1CLKSource__ specifies the ADC1 clock source. 3094 * This parameter can be one of the following values: 3095 * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock 3096 * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock 3097 * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock 3098 * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock 3099 * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock 3100 * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock 3101 * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock 3102 * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock 3103 * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock 3104 * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock 3105 * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock 3106 * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock 3107 * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock 3108 */ 3109 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ 3110 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__)) 3111 3112 /** @brief Macro to get the ADC1 clock 3113 * @retval The clock source can be one of the following values: 3114 * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock 3115 * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock 3116 * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock 3117 * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock 3118 * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock 3119 * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock 3120 * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock 3121 * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock 3122 * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock 3123 * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock 3124 * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock 3125 * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock 3126 * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock 3127 */ 3128 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES))) 3129 /** 3130 * @} 3131 */ 3132 3133 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3134 3135 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ 3136 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) 3137 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config 3138 * @{ 3139 */ 3140 3141 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 3142 * @param __I2C2CLKSource__ specifies the I2C2 clock source. 3143 * This parameter can be one of the following values: 3144 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 3145 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 3146 */ 3147 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ 3148 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) 3149 3150 /** @brief Macro to get the I2C2 clock source. 3151 * @retval The clock source can be one of the following values: 3152 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 3153 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 3154 */ 3155 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) 3156 /** 3157 * @} 3158 */ 3159 3160 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config 3161 * @{ 3162 */ 3163 3164 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). 3165 * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source. 3166 * This parameter can be one of the following values: 3167 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock 3168 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock 3169 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock 3170 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock 3171 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock 3172 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock 3173 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock 3174 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock 3175 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock 3176 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock 3177 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock 3178 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock 3179 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock 3180 */ 3181 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ 3182 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) 3183 3184 /** @brief Macro to get the ADC1 & ADC2 clock 3185 * @retval The clock source can be one of the following values: 3186 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock 3187 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock 3188 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock 3189 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock 3190 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock 3191 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock 3192 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock 3193 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock 3194 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock 3195 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock 3196 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock 3197 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock 3198 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock 3199 */ 3200 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) 3201 /** 3202 * @} 3203 */ 3204 3205 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config 3206 * @{ 3207 */ 3208 3209 /** @brief Macro to configure the TIM1 clock (TIM1CLK). 3210 * @param __TIM1CLKSource__ specifies the TIM1 clock source. 3211 * This parameter can be one of the following values: 3212 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock 3213 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock 3214 */ 3215 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ 3216 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) 3217 3218 /** @brief Macro to get the TIM1 clock (TIM1CLK). 3219 * @retval The clock source can be one of the following values: 3220 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock 3221 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock 3222 */ 3223 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) 3224 /** 3225 * @} 3226 */ 3227 3228 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config 3229 * @{ 3230 */ 3231 3232 /** @brief Macro to configure the I2S clock source (I2SCLK). 3233 * @note This function must be called before enabling the I2S APB clock. 3234 * @param __I2SCLKSource__ specifies the I2S clock source. 3235 * This parameter can be one of the following values: 3236 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source 3237 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 3238 * used as I2S clock source 3239 */ 3240 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ 3241 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) 3242 3243 /** @brief Macro to get the I2S clock source (I2SCLK). 3244 * @retval The clock source can be one of the following values: 3245 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source 3246 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 3247 * used as I2S clock source 3248 */ 3249 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) 3250 /** 3251 * @} 3252 */ 3253 3254 /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config 3255 * @{ 3256 */ 3257 3258 /** @brief Macro to configure the UART4 clock (UART4CLK). 3259 * @param __UART4CLKSource__ specifies the UART4 clock source. 3260 * This parameter can be one of the following values: 3261 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 3262 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 3263 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 3264 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 3265 */ 3266 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \ 3267 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__)) 3268 3269 /** @brief Macro to get the UART4 clock source. 3270 * @retval The clock source can be one of the following values: 3271 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 3272 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 3273 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 3274 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 3275 */ 3276 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW))) 3277 3278 /** @brief Macro to configure the UART5 clock (UART5CLK). 3279 * @param __UART5CLKSource__ specifies the UART5 clock source. 3280 * This parameter can be one of the following values: 3281 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 3282 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 3283 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 3284 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 3285 */ 3286 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \ 3287 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__)) 3288 3289 /** @brief Macro to get the UART5 clock source. 3290 * @retval The clock source can be one of the following values: 3291 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 3292 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 3293 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 3294 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 3295 */ 3296 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW))) 3297 /** 3298 * @} 3299 */ 3300 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 3301 /* STM32F302xC || STM32F303xC || STM32F358xx */ 3302 3303 #if defined(STM32F303xE) || defined(STM32F398xx)\ 3304 || defined(STM32F303xC) || defined(STM32F358xx) 3305 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config 3306 * @{ 3307 */ 3308 3309 /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK). 3310 * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source. 3311 * This parameter can be one of the following values: 3312 * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock 3313 * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock 3314 * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock 3315 * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock 3316 * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock 3317 * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock 3318 * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock 3319 * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock 3320 * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock 3321 * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock 3322 * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock 3323 * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock 3324 * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock 3325 */ 3326 #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \ 3327 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__)) 3328 3329 /** @brief Macro to get the ADC3 & ADC4 clock 3330 * @retval The clock source can be one of the following values: 3331 * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock 3332 * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock 3333 * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock 3334 * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock 3335 * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock 3336 * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock 3337 * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock 3338 * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock 3339 * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock 3340 * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock 3341 * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock 3342 * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock 3343 * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock 3344 */ 3345 #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34))) 3346 /** 3347 * @} 3348 */ 3349 3350 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config 3351 * @{ 3352 */ 3353 3354 /** @brief Macro to configure the TIM8 clock (TIM8CLK). 3355 * @param __TIM8CLKSource__ specifies the TIM8 clock source. 3356 * This parameter can be one of the following values: 3357 * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock 3358 * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock 3359 */ 3360 #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \ 3361 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__)) 3362 3363 /** @brief Macro to get the TIM8 clock (TIM8CLK). 3364 * @retval The clock source can be one of the following values: 3365 * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock 3366 * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock 3367 */ 3368 #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW))) 3369 3370 /** 3371 * @} 3372 */ 3373 #endif /* STM32F303xE || STM32F398xx || */ 3374 /* STM32F303xC || STM32F358xx */ 3375 3376 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 3377 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config 3378 * @{ 3379 */ 3380 3381 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). 3382 * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source. 3383 * This parameter can be one of the following values: 3384 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock 3385 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock 3386 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock 3387 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock 3388 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock 3389 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock 3390 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock 3391 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock 3392 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock 3393 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock 3394 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock 3395 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock 3396 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock 3397 */ 3398 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ 3399 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) 3400 3401 /** @brief Macro to get the ADC1 & ADC2 clock 3402 * @retval The clock source can be one of the following values: 3403 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock 3404 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock 3405 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock 3406 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock 3407 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock 3408 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock 3409 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock 3410 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock 3411 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock 3412 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock 3413 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock 3414 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock 3415 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock 3416 */ 3417 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) 3418 /** 3419 * @} 3420 */ 3421 3422 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config 3423 * @{ 3424 */ 3425 /** @brief Macro to configure the TIM1 clock (TIM1CLK). 3426 * @param __TIM1CLKSource__ specifies the TIM1 clock source. 3427 * This parameter can be one of the following values: 3428 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock 3429 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock 3430 */ 3431 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ 3432 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) 3433 3434 /** @brief Macro to get the TIM1 clock (TIM1CLK). 3435 * @retval The clock source can be one of the following values: 3436 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock 3437 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock 3438 */ 3439 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) 3440 /** 3441 * @} 3442 */ 3443 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 3444 3445 #if defined(STM32F334x8) 3446 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config 3447 * @{ 3448 */ 3449 /** @brief Macro to configure the HRTIM1 clock. 3450 * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source. 3451 * This parameter can be one of the following values: 3452 * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock 3453 * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock 3454 */ 3455 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ 3456 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__)) 3457 3458 /** @brief Macro to get the HRTIM1 clock source. 3459 * @retval The clock source can be one of the following values: 3460 * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock 3461 * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock 3462 */ 3463 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW))) 3464 /** 3465 * @} 3466 */ 3467 #endif /* STM32F334x8 */ 3468 3469 #if defined(STM32F373xC) || defined(STM32F378xx) 3470 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config 3471 * @{ 3472 */ 3473 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 3474 * @param __I2C2CLKSource__ specifies the I2C2 clock source. 3475 * This parameter can be one of the following values: 3476 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 3477 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 3478 */ 3479 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ 3480 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) 3481 3482 /** @brief Macro to get the I2C2 clock source. 3483 * @retval The clock source can be one of the following values: 3484 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 3485 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 3486 */ 3487 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) 3488 /** 3489 * @} 3490 */ 3491 3492 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config 3493 * @{ 3494 */ 3495 /** @brief Macro to configure the ADC1 clock (ADC1CLK). 3496 * @param __ADC1CLKSource__ specifies the ADC1 clock source. 3497 * This parameter can be one of the following values: 3498 * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock 3499 * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock 3500 * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock 3501 * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock 3502 */ 3503 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ 3504 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__)) 3505 3506 /** @brief Macro to get the ADC1 clock (ADC1CLK). 3507 * @retval The clock source can be one of the following values: 3508 * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock 3509 * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock 3510 * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock 3511 * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock 3512 */ 3513 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) 3514 /** 3515 * @} 3516 */ 3517 3518 /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config 3519 * @{ 3520 */ 3521 /** @brief Macro to configure the SDADCx clock (SDADCxCLK). 3522 * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler. 3523 * This parameter can be one of the following values: 3524 * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock 3525 * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock 3526 * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock 3527 * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock 3528 * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock 3529 * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock 3530 * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock 3531 * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock 3532 * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock 3533 * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock 3534 * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock 3535 * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock 3536 * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock 3537 * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock 3538 * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock 3539 * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock 3540 * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock 3541 */ 3542 #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \ 3543 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__)) 3544 3545 /** @brief Macro to get the SDADCx clock prescaler. 3546 * @retval The clock source can be one of the following values: 3547 * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock 3548 * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock 3549 * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock 3550 * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock 3551 * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock 3552 * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock 3553 * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock 3554 * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock 3555 * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock 3556 * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock 3557 * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock 3558 * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock 3559 * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock 3560 * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock 3561 * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock 3562 * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock 3563 * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock 3564 */ 3565 #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE))) 3566 /** 3567 * @} 3568 */ 3569 3570 /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config 3571 * @{ 3572 */ 3573 /** @brief Macro to configure the CEC clock. 3574 * @param __CECCLKSource__ specifies the CEC clock source. 3575 * This parameter can be one of the following values: 3576 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock 3577 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 3578 */ 3579 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 3580 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__)) 3581 3582 /** @brief Macro to get the HDMI CEC clock source. 3583 * @retval The clock source can be one of the following values: 3584 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock 3585 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 3586 */ 3587 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) 3588 /** 3589 * @} 3590 */ 3591 3592 #endif /* STM32F373xC || STM32F378xx */ 3593 3594 #if defined(STM32F302xE) || defined(STM32F303xE)\ 3595 || defined(STM32F302xC) || defined(STM32F303xC)\ 3596 || defined(STM32F302x8) \ 3597 || defined(STM32F373xC) 3598 3599 /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config 3600 * @{ 3601 */ 3602 /** @brief Macro to configure the USB clock (USBCLK). 3603 * @param __USBCLKSource__ specifies the USB clock source. 3604 * This parameter can be one of the following values: 3605 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock 3606 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock 3607 */ 3608 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 3609 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__)) 3610 3611 /** @brief Macro to get the USB clock source. 3612 * @retval The clock source can be one of the following values: 3613 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock 3614 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock 3615 */ 3616 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) 3617 /** 3618 * @} 3619 */ 3620 3621 #endif /* STM32F302xE || STM32F303xE || */ 3622 /* STM32F302xC || STM32F303xC || */ 3623 /* STM32F302x8 || */ 3624 /* STM32F373xC */ 3625 3626 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) 3627 3628 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config 3629 * @{ 3630 */ 3631 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 3632 * @param __I2C3CLKSource__ specifies the I2C3 clock source. 3633 * This parameter can be one of the following values: 3634 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 3635 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 3636 */ 3637 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ 3638 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) 3639 3640 /** @brief Macro to get the I2C3 clock source. 3641 * @retval The clock source can be one of the following values: 3642 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 3643 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 3644 */ 3645 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) 3646 /** 3647 * @} 3648 */ 3649 3650 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config 3651 * @{ 3652 */ 3653 /** @brief Macro to configure the TIM2 clock (TIM2CLK). 3654 * @param __TIM2CLKSource__ specifies the TIM2 clock source. 3655 * This parameter can be one of the following values: 3656 * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock 3657 * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock 3658 */ 3659 #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \ 3660 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__)) 3661 3662 /** @brief Macro to get the TIM2 clock (TIM2CLK). 3663 * @retval The clock source can be one of the following values: 3664 * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock 3665 * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock 3666 */ 3667 #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW))) 3668 3669 /** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK). 3670 * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source. 3671 * This parameter can be one of the following values: 3672 * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock 3673 * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock 3674 */ 3675 #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \ 3676 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__)) 3677 3678 /** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK). 3679 * @retval The clock source can be one of the following values: 3680 * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock 3681 * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock 3682 */ 3683 #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW))) 3684 3685 /** @brief Macro to configure the TIM15 clock (TIM15CLK). 3686 * @param __TIM15CLKSource__ specifies the TIM15 clock source. 3687 * This parameter can be one of the following values: 3688 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock 3689 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock 3690 */ 3691 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ 3692 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) 3693 3694 /** @brief Macro to get the TIM15 clock (TIM15CLK). 3695 * @retval The clock source can be one of the following values: 3696 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock 3697 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock 3698 */ 3699 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) 3700 3701 /** @brief Macro to configure the TIM16 clock (TIM16CLK). 3702 * @param __TIM16CLKSource__ specifies the TIM16 clock source. 3703 * This parameter can be one of the following values: 3704 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock 3705 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock 3706 */ 3707 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ 3708 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) 3709 3710 /** @brief Macro to get the TIM16 clock (TIM16CLK). 3711 * @retval The clock source can be one of the following values: 3712 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock 3713 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock 3714 */ 3715 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) 3716 3717 /** @brief Macro to configure the TIM17 clock (TIM17CLK). 3718 * @param __TIM17CLKSource__ specifies the TIM17 clock source. 3719 * This parameter can be one of the following values: 3720 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock 3721 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock 3722 */ 3723 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ 3724 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) 3725 3726 /** @brief Macro to get the TIM17 clock (TIM17CLK). 3727 * @retval The clock source can be one of the following values: 3728 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock 3729 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock 3730 */ 3731 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) 3732 3733 /** 3734 * @} 3735 */ 3736 3737 #endif /* STM32f302xE || STM32f303xE || STM32F398xx */ 3738 3739 #if defined(STM32F303xE) || defined(STM32F398xx) 3740 /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config 3741 * @{ 3742 */ 3743 /** @brief Macro to configure the TIM20 clock (TIM20CLK). 3744 * @param __TIM20CLKSource__ specifies the TIM20 clock source. 3745 * This parameter can be one of the following values: 3746 * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock 3747 * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock 3748 */ 3749 #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \ 3750 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__)) 3751 3752 /** @brief Macro to get the TIM20 clock (TIM20CLK). 3753 * @retval The clock source can be one of the following values: 3754 * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock 3755 * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock 3756 */ 3757 #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW))) 3758 3759 /** 3760 * @} 3761 */ 3762 #endif /* STM32f303xE || STM32F398xx */ 3763 3764 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration 3765 * @{ 3766 */ 3767 3768 /** 3769 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3770 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. 3771 * This parameter can be one of the following values: 3772 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3773 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3774 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3775 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3776 * @retval None 3777 */ 3778 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ 3779 RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) 3780 3781 /** 3782 * @} 3783 */ 3784 3785 /** 3786 * @} 3787 */ 3788 3789 /* Exported functions --------------------------------------------------------*/ 3790 /** @addtogroup RCCEx_Exported_Functions 3791 * @{ 3792 */ 3793 3794 /** @addtogroup RCCEx_Exported_Functions_Group1 3795 * @{ 3796 */ 3797 3798 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3799 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3800 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 3801 3802 /** 3803 * @} 3804 */ 3805 3806 /** 3807 * @} 3808 */ 3809 3810 /** 3811 * @} 3812 */ 3813 3814 /** 3815 * @} 3816 */ 3817 3818 #ifdef __cplusplus 3819 } 3820 #endif 3821 3822 #endif /* __STM32F3xx_HAL_RCC_EX_H */ 3823 3824 3825
