1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_RCC_H 21 #define STM32WBxx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 #include "stm32wbxx_ll_rcc.h" 30 #include "stm32wbxx_ll_bus.h" 31 32 33 /** @addtogroup STM32WBxx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup RCC 38 * @{ 39 */ 40 41 /* Private constants ---------------------------------------------------------*/ 42 /** @addtogroup RCC_Private_Constants 43 * @{ 44 */ 45 /* Defines used for Flags */ 46 #define CR_REG_INDEX 1U 47 #define BDCR_REG_INDEX 2U 48 #define CSR_REG_INDEX 3U 49 #define CRRCR_REG_INDEX 4U 50 51 #define RCC_FLAG_MASK 0x1FU 52 53 /* Defines Oscillator Masks */ 54 #if defined(RCC_HSI48_SUPPORT) 55 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ 56 RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI | \ 57 RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | \ 58 RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 59 #else 60 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ 61 RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI1 | \ 62 RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 63 #endif /* RCC_HSI48_SUPPORT */ 64 65 /** @defgroup RCC_Reset_Flag Reset Flag 66 * @{ 67 */ 68 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 69 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 70 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 71 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 72 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 73 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 74 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 75 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 76 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 77 RCC_RESET_FLAG_LPWR) 78 /** 79 * @} 80 */ 81 82 /** 83 * @} 84 */ 85 86 /* Private macros ------------------------------------------------------------*/ 87 /** @addtogroup RCC_Private_Macros 88 * @{ 89 */ 90 91 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 92 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 93 94 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON)) 95 96 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 97 ((__LSE__) == RCC_LSE_BYPASS)) 98 99 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 100 101 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) 102 103 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 104 105 #define IS_RCC_LSI2_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)15U) 106 107 108 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 109 110 111 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) 112 113 #if defined(RCC_HSI48_SUPPORT) 114 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 115 #endif /* RCC_HSI48_SUPPORT */ 116 117 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 118 ((__PLL__) == RCC_PLL_ON)) 119 120 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 121 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 122 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 123 124 #define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || \ 125 ((__VALUE__) == RCC_PLLM_DIV2) || \ 126 ((__VALUE__) == RCC_PLLM_DIV3) || \ 127 ((__VALUE__) == RCC_PLLM_DIV4) || \ 128 ((__VALUE__) == RCC_PLLM_DIV5) || \ 129 ((__VALUE__) == RCC_PLLM_DIV6) || \ 130 ((__VALUE__) == RCC_PLLM_DIV7) || \ 131 ((__VALUE__) == RCC_PLLM_DIV8)) 132 133 #define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 134 135 #define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 136 137 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 138 139 #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 140 141 #if defined(SAI1) 142 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \ 143 (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 144 (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ 145 (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK | RCC_PLLSAI1_SAI1CLK | \ 146 RCC_PLLSAI1_USBCLK)) == 0U)) 147 #endif /* SAI1 */ 148 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 149 ((__RANGE__) == RCC_MSIRANGE_1) || \ 150 ((__RANGE__) == RCC_MSIRANGE_2) || \ 151 ((__RANGE__) == RCC_MSIRANGE_3) || \ 152 ((__RANGE__) == RCC_MSIRANGE_4) || \ 153 ((__RANGE__) == RCC_MSIRANGE_5) || \ 154 ((__RANGE__) == RCC_MSIRANGE_6) || \ 155 ((__RANGE__) == RCC_MSIRANGE_7) || \ 156 ((__RANGE__) == RCC_MSIRANGE_8) || \ 157 ((__RANGE__) == RCC_MSIRANGE_9) || \ 158 ((__RANGE__) == RCC_MSIRANGE_10) || \ 159 ((__RANGE__) == RCC_MSIRANGE_11)) 160 161 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \ 162 RCC_CLOCKTYPE_HCLK | \ 163 RCC_CLOCKTYPE_PCLK1 | \ 164 RCC_CLOCKTYPE_PCLK2 | \ 165 RCC_CLOCKTYPE_HCLK2 | \ 166 RCC_CLOCKTYPE_HCLK4))) 167 168 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 169 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 170 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 171 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 172 173 #define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV3) || \ 174 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV5) || ((__HCLK__) == RCC_SYSCLK_DIV6) || \ 175 ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV10) || ((__HCLK__) == RCC_SYSCLK_DIV16) || \ 176 ((__HCLK__) == RCC_SYSCLK_DIV32) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || \ 177 ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512)) 178 179 #define IS_RCC_PCLKx(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 180 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 181 ((__PCLK__) == RCC_HCLK_DIV16)) 182 183 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 184 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 185 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 186 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 187 188 #if defined(RCC_MCO3_SUPPORT) 189 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ 190 ((__MCOX__) == RCC_MCO2_PB6) || \ 191 ((__MCOX__) == RCC_MCO3_PA15)) 192 #else 193 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ 194 ((__MCOX__) == RCC_MCO2_PB6)) 195 #endif /* RCC_MCO3_SUPPORT */ 196 197 #if defined(RCC_HSI48_SUPPORT) 198 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 199 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 200 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 201 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 202 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 203 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 204 ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ 205 ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ 206 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 207 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 208 #else 209 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 210 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 211 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 212 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 213 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 214 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 215 ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ 216 ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ 217 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 218 #endif /* RCC_HSI48_SUPPORT */ 219 220 #define IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) 221 #define IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) 222 223 224 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 225 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 226 ((__DIV__) == RCC_MCODIV_16)) 227 228 229 230 231 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 232 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 233 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 234 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 235 236 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 237 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 238 /** 239 * @} 240 */ 241 242 /* Exported types ------------------------------------------------------------*/ 243 /** @defgroup RCC_Exported_Types RCC Exported Types 244 * @{ 245 */ 246 247 248 /** 249 * @brief RCC PLL configuration structure definition 250 */ 251 typedef struct 252 { 253 uint32_t PLLState; /*!< The new state of the PLL. 254 This parameter must be a value of @ref RCC_PLL_Config */ 255 256 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 257 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 258 259 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 260 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 261 262 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 263 This parameter must be a number between Min_Data = 6 and Max_Data = 127 */ 264 265 uint32_t PLLP; /*!< PLLP: Division factor for SAI & ADC clock. 266 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 267 268 uint32_t PLLQ; /*!< PLLQ: Division factor for RNG and USB clocks. 269 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 270 271 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 272 User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. 273 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 274 275 } RCC_PLLInitTypeDef; 276 277 /** 278 * @brief RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition 279 */ 280 typedef struct 281 { 282 uint32_t OscillatorType; /*!< The oscillators to be configured. 283 This parameter can be a combination of @ref RCC_Oscillator_Type */ 284 285 uint32_t HSEState; /*!< The new state of the HSE. 286 This parameter can be a value of @ref RCC_HSE_Config */ 287 288 uint32_t LSEState; /*!< The new state of the LSE. 289 This parameter can be a value of @ref RCC_LSE_Config */ 290 291 uint32_t HSIState; /*!< The new state of the HSI. 292 This parameter can be a value of @ref RCC_HSI_Config */ 293 294 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_HSICALIBRATION_DEFAULT).*/ 295 296 uint32_t LSIState; /*!< The new state of the LSI. 297 This parameter can be a value of @ref RCC_LSI_Config */ 298 299 uint32_t LSI2CalibrationValue; /*!< The LSI2 calibration trimming value . 300 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF */ 301 302 uint32_t MSIState; /*!< The new state of the MSI. 303 This parameter can be a value of @ref RCC_MSI_Config */ 304 305 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_MSICALIBRATION_DEFAULT). 306 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 307 308 uint32_t MSIClockRange; /*!< The MSI frequency range. 309 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 310 311 #if defined(RCC_HSI48_SUPPORT) 312 uint32_t HSI48State; /*!< The new state of the HSI48 . 313 This parameter can be a value of @ref RCC_HSI48_Config */ 314 #endif /* RCC_HSI48_SUPPORT */ 315 316 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 317 318 } RCC_OscInitTypeDef; 319 320 /** 321 * @brief RCC System, AHB and APB buses clock configuration structure definition 322 */ 323 typedef struct 324 { 325 uint32_t ClockType; /*!< The clock to be configured. 326 This parameter can be a combination of @ref RCC_System_Clock_Type */ 327 328 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 329 This parameter can be a value of @ref RCC_System_Clock_Source */ 330 331 uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). 332 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 333 334 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 335 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 336 337 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 338 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 339 340 uint32_t AHBCLK2Divider; /*!< The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). 341 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 342 343 uint32_t AHBCLK4Divider; /*!< The AHB shared clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK). 344 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 345 346 } RCC_ClkInitTypeDef; 347 348 /** 349 * @} 350 */ 351 352 /* Exported constants --------------------------------------------------------*/ 353 /** @defgroup RCC_Exported_Constants RCC Exported Constants 354 * @{ 355 */ 356 357 /** @defgroup RCC_Timeout_Value Timeout Values 358 * @{ 359 */ 360 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 361 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ 362 /** 363 * @} 364 */ 365 366 /** @defgroup RCC_Oscillator_Type Oscillator Type 367 * @{ 368 */ 369 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 370 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 371 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 372 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 373 #define RCC_OSCILLATORTYPE_LSI1 0x00000008U /*!< LSI1 to configure */ 374 #define RCC_OSCILLATORTYPE_LSI2 0x00000010U /*!< LSI2 to configure */ 375 #define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */ 376 #if defined(RCC_HSI48_SUPPORT) 377 #define RCC_OSCILLATORTYPE_HSI48 0x00000040U /*!< HSI48 to configure */ 378 #endif /* RCC_HSI48_SUPPORT */ 379 /** 380 * @} 381 */ 382 383 /** @defgroup RCC_HSE_Config HSE Config 384 * @{ 385 */ 386 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 387 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 388 /** 389 * @} 390 */ 391 392 /** @defgroup RCC_LSE_Config LSE Config 393 * @{ 394 */ 395 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 396 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 397 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 398 /** 399 * @} 400 */ 401 402 /** @defgroup RCC_HSI_Config HSI Config 403 * @{ 404 */ 405 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 406 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 407 408 #define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ 409 /** 410 * @} 411 */ 412 413 /** @defgroup RCC_LSI_Config LSI Config 414 * @{ 415 */ 416 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 417 #define RCC_LSI_ON (RCC_CSR_LSI1ON | RCC_CSR_LSI2ON) /*!< LSI1 or LSI2 clock activation */ 418 /** 419 * @} 420 */ 421 422 /** @defgroup RCC_MSI_Config MSI Config 423 * @{ 424 */ 425 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 426 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 427 428 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 429 /** 430 * @} 431 */ 432 433 #if defined(RCC_HSI48_SUPPORT) 434 /** @defgroup RCC_HSI48_Config HSI48 Config 435 * @{ 436 */ 437 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 438 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 439 /** 440 * @} 441 */ 442 #endif /* RCC_HSI48_SUPPORT */ 443 444 /** @defgroup RCC_PLL_Config PLL Config 445 * @{ 446 */ 447 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 448 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 449 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 450 /** 451 * @} 452 */ 453 454 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 455 * @{ 456 */ 457 #define RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1 /*!< PLLM division factor = 1 */ 458 #define RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2 /*!< PLLM division factor = 2 */ 459 #define RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3 /*!< PLLM division factor = 3 */ 460 #define RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4 /*!< PLLM division factor = 4 */ 461 #define RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5 /*!< PLLM division factor = 5 */ 462 #define RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6 /*!< PLLM division factor = 6 */ 463 #define RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7 /*!< PLLM division factor = 7 */ 464 #define RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8 /*!< PLLM division factor = 8 */ 465 /** 466 * @} 467 */ 468 469 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 470 * @{ 471 */ 472 #define RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2 /*!< PLLP division factor = 2 */ 473 #define RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3 /*!< PLLP division factor = 3 */ 474 #define RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4 /*!< PLLP division factor = 4 */ 475 #define RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5 /*!< PLLP division factor = 5 */ 476 #define RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6 /*!< PLLP division factor = 6 */ 477 #define RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7 /*!< PLLP division factor = 7 */ 478 #define RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8 /*!< PLLP division factor = 8 */ 479 #define RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9 /*!< PLLP division factor = 9 */ 480 #define RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10 /*!< PLLP division factor = 10 */ 481 #define RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11 /*!< PLLP division factor = 11 */ 482 #define RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12 /*!< PLLP division factor = 12 */ 483 #define RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13 /*!< PLLP division factor = 13 */ 484 #define RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14 /*!< PLLP division factor = 14 */ 485 #define RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15 /*!< PLLP division factor = 15 */ 486 #define RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16 /*!< PLLP division factor = 16 */ 487 #define RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17 /*!< PLLP division factor = 17 */ 488 #define RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18 /*!< PLLP division factor = 18 */ 489 #define RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19 /*!< PLLP division factor = 19 */ 490 #define RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20 /*!< PLLP division factor = 20 */ 491 #define RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21 /*!< PLLP division factor = 21 */ 492 #define RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22 /*!< PLLP division factor = 22 */ 493 #define RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23 /*!< PLLP division factor = 23 */ 494 #define RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24 /*!< PLLP division factor = 24 */ 495 #define RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25 /*!< PLLP division factor = 25 */ 496 #define RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26 /*!< PLLP division factor = 26 */ 497 #define RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27 /*!< PLLP division factor = 27 */ 498 #define RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28 /*!< PLLP division factor = 28 */ 499 #define RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29 /*!< PLLP division factor = 29 */ 500 #define RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30 /*!< PLLP division factor = 30 */ 501 #define RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31 /*!< PLLP division factor = 31 */ 502 #define RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32 /*!< PLLP division factor = 32 */ 503 /** 504 * @} 505 */ 506 507 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 508 * @{ 509 */ 510 #define RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2 /*!< PLLQ division factor = 2 */ 511 #define RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3 /*!< PLLQ division factor = 3 */ 512 #define RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4 /*!< PLLQ division factor = 4 */ 513 #define RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5 /*!< PLLQ division factor = 5 */ 514 #define RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6 /*!< PLLQ division factor = 6 */ 515 #define RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7 /*!< PLLQ division factor = 7 */ 516 #define RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8 /*!< PLLQ division factor = 8 */ 517 /** 518 * @} 519 */ 520 521 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 522 * @{ 523 */ 524 #define RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2 /*!< PLLR division factor = 2 */ 525 #define RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3 /*!< PLLR division factor = 3 */ 526 #define RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4 /*!< PLLR division factor = 4 */ 527 #define RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5 /*!< PLLR division factor = 5 */ 528 #define RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6 /*!< PLLR division factor = 6 */ 529 #define RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7 /*!< PLLR division factor = 7 */ 530 #define RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8 /*!< PLLR division factor = 8 */ 531 /** 532 * @} 533 */ 534 535 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 536 * @{ 537 */ 538 #define RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE /*!< No clock selected as PLL entry clock source */ 539 #define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI /*!< MSI clock selected as PLL entry clock source */ 540 #define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI /*!< HSI clock selected as PLL entry clock source */ 541 #define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE /*!< HSE clock selected as PLL entry clock source */ 542 /** 543 * @} 544 */ 545 546 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 547 * @{ 548 */ 549 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 550 #define RCC_PLL_USBCLK RCC_PLLCFGR_PLLQEN /*!< PLLUSBCLK selection from main PLL */ 551 #define RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN /*!< PLLRNGCLK selection from main PLL */ 552 #if defined(SAI1) 553 #define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */ 554 #endif /* SAI1 */ 555 #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ 556 /** 557 * @} 558 */ 559 560 #if defined(SAI1) 561 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 562 * @{ 563 */ 564 #define RCC_PLLSAI1_ADCCLK RCC_PLLSAI1CFGR_PLLREN /*!< PLLADCCLK selection from PLLSAI1 */ 565 #define RCC_PLLSAI1_USBCLK RCC_PLLSAI1CFGR_PLLQEN /*!< USBCLK selection from PLLSAI1 */ 566 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLPEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 567 /** 568 * @} 569 */ 570 #endif /* SAI1 */ 571 572 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 573 * @{ 574 */ 575 #define RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0 /*!< MSI = 100 KHz */ 576 #define RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1 /*!< MSI = 200 KHz */ 577 #define RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2 /*!< MSI = 400 KHz */ 578 #define RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3 /*!< MSI = 800 KHz */ 579 #define RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4 /*!< MSI = 1 MHz */ 580 #define RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5 /*!< MSI = 2 MHz */ 581 #define RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6 /*!< MSI = 4 MHz */ 582 #define RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7 /*!< MSI = 8 MHz */ 583 #define RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8 /*!< MSI = 16 MHz */ 584 #define RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9 /*!< MSI = 24 MHz */ 585 #define RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10 /*!< MSI = 32 MHz */ 586 #define RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11 /*!< MSI = 48 MHz */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup RCC_System_Clock_Type System Clock Type 592 * @{ 593 */ 594 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 595 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 596 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 597 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 598 #define RCC_CLOCKTYPE_HCLK2 0x00000020U /*!< HCLK2 to configure */ 599 #define RCC_CLOCKTYPE_HCLK4 0x00000040U /*!< HCLK4 to configure */ 600 /** 601 * @} 602 */ 603 604 /** @defgroup RCC_System_Clock_Source System Clock Source 605 * @{ 606 */ 607 #define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI /*!< MSI selection as system clock */ 608 #define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI /*!< HSI selection as system clock */ 609 #define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE /*!< HSE selection as system clock */ 610 #define RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL /*!< PLL selection as system clock */ 611 /** 612 * @} 613 */ 614 615 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 616 * @{ 617 */ 618 #define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI /*!< MSI used as system clock */ 619 #define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI /*!< HSI used as system clock */ 620 #define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE /*!< HSE used as system clock */ 621 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL /*!< PLL used as system clock */ 622 /** 623 * @} 624 */ 625 626 /** @defgroup RCC_AHBx_Clock_Source AHB Clock Source 627 * @{ 628 */ 629 #define RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1 /*!< SYSCLK not divided */ 630 #define RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2 /*!< SYSCLK divided by 2 */ 631 #define RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3 /*!< SYSCLK divided by 3 */ 632 #define RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4 /*!< SYSCLK divided by 4 */ 633 #define RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5 /*!< SYSCLK divided by 5 */ 634 #define RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6 /*!< SYSCLK divided by 6 */ 635 #define RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8 /*!< SYSCLK divided by 8 */ 636 #define RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10 /*!< SYSCLK divided by 10 */ 637 #define RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16 /*!< SYSCLK divided by 16 */ 638 #define RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32 /*!< SYSCLK divided by 32 */ 639 #define RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64 /*!< SYSCLK divided by 64 */ 640 #define RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128 /*!< SYSCLK divided by 128 */ 641 #define RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256 /*!< SYSCLK divided by 256 */ 642 #define RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512 /*!< SYSCLK divided by 512 */ 643 /** 644 * @} 645 */ 646 647 /** @defgroup RCC_APBx_Clock_Source APB1 Clock Source 648 * @{ 649 */ 650 #define RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1 /*!< HCLK not divided */ 651 #define RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2 /*!< HCLK divided by 2 */ 652 #define RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4 /*!< HCLK divided by 4 */ 653 #define RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8 /*!< HCLK divided by 8 */ 654 #define RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16 /*!< HCLK divided by 16 */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 660 * @{ 661 */ 662 #define RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE /*!< No clock used as RTC clock */ 663 #define RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE /*!< LSE oscillator clock used as RTC clock */ 664 #define RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI /*!< LSI oscillator clock used as RTC clock */ 665 #define RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32 /*!< HSE oscillator clock divided by 32 used as RTC clock */ 666 /** 667 * @} 668 */ 669 670 /** @defgroup RCC_MCO_Index MCO Index 671 * @{ 672 */ 673 674 /* @cond */ 675 /* 32 28 20 16 0 676 -------------------------------- 677 | MCO | GPIO | GPIO | GPIO | 678 | Index | AF | Port | Pin | 679 -------------------------------*/ 680 681 #define RCC_MCO_GPIOPORT_POS 16U 682 #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) 683 #define RCC_MCO_GPIOAF_POS 20U 684 #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) 685 #define RCC_MCO_INDEX_POS 28U 686 #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) 687 688 #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ 689 #define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ 690 /* @endcond */ 691 692 #define RCC_MCO1_PA8 (RCC_MCO1_INDEX | \ 693 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 694 #define RCC_MCO1 RCC_MCO1_PA8 /*!< Alias for compatibility */ 695 696 #define RCC_MCO2_PB6 (RCC_MCO2_INDEX | \ 697 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOB) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_6) 698 #define RCC_MCO2 RCC_MCO2_PB6 /*!< Alias for compatibility */ 699 700 #if defined(RCC_MCO3_SUPPORT) 701 /* @cond */ 702 #define RCC_MCO3_INDEX (0x2UL << RCC_MCO_INDEX_POS) /*!< MCO3 index */ 703 /* @endcond */ 704 705 #define RCC_MCO3_PA15 (RCC_MCO3_INDEX | \ 706 (GPIO_AF6_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_15) 707 #define RCC_MCO3 RCC_MCO3_PA15 /*!< Alias for compatibility */ 708 #endif /* RCC_MCO3_SUPPORT */ 709 710 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ 711 /** 712 * @} 713 */ 714 715 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 716 * @{ 717 */ 718 #define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */ 719 #define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selection as MCO1 source */ 720 #define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selection as MCO1 source */ 721 #define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selection as MCO1 source */ 722 #define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selection as MCO1 source */ 723 #define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< PLLCLK selection as MCO1 source */ 724 #define RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1 /*!< LSI1 selection as MCO1 source */ 725 #define RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2 /*!< LSI2 selection as MCO1 source */ 726 #define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selection as MCO1 source */ 727 #if defined(RCC_HSI48_SUPPORT) 728 #define RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48 /*!< HSI48 selection as MCO1 source */ 729 #endif /* RCC_HSI48_SUPPORT */ 730 #define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB /*!< HSE before stabilization selection as MCO1 source */ 731 732 /** 733 * @} 734 */ 735 736 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 737 * @{ 738 */ 739 #define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */ 740 #define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ 741 #define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ 742 #define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ 743 #define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16 /*!< MCO divided by 16 */ 744 /** 745 * @} 746 */ 747 748 /** @defgroup RCC_HSEAMPTHRESHOLD HSE bias current factor 749 * @{ 750 */ 751 #define RCC_HSEAMPTHRESHOLD_1_2 LL_RCC_HSEAMPTHRESHOLD_1_2 /*!< HSE bias current factor 1/2 */ 752 #define RCC_HSEAMPTHRESHOLD_3_4 LL_RCC_HSEAMPTHRESHOLD_3_4 /*!< HSE bias current factor 3/4 */ 753 754 /** 755 * @} 756 */ 757 758 /** @defgroup RCC_HSE_CURRENTMAX HSE current max limit 759 * @{ 760 */ 761 #define RCC_HSE_CURRENTMAX_0 LL_RCC_HSE_CURRENTMAX_0 /*!< HSE current max limit 0.18 mA/V */ 762 #define RCC_HSE_CURRENTMAX_1 LL_RCC_HSE_CURRENTMAX_1 /*!< HSE current max limit 0.57 mA/V */ 763 #define RCC_HSE_CURRENTMAX_2 LL_RCC_HSE_CURRENTMAX_2 /*!< HSE current max limit 0.78 mA/V */ 764 #define RCC_HSE_CURRENTMAX_3 LL_RCC_HSE_CURRENTMAX_3 /*!< HSE current max limit 1.13 mA/V */ 765 #define RCC_HSE_CURRENTMAX_4 LL_RCC_HSE_CURRENTMAX_4 /*!< HSE current max limit 0.61 mA/V */ 766 #define RCC_HSE_CURRENTMAX_5 LL_RCC_HSE_CURRENTMAX_5 /*!< HSE current max limit 1.65 mA/V */ 767 #define RCC_HSE_CURRENTMAX_6 LL_RCC_HSE_CURRENTMAX_6 /*!< HSE current max limit 2.12 mA/V */ 768 #define RCC_HSE_CURRENTMAX_7 LL_RCC_HSE_CURRENTMAX_7 /*!< HSE current max limit 2.84 mA/V */ 769 770 /** 771 * @} 772 */ 773 774 /** @defgroup RCC_Interrupt Interrupts 775 * @{ 776 */ 777 #define RCC_IT_LSI1RDY LL_RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ 778 #define RCC_IT_LSI2RDY LL_RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ 779 #define RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 780 #define RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 781 #define RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 782 #define RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 783 #define RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 784 #if defined(SAI1) 785 #define RCC_IT_PLLSAI1RDY LL_RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 786 #endif /* SAI1 */ 787 #define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 788 #define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 789 #if defined(RCC_HSI48_SUPPORT) 790 #define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 791 #endif /* RCC_HSI48_SUPPORT */ 792 /** 793 * @} 794 */ 795 796 797 /** @defgroup RCC_Flag Flags 798 * Elements values convention: XXXYYYYYb 799 * - YYYYY : Flag position in the register 800 * - XXX : Register index 801 * - 001: CR register 802 * - 010: BDCR register 803 * - 011: CSR register 804 * - 100: CRRCR register 805 * @{ 806 */ 807 /* Flags in the CR register */ 808 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 809 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 810 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 811 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 812 #if defined(SAI1) 813 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 814 #endif /* SAI1 */ 815 816 /* Flags in the BDCR register */ 817 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 818 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 819 820 /* Flags in the CSR register */ 821 #define RCC_FLAG_LSI1RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI1RDY_Pos) /*!< LSI1 Ready flag */ 822 #define RCC_FLAG_LSI2RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI2RDY_Pos) /*!< LSI2 Ready flag */ 823 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 824 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< Pin reset flag (NRST pin) */ 825 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 826 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 827 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Watchdog reset flag */ 828 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 829 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 830 831 /* Flags in the CRRCR register */ 832 #if defined(RCC_HSI48_SUPPORT) 833 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 834 #endif /* RCC_HSI48_SUPPORT */ 835 /** 836 * @} 837 */ 838 839 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration 840 * @{ 841 */ 842 #define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW /*!< LSE low drive capability */ 843 #define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW /*!< LSE medium low drive capability */ 844 #define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH /*!< LSE medium high drive capability */ 845 #define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH /*!< LSE high drive capability */ 846 /** 847 * @} 848 */ 849 850 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 851 * @{ 852 */ 853 #define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI /*!< MSI selection after wake-up from STOP */ 854 #define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI /*!< HSI selection after wake-up from STOP */ 855 /** 856 * @} 857 */ 858 859 /** 860 * @} 861 */ 862 863 /* Exported macros -----------------------------------------------------------*/ 864 865 /** @defgroup RCC_Exported_Macros RCC Exported Macros 866 * @{ 867 */ 868 869 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 870 * @brief Enable or disable the AHB1 peripheral clock. 871 * @note After reset, the peripheral clock (used for registers read/write access) 872 * is disabled and the application software has to enable this clock before 873 * using it. 874 * @{ 875 */ 876 877 #define __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) 878 #if defined(DMA2) 879 #define __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2) 880 #endif /* DMA2 */ 881 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 882 #define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC) 883 #if defined(TSC) 884 #define __HAL_RCC_TSC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC) 885 #endif /* TSC */ 886 887 #define __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1) 888 #if defined(DMA2) 889 #define __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2) 890 #endif /* DMA2 */ 891 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 892 #define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC) 893 #if defined(TSC) 894 #define __HAL_RCC_TSC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC) 895 #endif /* TSC */ 896 /** 897 * @} 898 */ 899 900 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 901 * @brief Enable or disable the AHB2 peripheral clock. 902 * @note After reset, the peripheral clock (used for registers read/write access) 903 * is disabled and the application software has to enable this clock before 904 * using it. 905 * @{ 906 */ 907 908 #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 909 #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 910 #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 911 #if defined(GPIOD) 912 #define __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD) 913 #endif /* GPIOD */ 914 #define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE) 915 #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 916 #if defined(ADC_SUPPORT_5_MSPS) 917 #define __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC) 918 #endif /* ADC_SUPPORT_5_MSPS */ 919 #if defined(AES1) 920 #define __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1) 921 #endif /* AES1 */ 922 #define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 923 #define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 924 #define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 925 #if defined(GPIOD) 926 #define __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD) 927 #endif /* GPIOD */ 928 #define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE) 929 #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 930 #if defined(ADC_SUPPORT_5_MSPS) 931 #define __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC) 932 #endif /* ADC_SUPPORT_5_MSPS */ 933 #if defined(AES1) 934 #define __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1) 935 #endif /* AES1 */ 936 937 /** 938 * @} 939 */ 940 941 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 942 * @brief Enable or disable the AHB3 peripheral clock. 943 * @note After reset, the peripheral clock (used for registers read/write access) 944 * is disabled and the application software has to enable this clock before 945 * using it. 946 * @{ 947 */ 948 949 #if defined(QUADSPI) 950 #define __HAL_RCC_QUADSPI_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 951 #endif /* QUADSPI */ 952 #define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) 953 #define __HAL_RCC_AES2_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2) 954 #define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) 955 #define __HAL_RCC_HSEM_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM) 956 #define __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC) 957 #define __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH) 958 959 #if defined(QUADSPI) 960 #define __HAL_RCC_QUADSPI_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 961 #endif /* QUADSPI */ 962 #define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) 963 #define __HAL_RCC_AES2_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2) 964 #define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) 965 #define __HAL_RCC_HSEM_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM) 966 #define __HAL_RCC_IPCC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC) 967 #define __HAL_RCC_FLASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH) 968 969 /** 970 * @} 971 */ 972 973 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 974 * @brief Enable or disable the APB1 peripheral clock. 975 * @note After reset, the peripheral clock (used for registers read/write access) 976 * is disabled and the application software has to enable this clock before 977 * using it. 978 * @{ 979 */ 980 981 #define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 982 #define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) 983 #define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) 984 #if defined(LCD) 985 #define __HAL_RCC_LCD_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD) 986 #endif /* LCD */ 987 #if defined(SPI2) 988 #define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) 989 #endif /* SPI2 */ 990 #define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) 991 #if defined(I2C3) 992 #define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) 993 #endif /* I2C3 */ 994 #if defined(CRS) 995 #define __HAL_RCC_CRS_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS) 996 #endif /* CRS */ 997 #if defined(USB) 998 #define __HAL_RCC_USB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB) 999 #endif /* USB */ 1000 #define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1001 #define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 1002 #if defined(LPUART1) 1003 #define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1) 1004 #endif /* LPUART1 */ 1005 1006 #define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 1007 #define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) 1008 #if defined(LCD) 1009 #define __HAL_RCC_LCD_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD) 1010 #endif /* LCD */ 1011 #if defined(SPI2) 1012 #define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) 1013 #endif /* SPI2 */ 1014 #define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) 1015 #if defined(I2C3) 1016 #define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) 1017 #endif /* I2C3 */ 1018 #if defined(CRS) 1019 #define __HAL_RCC_CRS_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS) 1020 #endif /* CRS */ 1021 #if defined(USB) 1022 #define __HAL_RCC_USB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB) 1023 #endif /* USB */ 1024 #define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1025 1026 #define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 1027 #if defined(LPUART1) 1028 #define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1) 1029 #endif /* LPUART1 */ 1030 1031 /** 1032 * @} 1033 */ 1034 1035 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1036 * @brief Enable or disable the APB2 peripheral clock. 1037 * @note After reset, the peripheral clock (used for registers read/write access) 1038 * is disabled and the application software has to enable this clock before 1039 * using it. 1040 * @{ 1041 */ 1042 1043 #if defined(ADC_SUPPORT_2_5_MSPS) 1044 #define __HAL_RCC_ADC_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC) 1045 #endif /* ADC_SUPPORT_2_5_MSPS */ 1046 #define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) 1047 #define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) 1048 #define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) 1049 #define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) 1050 #define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) 1051 #if defined(SAI1) 1052 #define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1) 1053 #endif /* SAI1 */ 1054 1055 #if defined(ADC_SUPPORT_2_5_MSPS) 1056 #define __HAL_RCC_ADC_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC) 1057 #endif /* ADC_SUPPORT_2_5_MSPS */ 1058 #define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) 1059 #define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) 1060 #define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) 1061 #define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) 1062 #define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) 1063 #if defined(SAI1) 1064 #define __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1) 1065 #endif /* SAI1 */ 1066 1067 /** 1068 * @} 1069 */ 1070 1071 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1072 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1073 * @note After reset, the peripheral clock (used for registers read/write access) 1074 * is disabled and the application software has to enable this clock before 1075 * using it. 1076 * @{ 1077 */ 1078 1079 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1) 1080 #if defined(DMA2) 1081 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2) 1082 #endif /* DMA2 */ 1083 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1084 #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC) 1085 #if defined(TSC) 1086 #define __HAL_RCC_TSC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC) 1087 #endif /* TSC */ 1088 1089 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)) 1090 #if defined(DMA2) 1091 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)) 1092 #endif /* DMA2 */ 1093 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)) 1094 #define __HAL_RCC_CRC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)) 1095 #if defined(TSC) 1096 #define __HAL_RCC_TSC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)) 1097 #endif /* TSC */ 1098 1099 /** 1100 * @} 1101 */ 1102 1103 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1104 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1105 * @note After reset, the peripheral clock (used for registers read/write access) 1106 * is disabled and the application software has to enable this clock before 1107 * using it. 1108 * @{ 1109 */ 1110 1111 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA) 1112 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB) 1113 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC) 1114 #if defined(GPIOD) 1115 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD) 1116 #endif /* GPIOD */ 1117 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE) 1118 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH) 1119 #if defined(ADC_SUPPORT_5_MSPS) 1120 #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC) 1121 #endif /* ADC_SUPPORT_5_MSPS */ 1122 #if defined(AES1) 1123 #define __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1) 1124 #endif /* AES1 */ 1125 1126 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)) 1127 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)) 1128 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)) 1129 #if defined(GPIOD) 1130 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)) 1131 #endif /* GPIOD */ 1132 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)) 1133 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)) 1134 #if defined(ADC_SUPPORT_5_MSPS) 1135 #define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)) 1136 #endif /* ADC_SUPPORT_5_MSPS */ 1137 #if defined(AES1) 1138 #define __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)) 1139 #endif /* AES1 */ 1140 1141 /** 1142 * @} 1143 */ 1144 1145 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1146 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1147 * @note After reset, the peripheral clock (used for registers read/write access) 1148 * is disabled and the application software has to enable this clock before 1149 * using it. 1150 * @{ 1151 */ 1152 1153 #if defined(QUADSPI) 1154 #define __HAL_RCC_QUADSPI_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 1155 #endif /* QUADSPI */ 1156 #define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) 1157 #define __HAL_RCC_AES2_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2) 1158 #define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) 1159 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM) 1160 #define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC) 1161 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH) 1162 1163 #if defined(QUADSPI) 1164 #define __HAL_RCC_QUADSPI_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)) 1165 #endif /* QUADSPI */ 1166 #define __HAL_RCC_PKA_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)) 1167 #define __HAL_RCC_AES2_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)) 1168 #define __HAL_RCC_RNG_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)) 1169 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)) 1170 #define __HAL_RCC_IPCC_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)) 1171 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)) 1172 1173 /** 1174 * @} 1175 */ 1176 1177 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1178 * @brief Check whether the APB1 peripheral clock is enabled or not. 1179 * @note After reset, the peripheral clock (used for registers read/write access) 1180 * is disabled and the application software has to enable this clock before 1181 * using it. 1182 * @{ 1183 */ 1184 1185 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB) 1186 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) 1187 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) 1188 #if defined(LCD) 1189 #define __HAL_RCC_LCD_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD) 1190 #endif /* LCD */ 1191 #if defined(SPI2) 1192 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) 1193 #endif /* SPI2 */ 1194 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) 1195 #if defined(I2C3) 1196 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) 1197 #endif /* I2C3 */ 1198 #if defined(CRS) 1199 #define __HAL_RCC_CRS_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS) 1200 #endif /* CRS */ 1201 #if defined(USB) 1202 #define __HAL_RCC_USB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB) 1203 #endif /* USB */ 1204 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1205 1206 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2) 1207 #if defined(LPUART1) 1208 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1) 1209 #endif /* LPUART1 */ 1210 1211 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)) 1212 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)) 1213 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)) 1214 #if defined(LCD) 1215 #define __HAL_RCC_LCD_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)) 1216 #endif /* LCD */ 1217 #if defined(SPI2) 1218 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)) 1219 #endif /* SPI2 */ 1220 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)) 1221 #if defined(I2C3) 1222 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)) 1223 #endif /* I2C3 */ 1224 #if defined(CRS) 1225 #define __HAL_RCC_CRS_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)) 1226 #endif /* CRS */ 1227 #if defined(USB) 1228 #define __HAL_RCC_USB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)) 1229 #endif /* USB */ 1230 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)) 1231 1232 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)) 1233 #if defined(LPUART1) 1234 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)) 1235 #endif /* LPUART1 */ 1236 1237 /** 1238 * @} 1239 */ 1240 1241 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1242 * @brief Check whether the APB2 peripheral clock is enabled or not. 1243 * @note After reset, the peripheral clock (used for registers read/write access) 1244 * is disabled and the application software has to enable this clock before 1245 * using it. 1246 * @{ 1247 */ 1248 1249 #if defined(ADC_SUPPORT_2_5_MSPS) 1250 #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC) 1251 #endif /* ADC_SUPPORT_2_5_MSPS */ 1252 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) 1253 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) 1254 #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) 1255 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) 1256 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) 1257 #if defined(SAI1) 1258 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1) 1259 #endif /* SAI1 */ 1260 1261 1262 #if defined(ADC_SUPPORT_2_5_MSPS) 1263 #define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC)) 1264 #endif /* ADC_SUPPORT_2_5_MSPS */ 1265 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)) 1266 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)) 1267 #define __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)) 1268 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)) 1269 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)) 1270 #if defined(SAI1) 1271 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)) 1272 #endif /* SAI1 */ 1273 1274 /** 1275 * @} 1276 */ 1277 1278 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 1279 * @brief Enable or disable the AHB1 peripheral clock. 1280 * @note After reset, the peripheral clock (used for registers read/write access) 1281 * is disabled and the application software has to enable this clock before 1282 * using it. 1283 * @{ 1284 */ 1285 1286 #define __HAL_RCC_C2DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1287 #if defined(DMA2) 1288 #define __HAL_RCC_C2DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1289 #endif /* DMA2 */ 1290 #define __HAL_RCC_C2DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1291 #define __HAL_RCC_C2SRAM1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1292 #define __HAL_RCC_C2CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1293 #if defined(TSC) 1294 #define __HAL_RCC_C2TSC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1295 #endif /* TSC */ 1296 1297 #define __HAL_RCC_C2DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1298 #if defined(DMA2) 1299 #define __HAL_RCC_C2DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1300 #endif /* DMA2 */ 1301 #define __HAL_RCC_C2DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1302 #define __HAL_RCC_C2SRAM1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1303 #define __HAL_RCC_C2CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1304 #if defined(TSC) 1305 #define __HAL_RCC_C2TSC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1306 #endif /* TSC */ 1307 1308 /** 1309 * @} 1310 */ 1311 1312 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 1313 * @brief Enable or disable the AHB2 peripheral clock. 1314 * @note After reset, the peripheral clock (used for registers read/write access) 1315 * is disabled and the application software has to enable this clock before 1316 * using it. 1317 * @{ 1318 */ 1319 1320 #define __HAL_RCC_C2GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1321 #define __HAL_RCC_C2GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1322 #define __HAL_RCC_C2GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1323 #if defined(GPIOD) 1324 #define __HAL_RCC_C2GPIOD_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1325 #endif /* GPIOD */ 1326 #define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1327 #define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1328 #if defined(ADC_SUPPORT_5_MSPS) 1329 #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1330 #endif /* ADC_SUPPORT_5_MSPS */ 1331 #if defined(AES1) 1332 #define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1333 #endif /* AES1 */ 1334 1335 #define __HAL_RCC_C2GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1336 #define __HAL_RCC_C2GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1337 #define __HAL_RCC_C2GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1338 #if defined(GPIOD) 1339 #define __HAL_RCC_C2GPIOD_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1340 #endif /* GPIOD */ 1341 #define __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1342 #define __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1343 #if defined(ADC_SUPPORT_5_MSPS) 1344 #define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1345 #endif /* ADC_SUPPORT_5_MSPS */ 1346 #if defined(AES1) 1347 #define __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1348 #endif /* AES1 */ 1349 1350 /** 1351 * @} 1352 */ 1353 1354 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 1355 * @brief Enable or disable the AHB3 peripheral clock. 1356 * @note After reset, the peripheral clock (used for registers read/write access) 1357 * is disabled and the application software has to enable this clock before 1358 * using it. 1359 * @{ 1360 */ 1361 1362 #define __HAL_RCC_C2PKA_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1363 #define __HAL_RCC_C2AES2_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1364 #define __HAL_RCC_C2RNG_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1365 #define __HAL_RCC_C2HSEM_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1366 #define __HAL_RCC_C2IPCC_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1367 #define __HAL_RCC_C2FLASH_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1368 1369 #define __HAL_RCC_C2PKA_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1370 #define __HAL_RCC_C2AES2_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1371 #define __HAL_RCC_C2RNG_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1372 #define __HAL_RCC_C2HSEM_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1373 #define __HAL_RCC_C2IPCC_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1374 #define __HAL_RCC_C2FLASH_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1375 1376 /** 1377 * @} 1378 */ 1379 1380 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1381 * @brief Enable or disable the APB1 peripheral clock. 1382 * @note After reset, the peripheral clock (used for registers read/write access) 1383 * is disabled and the application software has to enable this clock before 1384 * using it. 1385 * @{ 1386 */ 1387 1388 #define __HAL_RCC_C2RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1389 #define __HAL_RCC_C2TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1390 #if defined(LCD) 1391 #define __HAL_RCC_C2LCD_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1392 #endif /* LCD */ 1393 #if defined(SPI2) 1394 #define __HAL_RCC_C2SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1395 #endif /* SPI2 */ 1396 #define __HAL_RCC_C2I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1397 #if defined(I2C3) 1398 #define __HAL_RCC_C2I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1399 #endif /* I2C3 */ 1400 #if defined(CRS) 1401 #define __HAL_RCC_C2CRS_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1402 #endif /* CRS */ 1403 #if defined(USB) 1404 #define __HAL_RCC_C2USB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB) 1405 #endif /* USB */ 1406 #define __HAL_RCC_C2LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1407 1408 #define __HAL_RCC_C2LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1409 #if defined(LPUART1) 1410 #define __HAL_RCC_C2LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1411 #endif /* LPUART1 */ 1412 1413 #define __HAL_RCC_C2RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1414 #define __HAL_RCC_C2TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1415 #if defined(LCD) 1416 #define __HAL_RCC_C2LCD_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1417 #endif /* LCD */ 1418 #if defined(SPI2) 1419 #define __HAL_RCC_C2SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1420 #endif /* SPI2 */ 1421 #define __HAL_RCC_C2I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1422 #if defined(I2C3) 1423 #define __HAL_RCC_C2I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1424 #endif /* I2C3 */ 1425 #if defined(CRS) 1426 #define __HAL_RCC_C2CRS_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1427 #endif /* CRS */ 1428 #if defined(USB) 1429 #define __HAL_RCC_C2USB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB) 1430 #endif /* USB */ 1431 #define __HAL_RCC_C2LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1432 1433 #define __HAL_RCC_C2LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1434 #if defined(LPUART1) 1435 #define __HAL_RCC_C2LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1436 #endif /* LPUART1 */ 1437 1438 /** 1439 * @} 1440 */ 1441 1442 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1443 * @brief Enable or disable the APB2 peripheral clock. 1444 * @note After reset, the peripheral clock (used for registers read/write access) 1445 * is disabled and the application software has to enable this clock before 1446 * using it. 1447 * @{ 1448 */ 1449 1450 #if defined(ADC_SUPPORT_2_5_MSPS) 1451 #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC) 1452 #endif /* ADC_SUPPORT_2_5_MSPS */ 1453 #define __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1454 #define __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1455 #define __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1456 #define __HAL_RCC_C2TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1457 #define __HAL_RCC_C2TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1458 #if defined(SAI1) 1459 #define __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1460 #endif /* SAI1 */ 1461 1462 #if defined(ADC_SUPPORT_2_5_MSPS) 1463 #define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC) 1464 #endif /* ADC_SUPPORT_2_5_MSPS */ 1465 #define __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1466 #define __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1467 #define __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1468 #define __HAL_RCC_C2TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1469 #define __HAL_RCC_C2TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1470 #if defined(SAI1) 1471 #define __HAL_RCC_C2SAI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1472 #endif /* SAI1 */ 1473 1474 /** 1475 * @} 1476 */ 1477 1478 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1479 * @brief Enable or disable the APB3 peripheral clock. 1480 * @note After reset, the peripheral clock (used for registers read/write access) 1481 * is disabled and the application software has to enable this clock before 1482 * using it. 1483 * @{ 1484 */ 1485 1486 #define __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1487 #if defined(RCC_802_SUPPORT) 1488 #define __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802) 1489 #endif /* RCC_802_SUPPORT */ 1490 1491 #define __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1492 #if defined(RCC_802_SUPPORT) 1493 #define __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802) 1494 #endif /* RCC_802_SUPPORT */ 1495 1496 /** 1497 * @} 1498 */ 1499 1500 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1501 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1502 * @note After reset, the peripheral clock (used for registers read/write access) 1503 * is disabled and the application software has to enable this clock before 1504 * using it. 1505 * @{ 1506 */ 1507 1508 #define __HAL_RCC_C2DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1509 #if defined(DMA2) 1510 #define __HAL_RCC_C2DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1511 #endif /* DMA2 */ 1512 #define __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1513 #define __HAL_RCC_C2SRAM1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1514 #define __HAL_RCC_C2CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1515 #if defined(TSC) 1516 #define __HAL_RCC_C2TSC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1517 #endif /* TSC */ 1518 1519 #define __HAL_RCC_C2DMA1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)) 1520 #if defined(DMA2) 1521 #define __HAL_RCC_C2DMA2_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)) 1522 #endif /* DMA2 */ 1523 #define __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)) 1524 #define __HAL_RCC_C2SRAM1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)) 1525 #define __HAL_RCC_C2CRC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)) 1526 #if defined(TSC) 1527 #define __HAL_RCC_C2TSC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)) 1528 #endif /* TSC */ 1529 1530 /** 1531 * @} 1532 */ 1533 1534 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1535 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1536 * @note After reset, the peripheral clock (used for registers read/write access) 1537 * is disabled and the application software has to enable this clock before 1538 * using it. 1539 * @{ 1540 */ 1541 1542 #define __HAL_RCC_C2GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1543 #define __HAL_RCC_C2GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1544 #define __HAL_RCC_C2GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1545 #if defined(GPIOD) 1546 #define __HAL_RCC_C2GPIOD_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1547 #endif /* GPIOD */ 1548 #define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1549 #define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1550 #if defined(ADC_SUPPORT_5_MSPS) 1551 #define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1552 #endif /* ADC_SUPPORT_5_MSPS */ 1553 #if defined(AES1) 1554 #define __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1555 #endif /* AES1 */ 1556 1557 #define __HAL_RCC_C2GPIOA_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)) 1558 #define __HAL_RCC_C2GPIOB_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)) 1559 #define __HAL_RCC_C2GPIOC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)) 1560 #if defined(GPIOD) 1561 #define __HAL_RCC_C2GPIOD_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)) 1562 #endif /* GPIOD */ 1563 #define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)) 1564 #define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)) 1565 #if defined(ADC_SUPPORT_5_MSPS) 1566 #define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)) 1567 #endif /* ADC_SUPPORT_5_MSPS */ 1568 #if defined(AES1) 1569 #define __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)) 1570 #endif /* AES1 */ 1571 1572 /** 1573 * @} 1574 */ 1575 1576 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1577 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1578 * @note After reset, the peripheral clock (used for registers read/write access) 1579 * is disabled and the application software has to enable this clock before 1580 * using it. 1581 * @{ 1582 */ 1583 1584 #define __HAL_RCC_C2PKA_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1585 #define __HAL_RCC_C2AES2_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1586 #define __HAL_RCC_C2RNG_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1587 #define __HAL_RCC_C2HSEM_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1588 #define __HAL_RCC_C2IPCC_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1589 #define __HAL_RCC_C2FLASH_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1590 1591 #define __HAL_RCC_C2PKA_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)) 1592 #define __HAL_RCC_C2AES2_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2)) 1593 #define __HAL_RCC_C2RNG_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)) 1594 #define __HAL_RCC_C2HSEM_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)) 1595 #define __HAL_RCC_C2IPCC_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)) 1596 #define __HAL_RCC_C2FLASH_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)) 1597 1598 /** 1599 * @} 1600 */ 1601 1602 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1603 * @brief Check whether the APB1 peripheral clock is enabled or not. 1604 * @note After reset, the peripheral clock (used for registers read/write access) 1605 * is disabled and the application software has to enable this clock before 1606 * using it. 1607 * @{ 1608 */ 1609 1610 #define __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1611 #define __HAL_RCC_C2TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1612 #if defined(LCD) 1613 #define __HAL_RCC_C2LCD_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1614 #endif /* LCD */ 1615 #if defined(SPI2) 1616 #define __HAL_RCC_C2SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1617 #endif /* SPI2 */ 1618 #define __HAL_RCC_C2I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1619 #if defined(I2C3) 1620 #define __HAL_RCC_C2I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1621 #endif /* I2C3 */ 1622 #if defined(CRS) 1623 #define __HAL_RCC_C2CRS_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1624 #endif /* CRS */ 1625 #if defined(USB) 1626 #define __HAL_RCC_C2USB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB) 1627 #endif /* USB */ 1628 #define __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1629 1630 #define __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1631 #if defined(LPUART1) 1632 #define __HAL_RCC_C2LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1633 #endif /* LPUART1 */ 1634 1635 #define __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)) 1636 #define __HAL_RCC_C2TIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)) 1637 #if defined(LCD) 1638 #define __HAL_RCC_C2LCD_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)) 1639 #endif /* LCD */ 1640 #if defined(SPI2) 1641 #define __HAL_RCC_C2SPI2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)) 1642 #endif /* SPI2 */ 1643 #define __HAL_RCC_C2I2C1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)) 1644 #if defined(I2C3) 1645 #define __HAL_RCC_C2I2C3_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)) 1646 #endif /* I2C3 */ 1647 #if defined(CRS) 1648 #define __HAL_RCC_C2CRS_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)) 1649 #endif /* CRS */ 1650 #if defined(USB) 1651 #define __HAL_RCC_C2USB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)) 1652 #endif /* USB */ 1653 #define __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) 1654 1655 #define __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)) 1656 #if defined(LPUART1) 1657 #define __HAL_RCC_C2LPUART1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) 1658 #endif /* LPUART1*/ 1659 1660 /** 1661 * @} 1662 */ 1663 1664 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1665 * @brief Check whether the APB2 peripheral clock is enabled or not. 1666 * @note After reset, the peripheral clock (used for registers read/write access) 1667 * is disabled and the application software has to enable this clock before 1668 * using it. 1669 * @{ 1670 */ 1671 1672 #if defined(ADC_SUPPORT_2_5_MSPS) 1673 #define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC) 1674 #endif /* ADC_SUPPORT_2_5_MSPS */ 1675 #define __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1676 #define __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1677 #define __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1678 #define __HAL_RCC_C2TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1679 #define __HAL_RCC_C2TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1680 #if defined(SAI1) 1681 #define __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1682 #endif /* SAI1 */ 1683 1684 #if defined(ADC_SUPPORT_2_5_MSPS) 1685 #define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC)) 1686 #endif /* ADC_SUPPORT_2_5_MSPS */ 1687 #define __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)) 1688 #define __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)) 1689 #define __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)) 1690 #define __HAL_RCC_C2TIM16_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)) 1691 #define __HAL_RCC_C2TIM17_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)) 1692 #if defined(SAI1) 1693 #define __HAL_RCC_C2SAI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)) 1694 #endif /* SAI1 */ 1695 1696 /** 1697 * @} 1698 */ 1699 1700 1701 /** @defgroup RCC_APB3_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 1702 * @brief Check whether the APB3 peripheral clock is enabled or not. 1703 * @note After reset, the peripheral clock (used for registers read/write access) 1704 * is disabled and the application software has to enable this clock before 1705 * using it. 1706 * @{ 1707 */ 1708 1709 #define __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1710 #if defined(RCC_802_SUPPORT) 1711 #define __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802) 1712 #endif /* RCC_802_SUPPORT */ 1713 1714 #define __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)) 1715 #if defined(RCC_802_SUPPORT) 1716 #define __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)) 1717 #endif /* RCC_802_SUPPORT */ 1718 1719 /** 1720 * @} 1721 */ 1722 1723 1724 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1725 * @brief Force or release AHB1 peripheral reset. 1726 * @{ 1727 */ 1728 #define __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL) 1729 #define __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1) 1730 #if defined(DMA2) 1731 #define __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2) 1732 #endif /* DMA2 */ 1733 #define __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1734 #define __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC) 1735 #if defined(TSC) 1736 #define __HAL_RCC_TSC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC) 1737 #endif /* TSC */ 1738 1739 1740 #define __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL) 1741 #define __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1) 1742 #if defined(DMA2) 1743 #define __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2) 1744 #endif /* DMA2 */ 1745 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1746 #define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC) 1747 #if defined(TSC) 1748 #define __HAL_RCC_TSC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC) 1749 #endif /* TSC */ 1750 1751 1752 /** 1753 * @} 1754 */ 1755 1756 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1757 * @brief Force or release AHB2 peripheral reset. 1758 * @{ 1759 */ 1760 #define __HAL_RCC_AHB2_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) 1761 #define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1762 #define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1763 #define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1764 #if defined(GPIOD) 1765 #define __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD) 1766 #endif /* GPIOD */ 1767 #define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE) 1768 #define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1769 #if defined(ADC_SUPPORT_5_MSPS) 1770 #define __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC) 1771 #endif /* ADC_SUPPORT_5_MSPS */ 1772 #if defined(AES1) 1773 #define __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1) 1774 #endif /* AES1 */ 1775 1776 #define __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) 1777 #define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1778 #define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1779 #define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1780 #if defined(GPIOD) 1781 #define __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD) 1782 #endif /* GPIOD */ 1783 #define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE) 1784 #define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1785 #if defined(ADC_SUPPORT_5_MSPS) 1786 #define __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC) 1787 #endif /* ADC_SUPPORT_5_MSPS */ 1788 #if defined(AES1) 1789 #define __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1) 1790 #endif /* AES1 */ 1791 1792 /** 1793 * @} 1794 */ 1795 1796 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1797 * @brief Force or release AHB3 peripheral reset. 1798 * @{ 1799 */ 1800 #define __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) 1801 #if defined(QUADSPI) 1802 #define __HAL_RCC_QUADSPI_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI) 1803 #endif /* QUADSPI */ 1804 #define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) 1805 #define __HAL_RCC_AES2_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2) 1806 #define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) 1807 #define __HAL_RCC_HSEM_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM) 1808 #define __HAL_RCC_IPCC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC) 1809 #define __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH) 1810 1811 #define __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) 1812 #if defined(QUADSPI) 1813 #define __HAL_RCC_QUADSPI_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI) 1814 #endif /* QUADSPI */ 1815 #define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) 1816 #define __HAL_RCC_AES2_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2) 1817 #define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) 1818 #define __HAL_RCC_HSEM_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM) 1819 #define __HAL_RCC_IPCC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC) 1820 #define __HAL_RCC_FLASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH) 1821 /** 1822 * @} 1823 */ 1824 1825 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1826 * @brief Force or release APB1 peripheral reset. 1827 * @{ 1828 */ 1829 1830 #define __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL) 1831 #define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) 1832 #if defined(LCD) 1833 #define __HAL_RCC_LCD_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD) 1834 #endif /* LCD */ 1835 #if defined(SPI2) 1836 #define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) 1837 #endif /* SPI2 */ 1838 #define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) 1839 #if defined(I2C3) 1840 #define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) 1841 #endif /* I2C3 */ 1842 #if defined(CRS) 1843 #define __HAL_RCC_CRS_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS) 1844 #endif /* CRS */ 1845 #if defined(USB) 1846 #define __HAL_RCC_USB_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB) 1847 #endif /* USB */ 1848 #define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1849 1850 #define __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL) 1851 #if defined(LPUART1) 1852 #define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1) 1853 #endif /* LPUART1 */ 1854 #define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1855 1856 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 1857 __HAL_RCC_APB1L_FORCE_RESET();\ 1858 __HAL_RCC_APB1H_FORCE_RESET();\ 1859 } while(0U) 1860 1861 #define __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL) 1862 #define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) 1863 #if defined(LCD) 1864 #define __HAL_RCC_LCD_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD) 1865 #endif /* LCD */ 1866 #if defined(SPI2) 1867 #define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) 1868 #endif /* SPI2 */ 1869 #define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) 1870 #if defined(I2C3) 1871 #define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) 1872 #endif /* I2C3 */ 1873 #if defined(CRS) 1874 #define __HAL_RCC_CRS_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS) 1875 #endif /* CRS */ 1876 #if defined(USB) 1877 #define __HAL_RCC_USB_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB) 1878 #endif /* USB */ 1879 #define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1880 1881 #define __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL) 1882 #if defined(LPUART1) 1883 #define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1) 1884 #endif /* LPUART1 */ 1885 #define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1886 1887 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 1888 __HAL_RCC_APB1L_RELEASE_RESET();\ 1889 __HAL_RCC_APB1H_RELEASE_RESET();\ 1890 } while(0U) 1891 /** 1892 * @} 1893 */ 1894 1895 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1896 * @brief Force or release APB2 peripheral reset. 1897 * @{ 1898 */ 1899 #define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL) 1900 #if defined(ADC_SUPPORT_2_5_MSPS) 1901 #define __HAL_RCC_ADC_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC) 1902 #endif /* ADC_SUPPORT_2_5_MSPS */ 1903 #define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) 1904 #define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) 1905 #define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) 1906 #define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) 1907 #define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) 1908 #if defined(SAI1) 1909 #define __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1) 1910 #endif /* SAI1 */ 1911 1912 #define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) 1913 #if defined(ADC_SUPPORT_2_5_MSPS) 1914 #define __HAL_RCC_ADC_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC) 1915 #endif /* ADC_SUPPORT_2_5_MSPS */ 1916 #define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) 1917 #define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) 1918 #define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) 1919 #define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) 1920 #define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) 1921 #if defined(SAI1) 1922 #define __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1) 1923 #endif /* SAI1 */ 1924 /** 1925 * @} 1926 */ 1927 1928 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 1929 * @brief Force or release APB3 peripheral reset. 1930 * @{ 1931 */ 1932 #define __HAL_RCC_APB3_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL) 1933 #define __HAL_RCC_RF_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_RF) 1934 1935 #define __HAL_RCC_APB3_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL) 1936 #define __HAL_RCC_RF_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_RF) 1937 1938 /** 1939 * @} 1940 */ 1941 1942 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 1943 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1944 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1945 * power consumption. 1946 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1947 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1948 * @{ 1949 */ 1950 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1951 #if defined(DMA2) 1952 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1953 #endif /* DMA2 */ 1954 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1955 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) 1956 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1957 #if defined(TSC) 1958 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) 1959 #endif /* TSC */ 1960 1961 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1962 #if defined(DMA2) 1963 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1964 #endif /* DMA2 */ 1965 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1966 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) 1967 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1968 #if defined(TSC) 1969 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) 1970 #endif /* TSC */ 1971 1972 #define __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1973 #if defined(DMA2) 1974 #define __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1975 #endif /* DMA2 */ 1976 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1977 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1978 #define __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1979 #if defined(TSC) 1980 #define __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) 1981 #endif /* TSC */ 1982 1983 #define __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1984 #if defined(DMA2) 1985 #define __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1986 #endif /* DMA2 */ 1987 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1988 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1989 1990 #define __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1991 #if defined(TSC) 1992 #define __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) 1993 #endif /* TSC */ 1994 1995 /** 1996 * @} 1997 */ 1998 1999 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2000 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2001 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2002 * power consumption. 2003 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2004 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2005 * @{ 2006 */ 2007 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 2008 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 2009 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 2010 #if defined(GPIOD) 2011 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) 2012 #endif /* GPIOD */ 2013 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) 2014 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 2015 #if defined(ADC_SUPPORT_5_MSPS) 2016 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) 2017 #endif /* ADC_SUPPORT_5_MSPS */ 2018 #if defined(AES1) 2019 #define __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) 2020 #endif /* AES1 */ 2021 2022 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 2023 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 2024 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 2025 #if defined(GPIOD) 2026 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) 2027 #endif /* GPIOD */ 2028 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) 2029 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 2030 #if defined(ADC_SUPPORT_5_MSPS) 2031 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) 2032 #endif /* ADC_SUPPORT_5_MSPS */ 2033 #if defined(AES1) 2034 #define __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) 2035 #endif /* AES1 */ 2036 2037 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 2038 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 2039 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 2040 #if defined(GPIOD) 2041 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 2042 #endif /* GPIOD */ 2043 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 2044 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 2045 #if defined(ADC_SUPPORT_5_MSPS) 2046 #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) 2047 #endif /* ADC_SUPPORT_5_MSPS */ 2048 #if defined(AES1) 2049 #define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) 2050 #endif /* AES1 */ 2051 2052 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 2053 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 2054 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 2055 #if defined(GPIOD) 2056 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 2057 #endif /* GPIOD */ 2058 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 2059 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 2060 #if defined(ADC_SUPPORT_5_MSPS) 2061 #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) 2062 #endif /* ADC_SUPPORT_5_MSPS */ 2063 #if defined(AES1) 2064 #define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) 2065 #endif /* AES1 */ 2066 2067 /** 2068 * @} 2069 */ 2070 2071 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2072 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2073 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2074 * power consumption. 2075 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2076 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2077 * @{ 2078 */ 2079 #if defined(QUADSPI) 2080 #define __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) 2081 #endif /* QUADSPI */ 2082 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 2083 #define __HAL_RCC_AES2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) 2084 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 2085 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 2086 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 2087 2088 #if defined(QUADSPI) 2089 #define __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) 2090 #endif /* QUADSPI */ 2091 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 2092 #define __HAL_RCC_AES2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) 2093 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 2094 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 2095 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 2096 2097 #define __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 2098 #define __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2) 2099 #define __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 2100 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 2101 #define __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 2102 2103 #define __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 2104 #define __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2) 2105 #define __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 2106 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 2107 #define __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 2108 2109 /** 2110 * @} 2111 */ 2112 2113 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2114 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2115 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2116 * power consumption. 2117 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2118 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2119 * @{ 2120 */ 2121 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 2122 #if defined(LCD) 2123 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD) 2124 #endif /* LCD */ 2125 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 2126 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 2127 #if defined(SPI2) 2128 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 2129 #endif /* SPI2 */ 2130 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 2131 #if defined(I2C3) 2132 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 2133 #endif /* I2C3 */ 2134 #if defined(CRS) 2135 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS) 2136 #endif /* CRS */ 2137 #if defined(USB) 2138 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB) 2139 #endif /* USB */ 2140 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 2141 #if defined(LPUART1) 2142 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 2143 #endif /* LPUART1 */ 2144 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 2145 2146 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 2147 #if defined(LCD) 2148 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD) 2149 #endif /* LCD */ 2150 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 2151 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 2152 #if defined(SPI2) 2153 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 2154 #endif /* SPI2 */ 2155 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 2156 #if defined(I2C3) 2157 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 2158 #endif /* I2C3 */ 2159 #if defined(CRS) 2160 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS) 2161 #endif /* CRS */ 2162 #if defined(USB) 2163 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB) 2164 #endif /* USB */ 2165 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 2166 #if defined(LPUART1) 2167 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 2168 #endif /* LPUART1 */ 2169 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 2170 2171 #define __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 2172 #if defined(LCD) 2173 #define __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) 2174 #endif /* LCD */ 2175 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 2176 #if defined(SPI2) 2177 #define __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 2178 #endif /* SPI2 */ 2179 #define __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 2180 #if defined(I2C3) 2181 #define __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 2182 #endif /* I2C3 */ 2183 #if defined(CRS) 2184 #define __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) 2185 #endif /* CRS */ 2186 #if defined(USB) 2187 #define __HAL_RCC_C2USB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) 2188 #endif /* USB */ 2189 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 2190 #if defined(LPUART1) 2191 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 2192 #endif /* LPUART1 */ 2193 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 2194 2195 #define __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 2196 #if defined(LCD) 2197 #define __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) 2198 #endif /* LCD */ 2199 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 2200 #if defined(SPI2) 2201 #define __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 2202 #endif /* SPI2 */ 2203 #define __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 2204 #if defined(I2C3) 2205 #define __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 2206 #endif /* I2C3 */ 2207 #if defined(CRS) 2208 #define __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) 2209 #endif /* CRS */ 2210 #if defined(USB) 2211 #define __HAL_RCC_C2USB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) 2212 #endif /* USB */ 2213 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 2214 #if defined(LPUART1) 2215 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 2216 #endif /* LPUART1 */ 2217 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 2218 2219 /** 2220 * @} 2221 */ 2222 2223 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2224 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2225 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2226 * power consumption. 2227 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2228 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2229 * @{ 2230 */ 2231 #if defined(ADC_SUPPORT_2_5_MSPS) 2232 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC) 2233 #endif /* ADC_SUPPORT_2_5_MSPS */ 2234 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 2235 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 2236 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 2237 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 2238 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 2239 #if defined(SAI1) 2240 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) 2241 #endif /* SAI1 */ 2242 2243 #if defined(ADC_SUPPORT_2_5_MSPS) 2244 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC) 2245 #endif /* ADC_SUPPORT_2_5_MSPS */ 2246 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 2247 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 2248 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 2249 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 2250 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 2251 #if defined(SAI1) 2252 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) 2253 #endif /* SAI1 */ 2254 2255 #if defined(ADC_SUPPORT_2_5_MSPS) 2256 #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) 2257 #endif /* ADC_SUPPORT_2_5_MSPS */ 2258 #define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 2259 #define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 2260 #define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 2261 #define __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 2262 #define __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 2263 #if defined(SAI1) 2264 #define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) 2265 #endif /* SAI1 */ 2266 2267 #if defined(ADC_SUPPORT_2_5_MSPS) 2268 #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) 2269 #endif /* ADC_SUPPORT_2_5_MSPS */ 2270 #define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 2271 #define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 2272 #define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 2273 #define __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 2274 #define __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 2275 #if defined(SAI1) 2276 #define __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) 2277 #endif /* SAI1 */ 2278 /** 2279 * @} 2280 */ 2281 2282 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 2283 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2284 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2285 * power consumption. 2286 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2287 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2288 * @{ 2289 */ 2290 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) 2291 #if defined(DMA2) 2292 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) 2293 #endif /* DMA2 */ 2294 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) 2295 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) 2296 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) 2297 #if defined(TSC) 2298 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) 2299 #endif /* TSC */ 2300 2301 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) 2302 #if defined(DMA2) 2303 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) 2304 #endif /* DMA2 */ 2305 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) 2306 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) 2307 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) 2308 #if defined(TSC) 2309 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) 2310 #endif /* TSC */ 2311 2312 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET) 2313 #if defined(DMA2) 2314 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET) 2315 #endif /* DMA2 */ 2316 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET) 2317 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET) 2318 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET) 2319 #if defined(TSC) 2320 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET) 2321 #endif /* TSC */ 2322 2323 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET) 2324 #if defined(DMA2) 2325 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET) 2326 #endif /* DMA2 */ 2327 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET) 2328 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET) 2329 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET) 2330 #if defined(TSC) 2331 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET) 2332 #endif /* TSC */ 2333 /** 2334 * @} 2335 */ 2336 2337 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 2338 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2339 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2340 * power consumption. 2341 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2342 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2343 * @{ 2344 */ 2345 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) 2346 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) 2347 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) 2348 #if defined(GPIOD) 2349 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) 2350 #endif /* GPIOD */ 2351 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) 2352 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) 2353 #if defined(ADC_SUPPORT_5_MSPS) 2354 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) 2355 #endif /* ADC_SUPPORT_5_MSPS */ 2356 #if defined(AES1) 2357 #define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET) 2358 #endif /* AES1 */ 2359 2360 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) 2361 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) 2362 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) 2363 #if defined(GPIOD) 2364 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) 2365 #endif /* GPIOD */ 2366 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) 2367 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) 2368 #if defined(ADC_SUPPORT_5_MSPS) 2369 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) 2370 #endif /* ADC_SUPPORT_5_MSPS */ 2371 #if defined(AES1) 2372 #define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET) 2373 #endif /* AES1 */ 2374 2375 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET) 2376 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET) 2377 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET) 2378 #if defined(GPIOD) 2379 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET) 2380 #endif /* GPIOD */ 2381 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET) 2382 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET) 2383 #if defined(ADC_SUPPORT_5_MSPS) 2384 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET) 2385 #endif /* ADC_SUPPORT_5_MSPS */ 2386 #if defined(AES1) 2387 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET) 2388 #endif /* AES1 */ 2389 2390 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET) 2391 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET) 2392 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET) 2393 #if defined(GPIOD) 2394 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET) 2395 #endif /* GPIOD */ 2396 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET) 2397 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET) 2398 #if defined(ADC_SUPPORT_5_MSPS) 2399 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET) 2400 #endif /* ADC_SUPPORT_5_MSPS */ 2401 #if defined(AES1) 2402 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET) 2403 #endif /* AES1 */ 2404 2405 /** 2406 * @} 2407 */ 2408 2409 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 2410 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2411 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2412 * power consumption. 2413 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2414 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2415 * @{ 2416 */ 2417 #if defined(QUADSPI) 2418 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET) 2419 #endif /* QUADSPI */ 2420 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET) 2421 #define __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET) 2422 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET) 2423 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET) 2424 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET) 2425 2426 #if defined(QUADSPI) 2427 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET) 2428 #endif /* QUADSPI */ 2429 #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET) 2430 #define __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET) 2431 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET) 2432 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) == RESET) 2433 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) == RESET) 2434 2435 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) != RESET) 2436 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) != RESET) 2437 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) != RESET) 2438 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) != RESET) 2439 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) != RESET) 2440 2441 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) == RESET) 2442 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) == RESET) 2443 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) == RESET) 2444 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) == RESET) 2445 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) == RESET) 2446 2447 /** 2448 * @} 2449 */ 2450 2451 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 2452 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2453 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2454 * power consumption. 2455 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2456 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2457 * @{ 2458 */ 2459 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) 2460 #if defined(LCD) 2461 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) 2462 #endif /* LCD */ 2463 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) 2464 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) 2465 #if defined(SPI2) 2466 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) 2467 #endif /* SPI2 */ 2468 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) 2469 #if defined(I2C3) 2470 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) 2471 #endif /* I2C3 */ 2472 #if defined(CRS) 2473 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) 2474 #endif /* CRS */ 2475 #if defined(USB) 2476 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != RESET) 2477 #endif /* USB */ 2478 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) 2479 #if defined(LPUART1) 2480 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) 2481 #endif /* LPUART1 */ 2482 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) 2483 2484 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) 2485 #if defined(LCD) 2486 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) 2487 #endif /* LCD */ 2488 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) 2489 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) 2490 #if defined(SPI2) 2491 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) 2492 #endif /* SPI2 */ 2493 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) 2494 #if defined(I2C3) 2495 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) 2496 #endif /* I2C3 */ 2497 #if defined(CRS) 2498 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) 2499 #endif /* CRS */ 2500 #if defined(USB) 2501 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == RESET) 2502 #endif /* USB */ 2503 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) 2504 #if defined(LPUART1) 2505 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) 2506 #endif /* LPUART1 */ 2507 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) 2508 2509 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET) 2510 #if defined(LCD) 2511 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) != RESET) 2512 #endif /* LCD */ 2513 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) \ 2514 != RESET) 2515 #if defined(SPI2) 2516 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET) 2517 #endif /* SPI2 */ 2518 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET) 2519 #if defined(I2C3) 2520 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET) 2521 #endif /* I2C3 */ 2522 #if defined(CRS) 2523 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) != RESET) 2524 #endif /* CRS */ 2525 #if defined(USB) 2526 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) != RESET) 2527 #endif /* USB */ 2528 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) \ 2529 != RESET) 2530 #if defined(LPUART1) 2531 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) \ 2532 != RESET) 2533 #endif /* LPUART1 */ 2534 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) \ 2535 != RESET) 2536 2537 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET) 2538 #if defined(LCD) 2539 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) == RESET) 2540 #endif /* LCD */ 2541 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) \ 2542 == RESET) 2543 #if defined(SPI2) 2544 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET) 2545 #endif /* SPI2 */ 2546 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET) 2547 #if defined(I2C3) 2548 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET) 2549 #endif /* I2C3 */ 2550 #if defined(CRS) 2551 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) == RESET) 2552 #endif /* CRS */ 2553 #if defined(USB) 2554 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) == RESET) 2555 #endif /* USB */ 2556 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) \ 2557 == RESET) 2558 #if defined(LPUART1) 2559 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) \ 2560 == RESET) 2561 #endif /* LPUART1 */ 2562 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) \ 2563 == RESET) 2564 2565 /** 2566 * @} 2567 */ 2568 2569 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 2570 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2571 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2572 * power consumption. 2573 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2574 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2575 * @{ 2576 */ 2577 #if defined(ADC_SUPPORT_2_5_MSPS) 2578 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) != RESET) 2579 #endif /* ADC_SUPPORT_2_5_MSPS */ 2580 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) 2581 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) 2582 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) 2583 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) 2584 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) 2585 #if defined(SAI1) 2586 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) 2587 #endif /* SAI1 */ 2588 2589 #if defined(ADC_SUPPORT_2_5_MSPS) 2590 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) == RESET) 2591 #endif /* ADC_SUPPORT_2_5_MSPS */ 2592 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) 2593 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) 2594 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) 2595 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) 2596 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) 2597 #if defined(SAI1) 2598 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) 2599 #endif /* SAI1 */ 2600 2601 #if defined(ADC_SUPPORT_2_5_MSPS) 2602 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) != RESET) 2603 #endif /* ADC_SUPPORT_2_5_MSPS */ 2604 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET) 2605 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET) 2606 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) \ 2607 != RESET) 2608 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET) 2609 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET) 2610 #if defined(SAI1) 2611 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET) 2612 #endif /* SAI1 */ 2613 2614 #if defined(ADC_SUPPORT_2_5_MSPS) 2615 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) == RESET) 2616 #endif /* ADC_SUPPORT_2_5_MSPS */ 2617 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET) 2618 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET) 2619 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) \ 2620 == RESET) 2621 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET) 2622 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET) 2623 #if defined(SAI1) 2624 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET) 2625 #endif /* SAI1 */ 2626 2627 /** 2628 * @} 2629 */ 2630 2631 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 2632 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. 2633 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2634 * power consumption. 2635 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2636 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2637 * @{ 2638 */ 2639 #define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) 2640 #if defined(RCC_802_SUPPORT) 2641 #define __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) 2642 #endif /* RCC_802_SUPPORT */ 2643 2644 #define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) 2645 #if defined(RCC_802_SUPPORT) 2646 #define __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) 2647 #endif /* RCC_802_SUPPORT */ 2648 /** 2649 * @} 2650 */ 2651 2652 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable_Status APB3 Peripheral Clock Sleep Enabled or Disabled Status 2653 * @brief Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2654 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2655 * power consumption. 2656 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2657 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2658 * @{ 2659 */ 2660 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET) 2661 #if defined(RCC_802_SUPPORT) 2662 #define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET) 2663 #endif /* RCC_802_SUPPORT */ 2664 2665 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET) 2666 #if defined(RCC_802_SUPPORT) 2667 #define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET) 2668 #endif /* RCC_802_SUPPORT */ 2669 /** 2670 * @} 2671 */ 2672 2673 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2674 * @{ 2675 */ 2676 2677 /** @brief Macros to force or release the Backup domain reset. 2678 * @note This function resets the RTC peripheral (including the backup registers) 2679 * and the RTC clock source selection in RCC_CSR register. 2680 * @note The BKPSRAM is not affected by this reset. 2681 * @retval None 2682 */ 2683 #define __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset() 2684 #define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset() 2685 2686 /** 2687 * @} 2688 */ 2689 2690 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2691 * @{ 2692 */ 2693 2694 /** @brief Macros to enable or disable the RTC clock. 2695 * @note As the RTC is in the Backup domain and write access is denied to 2696 * this domain after reset, you have to enable write access using 2697 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2698 * (to be done once after reset). 2699 * @note These macros must be used after the RTC clock source was selected. 2700 * @retval None 2701 */ 2702 #define __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC() 2703 #define __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC() 2704 2705 /** 2706 * @} 2707 */ 2708 2709 /** @brief Macros to enable the Internal High Speed oscillator (HSI). 2710 * @note The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes. 2711 * It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1 2712 * or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE 2713 * crystal oscillator and Security System CSS is enabled. 2714 * @note After enabling the HSI, the application software should wait on HSIRDY 2715 * flag to be set indicating that HSI clock is stable and can be used as 2716 * system clock source. 2717 * @retval None 2718 */ 2719 #define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() 2720 2721 /** @brief Macro to disable the Internal High Speed oscillator (HSI). 2722 * @note HSI can not be stopped if it is used as system clock source. In this case, 2723 * you have to select another source of the system clock then stop the HSI. 2724 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2725 * clock cycles. 2726 * @retval None 2727 */ 2728 #define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable() 2729 2730 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 2731 * @note The calibration is used to compensate for the variations in voltage 2732 * and temperature that influence the frequency of the internal HSI RC. 2733 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2734 * (default is RCC_HSICALIBRATION_DEFAULT). 2735 * This parameter must be a number between Min_data=0 and Max_Data=127. 2736 * @retval None 2737 */ 2738 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 2739 LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__) 2740 2741 /** 2742 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 2743 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 2744 * @note The enable of this function has not effect on the HSION bit. 2745 * This parameter can be: ENABLE or DISABLE. 2746 * @retval None 2747 */ 2748 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() LL_RCC_HSI_EnableAutoFromStop() 2749 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() LL_RCC_HSI_DisableAutoFromStop() 2750 2751 /** 2752 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2753 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2754 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2755 * speed because of the HSI startup time. 2756 * @note The enable of this function has not effect on the HSION bit. 2757 * @retval None 2758 */ 2759 #define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() 2760 #define __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode() 2761 2762 /** 2763 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 2764 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 2765 * It is used (enabled by hardware) as system clock source after 2766 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2767 * of failure of the HSE used directly or indirectly as system clock 2768 * (if the Clock Security System CSS is enabled). 2769 * @note MSI can not be stopped if it is used as system clock source. 2770 * In this case, you have to select another source of the system 2771 * clock then stop the MSI. 2772 * @note After enabling the MSI, the application software should wait on 2773 * MSIRDY flag to be set indicating that MSI clock is stable and can 2774 * be used as system clock source. 2775 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 2776 * clock cycles. 2777 * @retval None 2778 */ 2779 #define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() 2780 #define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() 2781 2782 /** @brief Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. 2783 * @note The calibration is used to compensate for the variations in voltage 2784 * and temperature that influence the frequency of the internal MSI RC. 2785 * Refer to the Application Note AN3300 for more details on how to 2786 * calibrate the MSI. 2787 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 2788 * (default is @ref RCC_MSICALIBRATION_DEFAULT). 2789 * This parameter must be a number between 0 and 255. 2790 * @retval None 2791 */ 2792 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 2793 LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__) 2794 2795 /** 2796 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 2797 * @note After restart from Reset , the MSI clock is around 4 MHz. 2798 * After stop the startup clock can be MSI (at any of its possible 2799 * frequencies, the one that was used before entering stop mode) or HSI. 2800 * After Standby its frequency can be selected between 4 possible values 2801 * (1, 2, 4 or 8 MHz). 2802 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 2803 * (MSIRDY=1). 2804 * @note The MSI clock range after reset can be modified on the fly. 2805 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 2806 * This parameter must be one of the following values: 2807 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 2808 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 2809 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 2810 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 2811 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2812 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz 2813 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset) 2814 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2815 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2816 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2817 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2818 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2819 * @retval None 2820 */ 2821 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) LL_RCC_MSI_SetRange(__MSIRANGEVALUE__) 2822 2823 2824 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 2825 * @retval MSI clock range. 2826 * This parameter must be one of the following values: 2827 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 2828 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 2829 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 2830 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 2831 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2832 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2833 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2834 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2835 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2836 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2837 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2838 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2839 */ 2840 #define __HAL_RCC_GET_MSI_RANGE() LL_RCC_MSI_GetRange() 2841 2842 2843 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI1). 2844 * @note After enabling the LSI1, the application software should wait on 2845 * LSI1RDY flag to be set indicating that LSI1 clock is stable and can 2846 * be used to clock the IWDG and/or the RTC. 2847 * @retval None 2848 */ 2849 #define __HAL_RCC_LSI1_ENABLE() LL_RCC_LSI1_Enable() 2850 #define __HAL_RCC_LSI1_DISABLE() LL_RCC_LSI1_Disable() 2851 2852 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI2). 2853 * @note After enabling the LSI2, the application software should wait on 2854 * LSI2RDY flag to be set indicating that LSI2 clock is stable and can 2855 * be used to clock the IWDG and/or the RTC. 2856 * @retval None 2857 */ 2858 #define __HAL_RCC_LSI2_ENABLE() LL_RCC_LSI2_Enable() 2859 #define __HAL_RCC_LSI2_DISABLE() LL_RCC_LSI2_Disable() 2860 2861 /** @brief Macro to adjust the Internal Low Speed oscillator (LSI2) calibration value. 2862 * @note The calibration is used to compensate for the variations in voltage 2863 * and temperature that influence the frequency of the internal HSI RC. 2864 * @param __LSI2TRIMMINGVALUE__ specifies the calibration trimming value 2865 * This parameter must be a number between Min_data=0 and Max_Data=15. 2866 * @retval None 2867 */ 2868 #define __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(__LSI2TRIMMINGVALUE__) LL_RCC_LSI2_SetTrimming(__LSI2TRIMMINGVALUE__) 2869 2870 /** 2871 * @brief Macro to configure the External High Speed oscillator (HSE). 2872 * @note After enabling the HSE (RCC_HSE_ON), the application 2873 * software should wait on HSERDY flag to be set indicating that HSE clock 2874 * is stable and can be used to clock the PLL and/or system clock. 2875 * @note HSE state can not be changed if it is used directly or through the 2876 * PLL as system clock. In this case, you have to select another source 2877 * of the system clock then change the HSE state (ex. disable it). 2878 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2879 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2880 * was previously enabled you have to enable it again after calling this 2881 * function. 2882 * @param __STATE__ specifies the new state of the HSE. 2883 * This parameter can be one of the following values: 2884 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2885 * 6 HSE oscillator clock cycles. 2886 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2887 * @note (*) Value not defined for all devices 2888 * @retval None 2889 */ 2890 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 2891 do { \ 2892 if((__STATE__) == RCC_HSE_ON) \ 2893 { \ 2894 LL_RCC_HSE_Enable(); \ 2895 } \ 2896 else \ 2897 { \ 2898 LL_RCC_HSE_Disable(); \ 2899 } \ 2900 } while(0U) 2901 2902 /** @brief Macros to enable or disable the HSE Prescaler 2903 * @note HSE div2 could be used as Sysclk or PLL entry in Range2 2904 * @retval None 2905 */ 2906 #define __HAL_RCC_HSE_DIV2_ENABLE() LL_RCC_HSE_EnableDiv2() 2907 #define __HAL_RCC_HSE_DIV2_DISABLE() LL_RCC_HSE_DisableDiv2() 2908 2909 /** 2910 * @brief Macro to configure the External Low Speed oscillator (LSE). 2911 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2912 * supported by this macro. User should request a transition to LSE Off 2913 * first and then LSE On or LSE Bypass. 2914 * @note As the LSE is in the Backup domain and write access is denied to 2915 * this domain after reset, you have to enable write access using 2916 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2917 * (to be done once after reset). 2918 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2919 * software should wait on LSERDY flag to be set indicating that LSE clock 2920 * is stable and can be used to clock the RTC. 2921 * @param __STATE__ specifies the new state of the LSE. 2922 * This parameter can be one of the following values: 2923 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2924 * 6 LSE oscillator clock cycles. 2925 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2926 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2927 * @retval None 2928 */ 2929 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 2930 do { \ 2931 if((__STATE__) == RCC_LSE_ON) \ 2932 { \ 2933 LL_RCC_LSE_Enable(); \ 2934 } \ 2935 else if((__STATE__) == RCC_LSE_BYPASS) \ 2936 { \ 2937 LL_RCC_LSE_EnableBypass(); \ 2938 LL_RCC_LSE_Enable(); \ 2939 } \ 2940 else \ 2941 { \ 2942 LL_RCC_LSE_Disable(); \ 2943 LL_RCC_LSE_DisableBypass(); \ 2944 } \ 2945 } while(0U) 2946 2947 2948 #if defined(RCC_HSI48_SUPPORT) 2949 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 2950 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 2951 * @note After enabling the HSI48, the application software should wait on HSI48RDY 2952 * flag to be set indicating that HSI48 clock is stable. 2953 * This parameter can be: ENABLE or DISABLE. 2954 * @retval None 2955 */ 2956 #define __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable() 2957 #define __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable() 2958 #endif 2959 2960 /** @brief Macros to configure HSE sense amplifier threshold. 2961 * @note to configure HSE sense amplifier, first disable HSE 2962 * using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2963 * 2964 * @param __HSE_AMPTHRES__ specifies the HSE sense amplifier threshold. 2965 * This parameter can be one of the following values: 2966 * @arg @ref RCC_HSEAMPTHRESHOLD_1_2 HSE bias current factor 1/2. 2967 * @arg @ref RCC_HSEAMPTHRESHOLD_3_4 HSE bias current factor 3/4. 2968 * @retval None 2969 */ 2970 #define __HAL_RCC_HSE_AMPCONFIG(__HSE_AMPTHRES__) LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__) 2971 2972 /** @brief Macros to configure HSE current control. 2973 * @note to configure HSE current control, first disable HSE 2974 * using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2975 * 2976 * @param __HSE_CURRENTMAX__ specifies the HSE current max limit. 2977 * This parameter can be one of the following values: 2978 * @arg @ref RCC_HSE_CURRENTMAX_0 HSE current max limit 0.18 mA/V. 2979 * @arg @ref RCC_HSE_CURRENTMAX_1 HSE current max limit 0.57 mA/V. 2980 * @arg @ref RCC_HSE_CURRENTMAX_2 HSE current max limit 0.78 mA/V. 2981 * @arg @ref RCC_HSE_CURRENTMAX_3 HSE current max limit 1.13 mA/V. 2982 * @arg @ref RCC_HSE_CURRENTMAX_4 HSE current max limit 0.61 mA/V. 2983 * @arg @ref RCC_HSE_CURRENTMAX_5 HSE current max limit 1.65 mA/V. 2984 * @arg @ref RCC_HSE_CURRENTMAX_6 HSE current max limit 2.12 mA/V. 2985 * @arg @ref RCC_HSE_CURRENTMAX_7 HSE current max limit 2.84 mA/V. 2986 * @retval None 2987 */ 2988 #define __HAL_RCC_HSE_CURRENTCONFIG(__HSE_CURRENTMAX__) LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__) 2989 2990 /** @brief Macros to configure HSE capacitor tuning. 2991 * @note to configure HSE current control, first disable HSE 2992 * using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2993 * 2994 * @param __HSE_LOAD_CAPACITANCE__ specifies the HSE capacitor value. 2995 * This Value Between Min_Data = 0 and Max_Data = 63 2996 * @retval None 2997 */ 2998 #define __HAL_RCC_HSE_CAPACITORTUNING(__HSE_LOAD_CAPACITANCE__) LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__) 2999 3000 3001 /** @brief Macros to configure the RTC clock (RTCCLK). 3002 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 3003 * This parameter can be one of the following values: 3004 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 3005 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3006 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3007 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3008 * @note As the RTC clock configuration bits are in the Backup domain and write 3009 * access is denied to this domain after reset, you have to enable write 3010 * access using the Power Backup Access macro before to configure 3011 * the RTC clock source (to be done once after reset). 3012 * @note Once the RTC clock is configured it cannot be changed unless the 3013 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 3014 * a Power On Reset (POR). 3015 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 3016 * work in STOP and STANDBY modes, and can be used as wakeup source. 3017 * However, when the HSE clock is used as RTC clock source, the RTC 3018 * cannot be used in STOP and STANDBY modes. 3019 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 3020 * RTC clock source). 3021 * @retval None 3022 */ 3023 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__) 3024 3025 /** @brief Macro to get the RTC clock source. 3026 * @retval The returned value can be one of the following: 3027 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 3028 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3029 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3030 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3031 */ 3032 #define __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource() 3033 3034 /** @brief Macros to enable or disable the main PLL. 3035 * @note After enabling the main PLL, the application software should wait on 3036 * PLLRDY flag to be set indicating that PLL clock is stable and can 3037 * be used as system clock source. 3038 * @note The main PLL can not be disabled if it is used as system clock source 3039 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 3040 * @retval None 3041 */ 3042 #define __HAL_RCC_PLL_ENABLE() LL_RCC_PLL_Enable() 3043 #define __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable() 3044 3045 /** @brief Macro to configure the PLL clock source. 3046 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3047 * This parameter can be one of the following values: 3048 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3049 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3050 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3051 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3052 * @note This function must be used only when the main PLL is disabled. 3053 * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). 3054 * @retval None 3055 * 3056 */ 3057 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 3058 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 3059 3060 /** @brief Macro to configure the PLL multiplication factor. 3061 * @note This function must be used only when the main PLL is disabled. 3062 * @param __PLLM__ specifies the division factor for PLL VCO input clock 3063 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 3064 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3065 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 3066 * of 16 MHz to limit PLL jitter. 3067 * @retval None 3068 * 3069 */ 3070 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 3071 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 3072 3073 /** 3074 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 3075 * @note This function must be used only when the main PLL is disabled. 3076 * 3077 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3078 * This parameter can be one of the following values: 3079 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3080 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3081 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3082 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3083 * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). 3084 * 3085 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 3086 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 3087 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3088 * frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency 3089 * of 16 MHz to limit PLL jitter. 3090 * 3091 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 3092 * This parameter must be a number between 6 and 127. 3093 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3094 * output frequency is between 96 and 344 MHz. 3095 * 3096 * @param __PLLP__ specifies the division factor for ADC and SAI1 clock. 3097 * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. 3098 * 3099 * @param __PLLQ__ specifies the division factor for USB and RNG clocks. 3100 * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider 3101 * @note If the USB FS is used in your application, you have to set the 3102 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 3103 * the RNG need a frequency lower than or equal to 48 MHz to work 3104 * correctly. 3105 * 3106 * @param __PLLR__ specifies the division factor for the main system clock. 3107 * This parameter must be a value of @ref RCC_PLLR_Clock_Divider 3108 * @note You have to set the PLLR parameter correctly to not exceed 48 MHZ. 3109 * @retval None 3110 */ 3111 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 3112 MODIFY_REG( RCC->PLLCFGR, \ 3113 (RCC_PLLCFGR_PLLSRC | \ 3114 RCC_PLLCFGR_PLLM | \ 3115 RCC_PLLCFGR_PLLN | \ 3116 RCC_PLLCFGR_PLLP | \ 3117 RCC_PLLCFGR_PLLQ | \ 3118 RCC_PLLCFGR_PLLR), \ 3119 ((uint32_t) (__PLLSOURCE__) | \ 3120 (uint32_t) (__PLLM__) | \ 3121 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 3122 (uint32_t) (__PLLP__) | \ 3123 (uint32_t) (__PLLQ__) | \ 3124 (uint32_t) (__PLLR__))) 3125 3126 /** @brief Macro to get the oscillator used as PLL clock source. 3127 * @retval The oscillator used as PLL clock source. The returned value can be one 3128 * of the following: 3129 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 3130 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3131 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3132 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3133 */ 3134 #define __HAL_RCC_GET_PLL_OSCSOURCE() LL_RCC_PLL_GetMainSource() 3135 3136 /** 3137 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK) 3138 * @note Enabling/disabling clock outputs RCC_PLL_SAI1CLK and RCC_PLL_USBCLK can be done at anytime 3139 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 3140 * be stopped if used as System Clock. 3141 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 3142 * This parameter can be one or a combination of the following values: 3143 * @arg @ref RCC_PLL_SAI1CLK This clock is used to generate the clock for SAI 3144 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate the clock for ADC 3145 * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) 3146 * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG 3147 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) 3148 * @retval None 3149 */ 3150 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3151 3152 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3153 3154 /** 3155 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK) 3156 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 3157 * This parameter can be one of the following values: 3158 * @arg @ref RCC_PLL_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality 3159 * audio performance on SAI interface 3160 * @arg @ref RCC_PLL_ADCCLK same 3161 * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) 3162 * @arg @ref RCC_PLL_RNGCLK same 3163 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) 3164 * @retval SET / RESET 3165 */ 3166 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3167 3168 /** 3169 * @brief Macro to configure the system clock source. 3170 * @param __SYSCLKSOURCE__ specifies the system clock source. 3171 * This parameter can be one of the following values: 3172 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 3173 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 3174 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 3175 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 3176 * @retval None 3177 */ 3178 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__) 3179 3180 /** @brief Macro to get the clock source used as system clock. 3181 * @retval The clock source used as system clock. The returned value can be one 3182 * of the following: 3183 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock. 3184 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 3185 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 3186 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. 3187 */ 3188 #define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource() 3189 3190 /** 3191 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3192 * @note As the LSE is in the Backup domain and write access is denied to 3193 * this domain after reset, you have to enable write access using 3194 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3195 * (to be done once after reset). 3196 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 3197 * This parameter can be one of the following values: 3198 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3199 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3200 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3201 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3202 * @retval None 3203 */ 3204 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__) 3205 3206 /** 3207 * @brief Macro to configure the wake up from stop clock. 3208 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 3209 * This parameter can be one of the following values: 3210 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 3211 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 3212 * @retval None 3213 */ 3214 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__) 3215 3216 3217 /** @brief Macro to configure the MCO clock. 3218 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 3219 * This parameter can be one of the following values: 3220 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 3221 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 3222 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 3223 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 3224 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 3225 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 3226 * @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source 3227 * @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source 3228 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3229 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source (*) 3230 * 3231 * @param __MCODIV__ specifies the MCO clock prescaler. 3232 * This parameter can be one of the following values: 3233 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3234 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3235 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3236 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3237 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3238 * 3239 * @note (*) Value not defined for all devices 3240 */ 3241 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__)) 3242 3243 3244 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3245 * @brief macros to manage the specified RCC Flags and interrupts. 3246 * @{ 3247 */ 3248 3249 /** @brief Enable RCC interrupt. 3250 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 3251 * This parameter can be any combination of the following values: 3252 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt enable 3253 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 3254 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 3255 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 3256 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 3257 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 3258 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable 3259 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 3260 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*) 3261 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable 3262 * 3263 * @note (*) Value not defined for all devices 3264 * 3265 * @retval None 3266 */ 3267 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3268 3269 /** @brief Disable RCC interrupt. 3270 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 3271 * This parameter can be any combination of the following values: 3272 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt enable 3273 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 3274 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 3275 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 3276 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 3277 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 3278 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable 3279 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 3280 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*) 3281 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable 3282 * 3283 * @note (*) Value not defined for all devices 3284 * 3285 * @retval None 3286 */ 3287 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3288 3289 /** @brief Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] 3290 * bits to clear the selected interrupt pending bits. 3291 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3292 * This parameter can be any combination of the following values: 3293 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt clear 3294 * @arg @ref RCC_IT_LSERDY LSE ready interrupt clear 3295 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt clear 3296 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt clear 3297 * @arg @ref RCC_IT_HSERDY HSE ready interrupt clear 3298 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt clear 3299 * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt clear 3300 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear 3301 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear 3302 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt clear (*) 3303 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt clear 3304 * 3305 * @note (*) Value not defined for all devices 3306 */ 3307 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 3308 3309 /** @brief Check whether the RCC interrupt has occurred or not. 3310 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 3311 * This parameter can be one of the following values: 3312 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt flag 3313 * @arg @ref RCC_IT_LSERDY LSE ready interrupt flag 3314 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt flag 3315 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt flag 3316 * @arg @ref RCC_IT_HSERDY HSE ready interrupt flag 3317 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt flag 3318 * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt flag 3319 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag 3320 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag 3321 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt flag (*) 3322 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt flag 3323 * 3324 * @note (*) Value not defined for all devices 3325 * 3326 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 3327 */ 3328 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 3329 3330 /** @brief Set RMVF bit to clear the reset flags. 3331 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3332 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3333 * @retval None 3334 */ 3335 #define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags() 3336 3337 /** @brief Check whether the selected RCC flag is set or not. 3338 * @param __FLAG__ specifies the flag to check. 3339 * This parameter can be one of the following values: 3340 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 3341 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3342 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3343 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 3344 * @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready 3345 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 (*) 3346 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3347 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3348 * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready 3349 * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready 3350 * @arg @ref RCC_FLAG_BORRST BOR reset 3351 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3352 * @arg @ref RCC_FLAG_PINRST Pin reset 3353 * @arg @ref RCC_FLAG_SFTRST Software reset 3354 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3355 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3356 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3357 * 3358 * @note (*) Value not defined for all devices 3359 * 3360 * @retval The new state of __FLAG__ (TRUE or FALSE). 3361 */ 3362 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 3363 ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ 3364 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 3365 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ 3366 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ 3367 ? 1U : 0U) 3368 3369 /** 3370 * @} 3371 */ 3372 3373 /** 3374 * @} 3375 */ 3376 3377 /* Include RCC HAL Extended module */ 3378 #include "stm32wbxx_hal_rcc_ex.h" 3379 3380 /* Exported functions --------------------------------------------------------*/ 3381 /** @addtogroup RCC_Exported_Functions 3382 * @{ 3383 */ 3384 3385 3386 /** @addtogroup RCC_Exported_Functions_Group1 3387 * @{ 3388 */ 3389 3390 /* Initialization and de-initialization functions ******************************/ 3391 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3392 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3393 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 3394 3395 /** 3396 * @} 3397 */ 3398 3399 /** @addtogroup RCC_Exported_Functions_Group2 3400 * @{ 3401 */ 3402 3403 /* Peripheral Control functions ************************************************/ 3404 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3405 void HAL_RCC_EnableCSS(void); 3406 uint32_t HAL_RCC_GetSysClockFreq(void); 3407 3408 uint32_t HAL_RCC_GetHCLKFreq(void); 3409 uint32_t HAL_RCC_GetHCLK2Freq(void); 3410 uint32_t HAL_RCC_GetHCLK4Freq(void); 3411 3412 uint32_t HAL_RCC_GetPCLK1Freq(void); 3413 uint32_t HAL_RCC_GetPCLK2Freq(void); 3414 3415 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3416 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3417 /* LSE & HSE CSS NMI IRQ handler */ 3418 void HAL_RCC_NMI_IRQHandler(void); 3419 /* User Callbacks in non blocking mode (IT mode) */ 3420 void HAL_RCC_CSSCallback(void); 3421 3422 uint32_t HAL_RCC_GetResetSource(void); 3423 /** 3424 * @} 3425 */ 3426 3427 /** 3428 * @} 3429 */ 3430 3431 /** 3432 * @} 3433 */ 3434 3435 /** 3436 * @} 3437 */ 3438 3439 #ifdef __cplusplus 3440 } 3441 #endif 3442 3443 #endif /* STM32WBxx_HAL_RCC_H */ 3444
