1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32H5xx_HAL_RCC_EX_H 21 #define __STM32H5xx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief PLL2 Clock structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. 49 This parameter must be a value of @ref RCC_PLL2_Clock_Source */ 50 51 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 52 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 53 54 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 55 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 56 57 uint32_t PLL2P; /*!< PLL2P: Division factor for peripheral clock. 58 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 59 60 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 61 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 62 63 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 65 odd division factors are not allowed */ 66 67 uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range 68 This parameter must be a value of @ref RCC_PLL2_VCI_Range */ 69 70 uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range 71 This parameter must be a value of @ref RCC_PLL2_VCO_Range */ 72 73 uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 74 PLL2 VCO It should be a value between 0 and 8191 */ 75 76 uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled. 77 This parameter must be a value or a combination of @ref RCC_PLL2_Clock_Output */ 78 } RCC_PLL2InitTypeDef; 79 80 81 #if defined(RCC_CR_PLL3ON) 82 /** 83 * @brief PLL3 Clock structure definition 84 */ 85 typedef struct 86 { 87 uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source. 88 This parameter must be a value of @ref RCC_PLL3_Clock_Source */ 89 90 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 91 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 92 93 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 94 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 95 96 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 97 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 98 99 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 100 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 101 102 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 103 This parameter must be a number between Min_Data = 1 and Max_Data = 128 104 odd division factors are not allowed */ 105 106 uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range 107 This parameter must be a value of @ref RCC_PLL3_VCI_Range */ 108 109 uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range 110 This parameter must be a value of @ref RCC_PLL3_VCO_Range */ 111 112 uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 113 PLL3 VCO It should be a value between 0 and 8191 */ 114 115 uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled. 116 This parameter must be a value or a combination of @ref RCC_PLL3_Clock_Output */ 117 } RCC_PLL3InitTypeDef; 118 #endif /* RCC_CR_PLL3ON */ 119 120 /** 121 * @brief RCC PLL1 Clocks structure definition 122 */ 123 typedef struct 124 { 125 uint32_t PLL1_P_Frequency; 126 uint32_t PLL1_Q_Frequency; 127 uint32_t PLL1_R_Frequency; 128 } PLL1_ClocksTypeDef; 129 130 /** 131 * @brief RCC PLL2 Clocks structure definition 132 */ 133 typedef struct 134 { 135 uint32_t PLL2_P_Frequency; 136 uint32_t PLL2_Q_Frequency; 137 uint32_t PLL2_R_Frequency; 138 } PLL2_ClocksTypeDef; 139 140 #if defined(RCC_CR_PLL3ON) 141 /** 142 * @brief RCC PLL3 Clocks structure definition 143 */ 144 typedef struct 145 { 146 uint32_t PLL3_P_Frequency; 147 uint32_t PLL3_Q_Frequency; 148 uint32_t PLL3_R_Frequency; 149 } PLL3_ClocksTypeDef; 150 #endif /* RCC_CR_PLL3ON */ 151 152 153 /** 154 * @brief RCC extended clocks structure definition 155 */ 156 typedef struct 157 { 158 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 159 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 160 161 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 162 This parameter will be used only when PLL2 is selected as kernel clock Source 163 for some peripherals */ 164 165 #if defined(RCC_CR_PLL3ON) 166 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 167 This parameter will be used only when PLL2 is selected as kernel clock Source 168 for some peripherals */ 169 #endif /* RCC_CR_PLL3ON */ 170 171 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 172 This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ 173 174 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 175 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 176 177 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 178 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 179 180 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 181 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 182 183 #if defined(UART4) 184 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 185 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 186 #endif /* UART4 */ 187 188 #if defined(UART5) 189 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 190 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 191 #endif /* UART5 */ 192 193 #if defined(USART6) 194 uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. 195 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ 196 #endif /* USART6 */ 197 198 #if defined(UART7) 199 uint32_t Uart7ClockSelection; /*!< Specifies UART7 clock source. 200 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ 201 #endif /* UART7 */ 202 203 #if defined(UART8) 204 uint32_t Uart8ClockSelection; /*!< Specifies UART8 clock source. 205 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ 206 #endif /* UART8 */ 207 208 #if defined(UART9) 209 uint32_t Uart9ClockSelection; /*!< Specifies UART9 clock source. 210 This parameter can be a value of @ref RCCEx_UART9_Clock_Source */ 211 #endif /* UART9 */ 212 213 #if defined(USART10) 214 uint32_t Usart10ClockSelection; /*!< Specifies USART10 clock source. 215 This parameter can be a value of @ref RCCEx_USART10_Clock_Source */ 216 #endif /* USART10 */ 217 218 #if defined(USART11) 219 uint32_t Usart11ClockSelection; /*!< Specifies USART11 clock source. 220 This parameter can be a value of @ref RCCEx_USART11_Clock_Source */ 221 #endif /* USART11 */ 222 223 #if defined(UART12) 224 uint32_t Uart12ClockSelection; /*!< Specifies UART12 clock source. 225 This parameter can be a value of @ref RCCEx_UART12_Clock_Source */ 226 #endif /* UART12 */ 227 228 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 229 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 230 231 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 232 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 233 234 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 235 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 236 237 #if defined(I2C3) 238 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 239 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 240 #endif /* I2C3 */ 241 242 #if defined(I2C4) 243 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 244 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 245 #endif /* I2C4 */ 246 247 uint32_t I3c1ClockSelection; /*!< Specifies I3C1 clock source. 248 This parameter can be a value of @ref RCCEx_I3C1_Clock_Source */ 249 250 #if defined(I3C2) 251 uint32_t I3c2ClockSelection; /*!< Specifies I3C2 clock source. 252 This parameter can be a value of @ref RCCEx_I3C2_Clock_Source */ 253 #endif /* I3C2*/ 254 255 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 256 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 257 258 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 259 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 260 261 #if defined(LPTIM3) 262 uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. 263 This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ 264 #endif /* LPTIM3 */ 265 266 #if defined(LPTIM4) 267 uint32_t Lptim4ClockSelection; /*!< Specifies LPTIM4 clock source. 268 This parameter can be a value of @ref RCCEx_LPTIM4_Clock_Source */ 269 #endif /* LPTIM4 */ 270 271 #if defined(LPTIM5) 272 uint32_t Lptim5ClockSelection; /*!< Specifies LPTIM5 clock source. 273 This parameter can be a value of @ref RCCEx_LPTIM5_Clock_Source */ 274 #endif /* LPTIM5 */ 275 276 #if defined(LPTIM6) 277 uint32_t Lptim6ClockSelection; /*!< Specifies LPTIM6 clock source. 278 This parameter can be a value of @ref RCCEx_LPTIM6_Clock_Source */ 279 #endif /* LPTIM6 */ 280 281 uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source. 282 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 283 #if defined(SAI1) 284 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 285 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 286 #endif /* SAI1*/ 287 288 #if defined(SAI2) 289 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 290 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 291 #endif /* SAI2*/ 292 293 uint32_t RngClockSelection; /*!< Specifies RNG clock source. 294 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 295 296 #if defined(SDMMC1) 297 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source. 298 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 299 #endif /* SDMMC1 */ 300 301 #if defined(SDMMC2) 302 uint32_t Sdmmc2ClockSelection; /*!< Specifies SDMMC2 clock source. 303 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ 304 #endif /* SDMMC2 */ 305 306 uint32_t AdcDacClockSelection; /*!< Specifies ADC1, ADC2 and DAC interface clock source. 307 This parameter can be a value of @ref RCCEx_ADCDAC_Clock_Source */ 308 309 uint32_t DacLowPowerClockSelection; /*!< Specifies DAC low-power clock source used in Sample and hold mode. 310 This parameter can be a value of @ref RCCEx_DAC_Low_Power_Clock_Source */ 311 312 #if defined(OCTOSPI1) 313 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 314 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 315 #endif /* OCTOSPI1 */ 316 317 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source. 318 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 319 320 uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source. 321 This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ 322 323 uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source. 324 This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ 325 326 #if defined(SPI4) 327 uint32_t Spi4ClockSelection; /*!< Specifies SPI4 clock source. 328 This parameter can be a value of @ref RCCEx_SPI4_Clock_Source */ 329 #endif /* SPI4 */ 330 331 #if defined(SPI5) 332 uint32_t Spi5ClockSelection; /*!< Specifies SPI5 clock source. 333 This parameter can be a value of @ref RCCEx_SPI5_Clock_Source */ 334 #endif /* SPI5 */ 335 336 #if defined(SPI6) 337 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source. 338 This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ 339 #endif /* SPI6 */ 340 341 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 342 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 343 344 #if defined(CEC) 345 uint32_t CecClockSelection; /*!< Specifies CEC clock source. 346 This parameter can be a value of @ref RCC_CEC_Clock_Source */ 347 #endif /* CEC */ 348 349 uint32_t UsbClockSelection; /*!< Specifies USB clock source. 350 This parameter can be a value of @ref RCC_USB_Clock_Source */ 351 352 uint32_t TimPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 353 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 354 355 } RCC_PeriphCLKInitTypeDef; 356 357 #if defined(CRS) 358 359 /** 360 * @brief RCC_CRS Init structure definition 361 */ 362 typedef struct 363 { 364 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 365 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 366 367 uint32_t Source; /*!< Specifies the SYNC signal source. 368 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 369 370 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 371 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 372 373 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC 374 event. It can be calculated in using macro 375 __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 376 This parameter must be a number between 0 and 0xFFFF or a value of 377 @ref RCCEx_CRS_ReloadValueDefault .*/ 378 379 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 380 This parameter must be a number between 0 and 0xFF or a value of 381 @ref RCCEx_CRS_ErrorLimitDefault */ 382 383 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 384 This parameter must be a number between 0 and 0x7F or a value of 385 @ref RCCEx_CRS_HSI48CalibrationDefault */ 386 387 } RCC_CRSInitTypeDef; 388 389 /** 390 * @brief RCC_CRS Synchronization structure definition 391 */ 392 typedef struct 393 { 394 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 395 This parameter must be a number between 0 and 0xFFFF */ 396 397 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 398 This parameter must be a number between 0 and 0x3F */ 399 400 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 401 value latched in the time of the last SYNC event. 402 This parameter must be a number between 0 and 0xFFFF */ 403 404 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 405 frequency error counter latched in the time of the last SYNC event. 406 It shows whether the actual frequency is below or above the target. 407 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection */ 408 409 } RCC_CRSSynchroInfoTypeDef; 410 411 #endif /* CRS */ 412 /** 413 * @} 414 */ 415 416 417 /* Exported constants --------------------------------------------------------*/ 418 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 419 * @{ 420 */ 421 422 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Microcontroller Clock Output Source 423 * @{ 424 */ 425 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed microcontroller clock output */ 426 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed microcontroller clock output */ 427 /** 428 * @} 429 */ 430 431 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 432 * @{ 433 */ 434 #define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001U) 435 #define RCC_PERIPHCLK_USART2 ((uint64_t)0x00000002U) 436 #define RCC_PERIPHCLK_USART3 ((uint64_t)0x00000004U) 437 #if defined(UART4) 438 #define RCC_PERIPHCLK_UART4 ((uint64_t)0x00000008U) 439 #endif /* UART4 */ 440 #if defined(UART5) 441 #define RCC_PERIPHCLK_UART5 ((uint64_t)0x00000010U) 442 #endif /* UART5 */ 443 #if defined(USART6) 444 #define RCC_PERIPHCLK_USART6 ((uint64_t)0x00000020U) 445 #endif /* USART6 */ 446 #if defined(UART7) 447 #define RCC_PERIPHCLK_UART7 ((uint64_t)0x00000040U) 448 #endif /* UART7 */ 449 #if defined(UART8) 450 #define RCC_PERIPHCLK_UART8 ((uint64_t)0x00000080U) 451 #endif /* UART8 */ 452 #if defined(UART9) 453 #define RCC_PERIPHCLK_UART9 ((uint64_t)0x00000100U) 454 #endif /* UART9 */ 455 #if defined(USART10) 456 #define RCC_PERIPHCLK_USART10 ((uint64_t)0x00000200U) 457 #endif /* USART10 */ 458 #if defined(USART11) 459 #define RCC_PERIPHCLK_USART11 ((uint64_t)0x00000400U) 460 #endif /* USART11 */ 461 #if defined(UART12) 462 #define RCC_PERIPHCLK_UART12 ((uint64_t)0x00000800U) 463 #endif /* UART12 */ 464 #define RCC_PERIPHCLK_LPUART1 ((uint64_t)0x00001000U) 465 #define RCC_PERIPHCLK_I2C1 ((uint64_t)0x00002000U) 466 #define RCC_PERIPHCLK_I2C2 ((uint64_t)0x00004000U) 467 #if defined(I2C3) 468 #define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00008000U) 469 #endif /* I2C3 */ 470 #define RCC_PERIPHCLK_I3C1 ((uint64_t)0x00010000U) 471 #define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00020000U) 472 #define RCC_PERIPHCLK_LPTIM2 ((uint64_t)0x00040000U) 473 #if defined(SAI1) 474 #define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00080000U) 475 #endif /* SAI1 */ 476 #if defined(SAI2) 477 #define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00100000U) 478 #endif /* SAI2 */ 479 #define RCC_PERIPHCLK_ADCDAC ((uint64_t)0x00200000U) 480 #define RCC_PERIPHCLK_ADC RCC_PERIPHCLK_ADCDAC 481 #define RCC_PERIPHCLK_DAC RCC_PERIPHCLK_ADCDAC 482 #if defined(SDMMC1) 483 #define RCC_PERIPHCLK_SDMMC1 ((uint64_t)0x00400000U) 484 #endif /* SDMMC1 */ 485 #if defined(SDMMC2) 486 #define RCC_PERIPHCLK_SDMMC2 ((uint64_t)0x00800000U) 487 #endif /* SDMMC2 */ 488 #define RCC_PERIPHCLK_CKPER ((uint64_t)0x01000000U) 489 #define RCC_PERIPHCLK_RTC ((uint64_t)0x02000000U) 490 #define RCC_PERIPHCLK_RNG ((uint64_t)0x04000000U) 491 #define RCC_PERIPHCLK_SPI1 ((uint64_t)0x08000000U) 492 #define RCC_PERIPHCLK_SPI2 ((uint64_t)0x10000000U) 493 #define RCC_PERIPHCLK_SPI3 ((uint64_t)0x20000000U) 494 #if defined(SPI4) 495 #define RCC_PERIPHCLK_SPI4 ((uint64_t)0x40000000U) 496 #endif /* SPI4 */ 497 #if defined(SPI5) 498 #define RCC_PERIPHCLK_SPI5 ((uint64_t)0x80000000U) 499 #endif /* SPI5 */ 500 #if defined(SPI6) 501 #define RCC_PERIPHCLK_SPI6 ((uint64_t)0x100000000U) 502 #endif /* SPI6 */ 503 #if defined(OCTOSPI1) 504 #define RCC_PERIPHCLK_OSPI ((uint64_t)0x200000000U) 505 #endif /* OCTOSPI1 */ 506 #define RCC_PERIPHCLK_FDCAN ((uint64_t)0x400000000U) 507 #if defined(CEC) 508 #define RCC_PERIPHCLK_CEC ((uint64_t)0x800000000U) 509 #endif /* CEC */ 510 #define RCC_PERIPHCLK_USB ((uint64_t)0x1000000000U) 511 #if defined(LPTIM3) 512 #define RCC_PERIPHCLK_LPTIM3 ((uint64_t)0x2000000000U) 513 #endif /* LPTIM3 */ 514 #if defined(LPTIM4) 515 #define RCC_PERIPHCLK_LPTIM4 ((uint64_t)0x4000000000U) 516 #endif /* LPTIM4 */ 517 #if defined(LPTIM5) 518 #define RCC_PERIPHCLK_LPTIM5 ((uint64_t)0x8000000000U) 519 #endif /* LPTIM5 */ 520 #if defined(LPTIM6) 521 #define RCC_PERIPHCLK_LPTIM6 ((uint64_t)0x10000000000U) 522 #endif /* LPTIM6 */ 523 #define RCC_PERIPHCLK_DAC_LP ((uint64_t)0x20000000000U) 524 #if defined(I2C4) 525 #define RCC_PERIPHCLK_I2C4 ((uint64_t)0x40000000000U) 526 #endif /* I2C4 */ 527 #define RCC_PERIPHCLK_TIM ((uint64_t)0x80000000000U) 528 #if defined(I3C2) 529 #define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U) 530 #endif /* I3C2 */ 531 532 /** 533 * @} 534 */ 535 536 537 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 538 * @{ 539 */ 540 #define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN 541 #define RCC_PLL2_DIVQ RCC_PLL2CFGR_PLL2QEN 542 #define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN 543 /** 544 * @} 545 */ 546 547 #if defined(RCC_CR_PLL3ON) 548 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 549 * @{ 550 */ 551 #define RCC_PLL3_DIVP RCC_PLL3CFGR_PLL3PEN 552 #define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN 553 #define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN 554 /** 555 * @} 556 */ 557 #endif /* RCC_CR_PLL3ON */ 558 559 /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range 560 * @{ 561 */ 562 #define RCC_PLL2_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 563 #define RCC_PLL2_VCIRANGE_1 RCC_PLL2CFGR_PLL2RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 564 #define RCC_PLL2_VCIRANGE_2 RCC_PLL2CFGR_PLL2RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 565 #define RCC_PLL2_VCIRANGE_3 (RCC_PLL2CFGR_PLL2RGE_0 | RCC_PLL2CFGR_PLL2RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 566 /** 567 * @} 568 */ 569 570 /** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range 571 * @{ 572 */ 573 #define RCC_PLL2_VCORANGE_WIDE (0x00000000U) /*!< Wide VCO range: 192 to 836 MHz */ 574 #define RCC_PLL2_VCORANGE_MEDIUM RCC_PLL2CFGR_PLL2VCOSEL /*!< Medium VCO range: 150 to 420 MHz */ 575 576 /** 577 * @} 578 */ 579 580 /** @defgroup RCC_PLL2_Clock_Source RCC PLL2 Clock Source 581 * @{ 582 */ 583 #define RCC_PLL2_SOURCE_NONE (0x00000000U) 584 #define RCC_PLL2_SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_0 585 #define RCC_PLL2_SOURCE_CSI RCC_PLL2CFGR_PLL2SRC_1 586 #define RCC_PLL2_SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) 587 /** 588 * @} 589 */ 590 591 #if defined(RCC_CR_PLL3ON) 592 /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range 593 * @{ 594 */ 595 #define RCC_PLL3_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 596 #define RCC_PLL3_VCIRANGE_1 RCC_PLL3CFGR_PLL3RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 597 #define RCC_PLL3_VCIRANGE_2 RCC_PLL3CFGR_PLL3RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 598 #define RCC_PLL3_VCIRANGE_3 (RCC_PLL3CFGR_PLL3RGE_0 | RCC_PLL3CFGR_PLL3RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range 604 * @{ 605 */ 606 #define RCC_PLL3_VCORANGE_WIDE (0x00000000U) /*!< Wide VCO range: 192 to 836 MHz */ 607 #define RCC_PLL3_VCORANGE_MEDIUM RCC_PLL3CFGR_PLL3VCOSEL /*!< Medium VCO range: 150 to 420 MHz */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup RCC_PLL3_Clock_Source RCC PLL3 Clock Source 613 * @{ 614 */ 615 #define RCC_PLL3_SOURCE_NONE (0x00000000U) 616 #define RCC_PLL3_SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_0 617 #define RCC_PLL3_SOURCE_CSI RCC_PLL3CFGR_PLL3SRC_1 618 #define RCC_PLL3_SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) 619 /** 620 * @} 621 */ 622 #endif /* RCC_CR_PLL3ON */ 623 624 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 625 * @{ 626 */ 627 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 628 #define RCC_USART1CLKSOURCE_PLL2Q RCC_CCIPR1_USART1SEL_0 629 #if defined(RCC_CR_PLL3ON) 630 #define RCC_USART1CLKSOURCE_PLL3Q RCC_CCIPR1_USART1SEL_1 631 #endif /* RCC_CR_PLL3ON */ 632 #define RCC_USART1CLKSOURCE_HSI (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) 633 #define RCC_USART1CLKSOURCE_CSI RCC_CCIPR1_USART1SEL_2 634 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_2) 635 /** 636 * @} 637 */ 638 639 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 640 * @{ 641 */ 642 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 643 #define RCC_USART2CLKSOURCE_PLL2Q RCC_CCIPR1_USART2SEL_0 644 #if defined(RCC_CR_PLL3ON) 645 #define RCC_USART2CLKSOURCE_PLL3Q RCC_CCIPR1_USART2SEL_1 646 #endif /* RCC_CR_PLL3ON */ 647 #define RCC_USART2CLKSOURCE_HSI (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) 648 #define RCC_USART2CLKSOURCE_CSI RCC_CCIPR1_USART2SEL_2 649 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_2) 650 /** 651 * @} 652 */ 653 654 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 655 * @{ 656 */ 657 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 658 #define RCC_USART3CLKSOURCE_PLL2Q RCC_CCIPR1_USART3SEL_0 659 #if defined(RCC_CR_PLL3ON) 660 #define RCC_USART3CLKSOURCE_PLL3Q RCC_CCIPR1_USART3SEL_1 661 #endif /* RCC_CR_PLL3ON */ 662 #define RCC_USART3CLKSOURCE_HSI (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) 663 #define RCC_USART3CLKSOURCE_CSI RCC_CCIPR1_USART3SEL_2 664 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_2) 665 /** 666 * @} 667 */ 668 669 #if defined(UART4) 670 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 671 * @{ 672 */ 673 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 674 #define RCC_UART4CLKSOURCE_PLL2Q RCC_CCIPR1_UART4SEL_0 675 #define RCC_UART4CLKSOURCE_PLL3Q RCC_CCIPR1_UART4SEL_1 676 #define RCC_UART4CLKSOURCE_HSI (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) 677 #define RCC_UART4CLKSOURCE_CSI RCC_CCIPR1_UART4SEL_2 678 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_2) 679 /** 680 * @} 681 */ 682 #endif /* UART4 */ 683 684 #if defined(UART5) 685 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 686 * @{ 687 */ 688 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 689 #define RCC_UART5CLKSOURCE_PLL2Q RCC_CCIPR1_UART5SEL_0 690 #define RCC_UART5CLKSOURCE_PLL3Q RCC_CCIPR1_UART5SEL_1 691 #define RCC_UART5CLKSOURCE_HSI (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) 692 #define RCC_UART5CLKSOURCE_CSI RCC_CCIPR1_UART5SEL_2 693 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_2) 694 /** 695 * @} 696 */ 697 #endif /* UART5 */ 698 699 #if defined(USART6) 700 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source 701 * @{ 702 */ 703 #define RCC_USART6CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 704 #define RCC_USART6CLKSOURCE_PLL2Q RCC_CCIPR1_USART6SEL_0 705 #define RCC_USART6CLKSOURCE_PLL3Q RCC_CCIPR1_USART6SEL_1 706 #define RCC_USART6CLKSOURCE_HSI (RCC_CCIPR1_USART6SEL_0 | RCC_CCIPR1_USART6SEL_1) 707 #define RCC_USART6CLKSOURCE_CSI RCC_CCIPR1_USART6SEL_2 708 #define RCC_USART6CLKSOURCE_LSE (RCC_CCIPR1_USART6SEL_0 | RCC_CCIPR1_USART6SEL_2) 709 /** 710 * @} 711 */ 712 #endif /* USART6 */ 713 714 #if defined(UART7) 715 /** @defgroup RCCEx_UART7_Clock_Source UART7 Clock Source 716 * @{ 717 */ 718 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 719 #define RCC_UART7CLKSOURCE_PLL2Q RCC_CCIPR1_UART7SEL_0 720 #define RCC_UART7CLKSOURCE_PLL3Q RCC_CCIPR1_UART7SEL_1 721 #define RCC_UART7CLKSOURCE_HSI (RCC_CCIPR1_UART7SEL_0 | RCC_CCIPR1_UART7SEL_1) 722 #define RCC_UART7CLKSOURCE_CSI RCC_CCIPR1_UART7SEL_2 723 #define RCC_UART7CLKSOURCE_LSE (RCC_CCIPR1_UART7SEL_0 | RCC_CCIPR1_UART7SEL_2) 724 /** 725 * @} 726 */ 727 #endif /* UART7 */ 728 729 #if defined(UART8) 730 /** @defgroup RCCEx_UART8_Clock_Source UART8 Clock Source 731 * @{ 732 */ 733 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 734 #define RCC_UART8CLKSOURCE_PLL2Q RCC_CCIPR1_UART8SEL_0 735 #define RCC_UART8CLKSOURCE_PLL3Q RCC_CCIPR1_UART8SEL_1 736 #define RCC_UART8CLKSOURCE_HSI (RCC_CCIPR1_UART8SEL_0 | RCC_CCIPR1_UART8SEL_1) 737 #define RCC_UART8CLKSOURCE_CSI RCC_CCIPR1_UART8SEL_2 738 #define RCC_UART8CLKSOURCE_LSE (RCC_CCIPR1_UART8SEL_0 | RCC_CCIPR1_UART8SEL_2) 739 /** 740 * @} 741 */ 742 #endif /* UART8 */ 743 744 #if defined(UART9) 745 /** @defgroup RCCEx_UART9_Clock_Source UART9 Clock Source 746 * @{ 747 */ 748 #define RCC_UART9CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 749 #define RCC_UART9CLKSOURCE_PLL2Q RCC_CCIPR1_UART9SEL_0 750 #define RCC_UART9CLKSOURCE_PLL3Q RCC_CCIPR1_UART9SEL_1 751 #define RCC_UART9CLKSOURCE_HSI (RCC_CCIPR1_UART9SEL_0 | RCC_CCIPR1_UART9SEL_1) 752 #define RCC_UART9CLKSOURCE_CSI RCC_CCIPR1_UART9SEL_2 753 #define RCC_UART9CLKSOURCE_LSE (RCC_CCIPR1_UART9SEL_0 | RCC_CCIPR1_UART9SEL_2) 754 /** 755 * @} 756 */ 757 #endif /* UART9 */ 758 759 #if defined(USART10) 760 /** @defgroup RCCEx_USART10_Clock_Source USART10 Clock Source 761 * @{ 762 */ 763 #define RCC_USART10CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 764 #define RCC_USART10CLKSOURCE_PLL2Q RCC_CCIPR1_USART10SEL_0 765 #define RCC_USART10CLKSOURCE_PLL3Q RCC_CCIPR1_USART10SEL_1 766 #define RCC_USART10CLKSOURCE_HSI (RCC_CCIPR1_USART10SEL_0 | RCC_CCIPR1_USART10SEL_1) 767 #define RCC_USART10CLKSOURCE_CSI RCC_CCIPR1_USART10SEL_2 768 #define RCC_USART10CLKSOURCE_LSE (RCC_CCIPR1_USART10SEL_0 | RCC_CCIPR1_USART10SEL_2) 769 /** 770 * @} 771 */ 772 #endif /* USART10 */ 773 774 #if defined(USART11) 775 /** @defgroup RCCEx_USART11_Clock_Source USART11 Clock Source 776 * @{ 777 */ 778 #define RCC_USART11CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 779 #define RCC_USART11CLKSOURCE_PLL2Q RCC_CCIPR2_USART11SEL_0 780 #define RCC_USART11CLKSOURCE_PLL3Q RCC_CCIPR2_USART11SEL_1 781 #define RCC_USART11CLKSOURCE_HSI (RCC_CCIPR2_USART11SEL_0 | RCC_CCIPR2_USART11SEL_1) 782 #define RCC_USART11CLKSOURCE_CSI RCC_CCIPR2_USART11SEL_2 783 #define RCC_USART11CLKSOURCE_LSE (RCC_CCIPR2_USART11SEL_0 | RCC_CCIPR2_USART11SEL_2) 784 /** 785 * @} 786 */ 787 #endif /* USART11 */ 788 789 #if defined(UART12) 790 /** @defgroup RCCEx_UART12_Clock_Source UART12 Clock Source 791 * @{ 792 */ 793 #define RCC_UART12CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 794 #define RCC_UART12CLKSOURCE_PLL2Q RCC_CCIPR2_UART12SEL_0 795 #define RCC_UART12CLKSOURCE_PLL3Q RCC_CCIPR2_UART12SEL_1 796 #define RCC_UART12CLKSOURCE_HSI (RCC_CCIPR2_UART12SEL_0 | RCC_CCIPR2_UART12SEL_1) 797 #define RCC_UART12CLKSOURCE_CSI RCC_CCIPR2_UART12SEL_2 798 #define RCC_UART12CLKSOURCE_LSE (RCC_CCIPR2_UART12SEL_0 | RCC_CCIPR2_UART12SEL_2) 799 /** 800 * @} 801 */ 802 #endif /* UART12 */ 803 804 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 805 * @{ 806 */ 807 #define RCC_LPUART1CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 808 #define RCC_LPUART1CLKSOURCE_PLL2Q RCC_CCIPR3_LPUART1SEL_0 809 #if defined(RCC_CR_PLL3ON) 810 #define RCC_LPUART1CLKSOURCE_PLL3Q RCC_CCIPR3_LPUART1SEL_1 811 #endif /* RCC_CR_PLL3ON */ 812 #define RCC_LPUART1CLKSOURCE_HSI (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) 813 #define RCC_LPUART1CLKSOURCE_CSI RCC_CCIPR3_LPUART1SEL_2 814 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_2) 815 816 /** 817 * @} 818 */ 819 820 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 821 * @{ 822 */ 823 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 824 #if defined(RCC_CR_PLL3ON) 825 #define RCC_I2C1CLKSOURCE_PLL3R RCC_CCIPR4_I2C1SEL_0 826 #else 827 #define RCC_I2C1CLKSOURCE_PLL2R RCC_CCIPR4_I2C1SEL_0 828 #endif /* RCC_CR_PLL3ON */ 829 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR4_I2C1SEL_1 830 #define RCC_I2C1CLKSOURCE_CSI (RCC_CCIPR4_I2C1SEL_1 | RCC_CCIPR4_I2C1SEL_0) 831 /** 832 * @} 833 */ 834 835 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 836 * @{ 837 */ 838 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 839 #if defined(RCC_CR_PLL3ON) 840 #define RCC_I2C2CLKSOURCE_PLL3R RCC_CCIPR4_I2C2SEL_0 841 #else 842 #define RCC_I2C2CLKSOURCE_PLL2R RCC_CCIPR4_I2C2SEL_0 843 #endif /* RCC_CR_PLL3ON */ 844 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR4_I2C2SEL_1 845 #define RCC_I2C2CLKSOURCE_CSI (RCC_CCIPR4_I2C2SEL_1 | RCC_CCIPR4_I2C2SEL_0) 846 /** 847 * @} 848 */ 849 850 #if defined(I2C3) 851 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 852 * @{ 853 */ 854 #define RCC_I2C3CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 855 #define RCC_I2C3CLKSOURCE_PLL3R RCC_CCIPR4_I2C3SEL_0 856 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR4_I2C3SEL_1 857 #define RCC_I2C3CLKSOURCE_CSI (RCC_CCIPR4_I2C3SEL_0 | RCC_CCIPR4_I2C3SEL_1) 858 /** 859 * @} 860 */ 861 #endif /* I2C3 */ 862 863 #if defined(I2C4) 864 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 865 * @{ 866 */ 867 #define RCC_I2C4CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 868 #define RCC_I2C4CLKSOURCE_PLL3R RCC_CCIPR4_I2C4SEL_0 869 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR4_I2C4SEL_1 870 #define RCC_I2C4CLKSOURCE_CSI (RCC_CCIPR4_I2C4SEL_0 | RCC_CCIPR4_I2C4SEL_1) 871 /** 872 * @} 873 */ 874 #endif /* I2C4 */ 875 876 /** @defgroup RCCEx_I3C1_Clock_Source I3C1 Clock Source 877 * @{ 878 */ 879 #define RCC_I3C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 880 #if defined(RCC_CR_PLL3ON) 881 #define RCC_I3C1CLKSOURCE_PLL3R RCC_CCIPR4_I3C1SEL_0 882 #else 883 #define RCC_I3C1CLKSOURCE_PLL2R RCC_CCIPR4_I3C1SEL_0 884 #endif /* RCC_CR_PLL3ON */ 885 #define RCC_I3C1CLKSOURCE_HSI RCC_CCIPR4_I3C1SEL_1 886 /** 887 * @} 888 */ 889 890 #if defined(I3C2) 891 /** @defgroup RCCEx_I3C2_Clock_Source I3C2 Clock Source 892 * @{ 893 */ 894 #define RCC_I3C2CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 895 #define RCC_I3C2CLKSOURCE_PLL2R RCC_CCIPR4_I3C2SEL_0 896 #define RCC_I3C2CLKSOURCE_HSI RCC_CCIPR4_I3C2SEL_1 897 /** 898 * @} 899 */ 900 #endif /* I3C2 */ 901 902 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 903 * @{ 904 */ 905 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U) 906 #define RCC_RNGCLKSOURCE_PLL1Q RCC_CCIPR5_RNGSEL_0 907 #define RCC_RNGCLKSOURCE_LSE RCC_CCIPR5_RNGSEL_1 908 #define RCC_RNGCLKSOURCE_LSI (RCC_CCIPR5_RNGSEL_0 | RCC_CCIPR5_RNGSEL_1) 909 /** 910 * @} 911 */ 912 913 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 914 * @{ 915 */ 916 #define RCC_SPI1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 917 #define RCC_SPI1CLKSOURCE_PLL2P RCC_CCIPR3_SPI1SEL_0 918 #if defined(RCC_CR_PLL3ON) 919 #define RCC_SPI1CLKSOURCE_PLL3P RCC_CCIPR3_SPI1SEL_1 920 #endif /* RCC_CR_PLL3ON */ 921 #define RCC_SPI1CLKSOURCE_PIN (RCC_CCIPR3_SPI1SEL_0 | RCC_CCIPR3_SPI1SEL_1) 922 #define RCC_SPI1CLKSOURCE_CLKP RCC_CCIPR3_SPI1SEL_2 923 /** 924 * @} 925 */ 926 927 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 928 * @{ 929 */ 930 #define RCC_SPI2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 931 #define RCC_SPI2CLKSOURCE_PLL2P RCC_CCIPR3_SPI2SEL_0 932 #if defined(RCC_CR_PLL3ON) 933 #define RCC_SPI2CLKSOURCE_PLL3P RCC_CCIPR3_SPI2SEL_1 934 #endif /* RCC_CR_PLL3ON */ 935 #define RCC_SPI2CLKSOURCE_PIN (RCC_CCIPR3_SPI2SEL_0 | RCC_CCIPR3_SPI2SEL_1) 936 #define RCC_SPI2CLKSOURCE_CLKP RCC_CCIPR3_SPI2SEL_2 937 /** 938 * @} 939 */ 940 941 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 942 * @{ 943 */ 944 #define RCC_SPI3CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 945 #define RCC_SPI3CLKSOURCE_PLL2P RCC_CCIPR3_SPI3SEL_0 946 #if defined(RCC_CR_PLL3ON) 947 #define RCC_SPI3CLKSOURCE_PLL3P RCC_CCIPR3_SPI3SEL_1 948 #endif /* RCC_CR_PLL3ON */ 949 #define RCC_SPI3CLKSOURCE_PIN (RCC_CCIPR3_SPI3SEL_0 | RCC_CCIPR3_SPI3SEL_1) 950 #define RCC_SPI3CLKSOURCE_CLKP RCC_CCIPR3_SPI3SEL_2 951 /** 952 * @} 953 */ 954 955 #if defined(SPI4) 956 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source 957 * @{ 958 */ 959 #define RCC_SPI4CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 960 #define RCC_SPI4CLKSOURCE_PLL2Q RCC_CCIPR3_SPI4SEL_0 961 #define RCC_SPI4CLKSOURCE_PLL3Q RCC_CCIPR3_SPI4SEL_1 962 #define RCC_SPI4CLKSOURCE_HSI (RCC_CCIPR3_SPI4SEL_0 | RCC_CCIPR3_SPI4SEL_1) 963 #define RCC_SPI4CLKSOURCE_CSI RCC_CCIPR3_SPI4SEL_2 964 #define RCC_SPI4CLKSOURCE_HSE (RCC_CCIPR3_SPI4SEL_0 | RCC_CCIPR3_SPI4SEL_2) 965 /** 966 * @} 967 */ 968 #endif /* SPI4 */ 969 970 #if defined(SPI5) 971 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source 972 * @{ 973 */ 974 #define RCC_SPI5CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 975 #define RCC_SPI5CLKSOURCE_PLL2Q RCC_CCIPR3_SPI5SEL_0 976 #define RCC_SPI5CLKSOURCE_PLL3Q RCC_CCIPR3_SPI5SEL_1 977 #define RCC_SPI5CLKSOURCE_HSI (RCC_CCIPR3_SPI5SEL_0 | RCC_CCIPR3_SPI5SEL_1) 978 #define RCC_SPI5CLKSOURCE_CSI RCC_CCIPR3_SPI5SEL_2 979 #define RCC_SPI5CLKSOURCE_HSE (RCC_CCIPR3_SPI5SEL_0 | RCC_CCIPR3_SPI5SEL_2) 980 /** 981 * @} 982 */ 983 #endif /* SPI5 */ 984 985 #if defined(SPI6) 986 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 987 * @{ 988 */ 989 #define RCC_SPI6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 990 #define RCC_SPI6CLKSOURCE_PLL2Q RCC_CCIPR3_SPI6SEL_0 991 #define RCC_SPI6CLKSOURCE_PLL3Q RCC_CCIPR3_SPI6SEL_1 992 #define RCC_SPI6CLKSOURCE_HSI (RCC_CCIPR3_SPI6SEL_0 | RCC_CCIPR3_SPI6SEL_1) 993 #define RCC_SPI6CLKSOURCE_CSI RCC_CCIPR3_SPI6SEL_2 994 #define RCC_SPI6CLKSOURCE_HSE (RCC_CCIPR3_SPI6SEL_0 | RCC_CCIPR3_SPI6SEL_2) 995 /** 996 * @} 997 */ 998 #endif /* SPI6 */ 999 1000 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 1001 * @{ 1002 */ 1003 #define RCC_LPTIM1CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1004 #define RCC_LPTIM1CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM1SEL_0 1005 #if defined(RCC_CR_PLL3ON) 1006 #define RCC_LPTIM1CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM1SEL_1 1007 #endif /* RCC_CR_PLL3ON */ 1008 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_1) 1009 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR2_LPTIM1SEL_2 1010 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_2) 1011 /** 1012 * @} 1013 */ 1014 1015 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 1016 * @{ 1017 */ 1018 #define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 1019 #define RCC_LPTIM2CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM2SEL_0 1020 #if defined(RCC_CR_PLL3ON) 1021 #define RCC_LPTIM2CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM2SEL_1 1022 #endif /* RCC_CR_PLL3ON */ 1023 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_1) 1024 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR2_LPTIM2SEL_2 1025 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_2) 1026 /** 1027 * @} 1028 */ 1029 1030 #if defined(LPTIM3) 1031 /** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source 1032 * @{ 1033 */ 1034 #define RCC_LPTIM3CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1035 #define RCC_LPTIM3CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM3SEL_0 1036 #define RCC_LPTIM3CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM3SEL_1 1037 #define RCC_LPTIM3CLKSOURCE_LSE (RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_1) 1038 #define RCC_LPTIM3CLKSOURCE_LSI RCC_CCIPR2_LPTIM3SEL_2 1039 #define RCC_LPTIM3CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_2) 1040 /** 1041 * @} 1042 */ 1043 #endif /* LPTIM3 */ 1044 1045 #if defined(LPTIM4) 1046 /** @defgroup RCCEx_LPTIM4_Clock_Source LPTIM4 Clock Source 1047 * @{ 1048 */ 1049 #define RCC_LPTIM4CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1050 #define RCC_LPTIM4CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM4SEL_0 1051 #define RCC_LPTIM4CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM4SEL_1 1052 #define RCC_LPTIM4CLKSOURCE_LSE (RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_1) 1053 #define RCC_LPTIM4CLKSOURCE_LSI RCC_CCIPR2_LPTIM4SEL_2 1054 #define RCC_LPTIM4CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_2) 1055 /** 1056 * @} 1057 */ 1058 #endif /* LPTIM4 */ 1059 1060 #if defined(LPTIM5) 1061 /** @defgroup RCCEx_LPTIM5_Clock_Source LPTIM5 Clock Source 1062 * @{ 1063 */ 1064 #define RCC_LPTIM5CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1065 #define RCC_LPTIM5CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM5SEL_0 1066 #define RCC_LPTIM5CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM5SEL_1 1067 #define RCC_LPTIM5CLKSOURCE_LSE (RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_1) 1068 #define RCC_LPTIM5CLKSOURCE_LSI RCC_CCIPR2_LPTIM5SEL_2 1069 #define RCC_LPTIM5CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_2) 1070 /** 1071 * @} 1072 */ 1073 #endif /* LPTIM5 */ 1074 1075 #if defined(LPTIM6) 1076 /** @defgroup RCCEx_LPTIM6_Clock_Source LPTIM6 Clock Source 1077 * @{ 1078 */ 1079 #define RCC_LPTIM6CLKSOURCE_PCLK3 ((uint32_t)0x00000000U) 1080 #define RCC_LPTIM6CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM6SEL_0 1081 #define RCC_LPTIM6CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM6SEL_1 1082 #define RCC_LPTIM6CLKSOURCE_LSE (RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_1) 1083 #define RCC_LPTIM6CLKSOURCE_LSI RCC_CCIPR2_LPTIM6SEL_2 1084 #define RCC_LPTIM6CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_2) 1085 /** 1086 * @} 1087 */ 1088 #endif /* LPTIM6 */ 1089 1090 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source 1091 * @{ 1092 */ 1093 #define RCC_FDCANCLKSOURCE_HSE ((uint32_t)0x00000000U) 1094 #define RCC_FDCANCLKSOURCE_PLL1Q RCC_CCIPR5_FDCANSEL_0 1095 #define RCC_FDCANCLKSOURCE_PLL2Q RCC_CCIPR5_FDCANSEL_1 1096 /** 1097 * @} 1098 */ 1099 1100 /** @defgroup RCCEx_ADCDAC_Clock_Source ADCDAC Kernel Clock Source 1101 * @{ 1102 */ 1103 #define RCC_ADCDACCLKSOURCE_HCLK ((uint32_t)0x00000000U) 1104 #define RCC_ADCDACCLKSOURCE_SYSCLK RCC_CCIPR5_ADCDACSEL_0 1105 #define RCC_ADCDACCLKSOURCE_PLL2R RCC_CCIPR5_ADCDACSEL_1 1106 #define RCC_ADCDACCLKSOURCE_HSE (RCC_CCIPR5_ADCDACSEL_1 | RCC_CCIPR5_ADCDACSEL_0) 1107 #define RCC_ADCDACCLKSOURCE_HSI RCC_CCIPR5_ADCDACSEL_2 1108 #define RCC_ADCDACCLKSOURCE_CSI (RCC_CCIPR5_ADCDACSEL_2 | RCC_CCIPR5_ADCDACSEL_0) 1109 1110 /** 1111 * @} 1112 */ 1113 1114 /** @defgroup RCCEx_DAC_Low_Power_Clock_Source DAC Low Power Kernel Clock Source 1115 * @{ 1116 */ 1117 #define RCC_DACLPCLKSOURCE_LSE ((uint32_t)0x00000000U) 1118 #define RCC_DACLPCLKSOURCE_LSI RCC_CCIPR5_DACSEL 1119 /** 1120 * @} 1121 */ 1122 1123 #if defined(SAI1) 1124 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 1125 * @{ 1126 */ 1127 #define RCC_SAI1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1128 #define RCC_SAI1CLKSOURCE_PLL2P RCC_CCIPR5_SAI1SEL_0 1129 #define RCC_SAI1CLKSOURCE_PLL3P RCC_CCIPR5_SAI1SEL_1 1130 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR5_SAI1SEL_1 | RCC_CCIPR5_SAI1SEL_0) 1131 #define RCC_SAI1CLKSOURCE_CLKP RCC_CCIPR5_SAI1SEL_2 1132 /** 1133 * @} 1134 */ 1135 #endif /* SAI1 */ 1136 1137 #if defined(SAI2) 1138 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 1139 * @{ 1140 */ 1141 #define RCC_SAI2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1142 #define RCC_SAI2CLKSOURCE_PLL2P RCC_CCIPR5_SAI2SEL_0 1143 #define RCC_SAI2CLKSOURCE_PLL3P RCC_CCIPR5_SAI2SEL_1 1144 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR5_SAI2SEL_1 | RCC_CCIPR5_SAI2SEL_0) 1145 #define RCC_SAI2CLKSOURCE_CLKP RCC_CCIPR5_SAI2SEL_2 1146 /** 1147 * @} 1148 */ 1149 #endif /* SAI2 */ 1150 1151 /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source 1152 * @{ 1153 */ 1154 #define RCC_CLKPSOURCE_HSI (0x00000000U) 1155 #define RCC_CLKPSOURCE_CSI RCC_CCIPR5_CKERPSEL_0 1156 #define RCC_CLKPSOURCE_HSE RCC_CCIPR5_CKERPSEL_1 1157 /** 1158 * @} 1159 */ 1160 1161 #if defined(SDMMC1) 1162 /** @defgroup RCCEx_SDMMC_Clock_Source SDMMC1 Clock Source 1163 * @{ 1164 */ 1165 #define RCC_SDMMC1CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1166 #define RCC_SDMMC1CLKSOURCE_PLL2R RCC_CCIPR4_SDMMC1SEL 1167 /** 1168 * @} 1169 */ 1170 #endif /* SDMMC1 */ 1171 1172 #if defined(SDMMC2) 1173 /** @defgroup RCCEx_SDMMC_Clock_Source SDMMC2 Clock Source 1174 * @{ 1175 */ 1176 #define RCC_SDMMC2CLKSOURCE_PLL1Q ((uint32_t)0x00000000U) 1177 #define RCC_SDMMC2CLKSOURCE_PLL2R RCC_CCIPR4_SDMMC2SEL 1178 /** 1179 * @} 1180 */ 1181 #endif /* SDMMC2 */ 1182 1183 #if defined(OCTOSPI1) 1184 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 1185 * @{ 1186 */ 1187 #define RCC_OSPICLKSOURCE_HCLK ((uint32_t)0x00000000U) 1188 #define RCC_OSPICLKSOURCE_PLL1Q RCC_CCIPR4_OCTOSPISEL_0 1189 #define RCC_OSPICLKSOURCE_PLL2R RCC_CCIPR4_OCTOSPISEL_1 1190 #define RCC_OSPICLKSOURCE_CLKP (RCC_CCIPR4_OCTOSPISEL_0 | RCC_CCIPR4_OCTOSPISEL_1) 1191 /** 1192 * @} 1193 */ 1194 #endif /* OCTOSPI1 */ 1195 1196 #if defined(CEC) 1197 /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source 1198 * @{ 1199 */ 1200 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) 1201 #define RCC_CECCLKSOURCE_LSI RCC_CCIPR5_CECSEL_0 1202 #define RCC_CECCLKSOURCE_CSI_DIV122 RCC_CCIPR5_CECSEL_1 1203 /** 1204 * @} 1205 */ 1206 #endif /* CEC */ 1207 1208 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 1209 * @{ 1210 */ 1211 #define RCC_USBCLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 1212 #if defined(RCC_CR_PLL3ON) 1213 #define RCC_USBCLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 1214 #else 1215 #define RCC_USBCLKSOURCE_PLL2Q RCC_CCIPR4_USBSEL_1 1216 #endif /* RCC_CR_PLL3ON */ 1217 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR4_USBSEL 1218 /** 1219 * @} 1220 */ 1221 1222 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 1223 * @{ 1224 */ 1225 #define RCC_TIMPRES_DEACTIVATED (0x00000000U) 1226 #define RCC_TIMPRES_ACTIVATED RCC_CFGR1_TIMPRE 1227 1228 /** 1229 * @} 1230 */ 1231 1232 #if defined(CRS) 1233 1234 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 1235 * @{ 1236 */ 1237 #define RCC_CRS_NONE ((uint32_t)0x00000000U) 1238 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U) 1239 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U) 1240 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U) 1241 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U) 1242 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U) 1243 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U) 1244 /** 1245 * @} 1246 */ 1247 1248 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 1249 * @{ 1250 */ 1251 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ 1252 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 1253 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 1254 /** 1255 * @} 1256 */ 1257 1258 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 1259 * @{ 1260 */ 1261 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ 1262 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 1263 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 1264 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 1265 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 1266 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 1267 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 1268 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 1269 /** 1270 * @} 1271 */ 1272 1273 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 1274 * @{ 1275 */ 1276 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ 1277 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 1278 /** 1279 * @} 1280 */ 1281 1282 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 1283 * @{ 1284 */ 1285 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 1286 to a target frequency of 48 MHz and a synchronization 1287 signal frequency of 1 kHz (SOF signal from USB). */ 1288 /** 1289 * @} 1290 */ 1291 1292 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 1293 * @{ 1294 */ 1295 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ 1296 /** 1297 * @} 1298 */ 1299 1300 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 1301 * @{ 1302 */ 1303 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the 1304 middle of the trimming interval. The trimming step 1305 is around 67 kHz between two consecutive TRIM 1306 steps. A higher TRIM value corresponds to a higher 1307 output frequency */ 1308 /** 1309 * @} 1310 */ 1311 1312 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 1313 * @{ 1314 */ 1315 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 1316 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 1317 /** 1318 * @} 1319 */ 1320 1321 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 1322 * @{ 1323 */ 1324 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 1325 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 1326 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 1327 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 1328 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 1329 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 1330 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 1331 /** 1332 * @} 1333 */ 1334 1335 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 1336 * @{ 1337 */ 1338 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 1339 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 1340 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 1341 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 1342 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 1343 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 1344 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 1345 /** 1346 * @} 1347 */ 1348 1349 #endif /* CRS */ 1350 1351 /** 1352 * @} 1353 */ 1354 1355 /* Exported macros -----------------------------------------------------------*/ 1356 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1357 * @{ 1358 */ 1359 1360 /** @brief Macros to enable or disable the HSI and CSI divided clock for Timers 12, 15 and LPTimer2 input capture. 1361 * @note HSI and CSI clocks without division are available when TIMIC is enabled 1362 * @retval None 1363 */ 1364 #define __HAL_RCC_TIMIC_ENABLE() SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/128 and HSI/8 generation for Timers 12,15 and LPTimer2 Input capture */ 1365 #define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock available for Timers Input capture */ 1366 1367 /** @brief Macro to configure the PLL2 clock source. 1368 * @note This function must be used only when all PLL2 is disabled. 1369 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1370 * This parameter can be one of the following values: 1371 * @arg RCC_PLL2_SOURCE_NONE: No oscillator clock selected as PLL2 clock entry 1372 * @arg RCC_PLL2_SOURCE_CSI: CSI oscillator clock selected as PLL2 clock entry 1373 * @arg RCC_PLL2_SOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry 1374 * @arg RCC_PLL2_SOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry 1375 * 1376 */ 1377 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, \ 1378 (__PLL2SOURCE__)) 1379 1380 /** @brief Macro to get the oscillator used as PLL2 clock source. 1381 * @retval The oscillator used as PLL2 clock source. The returned value can be one 1382 * of the following: 1383 * - RCC_PLL2_SOURCE_NONE: No oscillator is used as PLL clock source. 1384 * - RCC_PLL2_SOURCE_CSI: CSI oscillator is used as PLL clock source. 1385 * - RCC_PLL2_SOURCE_HSI: HSI oscillator is used as PLL clock source. 1386 * - RCC_PLL2_SOURCE_HSE: HSE oscillator is used as PLL clock source. 1387 */ 1388 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) 1389 1390 /** 1391 * @brief Macro to configures the PLL2 source, multiplication and division factors. 1392 * @note This function must be used only when PLL2 is disabled. 1393 * 1394 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1395 * This parameter can be one of the following values: 1396 * @arg @ref RCC_PLL2_SOURCE_NONE No clock selected as PLL2 clock entry 1397 * @arg @ref RCC_PLL2_SOURCE_CSI CSI oscillator clock selected as PLL2 clock entry 1398 * @arg @ref RCC_PLL2_SOURCE_HSI HSI oscillator clock selected as PLL2 clock entry 1399 * @arg @ref RCC_PLL2_SOURCE_HSE HSE oscillator clock selected as PLL2 clock entry 1400 * 1401 * @param __PLL2M__ specifies the division factor of PLL2 input clock. 1402 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1403 * 1404 * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock 1405 * This parameter must be a number between 4 and 512. 1406 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1407 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1408 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 1409 * 1410 * @param __PLL2P__: specifies the division factor for peripheral kernel clocks 1411 * This parameter must be a number between 1 and 128 1412 * 1413 * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks 1414 * This parameter must be a number between 1 and 128 1415 * 1416 * @param __PLL2R__: specifies the division factor for peripheral kernel clocks 1417 * This parameter must be a number between 1 and 128 1418 * 1419 * @retval None 1420 */ 1421 #define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ 1422 do{ \ 1423 MODIFY_REG(RCC->PLL2CFGR, (RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M), \ 1424 ((__PLL2SOURCE__) << RCC_PLL2CFGR_PLL2SRC_Pos) | ((__PLL2M__) << RCC_PLL2CFGR_PLL2M_Pos)); \ 1425 WRITE_REG(RCC->PLL2DIVR , ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | \ 1426 ((((__PLL2P__) - 1U) << RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) | \ 1427 ((((__PLL2Q__) - 1U) << RCC_PLL2DIVR_PLL2Q_Pos) & RCC_PLL2DIVR_PLL2Q) | \ 1428 ((((__PLL2R__) - 1U) << RCC_PLL2DIVR_PLL2R_Pos) & RCC_PLL2DIVR_PLL2R))); \ 1429 } while(0) 1430 /** 1431 * @brief Macro to configure the PLL2 clock multiplication factor N. 1432 * 1433 * @note This function must be used only when the PLL2 is disabled. 1434 * @note PLL2 clock source is independent from the main PLL and is configured through 1435 * __HAL_RCC_PLL2_CONFIG() macro. 1436 * 1437 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock. 1438 * This parameter must be a number between 4 and 512. 1439 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1440 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1441 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 1442 * 1443 * @retval None 1444 */ 1445 #define __HAL_RCC_PLL2_MULN_CONFIG(__PLL2N__) \ 1446 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, ((__PLL2N__) - 1U) << RCC_PLL2DIVR_N2_Pos) 1447 1448 /** @brief Macro to configure the PLL2 input clock division factor M. 1449 * 1450 * @note This function must be used only when the PLL2 is disabled. 1451 * @note PLL2 clock source is independent from the main PLL and is configured through 1452 * __HAL_RCC_PLL2_CONFIG() macro. 1453 * 1454 * @param __PLL2M__ specifies the division factor for PLL2 clock. 1455 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1456 * In order to save power when PLL2 is not used, the value of PLL2M must be set to 0. 1457 * 1458 * @retval None 1459 */ 1460 #define __HAL_RCC_PLL2_DIVM_CONFIG(__PLL2M__) \ 1461 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_DIVM2, (__PLL2M__) << RCC_PLL2CFGR_DIVM2_Pos) 1462 1463 /** @brief Macro to configure the PLL2 clock division factor P. 1464 * 1465 * @note This function must be used only when the PLL2 is disabled. 1466 * @note PLL2 clock source is independent from the main PLL and is configured through 1467 * __HAL_RCC_PLL2_CONFIG() macro. 1468 * 1469 * @param __PLL2P__ specifies the division factor for PLL2 output P clock. 1470 * This parameter must be a number in the range (1 to 128). 1471 * Use to set PLL2 output P clock frequency = f(PLL2) / PLL2P 1472 * 1473 * @retval None 1474 */ 1475 #define __HAL_RCC_PLL2_DIVP_CONFIG(__PLL2P__) \ 1476 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, ((__PLL2P__) - 1U) << RCC_PLL2DIVR_P2_Pos) 1477 1478 /** @brief Macro to configure the PLL2 clock division factor Q. 1479 * 1480 * @note This function must be used only when the PLL2 is disabled. 1481 * @note PLL2 clock source is independent from the main PLL and is configured through 1482 * __HAL_RCC_PLL2_CONFIG() macro. 1483 * 1484 * @param __PLL2Q__ specifies the division factor for PLL2 output Q clock. 1485 * This parameter must be a number in the range (1 to 128). 1486 * Use to set PLL2 output Q clock frequency = f(PLL2) / PLL2Q 1487 * 1488 * @retval None 1489 */ 1490 #define __HAL_RCC_PLL2_DIVQ_CONFIG(__PLL2Q__) \ 1491 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, ((__PLL2Q__) - 1U) << RCC_PLL2DIVR_Q2_Pos) 1492 1493 /** @brief Macro to configure the PLL2 clock division factor R. 1494 * 1495 * @note This function must be used only when the PLL2 is disabled. 1496 * @note PLL2 clock source is independent from the main PLL and is configured through 1497 * __HAL_RCC_PLL2_CONFIG() macro. 1498 * 1499 * @param __PLL2R__ specifies the division factor for PLL2 output R clock. 1500 * This parameter must be a number in the range (1 to 128). 1501 * Use to set PLL2 output R clock frequency = f(PLL2) / PLL2R 1502 * 1503 * @retval None 1504 */ 1505 #define __HAL_RCC_PLL2_DIVR_CONFIG(__PLL2R__) \ 1506 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, ((__PLL2R__) - 1U) << RCC_PLL2DIVR_R2_Pos) 1507 1508 /** @brief Macros to enable or disable the PLL2. 1509 * @note After enabling PLL2, the application software should wait on 1510 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1511 * be used as kernel clock source. 1512 * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1513 * @retval None 1514 */ 1515 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 1516 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 1517 1518 /** 1519 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 1520 * @note Enabling/disabling those clocks can be done at any time without the need to stop the PLL2, 1521 * This is mainly used to save Power. 1522 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. 1523 * This parameter can be one or a combination of the following values: 1524 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve 1525 * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. 1526 * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG 1527 * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. 1528 * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. 1529 * @retval None 1530 */ 1531 #define __HAL_RCC_PLL2_CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1532 #define __HAL_RCC_PLL2_CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1533 1534 /** 1535 * @brief Macro to get the PLL2 clock output enable status. 1536 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be output. 1537 * This parameter can be one or a combination of the following values: 1538 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate kernel clock to achieve 1539 * high-quality audio performance on SAI interface, SPI/I2S and LPTIM peripherals. 1540 * @arg RCC_PLL2_DIVQ: This clock is used to generate kernel clock for the random number generator RNG 1541 * (<=48 MHz), SPI, FDCAN and UART/USART peripherals. 1542 * @arg RCC_PLL2_DIVR: This clock is used to generate kernel clock for ADC and DAC peripherals. 1543 * @retval SET / RESET 1544 */ 1545 #define __HAL_RCC_GET_PLL2_CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1546 1547 /** 1548 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1549 * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL2 1550 * @retval None 1551 */ 1552 #define __HAL_RCC_PLL2_FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1553 #define __HAL_RCC_PLL2_FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1554 1555 /** 1556 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1557 * 1558 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1559 * 1560 * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1561 * It should be a value between 0 and 8191 1562 * @note Warning: the software has to set correctly these bits to insure that the VCO 1563 * output frequency is between its valid frequency range, which is: 1564 * 192 to 836 MHz if PLL2VCOSEL = 0 1565 * 150 to 420 MHz if PLL2VCOSEL = 1. 1566 * 1567 * @retval None 1568 */ 1569 #define __HAL_RCC_PLL2_FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, \ 1570 (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) 1571 1572 /** @brief Macro to select the PLL2 reference frequency range. 1573 * @param __PLL2VCIRange__: specifies the PLL2 input frequency range 1574 * This parameter can be one of the following values: 1575 * @arg RCC_PLL2_VCIRANGE_0: Range frequency is between 1 and 2 MHz 1576 * @arg RCC_PLL2_VCIRANGE_1: Range frequency is between 2 and 4 MHz 1577 * @arg RCC_PLL2_VCIRANGE_2: Range frequency is between 4 and 8 MHz 1578 * @arg RCC_PLL2_VCIRANGE_3: Range frequency is between 8 and 16 MHz 1579 * @retval None 1580 */ 1581 #define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ 1582 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) 1583 1584 /** @brief Macro to select the PLL2 reference frequency range. 1585 * @param __RCC_PLL2VCORange__: specifies the PLL2 output frequency range 1586 * This parameter can be one of the following values: 1587 * @arg RCC_PLL2_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz 1588 * @arg RCC_PLL2_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz 1589 * 1590 * @retval None 1591 */ 1592 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ 1593 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) 1594 1595 #if defined(RCC_CR_PLL3ON) 1596 /** @brief Macro to configure the PLL3 clock source. 1597 * @note This function must be used only when all PLL3 is disabled. 1598 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1599 * This parameter can be one of the following values: 1600 * @arg RCC_PLL3_SOURCE_NONE: No oscillator clock selected as PLL3 clock entry 1601 * @arg RCC_PLL3_SOURCE_CSI: CSI oscillator clock selected as PLL3 clock entry 1602 * @arg RCC_PLL3_SOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry 1603 * @arg RCC_PLL3_SOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry 1604 * 1605 */ 1606 #define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ 1607 (__PLL3SOURCE__)) 1608 1609 /** @brief Macro to get the oscillator used as PLL3 clock source. 1610 * @retval The oscillator used as PLL3 clock source. The returned value can be one 1611 * of the following: 1612 * - RCC_PLL3_SOURCE_NONE: No oscillator is used as PLL3 clock source. 1613 * - RCC_PLL3_SOURCE_CSI: CSI oscillator is used as PLL3 clock source. 1614 * - RCC_PLL3_SOURCE_HSI: HSI oscillator is used as PLL3 clock source. 1615 * - RCC_PLL3_SOURCE_HSE: HSE oscillator is used as PLL3 clock source. 1616 */ 1617 #define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) 1618 1619 /** 1620 * @brief Macro to configures the PLL3 source, multiplication and division factors. 1621 * @note This function must be used only when PLL3 is disabled. 1622 * 1623 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1624 * This parameter can be one of the following values: 1625 * @arg @ref RCC_PLL3_SOURCE_NONE No clock selected as PLL3 clock entry 1626 * @arg @ref RCC_PLL3_SOURCE_CSI CSI oscillator clock selected as PLL3 clock entry 1627 * @arg @ref RCC_PLL3_SOURCE_HSI HSI oscillator clock selected as PLL3 clock entry 1628 * @arg @ref RCC_PLL3_SOURCE_HSE HSE oscillator clock selected as PLL3 clock entry 1629 * 1630 * @param __PLL3M__ specifies the division factor of PLL3 input clock. 1631 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1632 * 1633 * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock 1634 * This parameter must be a number between 4 and 512. 1635 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1636 * output frequency is between 150 and 420 MHz (when in medium VCO range) 1637 * or between 192 and 836 MHZ (when in wide VCO range) 1638 * 1639 * @param __PLL3P__: specifies the division factor for peripheral kernel clocks 1640 * This parameter must be a number between 1 and 128 1641 * 1642 * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks 1643 * This parameter must be a number between 1 and 128 1644 * 1645 * @param __PLL3R__: specifies the division factor for peripheral kernel clocks 1646 * This parameter must be a number between 1 and 128 1647 * 1648 * @retval None 1649 */ 1650 #define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ 1651 do{\ 1652 MODIFY_REG(RCC->PLL3CFGR, (RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M), \ 1653 ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos) | ((__PLL3M__) << RCC_PLL3CFGR_PLL3M_Pos)); \ 1654 WRITE_REG(RCC->PLL3DIVR , ( (((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | \ 1655 ((((__PLL3P__) - 1U) << RCC_PLL3DIVR_PLL3P_Pos) & RCC_PLL3DIVR_PLL3P) | \ 1656 ((((__PLL3Q__) - 1U) << RCC_PLL3DIVR_PLL3Q_Pos) & RCC_PLL3DIVR_PLL3Q) | \ 1657 ((((__PLL3R__) - 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ 1658 } while(0) 1659 1660 /** 1661 * @brief Macro to configure the PLL3 clock multiplication factor N. 1662 * 1663 * @note This function must be used only when the PLL3 is disabled. 1664 * @note PLL3 clock source is independent from the main PLL and is configured through 1665 * __HAL_RCC_PLL3_CONFIG() macro. 1666 * 1667 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock. 1668 * This parameter must be a number between 8 and 86. 1669 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1670 * output frequency is between 192 and 836 MHz (Wide range) or 150 and 420 Mhz (Medium range). 1671 * PLL3 clock frequency = f(PLL3) multiplied by PLL3N 1672 * 1673 * @retval None 1674 */ 1675 #define __HAL_RCC_PLL3_MULN_CONFIG(__PLL3N__) \ 1676 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, ((__PLL3N__) - 1U) << RCC_PLL3DIVR_N3_Pos) 1677 1678 /** @brief Macro to configure the PLL3 input clock division factor M. 1679 * 1680 * @note This function must be used only when the PLL3 is disabled. 1681 * @note PLL3 clock source is independent from the main PLL and is configured through 1682 * __HAL_RCC_PLL3_CONFIG() macro. 1683 * 1684 * @param __PLL3M__ specifies the division factor for PLL3 clock. 1685 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 1686 * In order to save power when PLL3 is not used, the value of PLL3M must be set to 0. 1687 * 1688 * @retval None 1689 */ 1690 #define __HAL_RCC_PLL3_DIVM_CONFIG(__PLL3M__) \ 1691 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_DIVM3, (__PLL3M__) << RCC_PLL3CFGR_DIVM3_Pos) 1692 1693 /** @brief Macro to configure the PLL3 clock division factor P. 1694 * 1695 * @note This function must be used only when the PLL3 is disabled. 1696 * @note PLL3 clock source is independent from the main PLL and is configured through 1697 * __HAL_RCC_PLL3_CONFIG() macro. 1698 * 1699 * @param __PLL3P__ specifies the division factor for PLL3 output P clock. 1700 * This parameter must be a number in the range (1 to 128). 1701 * Use to set PLL3 output P clock frequency = f(PLL3) / PLL3P 1702 * 1703 * @retval None 1704 */ 1705 #define __HAL_RCC_PLL3_DIVP_CONFIG(__PLL3P__) \ 1706 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, ((__PLL3P__) - 1U) << RCC_PLL3DIVR_P3_Pos) 1707 1708 /** @brief Macro to configure the PLL3 clock division factor Q. 1709 * 1710 * @note This function must be used only when the PLL3 is disabled. 1711 * @note PLL3 clock source is independent from the main PLL and is configured through 1712 * __HAL_RCC_PLL3_CONFIG() macro. 1713 * 1714 * @param __PLL3Q__ specifies the division factor for PLL3 output Q clock. 1715 * This parameter must be a number in the range (1 to 128). 1716 * Use to set PLL3 output Q clock frequency = f(PLL3) / PLL3Q 1717 * 1718 * @retval None 1719 */ 1720 #define __HAL_RCC_PLL3_DIVQ_CONFIG(__PLL3Q__) \ 1721 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, ((__PLL3Q__) - 1U) << RCC_PLL3DIVR_Q3_Pos) 1722 1723 /** @brief Macro to configure the PLL3 clock division factor R. 1724 * 1725 * @note This function must be used only when the PLL3 is disabled. 1726 * @note PLL3 clock source is independent from the main PLL and is configured through 1727 * __HAL_RCC_PLL3_CONFIG() macro. 1728 * 1729 * @param __PLL3R__ specifies the division factor for PLL3 output R clock. 1730 * This parameter must be a number in the range (1 to 128). 1731 * Use to set PLL3 output R clock frequency = f(PLL3) / PLL3R 1732 * 1733 * @retval None 1734 */ 1735 #define __HAL_RCC_PLL3_DIVR_CONFIG(__PLL3R__) \ 1736 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, ((__PLL3R__) - 1U) << RCC_PLL3DIVR_R3_Pos) 1737 1738 /** 1739 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1740 * 1741 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1742 * 1743 * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1744 * It should be a value between 0 and 8191 1745 * @note Warning: the software has to set correctly these bits to insure that the VCO 1746 * output frequency is between its valid frequency range, which is: 1747 * 192 to 836 MHz if PLL3VCOSEL = 0 1748 * 150 to 420 MHz if PLL3VCOSEL = 1. 1749 * 1750 * @retval None 1751 */ 1752 #define __HAL_RCC_PLL3_FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ 1753 (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) 1754 1755 /** @brief Macro to select the PLL3 reference frequency range. 1756 * @param __PLL3VCIRange__: specifies the PLL3 input frequency range 1757 * This parameter can be one of the following values: 1758 * @arg RCC_PLL3_VCIRANGE_0: Range frequency is between 1 and 2 MHz 1759 * @arg RCC_PLL3_VCIRANGE_1: Range frequency is between 2 and 4 MHz 1760 * @arg RCC_PLL3_VCIRANGE_2: Range frequency is between 4 and 8 MHz 1761 * @arg RCC_PLL3_VCIRANGE_3: Range frequency is between 8 and 16 MHz 1762 * 1763 * @retval None 1764 */ 1765 #define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ 1766 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) 1767 1768 /** @brief Macro to select the PLL3 reference frequency range. 1769 * @param __RCC_PLL3VCORange__: specifies the PLL3 input frequency range 1770 * This parameter can be one of the following values: 1771 * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz 1772 * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz 1773 * 1774 * @retval None 1775 */ 1776 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ 1777 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) 1778 1779 /** 1780 * @brief Macros to enable or disable the PLL3. 1781 * @note The PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1782 * @retval None 1783 */ 1784 1785 /** @brief Macros to enable or disable the main PLL3. 1786 * @note After enabling PLL3, the application software should wait on 1787 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1788 * be used as kernel clock source. 1789 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1790 */ 1791 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1792 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1793 1794 /** 1795 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1796 * @note Enabling/disabling Fractional Part can be done at any time without the need to stop the PLL3 1797 * @retval None 1798 */ 1799 #define __HAL_RCC_PLL3_FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1800 #define __HAL_RCC_PLL3_FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1801 1802 /** 1803 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1804 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, 1805 * This is mainly used to save Power. 1806 * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted 1807 * This parameter can be one of the following values: 1808 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1809 * high-quality audio performance on SAI and SPI/I2S interfaces. 1810 * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART 1811 * and USB peripherals. 1812 * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. 1813 * 1814 * @retval None 1815 */ 1816 #define __HAL_RCC_PLL3_CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1817 #define __HAL_RCC_PLL3_CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1818 1819 /** 1820 * @brief Macro to get clock output enable status (PLL3_SAI2). 1821 * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be output. 1822 * This parameter can be one or a combination of the following values: 1823 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1824 * high-quality audio performance on SAI and SPI/I2S interfaces. 1825 * @arg RCC_PLL3_DIVQ: This clock is used to generate kernel clock for SPI, LPUART, UART/USART 1826 * and USB peripherals. 1827 * @arg RCC_PLL3_DIVR: This clock is used to generate kernel clock for I2C, I3C and LPTIM peripherals. 1828 * 1829 * @retval SET / RESET 1830 */ 1831 #define __HAL_RCC_GET_PLL3_CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1832 #endif /* RCC_CR_PLL3ON */ 1833 1834 /** @brief Macro to configure the ADC and DAC kernel clock source. 1835 * @param __ADCDAC_CLKSOURCE__ specifies the ADC and DAC kernel clock source. 1836 * This parameter can be one of the following values: 1837 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB bus clock selected as ADC and DAC kernel clock 1838 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock selected as ADC and DAC kernel clock 1839 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock selected as ADC and DAC kernel clock 1840 * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE clock selected as ADC and DAC kernel clock 1841 * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI clock selected as ADC and DAC kernel clock 1842 * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI clock selected as ADC and DAC kernel clock 1843 * @retval None 1844 */ 1845 #define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ 1846 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) 1847 1848 /** @brief Macro to get the ADC and DAC kernel clock source. 1849 * @retval The clock source can be one of the following values: 1850 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK AHB Bus clock used as ADC and DAC kernel clock 1851 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK System clock used as ADC and DAC kernel clock 1852 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2R PLL2R clock used as ADC and DAC kernel clock 1853 * @arg @ref RCC_ADCDACCLKSOURCE_HSE HSE oscillator used as ADC and DAC kernel clock 1854 * @arg @ref RCC_ADCDACCLKSOURCE_HSI HSI oscillator used as ADC and DAC kernel clock 1855 * @arg @ref RCC_ADCDACCLKSOURCE_CSI CSI oscillator used as ADC and DAC kernel clock 1856 */ 1857 #define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL))) 1858 1859 /** @brief Macro to configure the DAC kernel clock source in low-power mode. 1860 * @param __DACLPCLKSOURCE__ specifies the DAC kernel clock source in low-power mode. 1861 * This parameter can be one of the following values: 1862 * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator selected as DAC kernel clock in low-power mode 1863 * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator selected as DAC kernel clock in low-power mode 1864 * @retval None 1865 */ 1866 #define __HAL_RCC_DAC_LP_CONFIG(__DACLPCLKSOURCE__) \ 1867 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_DACSEL, (uint32_t)(__DACLPCLKSOURCE__)) 1868 1869 /** @brief Macro to get the DAC kernel clock source in low-power mode. 1870 * @retval The clock source can be one of the following values: 1871 * @arg @ref RCC_DACLPCLKSOURCE_LSE LSE oscillator used as DAC kernel clock in low-power mode 1872 * @arg @ref RCC_DACLPCLKSOURCE_LSI LSI oscillator used as DAC kernel clock in low-power mode 1873 */ 1874 #define __HAL_RCC_GET_DAC_LP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_DACSEL))) 1875 1876 /** @brief Macro to configure the FDCAN kernel clock (FDCANCLK). 1877 * 1878 * @param __FDCAN_CLKSOURCE__ specifies the FDCAN kernel clock source. 1879 * This parameter can be one of the following values: 1880 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE oscillator selected as FDCAN kernel clock 1881 * @arg @ref RCC_FDCANCLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN kernel clock 1882 * @arg @ref RCC_FDCANCLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN kernel clock 1883 * @retval None 1884 */ 1885 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ 1886 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 1887 1888 /** @brief Macro to get the FDCAN clock source. 1889 * @retval The clock source can be one of the following values: 1890 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE oscillator selected as FDCAN kernel clock 1891 * @arg @ref RCC_FDCANCLKSOURCE_PLL1Q PLL1Q Clock selected as FDCAN kernel clock 1892 * @arg @ref RCC_FDCANCLKSOURCE_PLL2Q PLL2Q Clock selected as FDCAN kernel clock 1893 */ 1894 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL))) 1895 1896 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1897 * 1898 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1899 * This parameter can be one of the following values: 1900 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock 1901 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock 1902 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) 1903 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1904 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1905 * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 1906 * @retval None 1907 * 1908 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1909 */ 1910 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1911 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1912 1913 /** @brief Macro to get the LPTIM1 clock source. 1914 * @retval The clock source can be one of the following values: 1915 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK3 PCLK3 selected as LPTIM1 clock 1916 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL2P PLL2P selected as LPTIM1 clock 1917 * @arg @ref RCC_LPTIM1CLKSOURCE_PLL3R PLL3R selected as LPTIM1 clock (*) 1918 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1919 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1920 * @arg @ref RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock 1921 * 1922 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1923 */ 1924 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL))) 1925 1926 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1927 * 1928 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1929 * This parameter can be one of the following values: 1930 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1931 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock 1932 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) 1933 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1934 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1935 * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock 1936 * @retval None 1937 * 1938 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1939 */ 1940 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1941 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 1942 1943 /** @brief Macro to get the LPTIM2 clock source. 1944 * @retval The clock source can be one of the following values: 1945 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1946 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL2P PLL2P selected as LPTIM2 clock 1947 * @arg @ref RCC_LPTIM2CLKSOURCE_PLL3R PLL3R selected as LPTIM2 clock (*) 1948 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1949 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1950 * @arg @ref RCC_LPTIM2CLKSOURCE_CLKP CLKP selected as LPTIM2 clock 1951 * 1952 * (*) : For stm32h56xxx and stm32h57xxx family lines. 1953 */ 1954 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM2SEL))) 1955 1956 #if defined(LPTIM3) 1957 /** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). 1958 * 1959 * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. 1960 * This parameter can be one of the following values: 1961 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock 1962 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock 1963 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock 1964 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1965 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1966 * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock 1967 * @retval None 1968 */ 1969 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ 1970 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) 1971 1972 /** @brief Macro to get the LPTIM3 clock source. 1973 * @retval The clock source can be one of the following values: 1974 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK3 PCLK3 selected as LPTIM3 clock 1975 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL2P PLL2P selected as LPTIM3 clock 1976 * @arg @ref RCC_LPTIM3CLKSOURCE_PLL3R PLL3R selected as LPTIM3 clock 1977 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1978 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1979 * @arg @ref RCC_LPTIM3CLKSOURCE_CLKP CLKP selected as LPTIM3 clock 1980 */ 1981 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM3SEL))) 1982 #endif /* LPTIM3 */ 1983 1984 #if defined(LPTIM4) 1985 /** @brief Macro to configure the LPTIM4 clock (LPTIM4CLK). 1986 * 1987 * @param __LPTIM4_CLKSOURCE__ specifies the LPTIM4 clock source. 1988 * This parameter can be one of the following values: 1989 * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock 1990 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock 1991 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock 1992 * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock 1993 * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock 1994 * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock 1995 * @retval None 1996 */ 1997 #define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4_CLKSOURCE__) \ 1998 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL, (uint32_t)(__LPTIM4_CLKSOURCE__)) 1999 2000 /** @brief Macro to get the LPTIM4 clock source. 2001 * @retval The clock source can be one of the following values: 2002 * @arg @ref RCC_LPTIM4CLKSOURCE_PCLK3 PCLK3 selected as LPTIM4 clock 2003 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL2P PLL2P selected as LPTIM4 clock 2004 * @arg @ref RCC_LPTIM4CLKSOURCE_PLL3R PLL3R selected as LPTIM4 clock 2005 * @arg @ref RCC_LPTIM4CLKSOURCE_LSE LSE selected as LPTIM4 clock 2006 * @arg @ref RCC_LPTIM4CLKSOURCE_LSI LSI selected as LPTIM4 clock 2007 * @arg @ref RCC_LPTIM4CLKSOURCE_CLKP CLKP selected as LPTIM4 clock 2008 */ 2009 #define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM4SEL))) 2010 #endif /* LPTIM4 */ 2011 2012 #if defined(LPTIM5) 2013 /** @brief Macro to configure the LPTIM5 clock (LPTIM5CLK). 2014 * 2015 * @param __LPTIM5_CLKSOURCE__ specifies the LPTIM5 clock source. 2016 * This parameter can be one of the following values: 2017 * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock 2018 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock 2019 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock 2020 * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock 2021 * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock 2022 * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock 2023 * @retval None 2024 */ 2025 #define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5_CLKSOURCE__) \ 2026 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL, (uint32_t)(__LPTIM5_CLKSOURCE__)) 2027 2028 /** @brief Macro to get the LPTIM5 clock source. 2029 * @retval The clock source can be one of the following values: 2030 * @arg @ref RCC_LPTIM5CLKSOURCE_PCLK3 PCLK3 selected as LPTIM5 clock 2031 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL2P PLL2P selected as LPTIM5 clock 2032 * @arg @ref RCC_LPTIM5CLKSOURCE_PLL3R PLL3R selected as LPTIM5 clock 2033 * @arg @ref RCC_LPTIM5CLKSOURCE_LSE LSE selected as LPTIM5 clock 2034 * @arg @ref RCC_LPTIM5CLKSOURCE_LSI LSI selected as LPTIM5 clock 2035 * @arg @ref RCC_LPTIM5CLKSOURCE_CLKP CLKP selected as LPTIM5 clock 2036 */ 2037 #define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM5SEL))) 2038 #endif /* LPTIM5 */ 2039 2040 #if defined(LPTIM6) 2041 /** @brief Macro to configure the LPTIM6 clock (LPTIM6CLK). 2042 * 2043 * @param __LPTIM6_CLKSOURCE__ specifies the LPTIM6 clock source. 2044 * This parameter can be one of the following values: 2045 * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock 2046 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock 2047 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock 2048 * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock 2049 * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock 2050 * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock 2051 * @retval None 2052 */ 2053 #define __HAL_RCC_LPTIM6_CONFIG(__LPTIM6_CLKSOURCE__) \ 2054 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL, (uint32_t)(__LPTIM6_CLKSOURCE__)) 2055 2056 /** @brief Macro to get the LPTIM6 clock source. 2057 * @retval The clock source can be one of the following values: 2058 * @arg @ref RCC_LPTIM6CLKSOURCE_PCLK3 PCLK3 selected as LPTIM6 clock 2059 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL2P PLL2P selected as LPTIM6 clock 2060 * @arg @ref RCC_LPTIM6CLKSOURCE_PLL3R PLL3R selected as LPTIM6 clock 2061 * @arg @ref RCC_LPTIM6CLKSOURCE_LSE LSE selected as LPTIM6 clock 2062 * @arg @ref RCC_LPTIM6CLKSOURCE_LSI LSI selected as LPTIM6 clock 2063 * @arg @ref RCC_LPTIM6CLKSOURCE_CLKP CLKP selected as LPTIM6 clock 2064 */ 2065 #define __HAL_RCC_GET_LPTIM6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM6SEL))) 2066 #endif /* LPTIM6 */ 2067 2068 /** @brief macro to configure the SPI1 clock source. 2069 * @retval The clock source can be one of the following values: 2070 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock 2071 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock 2072 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) 2073 * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock 2074 * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock 2075 * 2076 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2077 */ 2078 #define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ 2079 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) 2080 2081 /** @brief macro to get the SPI1 clock source. 2082 * @retval The clock source can be one of the following values: 2083 * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1Q selected as SPI1 clock 2084 * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2P selected as SPI1 clock 2085 * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3P selected as SPI1 clock (*) 2086 * @arg RCC_SPI1CLKSOURCE_PIN External Clock selected as SPI1 clock 2087 * @arg RCC_SPI1CLKSOURCE_CLKP CLKP selected as SPI1 clock 2088 * 2089 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2090 */ 2091 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL))) 2092 2093 /** @brief macro to configure the SPI2 clock source. 2094 * @retval The clock source can be one of the following values: 2095 * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock 2096 * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock 2097 * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) 2098 * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock 2099 * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock 2100 * 2101 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2102 */ 2103 #define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ 2104 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) 2105 2106 /** @brief macro to get the SPI2 clock source. 2107 * @retval The clock source can be one of the following values: 2108 * @arg RCC_SPI2CLKSOURCE_PLL1Q PLL1Q selected as SPI2 clock 2109 * @arg RCC_SPI2CLKSOURCE_PLL2P PLL2P selected as SPI2 clock 2110 * @arg RCC_SPI2CLKSOURCE_PLL3P PLL3P selected as SPI2 clock (*) 2111 * @arg RCC_SPI2CLKSOURCE_PIN External Clock selected as SPI2 clock 2112 * @arg RCC_SPI2CLKSOURCE_CLKP CLKP selected as SPI2 clock 2113 * 2114 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2115 */ 2116 #define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI2SEL))) 2117 2118 /** @brief macro to configure the SPI3 clock source. 2119 * @retval The clock source can be one of the following values: 2120 * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock 2121 * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock 2122 * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) 2123 * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock 2124 * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock 2125 * 2126 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2127 */ 2128 #define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ 2129 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) 2130 2131 /** @brief macro to get the SPI3 clock source. 2132 * @retval The clock source can be one of the following values: 2133 * @arg RCC_SPI3CLKSOURCE_PLL1Q PLL1Q used as SPI3 clock 2134 * @arg RCC_SPI3CLKSOURCE_PLL2P PLL2P used as SPI3 clock 2135 * @arg RCC_SPI3CLKSOURCE_PLL3P PLL3P used as SPI3 clock (*) 2136 * @arg RCC_SPI3CLKSOURCE_PIN External Clock used as SPI3 clock 2137 * @arg RCC_SPI3CLKSOURCE_CLKP CLKP used as SPI3 clock 2138 * 2139 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2140 */ 2141 #define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) 2142 2143 #if defined(SPI4) 2144 /** @brief macro to configure the SPI4 clock source. 2145 * @retval The clock source can be one of the following values: 2146 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock 2147 * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock 2148 * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock 2149 * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock 2150 * @arg RCC_SPI4CLKSOURCE_CSI CSI Clock used as SPI4 clock 2151 * @arg RCC_SPI4CLKSOURCE_HSE HSE Clock used as SPI4 clock 2152 */ 2153 #define __HAL_RCC_SPI4_CONFIG(__SPI4CLKSource__) \ 2154 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL, (uint32_t)(__SPI4CLKSource__)) 2155 2156 /** @brief macro to get the SPI4 clock source. 2157 * @retval The clock source can be one of the following values: 2158 * @arg RCC_SPI4CLKSOURCE_PCLK2 PCLK2 used as SPI4 clock 2159 * @arg RCC_SPI4CLKSOURCE_PLL2Q PLL2Q used as SPI4 clock 2160 * @arg RCC_SPI4CLKSOURCE_PLL3Q PLL3Q used as SPI4 clock 2161 * @arg RCC_SPI4CLKSOURCE_HSI HSI used as SPI4 clock 2162 * @arg RCC_SPI4CLKSOURCE_CSI CSI used as SPI4 clock 2163 * @arg RCC_SPI4CLKSOURCE_HSE HSE used as SPI4 clock 2164 */ 2165 #define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI4SEL))) 2166 #endif /* SPI4 */ 2167 2168 #if defined(SPI5) 2169 /** @brief macro to configure the SPI5 clock source. 2170 * @retval The clock source can be one of the following values: 2171 * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock 2172 * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock 2173 * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock 2174 * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock 2175 * @arg RCC_SPI5CLKSOURCE_CSI CSI Clock used as SPI5 clock 2176 * @arg RCC_SPI5CLKSOURCE_HSE HSE Clock used as SPI5 clock 2177 */ 2178 #define __HAL_RCC_SPI5_CONFIG(__SPI5CLKSource__) \ 2179 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL, (uint32_t)(__SPI5CLKSource__)) 2180 2181 /** @brief macro to get the SPI5 clock source. 2182 * @retval The clock source can be one of the following values: 2183 * @arg RCC_SPI5CLKSOURCE_PCLK3 PCLK3 used as SPI5 clock 2184 * @arg RCC_SPI5CLKSOURCE_PLL2Q PLL2Q used as SPI5 clock 2185 * @arg RCC_SPI5CLKSOURCE_PLL3Q PLL3Q used as SPI5 clock 2186 * @arg RCC_SPI5CLKSOURCE_HSI HSI used as SPI5 clock 2187 * @arg RCC_SPI5CLKSOURCE_CSI CSI used as SPI5 clock 2188 * @arg RCC_SPI5CLKSOURCE_HSE HSE used as SPI5 clock 2189 */ 2190 #define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI5SEL))) 2191 #endif /* SPI5 */ 2192 2193 #if defined(SPI6) 2194 /** @brief macro to configure the SPI6 clock source. 2195 * @retval The clock source can be one of the following values: 2196 * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock 2197 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock 2198 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock 2199 * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock 2200 * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock 2201 * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock 2202 */ 2203 #define __HAL_RCC_SPI6_CONFIG(__SPI6CLKSource__) \ 2204 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL, (uint32_t)(__SPI6CLKSource__)) 2205 2206 /** @brief macro to get the SPI6 clock source. 2207 * @retval The clock source can be one of the following values: 2208 * @arg RCC_SPI6CLKSOURCE_PCLK2 PCLK2 used as SPI6 clock 2209 * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2Q used as SPI6 clock 2210 * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3Q used as SPI6 clock 2211 * @arg RCC_SPI6CLKSOURCE_HSI HSI used as SPI6 clock 2212 * @arg RCC_SPI6CLKSOURCE_CSI CSI used as SPI6 clock 2213 * @arg RCC_SPI6CLKSOURCE_HSE HSE used as SPI6 clock 2214 */ 2215 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI6SEL))) 2216 #endif /* SPI6 */ 2217 2218 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 2219 * 2220 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 2221 * This parameter can be one of the following values: 2222 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 2223 * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) 2224 * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) 2225 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 2226 * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock 2227 * @retval None 2228 * 2229 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2230 * (**) : For stm32h503xx family line. 2231 */ 2232 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 2233 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 2234 2235 /** @brief Macro to get the I2C1 clock source. 2236 * @retval The clock source can be one of the following values: 2237 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 2238 * @arg @ref RCC_I2C1CLKSOURCE_PLL3R PLL3R selected as I2C1 clock (*) 2239 * @arg @ref RCC_I2C1CLKSOURCE_PLL2R PLL2R selected as I2C1 clock (**) 2240 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 2241 * @arg @ref RCC_I2C1CLKSOURCE_CSI CSI selected as I2C1 clock 2242 * 2243 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2244 * (**) : For stm32h503xx family line. 2245 */ 2246 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C1SEL))) 2247 2248 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 2249 * 2250 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 2251 * This parameter can be one of the following values: 2252 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 2253 * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) 2254 * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) 2255 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2256 * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock 2257 * @retval None 2258 * 2259 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2260 * (**) : For stm32h503xx family line. 2261 */ 2262 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 2263 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 2264 2265 /** @brief Macro to get the I2C2 clock source. 2266 * @retval The clock source can be one of the following values: 2267 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 2268 * @arg @ref RCC_I2C2CLKSOURCE_PLL3R PLL3R selected as I2C2 clock (*) 2269 * @arg @ref RCC_I2C2CLKSOURCE_PLL2R PLL2R selected as I2C2 clock (**) 2270 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 2271 * @arg @ref RCC_I2C2CLKSOURCE_CSI CSI selected as I2C2 clock 2272 * 2273 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2274 * (**) : For stm32h503xx family line. 2275 */ 2276 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C2SEL))) 2277 2278 #if defined(I2C3) 2279 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 2280 * 2281 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 2282 * This parameter can be one of the following values: 2283 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock 2284 * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock 2285 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2286 * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock 2287 * @retval None 2288 */ 2289 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 2290 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 2291 2292 /** @brief Macro to get the I2C3 clock source. 2293 * @retval The clock source can be one of the following values: 2294 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 PCLK3 selected as I2C3 clock 2295 * @arg @ref RCC_I2C3CLKSOURCE_PLL3R PLL3R selected as I2C3 clock 2296 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 2297 * @arg @ref RCC_I2C3CLKSOURCE_CSI CSI selected as I2C3 clock 2298 */ 2299 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C3SEL))) 2300 #endif /* I2C3 */ 2301 2302 #if defined(I2C4) 2303 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 2304 * 2305 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 2306 * This parameter can be one of the following values: 2307 * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock 2308 * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock 2309 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 2310 * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock 2311 * @retval None 2312 */ 2313 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 2314 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 2315 2316 /** @brief Macro to get the I2C4 clock source. 2317 * @retval The clock source can be one of the following values: 2318 * @arg @ref RCC_I2C4CLKSOURCE_PCLK3 PCLK3 selected as I2C4 clock 2319 * @arg @ref RCC_I2C4CLKSOURCE_PLL3R PLL3R selected as I2C4 clock 2320 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 2321 * @arg @ref RCC_I2C4CLKSOURCE_CSI CSI selected as I2C4 clock 2322 */ 2323 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I2C4SEL))) 2324 #endif /* I2C4 */ 2325 2326 /** @brief Macro to configure the I3C1 clock (I3C1CLK). 2327 * 2328 * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. 2329 * This parameter can be one of the following values: 2330 * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 2331 * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) 2332 * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) 2333 * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 2334 * @retval None 2335 * 2336 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2337 * (**) : For stm32h503xx family line. 2338 */ 2339 #define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ 2340 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL, (uint32_t)(__I3C1_CLKSOURCE__)) 2341 2342 /** @brief Macro to get the I3C1 clock source. 2343 * @retval The clock source can be one of the following values: 2344 * @arg @ref RCC_I3C1CLKSOURCE_PCLK1 PCLK1 selected as I3C1 clock 2345 * @arg @ref RCC_I3C1CLKSOURCE_PLL3R PLL3R selected as I3C1 clock (*) 2346 * @arg @ref RCC_I3C1CLKSOURCE_PLL2R PLL2R selected as I3C1 clock (**) 2347 * @arg @ref RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock 2348 * 2349 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2350 * (**) : For stm32h503xx family line. 2351 */ 2352 #define __HAL_RCC_GET_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C1SEL))) 2353 2354 #if defined(I3C2) 2355 /** @brief Macro to configure the I3C2 clock (I3C2CLK). 2356 * 2357 * @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source. 2358 * This parameter can be one of the following values: 2359 * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock 2360 * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock 2361 * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 2362 * @retval None 2363 */ 2364 #define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \ 2365 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL, (uint32_t)(__I3C2_CLKSOURCE__)) 2366 2367 /** @brief Macro to get the I3C2 clock source. 2368 * @retval The clock source can be one of the following values: 2369 * @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock 2370 * @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock 2371 * @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock 2372 */ 2373 #define __HAL_RCC_GET_I3C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL))) 2374 #endif /* I3C2 */ 2375 2376 /** @brief Macro to configure the USART1 clock (USART1CLK). 2377 * 2378 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 2379 * This parameter can be one of the following values: 2380 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2381 * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock 2382 * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) 2383 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2384 * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 2385 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2386 * @retval None 2387 * 2388 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2389 */ 2390 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 2391 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 2392 2393 /** @brief Macro to get the USART1 clock source. 2394 * @retval The clock source can be one of the following values: 2395 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 2396 * @arg @ref RCC_USART1CLKSOURCE_PLL2Q PLL2Q selected as USART1 clock 2397 * @arg @ref RCC_USART1CLKSOURCE_PLL3Q PLL3Q selected as USART1 clock (*) 2398 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 2399 * @arg @ref RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock 2400 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 2401 * 2402 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2403 */ 2404 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) 2405 2406 /** @brief Macro to configure the USART2 clock (USART2CLK). 2407 * 2408 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 2409 * This parameter can be one of the following values: 2410 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock 2411 * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock 2412 * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) 2413 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2414 * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock 2415 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2416 * @retval None 2417 * 2418 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2419 */ 2420 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 2421 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 2422 2423 /** @brief Macro to get the USART2 clock source. 2424 * @retval The clock source can be one of the following values: 2425 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK2 selected as USART2 clock 2426 * @arg @ref RCC_USART2CLKSOURCE_PLL2Q PLL2Q selected as USART2 clock 2427 * @arg @ref RCC_USART2CLKSOURCE_PLL3Q PLL3Q selected as USART2 clock (*) 2428 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 2429 * @arg @ref RCC_USART2CLKSOURCE_CSI CSI selected as USART2 clock 2430 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 2431 * 2432 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2433 */ 2434 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) 2435 2436 /** @brief Macro to configure the USART3 clock (USART3CLK). 2437 * 2438 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 2439 * This parameter can be one of the following values: 2440 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock 2441 * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock 2442 * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) 2443 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2444 * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock 2445 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2446 * @retval None 2447 * 2448 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2449 */ 2450 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 2451 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 2452 2453 /** @brief Macro to get the USART3 clock source. 2454 * @retval The clock source can be one of the following values: 2455 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK2 selected as USART3 clock 2456 * @arg @ref RCC_USART3CLKSOURCE_PLL2Q PLL2Q selected as USART3 clock 2457 * @arg @ref RCC_USART3CLKSOURCE_PLL3Q PLL3Q selected as USART3 clock (*) 2458 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 2459 * @arg @ref RCC_USART3CLKSOURCE_CSI CSI selected as USART3 clock 2460 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 2461 * 2462 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2463 */ 2464 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) 2465 2466 #if defined(UART4) 2467 /** @brief Macro to configure the UART4 clock (UART4CLK). 2468 * 2469 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 2470 * This parameter can be one of the following values: 2471 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2472 * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock 2473 * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock 2474 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2475 * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock 2476 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2477 * @retval None 2478 */ 2479 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 2480 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 2481 2482 /** @brief Macro to get the UART4 clock source. 2483 * @retval The clock source can be one of the following values: 2484 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 2485 * @arg @ref RCC_UART4CLKSOURCE_PLL2Q PLL2Q Clock selected as UART4 clock 2486 * @arg @ref RCC_UART4CLKSOURCE_PLL3Q PLL3Q Clock selected as UART4 clock 2487 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 2488 * @arg @ref RCC_UART4CLKSOURCE_CSI CSI selected as UART4 clock 2489 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 2490 */ 2491 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) 2492 #endif /* UART4 */ 2493 2494 #if defined(UART5) 2495 /** @brief Macro to configure the UART5 clock (UART5CLK). 2496 * 2497 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 2498 * This parameter can be one of the following values: 2499 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2500 * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock 2501 * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock 2502 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2503 * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock 2504 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2505 * @retval None 2506 */ 2507 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 2508 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 2509 2510 /** @brief Macro to get the UART5 clock source. 2511 * @retval The clock source can be one of the following values: 2512 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 2513 * @arg @ref RCC_UART5CLKSOURCE_PLL2Q PLL2Q Clock selected as UART5 clock 2514 * @arg @ref RCC_UART5CLKSOURCE_PLL3Q PLL3Q Clock selected as UART5 clock 2515 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 2516 * @arg @ref RCC_UART5CLKSOURCE_CSI CSI selected as UART5 clock 2517 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 2518 */ 2519 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) 2520 #endif /* UART5 */ 2521 2522 #if defined(USART6) 2523 /** @brief Macro to configure the USART6 clock (USART6CLK). 2524 * 2525 * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. 2526 * This parameter can be one of the following values: 2527 * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK2 selected as USART6 clock 2528 * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock 2529 * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock 2530 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2531 * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock 2532 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2533 * @retval None 2534 */ 2535 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ 2536 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) 2537 2538 /** @brief Macro to get the USART6 clock source. 2539 * @retval The clock source can be one of the following values: 2540 * @arg @ref RCC_USART6CLKSOURCE_PCLK2 PCLK2 selected as USART6 clock 2541 * @arg @ref RCC_USART6CLKSOURCE_PLL2Q PLL2Q selected as USART6 clock 2542 * @arg @ref RCC_USART6CLKSOURCE_PLL3Q PLL3Q selected as USART6 clock 2543 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 2544 * @arg @ref RCC_USART6CLKSOURCE_CSI CSI selected as USART6 clock 2545 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 2546 */ 2547 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART6SEL))) 2548 #endif /* USART6 */ 2549 2550 #if defined(UART7) 2551 /** @brief Macro to configure the UART7 clock (UART7CLK). 2552 * 2553 * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. 2554 * This parameter can be one of the following values: 2555 * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2556 * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock 2557 * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock 2558 * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2559 * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock 2560 * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2561 * @retval None 2562 */ 2563 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ 2564 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) 2565 2566 /** @brief Macro to get the UART7 clock source. 2567 * @retval The clock source can be one of the following values: 2568 * @arg @ref RCC_UART7CLKSOURCE_PCLK1 PCLK1 selected as UART7 clock 2569 * @arg @ref RCC_UART7CLKSOURCE_PLL2Q PLL2Q selected as UART7 clock 2570 * @arg @ref RCC_UART7CLKSOURCE_PLL3Q PLL3Q selected as UART7 clock 2571 * @arg @ref RCC_UART7CLKSOURCE_HSI HSI selected as UART7 clock 2572 * @arg @ref RCC_UART7CLKSOURCE_CSI CSI selected as UART7 clock 2573 * @arg @ref RCC_UART7CLKSOURCE_LSE LSE selected as UART7 clock 2574 */ 2575 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART7SEL))) 2576 #endif /* UART5 */ 2577 2578 #if defined(UART8) 2579 /** @brief Macro to configure the UART8 clock (UART8CLK). 2580 * 2581 * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. 2582 * This parameter can be one of the following values: 2583 * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2584 * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock 2585 * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock 2586 * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2587 * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock 2588 * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2589 * @retval None 2590 */ 2591 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ 2592 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) 2593 2594 /** @brief Macro to get the UART8 clock source. 2595 * @retval The clock source can be one of the following values: 2596 * @arg @ref RCC_UART8CLKSOURCE_PCLK1 PCLK1 selected as UART8 clock 2597 * @arg @ref RCC_UART8CLKSOURCE_PLL2Q PLL2Q selected as UART8 clock 2598 * @arg @ref RCC_UART8CLKSOURCE_PLL3Q PLL3Q selected as UART8 clock 2599 * @arg @ref RCC_UART8CLKSOURCE_HSI HSI selected as UART8 clock 2600 * @arg @ref RCC_UART8CLKSOURCE_CSI CSI selected as UART8 clock 2601 * @arg @ref RCC_UART8CLKSOURCE_LSE LSE selected as UART8 clock 2602 */ 2603 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART8SEL))) 2604 #endif /* UART8 */ 2605 2606 #if defined(UART9) 2607 /** @brief Macro to configure the UART9 clock (UART9CLK). 2608 * 2609 * @param __UART9_CLKSOURCE__ specifies the UART9 clock source. 2610 * This parameter can be one of the following values: 2611 * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock 2612 * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock 2613 * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock 2614 * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2615 * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock 2616 * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2617 * @retval None 2618 */ 2619 #define __HAL_RCC_UART9_CONFIG(__UART9_CLKSOURCE__) \ 2620 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART9SEL, (uint32_t)(__UART9_CLKSOURCE__)) 2621 2622 /** @brief Macro to get the UART9 clock source. 2623 * @retval The clock source can be one of the following values: 2624 * @arg @ref RCC_UART9CLKSOURCE_PCLK1 PCLK1 selected as UART9 clock 2625 * @arg @ref RCC_UART9CLKSOURCE_PLL2Q PLL2Q selected as UART9 clock 2626 * @arg @ref RCC_UART9CLKSOURCE_PLL3Q PLL3Q selected as UART9 clock 2627 * @arg @ref RCC_UART9CLKSOURCE_HSI HSI selected as UART9 clock 2628 * @arg @ref RCC_UART9CLKSOURCE_CSI CSI selected as UART9 clock 2629 * @arg @ref RCC_UART9CLKSOURCE_LSE LSE selected as UART9 clock 2630 */ 2631 #define __HAL_RCC_GET_UART9_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART9SEL))) 2632 #endif /* UART9 */ 2633 2634 #if defined(USART10) 2635 /** @brief Macro to configure the USART10 clock (USART10CLK). 2636 * 2637 * @param __USART10_CLKSOURCE__ specifies the USART10 clock source. 2638 * This parameter can be one of the following values: 2639 * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock 2640 * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock 2641 * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock 2642 * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2643 * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock 2644 * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2645 * @retval None 2646 */ 2647 #define __HAL_RCC_USART10_CONFIG(__USART10_CLKSOURCE__) \ 2648 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART10SEL, (uint32_t)(__USART10_CLKSOURCE__)) 2649 2650 /** @brief Macro to get the USART10 clock source. 2651 * @retval The clock source can be one of the following values: 2652 * @arg @ref RCC_USART10CLKSOURCE_PCLK1 PCLK1 selected as USART10 clock 2653 * @arg @ref RCC_USART10CLKSOURCE_PLL2Q PLL2Q selected as USART10 clock 2654 * @arg @ref RCC_USART10CLKSOURCE_PLL3Q PLL3Q selected as USART10 clock 2655 * @arg @ref RCC_USART10CLKSOURCE_HSI HSI selected as USART10 clock 2656 * @arg @ref RCC_USART10CLKSOURCE_CSI CSI selected as USART10 clock 2657 * @arg @ref RCC_USART10CLKSOURCE_LSE LSE selected as USART10 clock 2658 */ 2659 #define __HAL_RCC_GET_USART10_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART10SEL))) 2660 #endif /* USART10 */ 2661 2662 #if defined(USART11) 2663 /** @brief Macro to configure the USART11 clock (USART11CLK). 2664 * 2665 * @param __USART11_CLKSOURCE__ specifies the USART11 clock source. 2666 * This parameter can be one of the following values: 2667 * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock 2668 * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock 2669 * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock 2670 * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock 2671 * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock 2672 * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock 2673 * @retval None 2674 */ 2675 #define __HAL_RCC_USART11_CONFIG(__USART11_CLKSOURCE__) \ 2676 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART11SEL, (uint32_t)(__USART11_CLKSOURCE__)) 2677 2678 /** @brief Macro to get the USART11 clock source. 2679 * @retval The clock source can be one of the following values: 2680 * @arg @ref RCC_USART11CLKSOURCE_PCLK1 PCLK1 selected as USART11 clock 2681 * @arg @ref RCC_USART11CLKSOURCE_PLL2Q PLL2Q selected as USART11 clock 2682 * @arg @ref RCC_USART11CLKSOURCE_PLL3Q PLL3Q selected as USART11 clock 2683 * @arg @ref RCC_USART11CLKSOURCE_HSI HSI selected as USART11 clock 2684 * @arg @ref RCC_USART11CLKSOURCE_CSI CSI selected as USART11 clock 2685 * @arg @ref RCC_USART11CLKSOURCE_LSE LSE selected as USART11 clock 2686 */ 2687 #define __HAL_RCC_GET_USART11_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART11SEL))) 2688 #endif /* USART11 */ 2689 2690 #if defined(UART12) 2691 /** @brief Macro to configure the UART12 clock (UART12CLK). 2692 * 2693 * @param __UART12_CLKSOURCE__ specifies the UART12 clock source. 2694 * This parameter can be one of the following values: 2695 * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock 2696 * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock 2697 * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock 2698 * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock 2699 * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock 2700 * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock 2701 * @retval None 2702 */ 2703 #define __HAL_RCC_UART12_CONFIG(__UART12_CLKSOURCE__) \ 2704 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_UART12SEL, (uint32_t)(__UART12_CLKSOURCE__)) 2705 2706 /** @brief Macro to get the UART12 clock source. 2707 * @retval The clock source can be one of the following values: 2708 * @arg @ref RCC_UART12CLKSOURCE_PCLK1 PCLK1 selected as UART12 clock 2709 * @arg @ref RCC_UART12CLKSOURCE_PLL2Q PLL2Q selected as UART12 clock 2710 * @arg @ref RCC_UART12CLKSOURCE_PLL3Q PLL3Q selected as UART12 clock 2711 * @arg @ref RCC_UART12CLKSOURCE_HSI HSI selected as UART12 clock 2712 * @arg @ref RCC_UART12CLKSOURCE_CSI CSI selected as UART12 clock 2713 * @arg @ref RCC_UART12CLKSOURCE_LSE LSE selected as UART12 clock 2714 */ 2715 #define __HAL_RCC_GET_UART12_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_UART12SEL))) 2716 #endif /* UART12 */ 2717 2718 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 2719 * 2720 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 2721 * This parameter can be one of the following values: 2722 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 2723 * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock 2724 * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) 2725 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 2726 * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock 2727 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 2728 * 2729 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2730 * @retval None 2731 */ 2732 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 2733 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 2734 2735 /** @brief Macro to get the LPUART1 clock source. 2736 * @retval The clock source can be one of the following values: 2737 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 2738 * @arg @ref RCC_LPUART1CLKSOURCE_PLL2Q PLL2Q selected as LPUART1 clock 2739 * @arg @ref RCC_LPUART1CLKSOURCE_PLL3Q PLL3Q selected as LPUART1 clock (*) 2740 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 2741 * @arg @ref RCC_LPUART1CLKSOURCE_CSI CSI selected as LPUART1 clock 2742 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 2743 * 2744 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2745 */ 2746 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) 2747 2748 #if defined(OCTOSPI1) 2749 /** @brief Macro to configure the OctoSPI clock. 2750 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 2751 * This parameter can be one of the following values: 2752 * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock 2753 * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock 2754 * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock 2755 * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock 2756 * @retval None 2757 */ 2758 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 2759 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) 2760 2761 /** @brief Macro to get the OctoSPI clock source. 2762 * @retval The clock source can be one of the following values: 2763 * @arg @ref RCC_OSPICLKSOURCE_HCLK HCLK selected as OctoSPI clock 2764 * @arg @ref RCC_OSPICLKSOURCE_PLL1Q PLL1Q divider clock selected as OctoSPI clock 2765 * @arg @ref RCC_OSPICLKSOURCE_PLL2R PLL2R divider clock selected as OctoSPI clock 2766 * @arg @ref RCC_OSPICLKSOURCE_CLKP CLKP selected as OctoSPI clock 2767 */ 2768 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL))) 2769 #endif /* OCTOSPI1 */ 2770 2771 #if defined(SDMMC1) 2772 /** @brief Macro to configure the SDMMC1 clock (SDMMCCLK). 2773 * 2774 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. 2775 * This parameter can be one of the following values: 2776 * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock 2777 * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock 2778 */ 2779 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 2780 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) 2781 2782 /** @brief macro to get the SDMMC1 clock source. 2783 * @retval The clock source can be one of the following values: 2784 * @arg RCC_SDMMC1CLKSOURCE_PLL1Q PLL1Q selected as SDMMC1 clock 2785 * @arg RCC_SDMMC1CLKSOURCE_PLL2R PLL2R selected as SDMMC1 clock 2786 */ 2787 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC1SEL))) 2788 #endif /* SDMMC1 */ 2789 2790 #if defined(SDMMC2) 2791 /** @brief Macro to configure the SDMMC2 clock (SDMMCCLK). 2792 * 2793 * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. 2794 * This parameter can be one of the following values: 2795 * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock 2796 * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock 2797 */ 2798 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ 2799 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) 2800 2801 /** @brief macro to get the SDMMC2 clock source. 2802 * @retval The clock source can be one of the following values: 2803 * @arg RCC_SDMMC2CLKSOURCE_PLL1Q PLL1Q selected as SDMMC2 clock 2804 * @arg RCC_SDMMC2CLKSOURCE_PLL2R PLL2R selected as SDMMC2 clock 2805 */ 2806 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SDMMC2SEL))) 2807 #endif /*SDMMC2*/ 2808 2809 /** @brief macro to configure the RNG clock (RNGCLK). 2810 * 2811 * @param __RNGCLKSource__: specifies the RNG clock source. 2812 * This parameter can be one of the following values: 2813 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2814 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 2815 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2816 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2817 */ 2818 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ 2819 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, (uint32_t)(__RNGCLKSource__)) 2820 2821 /** @brief macro to get the RNG clock source. 2822 * @retval The clock source can be one of the following values: 2823 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 2824 * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock 2825 * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock 2826 * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock 2827 */ 2828 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_RNGSEL))) 2829 2830 #if defined(SAI1) 2831 /** 2832 * @brief Macro to configure the SAI1 clock source. 2833 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. 2834 * This parameter can be one of the following values: 2835 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock 2836 * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2Pselected as SAI1 clock 2837 * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock 2838 * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock 2839 * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock 2840 * @retval None 2841 */ 2842 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 2843 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) 2844 2845 /** @brief Macro to get the SAI1 clock source. 2846 * @retval The clock source can be one of the following values: 2847 * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q PLL1Q selected as SAI1 clock 2848 * @arg @ref RCC_SAI1CLKSOURCE_PLL2P PLL2P selected as SAI1 clock 2849 * @arg @ref RCC_SAI1CLKSOURCE_PLL3P PLL3P selected as SAI1 clock 2850 * @arg @ref RCC_SAI1CLKSOURCE_PIN External clock selected as SAI1 clock 2851 * @arg @ref RCC_SAI1CLKSOURCE_CLKP CLKP selected as SAI1 clock 2852 */ 2853 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI1SEL))) 2854 #endif /* SAI1 */ 2855 2856 #if defined(SAI2) 2857 /** 2858 * @brief Macro to configure the SAI2 clock source. 2859 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. 2860 * This parameter can be one of the following values: 2861 * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock 2862 * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock 2863 * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock 2864 * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock 2865 * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock 2866 * @retval None 2867 */ 2868 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 2869 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) 2870 2871 /** @brief Macro to get the SAI2 clock source. 2872 * @retval The clock source can be one of the following values: 2873 * @arg @ref RCC_SAI2CLKSOURCE_PLL1Q PLL1Q selected as SAI2 clock 2874 * @arg @ref RCC_SAI2CLKSOURCE_PLL2P PLL2P selected as SAI2 clock 2875 * @arg @ref RCC_SAI2CLKSOURCE_PLL3P PLL3P selected as SAI2 clock 2876 * @arg @ref RCC_SAI2CLKSOURCE_PIN External clock selected as SAI2 clock 2877 * @arg @ref RCC_SAI2CLKSOURCE_CLKP CLKP selected as SAI2 clock 2878 */ 2879 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_SAI2SEL))) 2880 #endif /* SAI2 */ 2881 2882 /** @brief Macro to configure the CLKP : Oscillator clock for peripheral 2883 * @param __CLKPSource__ specifies Oscillator clock for peripheral 2884 * This parameter can be one of the following values: 2885 * @arg RCC_CLKPSOURCE_HSI HSI oscillator selected as clock for peripheral 2886 * @arg RCC_CLKPSOURCE_CSI CSI oscillator selected as clock for peripheral 2887 * @arg RCC_CLKPSOURCE_HSE HSE oscillator selected as clock for peripheral 2888 */ 2889 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ 2890 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL, (uint32_t)(__CLKPSource__)) 2891 2892 /** @brief Macro to get the oscillator clock for peripheral clock source. 2893 * @retval The clock source can be one of the following values: 2894 * @arg RCC_CLKPSOURCE_HSI HSI selected Oscillator clock for peripheral 2895 * @arg RCC_CLKPSOURCE_CSI CSI selected Oscillator clock for peripheral 2896 * @arg RCC_CLKPSOURCE_HSE HSE selected Oscillator clock for peripheral 2897 */ 2898 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL))) 2899 2900 #if defined(CEC) 2901 /** @brief Macro to configure the CEC clock (CECCLK) 2902 * @param __CECCLKSource__ specifies the CEC clock source. 2903 * This parameter can be one of the following values: 2904 * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 2905 * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock 2906 * @arg RCC_CECCLKSOURCE_CSI_DIV122 CSI Divided by 122 selected as CEC clock 2907 */ 2908 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 2909 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CECSEL, (uint32_t)(__CECCLKSource__)) 2910 2911 /** @brief Macro to get the CEC clock source. 2912 * @retval The clock source can be one of the following values: 2913 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 2914 * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock 2915 * @arg RCC_CECCLKSOURCE_CSI_DIV122: CSI Divided by 122 selected as CEC clock 2916 */ 2917 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CECSEL))) 2918 #endif /* CEC */ 2919 2920 /** @brief Macro to configure the USB clock (USBCLK). 2921 * @param __USBCLKSource__ specifies the USB clock source. 2922 * This parameter can be one of the following values: 2923 * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock 2924 * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) 2925 * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) 2926 * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 2927 * 2928 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2929 * (**) : For stm32h503xx family line. 2930 */ 2931 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ 2932 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, (uint32_t)(__USBCLKSource__)) 2933 2934 /** @brief Macro to get the USB clock source. 2935 * @retval The clock source can be one of the following values: 2936 * @arg RCC_USBCLKSOURCE_PLL1Q PLL1Q selected as USB clock 2937 * @arg RCC_USBCLKSOURCE_PLL3Q PLL3Q selected as USB clock (*) 2938 * @arg RCC_USBCLKSOURCE_PLL2Q PLL2Q selected as USB clock (**) 2939 * @arg RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 2940 * 2941 * (*) : For stm32h56xxx and stm32h57xxx family lines. 2942 * (**) : For stm32h503xx family line. 2943 */ 2944 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_USBSEL))) 2945 2946 /** @brief Macro to configure the Timers clocks prescalers 2947 * @param __PRESC__ specifies the Timers clocks prescalers selection 2948 * This parameter can be one of the following values: 2949 * @arg RCC_TIMPRES_DEACTIVATED: The Timers kernels clocks prescaler is 2950 * equal to rcc_hclk1 if PPREx is corresponding to division by 1 or 2, 2951 * else it is equal to 2 x Frcc_pclkx (default after reset) 2952 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 2953 * equal to rcc_hclk1 if PPREx is corresponding to division by 1, 2 or 4, 2954 * else it is equal to 4 x Frcc_pclkx 2955 */ 2956 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR1 &= ~(RCC_CFGR1_TIMPRE);\ 2957 RCC->CFGR1 |= (__PRESC__); \ 2958 }while(0) 2959 2960 #if defined(CRS) 2961 2962 /** 2963 * @brief Enable the specified CRS interrupts. 2964 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 2965 * This parameter can be any combination of the following values: 2966 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2967 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2968 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2969 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2970 * @retval None 2971 */ 2972 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 2973 2974 /** 2975 * @brief Disable the specified CRS interrupts. 2976 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 2977 * This parameter can be any combination of the following values: 2978 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2979 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2980 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2981 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2982 * @retval None 2983 */ 2984 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 2985 2986 /** @brief Check whether the CRS interrupt has occurred or not. 2987 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 2988 * This parameter can be one of the following values: 2989 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2990 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2991 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2992 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2993 * @retval The new state of __INTERRUPT__ (0 or 1). 2994 */ 2995 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1U : 0U) 2996 2997 /** @brief Clear the CRS interrupt pending bits 2998 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2999 * This parameter can be any combination of the following values: 3000 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 3001 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 3002 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 3003 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 3004 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 3005 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 3006 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 3007 */ 3008 /* CRS IT Error Mask */ 3009 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF |\ 3010 RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 3011 3012 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 3013 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 3014 { \ 3015 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 3016 ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 3017 } \ 3018 else \ 3019 { \ 3020 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 3021 } \ 3022 } while(0) 3023 3024 /** 3025 * @brief Check whether the specified CRS flag is set or not. 3026 * @param __FLAG__ specifies the flag to check. 3027 * This parameter can be one of the following values: 3028 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3029 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3030 * @arg @ref RCC_CRS_FLAG_ERR Error 3031 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3032 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3033 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3034 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3035 * @retval The new state of _FLAG_ (TRUE or FALSE). 3036 */ 3037 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 3038 3039 /** 3040 * @brief Clear the CRS specified FLAG. 3041 * @param __FLAG__ specifies the flag to clear. 3042 * This parameter can be any combination of the following values: 3043 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 3044 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 3045 * @arg @ref RCC_CRS_FLAG_ERR Error 3046 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 3047 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 3048 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 3049 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 3050 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS 3051 and consequently RCC_CRS_FLAG_ERR 3052 * @retval None 3053 */ 3054 3055 /* CRS Flag Error Mask */ 3056 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF |\ 3057 RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 3058 3059 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 3060 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 3061 { \ 3062 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 3063 ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 3064 } \ 3065 else \ 3066 { \ 3067 WRITE_REG(CRS->ICR, (__FLAG__)); \ 3068 } \ 3069 } while(0) 3070 3071 /** 3072 * @} 3073 */ 3074 3075 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 3076 * @{ 3077 */ 3078 /** 3079 * @brief Enable the oscillator clock for frequency error counter. 3080 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 3081 * @retval None 3082 */ 3083 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 3084 3085 /** 3086 * @brief Disable the oscillator clock for frequency error counter. 3087 * @retval None 3088 */ 3089 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 3090 3091 /** 3092 * @brief Enable the automatic hardware adjustment of TRIM bits. 3093 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 3094 * @retval None 3095 */ 3096 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3097 3098 /** 3099 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 3100 * @retval None 3101 */ 3102 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 3103 3104 /** 3105 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 3106 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 3107 * of the synchronization source after prescaling. It is then decreased by one in order to 3108 * reach the expected synchronization on the zero value. The formula is the following: 3109 * RELOAD = (fTARGET / fSYNC) -1 3110 * @param __FTARGET__ Target frequency (value in Hz) 3111 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 3112 * @retval None 3113 */ 3114 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 3115 3116 3117 /** 3118 * @} 3119 */ 3120 3121 #endif /* CRS */ 3122 3123 /* Private constants ---------------------------------------------------------*/ 3124 /** @addtogroup RCCEx_Private_Constants 3125 * @{ 3126 */ 3127 /* Define used for IS_RCC_* macros below */ 3128 #if defined(SDMMC2) 3129 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3130 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 3131 RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ 3132 RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ 3133 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3134 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ 3135 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 3136 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ 3137 RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 3138 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ 3139 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \ 3140 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 3141 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | \ 3142 RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | \ 3143 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) 3144 #elif defined(RCC_CR_PLL3ON) 3145 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3146 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 3147 RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \ 3148 RCC_PERIPHCLK_USART10 | RCC_PERIPHCLK_USART11 | RCC_PERIPHCLK_UART12 | \ 3149 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3150 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | \ 3151 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 3152 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \ 3153 RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 3154 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \ 3155 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_I3C1 | \ 3156 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ 3157 RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \ 3158 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | \ 3159 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER) 3160 #else 3161 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 3162 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 3163 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | RCC_PERIPHCLK_TIM | \ 3164 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \ 3165 RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | \ 3166 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 3167 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB | \ 3168 RCC_PERIPHCLK_CKPER) 3169 #endif /*FDCAN2 && SDMMC2 */ 3170 /** 3171 * @} 3172 */ 3173 3174 /* Private macros ------------------------------------------------------------*/ 3175 /** @addtogroup RCCEx_Private_Macros 3176 * @{ 3177 */ 3178 3179 #define IS_RCC_PLL2_SOURCE(SOURCE) (((SOURCE) == RCC_PLL2_SOURCE_CSI) || \ 3180 ((SOURCE) == RCC_PLL2_SOURCE_HSI) || \ 3181 ((SOURCE) == RCC_PLL2_SOURCE_HSE)) 3182 3183 #define IS_RCC_PLL2_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3184 #define IS_RCC_PLL2_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3185 #define IS_RCC_PLL2_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3186 #define IS_RCC_PLL2_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3187 #define IS_RCC_PLL2_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3188 3189 #define IS_RCC_PLL2_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 3190 3191 #define IS_RCC_PLL2_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCIRANGE_0) || \ 3192 ((VALUE) == RCC_PLL2_VCIRANGE_1) || \ 3193 ((VALUE) == RCC_PLL2_VCIRANGE_2) || \ 3194 ((VALUE) == RCC_PLL2_VCIRANGE_3)) 3195 3196 #define IS_RCC_PLL2_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL2_VCORANGE_WIDE) || ((VALUE) == RCC_PLL2_VCORANGE_MEDIUM)) 3197 3198 #define IS_RCC_PLL2_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) 3199 3200 #if defined(RCC_CR_PLL3ON) 3201 #define IS_RCC_PLL3_SOURCE(SOURCE) (((SOURCE) == RCC_PLL3_SOURCE_CSI) || \ 3202 ((SOURCE) == RCC_PLL3_SOURCE_HSI) || \ 3203 ((SOURCE) == RCC_PLL3_SOURCE_HSE)) 3204 3205 #define IS_RCC_PLL3_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCIRANGE_0) || \ 3206 ((VALUE) == RCC_PLL3_VCIRANGE_1) || \ 3207 ((VALUE) == RCC_PLL3_VCIRANGE_2) || \ 3208 ((VALUE) == RCC_PLL3_VCIRANGE_3)) 3209 3210 #define IS_RCC_PLL3_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 3211 #define IS_RCC_PLL3_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3212 #define IS_RCC_PLL3_DIVP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3213 #define IS_RCC_PLL3_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3214 #define IS_RCC_PLL3_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3215 3216 #define IS_RCC_PLL3_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 3217 3218 #define IS_RCC_PLL3_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL3_VCORANGE_WIDE) || ((VALUE) == RCC_PLL3_VCORANGE_MEDIUM)) 3219 3220 #define IS_RCC_PLL3_CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) 3221 3222 #endif /* RCC_CR_PLL3ON */ 3223 3224 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 3225 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 3226 3227 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ 3228 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ 3229 ((SOURCE) == RCC_CLKPSOURCE_HSE)) 3230 3231 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != ((uint64_t)0x00)) && \ 3232 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == ((uint64_t)0x00))) 3233 #if defined(RCC_CR_PLL3ON) 3234 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 3235 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 3236 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ 3237 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL3Q) || \ 3238 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 3239 ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ 3240 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 3241 3242 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 3243 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 3244 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ 3245 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL3Q) || \ 3246 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 3247 ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ 3248 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 3249 3250 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 3251 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 3252 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ 3253 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL3Q) || \ 3254 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ 3255 ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ 3256 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) 3257 3258 #else 3259 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 3260 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 3261 ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ 3262 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ 3263 ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ 3264 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) 3265 3266 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 3267 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 3268 ((__SOURCE__) == RCC_USART2CLKSOURCE_PLL2Q) || \ 3269 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ 3270 ((__SOURCE__) == RCC_USART2CLKSOURCE_CSI) || \ 3271 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) 3272 3273 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 3274 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 3275 ((__SOURCE__) == RCC_USART3CLKSOURCE_PLL2Q) || \ 3276 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ 3277 ((__SOURCE__) == RCC_USART3CLKSOURCE_CSI) || \ 3278 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) 3279 3280 #endif /* RCC_CR_PLL3ON */ 3281 3282 #if defined(UART4) 3283 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 3284 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 3285 ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL2Q) || \ 3286 ((__SOURCE__) == RCC_UART4CLKSOURCE_PLL3Q) || \ 3287 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \ 3288 ((__SOURCE__) == RCC_UART4CLKSOURCE_CSI) || \ 3289 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)) 3290 #endif /* UART4 */ 3291 3292 #if defined(UART5) 3293 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 3294 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 3295 ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL2Q) || \ 3296 ((__SOURCE__) == RCC_UART5CLKSOURCE_PLL3Q) || \ 3297 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ 3298 ((__SOURCE__) == RCC_UART5CLKSOURCE_CSI) || \ 3299 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) 3300 #endif /* UART5 */ 3301 3302 #if defined(USART6) 3303 #define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ 3304 (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ 3305 ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL2Q) || \ 3306 ((__SOURCE__) == RCC_USART6CLKSOURCE_PLL3Q) || \ 3307 ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ 3308 ((__SOURCE__) == RCC_USART6CLKSOURCE_CSI) || \ 3309 ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) 3310 #endif /* USART6 */ 3311 3312 #if defined(UART7) 3313 #define IS_RCC_UART7CLKSOURCE(__SOURCE__) \ 3314 (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \ 3315 ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL2Q) || \ 3316 ((__SOURCE__) == RCC_UART7CLKSOURCE_PLL3Q) || \ 3317 ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI) || \ 3318 ((__SOURCE__) == RCC_UART7CLKSOURCE_CSI) || \ 3319 ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE)) 3320 #endif /* UART7 */ 3321 3322 #if defined(UART8) 3323 #define IS_RCC_UART8CLKSOURCE(__SOURCE__) \ 3324 (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \ 3325 ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL2Q) || \ 3326 ((__SOURCE__) == RCC_UART8CLKSOURCE_PLL3Q) || \ 3327 ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI) || \ 3328 ((__SOURCE__) == RCC_UART8CLKSOURCE_CSI) || \ 3329 ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE)) 3330 #endif /* UART8 */ 3331 3332 #if defined(UART9) 3333 #define IS_RCC_UART9CLKSOURCE(__SOURCE__) \ 3334 (((__SOURCE__) == RCC_UART9CLKSOURCE_PCLK1) || \ 3335 ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL2Q) || \ 3336 ((__SOURCE__) == RCC_UART9CLKSOURCE_PLL3Q) || \ 3337 ((__SOURCE__) == RCC_UART9CLKSOURCE_HSI) || \ 3338 ((__SOURCE__) == RCC_UART9CLKSOURCE_CSI) || \ 3339 ((__SOURCE__) == RCC_UART9CLKSOURCE_LSE)) 3340 #endif /* UART9 */ 3341 3342 #if defined(USART10) 3343 #define IS_RCC_USART10CLKSOURCE(__SOURCE__) \ 3344 (((__SOURCE__) == RCC_USART10CLKSOURCE_PCLK1) || \ 3345 ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL2Q) || \ 3346 ((__SOURCE__) == RCC_USART10CLKSOURCE_PLL3Q) || \ 3347 ((__SOURCE__) == RCC_USART10CLKSOURCE_HSI) || \ 3348 ((__SOURCE__) == RCC_USART10CLKSOURCE_CSI) || \ 3349 ((__SOURCE__) == RCC_USART10CLKSOURCE_LSE)) 3350 #endif /* USART10 */ 3351 3352 #if defined(USART11) 3353 #define IS_RCC_USART11CLKSOURCE(__SOURCE__) \ 3354 (((__SOURCE__) == RCC_USART11CLKSOURCE_PCLK1) || \ 3355 ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL2Q) || \ 3356 ((__SOURCE__) == RCC_USART11CLKSOURCE_PLL3Q) || \ 3357 ((__SOURCE__) == RCC_USART11CLKSOURCE_HSI) || \ 3358 ((__SOURCE__) == RCC_USART11CLKSOURCE_CSI) || \ 3359 ((__SOURCE__) == RCC_USART11CLKSOURCE_LSE)) 3360 #endif /* USART11 */ 3361 3362 #if defined(UART12) 3363 #define IS_RCC_UART12CLKSOURCE(__SOURCE__) \ 3364 (((__SOURCE__) == RCC_UART12CLKSOURCE_PCLK1) || \ 3365 ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL2Q) || \ 3366 ((__SOURCE__) == RCC_UART12CLKSOURCE_PLL3Q) || \ 3367 ((__SOURCE__) == RCC_UART12CLKSOURCE_HSI) || \ 3368 ((__SOURCE__) == RCC_UART12CLKSOURCE_CSI) || \ 3369 ((__SOURCE__) == RCC_UART12CLKSOURCE_LSE)) 3370 #endif /* UART12 */ 3371 3372 #if defined(RCC_CR_PLL3ON) 3373 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 3374 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ 3375 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ 3376 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL3Q) || \ 3377 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 3378 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 3379 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) 3380 3381 #else 3382 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 3383 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ 3384 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ 3385 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ 3386 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 3387 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI)) 3388 3389 #endif /* RCC_CR_PLL3ON */ 3390 3391 #if defined(RCC_CR_PLL3ON) 3392 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 3393 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 3394 ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL3R) || \ 3395 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 3396 ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) 3397 3398 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 3399 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 3400 ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL3R) || \ 3401 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ 3402 ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) 3403 3404 #else 3405 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 3406 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 3407 ((__SOURCE__) == RCC_I2C1CLKSOURCE_PLL2R) || \ 3408 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 3409 ((__SOURCE__) == RCC_I2C1CLKSOURCE_CSI)) 3410 3411 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 3412 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 3413 ((__SOURCE__) == RCC_I2C2CLKSOURCE_PLL2R) || \ 3414 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI) || \ 3415 ((__SOURCE__) == RCC_I2C2CLKSOURCE_CSI)) 3416 3417 #endif /* RCC_CR_PLL3ON */ 3418 3419 3420 #if defined(I2C3) 3421 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 3422 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \ 3423 ((__SOURCE__) == RCC_I2C3CLKSOURCE_PLL3R) || \ 3424 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \ 3425 ((__SOURCE__) == RCC_I2C3CLKSOURCE_CSI)) 3426 #endif /* I2C3 */ 3427 3428 #if defined(I2C4) 3429 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 3430 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK3) || \ 3431 ((__SOURCE__) == RCC_I2C4CLKSOURCE_PLL3R) || \ 3432 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI ) || \ 3433 ((__SOURCE__) == RCC_I2C4CLKSOURCE_CSI)) 3434 #endif /* I2C4 */ 3435 3436 #if defined(RCC_CR_PLL3ON) 3437 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 3438 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 3439 ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL3R) || \ 3440 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) 3441 3442 #else 3443 #define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ 3444 (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ 3445 ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL2R) || \ 3446 ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI)) 3447 3448 #endif /* RCC_CR_PLL3ON */ 3449 3450 #if defined(I3C2) 3451 #define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \ 3452 (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \ 3453 ((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \ 3454 ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI)) 3455 #endif /* I3C2 */ 3456 3457 #if defined(SAI1) 3458 #define IS_RCC_SAI1CLK(__SOURCE__) \ 3459 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q)|| \ 3460 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2P)|| \ 3461 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3P)|| \ 3462 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 3463 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP)) 3464 3465 #endif /* SAI1 */ 3466 3467 #if defined(SAI2) 3468 #define IS_RCC_SAI2CLK(__SOURCE__) \ 3469 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1Q)|| \ 3470 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2P)|| \ 3471 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3P)|| \ 3472 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 3473 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP)) 3474 #endif /* SAI2 */ 3475 3476 #if defined(RCC_CR_PLL3ON) 3477 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 3478 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ 3479 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ 3480 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL3R) || \ 3481 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 3482 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3483 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) 3484 3485 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 3486 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 3487 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ 3488 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL3R) || \ 3489 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ 3490 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 3491 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) 3492 3493 #else 3494 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 3495 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK3) || \ 3496 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ 3497 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ 3498 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3499 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) 3500 3501 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 3502 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 3503 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PLL2P) || \ 3504 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE) || \ 3505 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 3506 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP)) 3507 3508 #endif /* RCC_CR_PLL3ON */ 3509 3510 #if defined(LPTIM3) 3511 #define IS_RCC_LPTIM3CLK(__SOURCE__) \ 3512 (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK3) || \ 3513 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL2P) || \ 3514 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PLL3R) || \ 3515 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE) || \ 3516 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ 3517 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_CLKP)) 3518 3519 #endif /* LPTIM3 */ 3520 3521 #if defined(LPTIM4) 3522 #define IS_RCC_LPTIM4CLK(__SOURCE__) \ 3523 (((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PCLK3) || \ 3524 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL2P) || \ 3525 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PLL3R) || \ 3526 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSE) || \ 3527 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSI) || \ 3528 ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_CLKP)) 3529 3530 #endif /* LPTIM4 */ 3531 3532 #if defined(LPTIM5) 3533 #define IS_RCC_LPTIM5CLK(__SOURCE__) \ 3534 (((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PCLK3) || \ 3535 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL2P) || \ 3536 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PLL3R) || \ 3537 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSE) || \ 3538 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSI) || \ 3539 ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_CLKP)) 3540 #endif /* LPTIM5 */ 3541 3542 #if defined(LPTIM6) 3543 #define IS_RCC_LPTIM6CLK(__SOURCE__) \ 3544 (((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PCLK3) || \ 3545 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL2P) || \ 3546 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_PLL3R) || \ 3547 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSE) || \ 3548 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_LSI) || \ 3549 ((__SOURCE__) == RCC_LPTIM6CLKSOURCE_CLKP)) 3550 #endif /* LPTIM6 */ 3551 3552 #define IS_RCC_FDCANCLK(__SOURCE__) \ 3553 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 3554 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL1Q) || \ 3555 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2Q)) 3556 3557 #if defined(SDMMC1) 3558 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 3559 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL1Q) || \ 3560 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL2R)) 3561 #endif /* SDMMC1 */ 3562 3563 #if defined(SDMMC2) 3564 #define IS_RCC_SDMMC2CLKSOURCE(__SOURCE__) \ 3565 (((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL1Q) || \ 3566 ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_PLL2R)) 3567 #endif /*SDMMC2*/ 3568 3569 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 3570 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 3571 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL1Q) || \ 3572 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \ 3573 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI)) 3574 3575 #define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \ 3576 (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \ 3577 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \ 3578 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2R) || \ 3579 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \ 3580 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \ 3581 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_CSI)) 3582 3583 #define IS_RCC_DACLPCLKSOURCE(__SOURCE__) \ 3584 (((__SOURCE__) == RCC_DACLPCLKSOURCE_LSI) || \ 3585 ((__SOURCE__) == RCC_DACLPCLKSOURCE_LSE)) 3586 3587 #if defined(OCTOSPI1) 3588 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 3589 (((__SOURCE__) == RCC_OSPICLKSOURCE_HCLK) || \ 3590 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1Q) || \ 3591 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2R) || \ 3592 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) 3593 #endif /* OCTOSPI1 */ 3594 3595 #if defined(RCC_CR_PLL3ON) 3596 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 3597 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ 3598 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ 3599 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3P) || \ 3600 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ 3601 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) 3602 3603 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ 3604 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ 3605 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ 3606 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3P) || \ 3607 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ 3608 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) 3609 3610 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ 3611 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ 3612 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ 3613 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3P) || \ 3614 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ 3615 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) 3616 #else 3617 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 3618 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ 3619 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ 3620 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ 3621 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) 3622 3623 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ 3624 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL1Q) || \ 3625 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2P) || \ 3626 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN) || \ 3627 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)) 3628 3629 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ 3630 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL1Q) || \ 3631 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2P) || \ 3632 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN) || \ 3633 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)) 3634 3635 #endif /* RCC_CR_PLL3ON */ 3636 3637 #if defined(SPI4) 3638 #define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \ 3639 (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \ 3640 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2Q) || \ 3641 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3Q) || \ 3642 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ 3643 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ 3644 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) 3645 #endif /* SPI4 */ 3646 3647 #if defined(SPI5) 3648 #define IS_RCC_SPI5CLKSOURCE(__SOURCE__) \ 3649 (((__SOURCE__) == RCC_SPI5CLKSOURCE_PCLK3) || \ 3650 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2Q) || \ 3651 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3Q) || \ 3652 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ 3653 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ 3654 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) 3655 #endif /* SPI5 */ 3656 3657 #if defined(SPI6) 3658 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ 3659 (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK2) || \ 3660 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2Q) || \ 3661 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3Q) || \ 3662 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 3663 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 3664 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) 3665 #endif /* SPI6 */ 3666 3667 #if defined(RCC_CR_PLL3ON) 3668 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 3669 (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ 3670 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL3Q) || \ 3671 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 3672 #else 3673 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 3674 (((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \ 3675 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL2Q) || \ 3676 ((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)) 3677 #endif /* RCC_CR_PLL3ON */ 3678 3679 #if defined(CEC) 3680 #define IS_RCC_CECCLKSOURCE(__SOURCE__) \ 3681 (((__SOURCE__) == RCC_CECCLKSOURCE_LSE) || \ 3682 ((__SOURCE__) == RCC_CECCLKSOURCE_LSI) || \ 3683 ((__SOURCE__) == RCC_CECCLKSOURCE_CSI_DIV122)) 3684 #endif /*CEC*/ 3685 3686 #define IS_RCC_TIMPRES(VALUE) \ 3687 (((VALUE) == RCC_TIMPRES_DEACTIVATED) || \ 3688 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 3689 3690 #if defined(CRS) 3691 3692 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 3693 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 3694 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 3695 3696 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 3697 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 3698 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 3699 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 3700 3701 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 3702 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 3703 3704 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 3705 3706 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 3707 3708 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 3709 3710 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 3711 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 3712 3713 #endif /* CRS */ 3714 3715 /** 3716 * @} 3717 */ 3718 3719 /* Exported functions --------------------------------------------------------*/ 3720 /** @addtogroup RCCEx_Exported_Functions 3721 * @{ 3722 */ 3723 3724 /** @addtogroup RCCEx_Exported_Functions_Group1 3725 * @{ 3726 */ 3727 3728 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 3729 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 3730 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 3731 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks); 3732 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks); 3733 #if defined(RCC_CR_PLL3ON) 3734 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks); 3735 #endif /* RCC_CR_PLL3ON */ 3736 /** 3737 * @} 3738 */ 3739 3740 /** @addtogroup RCCEx_Exported_Functions_Group2 3741 * @{ 3742 */ 3743 3744 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init); 3745 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 3746 #if defined(RCC_CR_PLL3ON) 3747 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init); 3748 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); 3749 #endif /* RCC_CR_PLL3ON */ 3750 3751 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 3752 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 3753 void HAL_RCCEx_EnableLSECSS(void); 3754 void HAL_RCCEx_DisableLSECSS(void); 3755 void HAL_RCCEx_LSECSS_IRQHandler(void); 3756 void HAL_RCCEx_LSECSS_Callback(void); 3757 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 3758 void HAL_RCCEx_DisableLSCO(void); 3759 /** 3760 * @} 3761 */ 3762 3763 #if defined(CRS) 3764 3765 /** @addtogroup RCCEx_Exported_Functions_Group3 3766 * @{ 3767 */ 3768 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 3769 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 3770 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 3771 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 3772 void HAL_RCCEx_CRS_IRQHandler(void); 3773 void HAL_RCCEx_CRS_SyncOkCallback(void); 3774 void HAL_RCCEx_CRS_SyncWarnCallback(void); 3775 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 3776 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 3777 /** 3778 * @} 3779 */ 3780 3781 #endif /* CRS */ 3782 3783 /** 3784 * @} 3785 */ 3786 3787 /** 3788 * @} 3789 */ 3790 3791 /** 3792 * @} 3793 */ 3794 3795 #ifdef __cplusplus 3796 } 3797 #endif 3798 3799 #endif /* __STM32H5xx_HAL_RCC_EX_H */ 3800
