1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_RCC_H 22 #define STM32WBxx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 #include "stm32wbxx_ll_rcc.h" 31 #include "stm32wbxx_ll_bus.h" 32 33 34 /** @addtogroup STM32WBxx_HAL_Driver 35 * @{ 36 */ 37 38 /** @addtogroup RCC 39 * @{ 40 */ 41 42 /* Private constants ---------------------------------------------------------*/ 43 /** @addtogroup RCC_Private_Constants 44 * @{ 45 */ 46 /* Defines used for Flags */ 47 #define CR_REG_INDEX 1U 48 #define BDCR_REG_INDEX 2U 49 #define CSR_REG_INDEX 3U 50 #define CRRCR_REG_INDEX 4U 51 52 #define RCC_FLAG_MASK 0x1FU 53 54 /* Defines Oscillator Masks */ 55 #if defined(RCC_HSI48_SUPPORT) 56 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI | \ 57 RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 58 #else 59 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ 60 RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 61 #endif 62 63 /** @defgroup RCC_Reset_Flag Reset Flag 64 * @{ 65 */ 66 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 67 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 68 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 69 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 70 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 71 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 72 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 73 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 74 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 75 RCC_RESET_FLAG_LPWR) 76 /** 77 * @} 78 */ 79 80 /** 81 * @} 82 */ 83 84 /* Private macros ------------------------------------------------------------*/ 85 /** @addtogroup RCC_Private_Macros 86 * @{ 87 */ 88 89 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 90 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 91 92 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON)) 93 94 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 95 ((__LSE__) == RCC_LSE_BYPASS)) 96 97 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 98 99 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) 100 101 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 102 103 #define IS_RCC_LSI2_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)15U) 104 105 106 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 107 108 109 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) 110 111 #if defined(RCC_HSI48_SUPPORT) 112 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 113 #endif 114 115 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 116 ((__PLL__) == RCC_PLL_ON)) 117 118 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 119 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 120 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 121 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 122 123 #define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || \ 124 ((__VALUE__) == RCC_PLLM_DIV2) || \ 125 ((__VALUE__) == RCC_PLLM_DIV3) || \ 126 ((__VALUE__) == RCC_PLLM_DIV4) || \ 127 ((__VALUE__) == RCC_PLLM_DIV5) || \ 128 ((__VALUE__) == RCC_PLLM_DIV6) || \ 129 ((__VALUE__) == RCC_PLLM_DIV7) || \ 130 ((__VALUE__) == RCC_PLLM_DIV8)) 131 132 #define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 133 134 #define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 135 136 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 137 138 #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 139 140 #if defined(SAI1) 141 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \ 142 (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 143 (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ 144 (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK | RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK)) == 0U)) 145 #endif 146 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 147 ((__RANGE__) == RCC_MSIRANGE_1) || \ 148 ((__RANGE__) == RCC_MSIRANGE_2) || \ 149 ((__RANGE__) == RCC_MSIRANGE_3) || \ 150 ((__RANGE__) == RCC_MSIRANGE_4) || \ 151 ((__RANGE__) == RCC_MSIRANGE_5) || \ 152 ((__RANGE__) == RCC_MSIRANGE_6) || \ 153 ((__RANGE__) == RCC_MSIRANGE_7) || \ 154 ((__RANGE__) == RCC_MSIRANGE_8) || \ 155 ((__RANGE__) == RCC_MSIRANGE_9) || \ 156 ((__RANGE__) == RCC_MSIRANGE_10) || \ 157 ((__RANGE__) == RCC_MSIRANGE_11)) 158 159 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \ 160 RCC_CLOCKTYPE_HCLK | \ 161 RCC_CLOCKTYPE_PCLK1 | \ 162 RCC_CLOCKTYPE_PCLK2 | \ 163 RCC_CLOCKTYPE_HCLK2 | \ 164 RCC_CLOCKTYPE_HCLK4))) 165 166 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 167 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 168 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 169 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 170 171 #define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV3) || \ 172 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV5) || ((__HCLK__) == RCC_SYSCLK_DIV6) || \ 173 ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV10) || ((__HCLK__) == RCC_SYSCLK_DIV16) || \ 174 ((__HCLK__) == RCC_SYSCLK_DIV32) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || \ 175 ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512)) 176 177 #define IS_RCC_PCLKx(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 178 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 179 ((__PCLK__) == RCC_HCLK_DIV16)) 180 181 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 182 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 183 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 184 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 185 186 #if defined(RCC_MCO3_SUPPORT) 187 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \ 188 ((__MCOX__) == RCC_MCO2) || \ 189 ((__MCOX__) == RCC_MCO3)) 190 #else 191 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \ 192 ((__MCOX__) == RCC_MCO2)) 193 #endif 194 195 #if defined(RCC_HSI48_SUPPORT) 196 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 197 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 198 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 199 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 200 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 201 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 202 ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ 203 ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ 204 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 205 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 206 #else 207 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 208 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 209 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 210 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 211 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 212 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 213 ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ 214 ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ 215 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 216 #endif 217 218 #define IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) 219 #define IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) 220 221 222 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 223 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 224 ((__DIV__) == RCC_MCODIV_16)) 225 226 227 228 229 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 230 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 231 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 232 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 233 234 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 235 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 236 /** 237 * @} 238 */ 239 240 /* Exported types ------------------------------------------------------------*/ 241 /** @defgroup RCC_Exported_Types RCC Exported Types 242 * @{ 243 */ 244 245 246 /** 247 * @brief RCC PLL configuration structure definition 248 */ 249 typedef struct 250 { 251 uint32_t PLLState; /*!< The new state of the PLL. 252 This parameter must be a value of @ref RCC_PLL_Config */ 253 254 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 255 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 256 257 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 258 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 259 260 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 261 This parameter must be a number between Min_Data = 6 and Max_Data = 127 */ 262 263 uint32_t PLLP; /*!< PLLP: Division factor for SAI & ADC clock. 264 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 265 266 uint32_t PLLQ; /*!< PLLQ: Division factor for RNG and USB clocks. 267 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 268 269 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 270 User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. 271 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 272 273 } RCC_PLLInitTypeDef; 274 275 /** 276 * @brief RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition 277 */ 278 typedef struct 279 { 280 uint32_t OscillatorType; /*!< The oscillators to be configured. 281 This parameter can be a combination of @ref RCC_Oscillator_Type */ 282 283 uint32_t HSEState; /*!< The new state of the HSE. 284 This parameter can be a value of @ref RCC_HSE_Config */ 285 286 uint32_t LSEState; /*!< The new state of the LSE. 287 This parameter can be a value of @ref RCC_LSE_Config */ 288 289 uint32_t HSIState; /*!< The new state of the HSI. 290 This parameter can be a value of @ref RCC_HSI_Config */ 291 292 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_HSICALIBRATION_DEFAULT).*/ 293 294 uint32_t LSIState; /*!< The new state of the LSI. 295 This parameter can be a value of @ref RCC_LSI_Config */ 296 297 uint32_t LSI2CalibrationValue; /*!< The LSI2 calibration trimming value . 298 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF */ 299 300 uint32_t MSIState; /*!< The new state of the MSI. 301 This parameter can be a value of @ref RCC_MSI_Config */ 302 303 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_MSICALIBRATION_DEFAULT). 304 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 305 306 uint32_t MSIClockRange; /*!< The MSI frequency range. 307 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 308 309 #if defined(RCC_HSI48_SUPPORT) 310 uint32_t HSI48State; /*!< The new state of the HSI48 . 311 This parameter can be a value of @ref RCC_HSI48_Config */ 312 #endif 313 314 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 315 316 } RCC_OscInitTypeDef; 317 318 /** 319 * @brief RCC System, AHB and APB buses clock configuration structure definition 320 */ 321 typedef struct 322 { 323 uint32_t ClockType; /*!< The clock to be configured. 324 This parameter can be a combination of @ref RCC_System_Clock_Type */ 325 326 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 327 This parameter can be a value of @ref RCC_System_Clock_Source */ 328 329 uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). 330 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 331 332 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 333 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 334 335 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 336 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 337 338 uint32_t AHBCLK2Divider; /*!< The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). 339 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 340 341 uint32_t AHBCLK4Divider; /*!< The AHB shared clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK). 342 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 343 344 } RCC_ClkInitTypeDef; 345 346 /** 347 * @} 348 */ 349 350 /* Exported constants --------------------------------------------------------*/ 351 /** @defgroup RCC_Exported_Constants RCC Exported Constants 352 * @{ 353 */ 354 355 /** @defgroup RCC_Timeout_Value Timeout Values 356 * @{ 357 */ 358 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 359 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup RCC_Oscillator_Type Oscillator Type 365 * @{ 366 */ 367 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 368 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 369 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 370 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 371 #define RCC_OSCILLATORTYPE_LSI1 0x00000008U /*!< LSI1 to configure */ 372 #define RCC_OSCILLATORTYPE_LSI2 0x00000010U /*!< LSI2 to configure */ 373 #define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */ 374 #if defined(RCC_HSI48_SUPPORT) 375 #define RCC_OSCILLATORTYPE_HSI48 0x00000040U /*!< HSI48 to configure */ 376 #endif 377 /** 378 * @} 379 */ 380 381 /** @defgroup RCC_HSE_Config HSE Config 382 * @{ 383 */ 384 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 385 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 386 /** 387 * @} 388 */ 389 390 /** @defgroup RCC_LSE_Config LSE Config 391 * @{ 392 */ 393 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 394 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 395 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 396 /** 397 * @} 398 */ 399 400 /** @defgroup RCC_HSI_Config HSI Config 401 * @{ 402 */ 403 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 404 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 405 406 #define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ 407 /** 408 * @} 409 */ 410 411 /** @defgroup RCC_LSI_Config LSI Config 412 * @{ 413 */ 414 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 415 #define RCC_LSI_ON (RCC_CSR_LSI1ON | RCC_CSR_LSI2ON) /*!< LSI1 or LSI2 clock activation */ 416 /** 417 * @} 418 */ 419 420 /** @defgroup RCC_MSI_Config MSI Config 421 * @{ 422 */ 423 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 424 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 425 426 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 427 /** 428 * @} 429 */ 430 431 #if defined(RCC_HSI48_SUPPORT) 432 /** @defgroup RCC_HSI48_Config HSI48 Config 433 * @{ 434 */ 435 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 436 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 437 /** 438 * @} 439 */ 440 #endif 441 442 /** @defgroup RCC_PLL_Config PLL Config 443 * @{ 444 */ 445 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 446 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 447 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 453 * @{ 454 */ 455 #define RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1 /*!< PLLM division factor = 1 */ 456 #define RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2 /*!< PLLM division factor = 2 */ 457 #define RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3 /*!< PLLM division factor = 3 */ 458 #define RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4 /*!< PLLM division factor = 4 */ 459 #define RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5 /*!< PLLM division factor = 5 */ 460 #define RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6 /*!< PLLM division factor = 6 */ 461 #define RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7 /*!< PLLM division factor = 7 */ 462 #define RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8 /*!< PLLM division factor = 8 */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 468 * @{ 469 */ 470 #define RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2 /*!< PLLP division factor = 2 */ 471 #define RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3 /*!< PLLP division factor = 3 */ 472 #define RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4 /*!< PLLP division factor = 4 */ 473 #define RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5 /*!< PLLP division factor = 5 */ 474 #define RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6 /*!< PLLP division factor = 6 */ 475 #define RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7 /*!< PLLP division factor = 7 */ 476 #define RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8 /*!< PLLP division factor = 8 */ 477 #define RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9 /*!< PLLP division factor = 9 */ 478 #define RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10 /*!< PLLP division factor = 10 */ 479 #define RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11 /*!< PLLP division factor = 11 */ 480 #define RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12 /*!< PLLP division factor = 12 */ 481 #define RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13 /*!< PLLP division factor = 13 */ 482 #define RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14 /*!< PLLP division factor = 14 */ 483 #define RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15 /*!< PLLP division factor = 15 */ 484 #define RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16 /*!< PLLP division factor = 16 */ 485 #define RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17 /*!< PLLP division factor = 17 */ 486 #define RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18 /*!< PLLP division factor = 18 */ 487 #define RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19 /*!< PLLP division factor = 19 */ 488 #define RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20 /*!< PLLP division factor = 20 */ 489 #define RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21 /*!< PLLP division factor = 21 */ 490 #define RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22 /*!< PLLP division factor = 22 */ 491 #define RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23 /*!< PLLP division factor = 23 */ 492 #define RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24 /*!< PLLP division factor = 24 */ 493 #define RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25 /*!< PLLP division factor = 25 */ 494 #define RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26 /*!< PLLP division factor = 26 */ 495 #define RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27 /*!< PLLP division factor = 27 */ 496 #define RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28 /*!< PLLP division factor = 28 */ 497 #define RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29 /*!< PLLP division factor = 29 */ 498 #define RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30 /*!< PLLP division factor = 30 */ 499 #define RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31 /*!< PLLP division factor = 31 */ 500 #define RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32 /*!< PLLP division factor = 32 */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 506 * @{ 507 */ 508 #define RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2 /*!< PLLQ division factor = 2 */ 509 #define RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3 /*!< PLLQ division factor = 3 */ 510 #define RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4 /*!< PLLQ division factor = 4 */ 511 #define RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5 /*!< PLLQ division factor = 5 */ 512 #define RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6 /*!< PLLQ division factor = 6 */ 513 #define RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7 /*!< PLLQ division factor = 7 */ 514 #define RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8 /*!< PLLQ division factor = 8 */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 520 * @{ 521 */ 522 #define RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2 /*!< PLLR division factor = 2 */ 523 #define RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3 /*!< PLLR division factor = 3 */ 524 #define RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4 /*!< PLLR division factor = 4 */ 525 #define RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5 /*!< PLLR division factor = 5 */ 526 #define RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6 /*!< PLLR division factor = 6 */ 527 #define RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7 /*!< PLLR division factor = 7 */ 528 #define RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8 /*!< PLLR division factor = 8 */ 529 /** 530 * @} 531 */ 532 533 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 534 * @{ 535 */ 536 #define RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE /*!< No clock selected as PLL entry clock source */ 537 #define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI /*!< MSI clock selected as PLL entry clock source */ 538 #define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI /*!< HSI clock selected as PLL entry clock source */ 539 #define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE /*!< HSE clock selected as PLL entry clock source */ 540 /** 541 * @} 542 */ 543 544 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 545 * @{ 546 */ 547 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 548 #define RCC_PLL_USBCLK RCC_PLLCFGR_PLLQEN /*!< PLLUSBCLK selection from main PLL */ 549 #define RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN /*!< PLLRNGCLK selection from main PLL */ 550 #if defined(SAI1) 551 #define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */ 552 #endif 553 #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ 554 /** 555 * @} 556 */ 557 558 #if defined(SAI1) 559 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 560 * @{ 561 */ 562 #define RCC_PLLSAI1_ADCCLK RCC_PLLSAI1CFGR_PLLREN /*!< PLLADCCLK selection from PLLSAI1 */ 563 #define RCC_PLLSAI1_USBCLK RCC_PLLSAI1CFGR_PLLQEN /*!< USBCLK selection from PLLSAI1 */ 564 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLPEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 565 /** 566 * @} 567 */ 568 #endif 569 570 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 571 * @{ 572 */ 573 #define RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0 /*!< MSI = 100 KHz */ 574 #define RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1 /*!< MSI = 200 KHz */ 575 #define RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2 /*!< MSI = 400 KHz */ 576 #define RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3 /*!< MSI = 800 KHz */ 577 #define RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4 /*!< MSI = 1 MHz */ 578 #define RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5 /*!< MSI = 2 MHz */ 579 #define RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6 /*!< MSI = 4 MHz */ 580 #define RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7 /*!< MSI = 8 MHz */ 581 #define RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8 /*!< MSI = 16 MHz */ 582 #define RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9 /*!< MSI = 24 MHz */ 583 #define RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10 /*!< MSI = 32 MHz */ 584 #define RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11 /*!< MSI = 48 MHz */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup RCC_System_Clock_Type System Clock Type 590 * @{ 591 */ 592 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 593 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 594 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 595 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 596 #define RCC_CLOCKTYPE_HCLK2 0x00000020U /*!< HCLK2 to configure */ 597 #define RCC_CLOCKTYPE_HCLK4 0x00000040U /*!< HCLK4 to configure */ 598 /** 599 * @} 600 */ 601 602 /** @defgroup RCC_System_Clock_Source System Clock Source 603 * @{ 604 */ 605 #define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI /*!< MSI selection as system clock */ 606 #define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI /*!< HSI selection as system clock */ 607 #define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE /*!< HSE selection as system clock */ 608 #define RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL /*!< PLL selection as system clock */ 609 /** 610 * @} 611 */ 612 613 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 614 * @{ 615 */ 616 #define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI /*!< MSI used as system clock */ 617 #define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI /*!< HSI used as system clock */ 618 #define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE /*!< HSE used as system clock */ 619 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL /*!< PLL used as system clock */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup RCC_AHBx_Clock_Source AHB Clock Source 625 * @{ 626 */ 627 #define RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1 /*!< SYSCLK not divided */ 628 #define RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2 /*!< SYSCLK divided by 2 */ 629 #define RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3 /*!< SYSCLK divided by 3 */ 630 #define RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4 /*!< SYSCLK divided by 4 */ 631 #define RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5 /*!< SYSCLK divided by 5 */ 632 #define RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6 /*!< SYSCLK divided by 6 */ 633 #define RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8 /*!< SYSCLK divided by 8 */ 634 #define RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10 /*!< SYSCLK divided by 10 */ 635 #define RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16 /*!< SYSCLK divided by 16 */ 636 #define RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32 /*!< SYSCLK divided by 32 */ 637 #define RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64 /*!< SYSCLK divided by 64 */ 638 #define RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128 /*!< SYSCLK divided by 128 */ 639 #define RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256 /*!< SYSCLK divided by 256 */ 640 #define RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512 /*!< SYSCLK divided by 512 */ 641 /** 642 * @} 643 */ 644 645 /** @defgroup RCC_APBx_Clock_Source APB1 Clock Source 646 * @{ 647 */ 648 #define RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1 /*!< HCLK not divided */ 649 #define RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2 /*!< HCLK divided by 2 */ 650 #define RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4 /*!< HCLK divided by 4 */ 651 #define RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8 /*!< HCLK divided by 8 */ 652 #define RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16 /*!< HCLK divided by 16 */ 653 /** 654 * @} 655 */ 656 657 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 658 * @{ 659 */ 660 #define RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE /*!< No clock used as RTC clock */ 661 #define RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE /*!< LSE oscillator clock used as RTC clock */ 662 #define RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI /*!< LSI oscillator clock used as RTC clock */ 663 #define RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32 /*!< HSE oscillator clock divided by 32 used as RTC clock */ 664 /** 665 * @} 666 */ 667 668 /** @defgroup RCC_MCO_Index MCO Index 669 * @{ 670 */ 671 #define RCC_MCO1 0x00000000U /*!< MCO1 index */ 672 #define RCC_MCO2 0x00000001U /*!< MCO2 index */ 673 #if defined(RCC_MCO3_SUPPORT) 674 #define RCC_MCO3 0x00000002U /*!< MCO3 index */ 675 #endif 676 677 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ 678 /** 679 * @} 680 */ 681 682 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 683 * @{ 684 */ 685 #define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */ 686 #define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selection as MCO1 source */ 687 #define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selection as MCO1 source */ 688 #define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selection as MCO1 source */ 689 #define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selection as MCO1 source */ 690 #define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< PLLCLK selection as MCO1 source */ 691 #define RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1 /*!< LSI1 selection as MCO1 source */ 692 #define RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2 /*!< LSI2 selection as MCO1 source */ 693 #define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selection as MCO1 source */ 694 #if defined(RCC_HSI48_SUPPORT) 695 #define RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48 /*!< HSI48 selection as MCO1 source */ 696 #endif 697 #define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB /*!< HSE before stabilization selection as MCO1 source */ 698 699 /** 700 * @} 701 */ 702 703 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 704 * @{ 705 */ 706 #define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */ 707 #define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ 708 #define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ 709 #define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ 710 #define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16 /*!< MCO divided by 16 */ 711 /** 712 * @} 713 */ 714 715 /** @defgroup RCC_HSEAMPTHRESHOLD HSE bias current factor 716 * @{ 717 */ 718 #define RCC_HSEAMPTHRESHOLD_1_2 LL_RCC_HSEAMPTHRESHOLD_1_2 /*!< HSE bias current factor 1/2 */ 719 #define RCC_HSEAMPTHRESHOLD_3_4 LL_RCC_HSEAMPTHRESHOLD_3_4 /*!< HSE bias current factor 3/4 */ 720 721 /** 722 * @} 723 */ 724 725 /** @defgroup RCC_HSE_CURRENTMAX HSE current max limit 726 * @{ 727 */ 728 #define RCC_HSE_CURRENTMAX_0 LL_RCC_HSE_CURRENTMAX_0 /*!< HSE current max limit 0.18 mA/V */ 729 #define RCC_HSE_CURRENTMAX_1 LL_RCC_HSE_CURRENTMAX_1 /*!< HSE current max limit 0.57 mA/V */ 730 #define RCC_HSE_CURRENTMAX_2 LL_RCC_HSE_CURRENTMAX_2 /*!< HSE current max limit 0.78 mA/V */ 731 #define RCC_HSE_CURRENTMAX_3 LL_RCC_HSE_CURRENTMAX_3 /*!< HSE current max limit 1.13 mA/V */ 732 #define RCC_HSE_CURRENTMAX_4 LL_RCC_HSE_CURRENTMAX_4 /*!< HSE current max limit 0.61 mA/V */ 733 #define RCC_HSE_CURRENTMAX_5 LL_RCC_HSE_CURRENTMAX_5 /*!< HSE current max limit 1.65 mA/V */ 734 #define RCC_HSE_CURRENTMAX_6 LL_RCC_HSE_CURRENTMAX_6 /*!< HSE current max limit 2.12 mA/V */ 735 #define RCC_HSE_CURRENTMAX_7 LL_RCC_HSE_CURRENTMAX_7 /*!< HSE current max limit 2.84 mA/V */ 736 737 /** 738 * @} 739 */ 740 741 /** @defgroup RCC_Interrupt Interrupts 742 * @{ 743 */ 744 #define RCC_IT_LSI1RDY LL_RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ 745 #define RCC_IT_LSI2RDY LL_RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ 746 #define RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 747 #define RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 748 #define RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 749 #define RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 750 #define RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 751 #if defined(SAI1) 752 #define RCC_IT_PLLSAI1RDY LL_RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 753 #endif 754 #define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 755 #define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 756 #if defined(RCC_HSI48_SUPPORT) 757 #define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 758 #endif 759 /** 760 * @} 761 */ 762 763 764 /** @defgroup RCC_Flag Flags 765 * Elements values convention: XXXYYYYYb 766 * - YYYYY : Flag position in the register 767 * - XXX : Register index 768 * - 001: CR register 769 * - 010: BDCR register 770 * - 011: CSR register 771 * - 100: CRRCR register 772 * @{ 773 */ 774 /* Flags in the CR register */ 775 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 776 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 777 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 778 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 779 #if defined(SAI1) 780 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 781 #endif 782 783 /* Flags in the BDCR register */ 784 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 785 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 786 787 /* Flags in the CSR register */ 788 #define RCC_FLAG_LSI1RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI1RDY_Pos) /*!< LSI1 Ready flag */ 789 #define RCC_FLAG_LSI2RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI2RDY_Pos) /*!< LSI2 Ready flag */ 790 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 791 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< Pin reset flag (NRST pin) */ 792 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 793 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 794 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Watchdog reset flag */ 795 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 796 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 797 798 /* Flags in the CRRCR register */ 799 #if defined(RCC_HSI48_SUPPORT) 800 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 801 #endif 802 /** 803 * @} 804 */ 805 806 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration 807 * @{ 808 */ 809 #define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW /*!< LSE low drive capability */ 810 #define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW /*!< LSE medium low drive capability */ 811 #define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH /*!< LSE medium high drive capability */ 812 #define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH /*!< LSE high drive capability */ 813 /** 814 * @} 815 */ 816 817 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 818 * @{ 819 */ 820 #define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI /*!< MSI selection after wake-up from STOP */ 821 #define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI /*!< HSI selection after wake-up from STOP */ 822 /** 823 * @} 824 */ 825 826 /** 827 * @} 828 */ 829 830 /* Exported macros -----------------------------------------------------------*/ 831 832 /** @defgroup RCC_Exported_Macros RCC Exported Macros 833 * @{ 834 */ 835 836 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 837 * @brief Enable or disable the AHB1 peripheral clock. 838 * @note After reset, the peripheral clock (used for registers read/write access) 839 * is disabled and the application software has to enable this clock before 840 * using it. 841 * @{ 842 */ 843 844 #define __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) 845 #if defined(DMA2) 846 #define __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2) 847 #endif 848 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 849 #define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC) 850 #if defined(TSC) 851 #define __HAL_RCC_TSC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC) 852 #endif 853 854 #define __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1) 855 #if defined(DMA2) 856 #define __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2) 857 #endif 858 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 859 #define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC) 860 #if defined(TSC) 861 #define __HAL_RCC_TSC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC) 862 #endif 863 /** 864 * @} 865 */ 866 867 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 868 * @brief Enable or disable the AHB2 peripheral clock. 869 * @note After reset, the peripheral clock (used for registers read/write access) 870 * is disabled and the application software has to enable this clock before 871 * using it. 872 * @{ 873 */ 874 875 #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 876 #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 877 #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 878 #if defined(GPIOD) 879 #define __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD) 880 #endif 881 #define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE) 882 #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 883 #if defined(ADC_SUPPORT_5_MSPS) 884 #define __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC) 885 #endif 886 #if defined(AES1) 887 #define __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1) 888 #endif 889 #define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 890 #define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 891 #define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 892 #if defined(GPIOD) 893 #define __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD) 894 #endif 895 #define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE) 896 #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 897 #if defined(ADC_SUPPORT_5_MSPS) 898 #define __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC) 899 #endif 900 #if defined(AES1) 901 #define __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1) 902 #endif 903 904 /** 905 * @} 906 */ 907 908 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 909 * @brief Enable or disable the AHB3 peripheral clock. 910 * @note After reset, the peripheral clock (used for registers read/write access) 911 * is disabled and the application software has to enable this clock before 912 * using it. 913 * @{ 914 */ 915 916 #if defined(QUADSPI) 917 #define __HAL_RCC_QUADSPI_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 918 #endif 919 #define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) 920 #define __HAL_RCC_AES2_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2) 921 #define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) 922 #define __HAL_RCC_HSEM_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM) 923 #define __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC) 924 #define __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH) 925 926 #if defined(QUADSPI) 927 #define __HAL_RCC_QUADSPI_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 928 #endif 929 #define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) 930 #define __HAL_RCC_AES2_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2) 931 #define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) 932 #define __HAL_RCC_HSEM_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM) 933 #define __HAL_RCC_IPCC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC) 934 #define __HAL_RCC_FLASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH) 935 936 /** 937 * @} 938 */ 939 940 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 941 * @brief Enable or disable the APB1 peripheral clock. 942 * @note After reset, the peripheral clock (used for registers read/write access) 943 * is disabled and the application software has to enable this clock before 944 * using it. 945 * @{ 946 */ 947 948 #define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 949 #define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) 950 #define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) 951 #if defined(LCD) 952 #define __HAL_RCC_LCD_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD) 953 #endif 954 #if defined(SPI2) 955 #define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) 956 #endif 957 #define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) 958 #if defined(I2C3) 959 #define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) 960 #endif 961 #if defined(CRS) 962 #define __HAL_RCC_CRS_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS) 963 #endif 964 #if defined(USB) 965 #define __HAL_RCC_USB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB) 966 #endif 967 #define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 968 #define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 969 #if defined(LPUART1) 970 #define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1) 971 #endif 972 973 #define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 974 #define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) 975 #if defined(LCD) 976 #define __HAL_RCC_LCD_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD) 977 #endif 978 #if defined(SPI2) 979 #define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) 980 #endif 981 #define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) 982 #if defined(I2C3) 983 #define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) 984 #endif 985 #if defined(CRS) 986 #define __HAL_RCC_CRS_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS) 987 #endif 988 #if defined(USB) 989 #define __HAL_RCC_USB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB) 990 #endif 991 #define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 992 993 #define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 994 #if defined(LPUART1) 995 #define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1) 996 #endif 997 998 /** 999 * @} 1000 */ 1001 1002 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1003 * @brief Enable or disable the APB2 peripheral clock. 1004 * @note After reset, the peripheral clock (used for registers read/write access) 1005 * is disabled and the application software has to enable this clock before 1006 * using it. 1007 * @{ 1008 */ 1009 1010 #if defined(ADC_SUPPORT_2_5_MSPS) 1011 #define __HAL_RCC_ADC_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC) 1012 #endif 1013 #define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) 1014 #define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) 1015 #define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) 1016 #define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) 1017 #define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) 1018 #if defined(SAI1) 1019 #define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1) 1020 #endif 1021 1022 #if defined(ADC_SUPPORT_2_5_MSPS) 1023 #define __HAL_RCC_ADC_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC) 1024 #endif 1025 #define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) 1026 #define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) 1027 #define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) 1028 #define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) 1029 #define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) 1030 #if defined(SAI1) 1031 #define __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1) 1032 #endif 1033 1034 /** 1035 * @} 1036 */ 1037 1038 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1039 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1040 * @note After reset, the peripheral clock (used for registers read/write access) 1041 * is disabled and the application software has to enable this clock before 1042 * using it. 1043 * @{ 1044 */ 1045 1046 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1) 1047 #if defined(DMA2) 1048 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2) 1049 #endif 1050 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1051 #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC) 1052 #if defined(TSC) 1053 #define __HAL_RCC_TSC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC) 1054 #endif 1055 1056 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)) 1057 #if defined(DMA2) 1058 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)) 1059 #endif 1060 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)) 1061 #define __HAL_RCC_CRC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)) 1062 #if defined(TSC) 1063 #define __HAL_RCC_TSC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)) 1064 #endif 1065 1066 /** 1067 * @} 1068 */ 1069 1070 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1071 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1072 * @note After reset, the peripheral clock (used for registers read/write access) 1073 * is disabled and the application software has to enable this clock before 1074 * using it. 1075 * @{ 1076 */ 1077 1078 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA) 1079 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB) 1080 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC) 1081 #if defined(GPIOD) 1082 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD) 1083 #endif 1084 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE) 1085 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH) 1086 #if defined(ADC_SUPPORT_5_MSPS) 1087 #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC) 1088 #endif 1089 #if defined(AES1) 1090 #define __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1) 1091 #endif 1092 1093 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)) 1094 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)) 1095 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)) 1096 #if defined(GPIOD) 1097 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)) 1098 #endif 1099 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)) 1100 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)) 1101 #if defined(ADC_SUPPORT_5_MSPS) 1102 #define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)) 1103 #endif 1104 #if defined(AES1) 1105 #define __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)) 1106 #endif 1107 1108 /** 1109 * @} 1110 */ 1111 1112 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1113 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1114 * @note After reset, the peripheral clock (used for registers read/write access) 1115 * is disabled and the application software has to enable this clock before 1116 * using it. 1117 * @{ 1118 */ 1119 1120 #if defined(QUADSPI) 1121 #define __HAL_RCC_QUADSPI_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 1122 #endif 1123 #define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) 1124 #define __HAL_RCC_AES2_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2) 1125 #define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) 1126 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM) 1127 #define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC) 1128 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH) 1129 1130 #if defined(QUADSPI) 1131 #define __HAL_RCC_QUADSPI_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)) 1132 #endif 1133 #define __HAL_RCC_PKA_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)) 1134 #define __HAL_RCC_AES2_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)) 1135 #define __HAL_RCC_RNG_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)) 1136 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)) 1137 #define __HAL_RCC_IPCC_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)) 1138 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)) 1139 1140 /** 1141 * @} 1142 */ 1143 1144 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1145 * @brief Check whether the APB1 peripheral clock is enabled or not. 1146 * @note After reset, the peripheral clock (used for registers read/write access) 1147 * is disabled and the application software has to enable this clock before 1148 * using it. 1149 * @{ 1150 */ 1151 1152 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB) 1153 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) 1154 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) 1155 #if defined(LCD) 1156 #define __HAL_RCC_LCD_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD) 1157 #endif 1158 #if defined(SPI2) 1159 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) 1160 #endif 1161 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) 1162 #if defined(I2C3) 1163 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) 1164 #endif 1165 #if defined(CRS) 1166 #define __HAL_RCC_CRS_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS) 1167 #endif 1168 #if defined(USB) 1169 #define __HAL_RCC_USB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB) 1170 #endif 1171 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1172 1173 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2) 1174 #if defined(LPUART1) 1175 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1) 1176 #endif 1177 1178 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)) 1179 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)) 1180 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)) 1181 #if defined(LCD) 1182 #define __HAL_RCC_LCD_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)) 1183 #endif 1184 #if defined(SPI2) 1185 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)) 1186 #endif 1187 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)) 1188 #if defined(I2C3) 1189 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)) 1190 #endif 1191 #if defined(CRS) 1192 #define __HAL_RCC_CRS_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)) 1193 #endif 1194 #if defined(USB) 1195 #define __HAL_RCC_USB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)) 1196 #endif 1197 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)) 1198 1199 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)) 1200 #if defined(LPUART1) 1201 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)) 1202 #endif 1203 1204 /** 1205 * @} 1206 */ 1207 1208 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1209 * @brief Check whether the APB2 peripheral clock is enabled or not. 1210 * @note After reset, the peripheral clock (used for registers read/write access) 1211 * is disabled and the application software has to enable this clock before 1212 * using it. 1213 * @{ 1214 */ 1215 1216 #if defined(ADC_SUPPORT_2_5_MSPS) 1217 #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC) 1218 #endif 1219 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) 1220 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) 1221 #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) 1222 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) 1223 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) 1224 #if defined(SAI1) 1225 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1) 1226 #endif 1227 1228 1229 #if defined(ADC_SUPPORT_2_5_MSPS) 1230 #define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC)) 1231 #endif 1232 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)) 1233 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)) 1234 #define __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)) 1235 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)) 1236 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)) 1237 #if defined(SAI1) 1238 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)) 1239 #endif 1240 1241 /** 1242 * @} 1243 */ 1244 1245 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 1246 * @brief Enable or disable the AHB1 peripheral clock. 1247 * @note After reset, the peripheral clock (used for registers read/write access) 1248 * is disabled and the application software has to enable this clock before 1249 * using it. 1250 * @{ 1251 */ 1252 1253 #define __HAL_RCC_C2DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1254 #if defined(DMA2) 1255 #define __HAL_RCC_C2DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1256 #endif 1257 #define __HAL_RCC_C2DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1258 #define __HAL_RCC_C2SRAM1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1259 #define __HAL_RCC_C2CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1260 #if defined(TSC) 1261 #define __HAL_RCC_C2TSC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1262 #endif 1263 1264 #define __HAL_RCC_C2DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1265 #if defined(DMA2) 1266 #define __HAL_RCC_C2DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1267 #endif 1268 #define __HAL_RCC_C2DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1269 #define __HAL_RCC_C2SRAM1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1270 #define __HAL_RCC_C2CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1271 #if defined(TSC) 1272 #define __HAL_RCC_C2TSC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1273 #endif 1274 1275 /** 1276 * @} 1277 */ 1278 1279 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 1280 * @brief Enable or disable the AHB2 peripheral clock. 1281 * @note After reset, the peripheral clock (used for registers read/write access) 1282 * is disabled and the application software has to enable this clock before 1283 * using it. 1284 * @{ 1285 */ 1286 1287 #define __HAL_RCC_C2GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1288 #define __HAL_RCC_C2GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1289 #define __HAL_RCC_C2GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1290 #if defined(GPIOD) 1291 #define __HAL_RCC_C2GPIOD_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1292 #endif 1293 #define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1294 #define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1295 #if defined(ADC_SUPPORT_5_MSPS) 1296 #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1297 #endif 1298 #if defined(AES1) 1299 #define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1300 #endif 1301 1302 #define __HAL_RCC_C2GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1303 #define __HAL_RCC_C2GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1304 #define __HAL_RCC_C2GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1305 #if defined(GPIOD) 1306 #define __HAL_RCC_C2GPIOD_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1307 #endif 1308 #define __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1309 #define __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1310 #if defined(ADC_SUPPORT_5_MSPS) 1311 #define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1312 #endif 1313 #if defined(AES1) 1314 #define __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1315 #endif 1316 1317 /** 1318 * @} 1319 */ 1320 1321 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 1322 * @brief Enable or disable the AHB3 peripheral clock. 1323 * @note After reset, the peripheral clock (used for registers read/write access) 1324 * is disabled and the application software has to enable this clock before 1325 * using it. 1326 * @{ 1327 */ 1328 1329 #define __HAL_RCC_C2PKA_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1330 #define __HAL_RCC_C2AES2_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1331 #define __HAL_RCC_C2RNG_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1332 #define __HAL_RCC_C2HSEM_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1333 #define __HAL_RCC_C2IPCC_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1334 #define __HAL_RCC_C2FLASH_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1335 1336 #define __HAL_RCC_C2PKA_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1337 #define __HAL_RCC_C2AES2_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1338 #define __HAL_RCC_C2RNG_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1339 #define __HAL_RCC_C2HSEM_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1340 #define __HAL_RCC_C2IPCC_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1341 #define __HAL_RCC_C2FLASH_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1342 1343 /** 1344 * @} 1345 */ 1346 1347 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1348 * @brief Enable or disable the APB1 peripheral clock. 1349 * @note After reset, the peripheral clock (used for registers read/write access) 1350 * is disabled and the application software has to enable this clock before 1351 * using it. 1352 * @{ 1353 */ 1354 1355 #define __HAL_RCC_C2RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1356 #define __HAL_RCC_C2TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1357 #if defined(LCD) 1358 #define __HAL_RCC_C2LCD_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1359 #endif 1360 #if defined(SPI2) 1361 #define __HAL_RCC_C2SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1362 #endif 1363 #define __HAL_RCC_C2I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1364 #if defined(I2C3) 1365 #define __HAL_RCC_C2I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1366 #endif 1367 #if defined(CRS) 1368 #define __HAL_RCC_C2CRS_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1369 #endif 1370 #if defined(USB) 1371 #define __HAL_RCC_C2USB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB) 1372 #endif 1373 #define __HAL_RCC_C2LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1374 1375 #define __HAL_RCC_C2LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1376 #if defined(LPUART1) 1377 #define __HAL_RCC_C2LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1378 #endif 1379 1380 #define __HAL_RCC_C2RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1381 #define __HAL_RCC_C2TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1382 #if defined(LCD) 1383 #define __HAL_RCC_C2LCD_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1384 #endif 1385 #if defined(SPI2) 1386 #define __HAL_RCC_C2SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1387 #endif 1388 #define __HAL_RCC_C2I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1389 #if defined(I2C3) 1390 #define __HAL_RCC_C2I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1391 #endif 1392 #if defined(CRS) 1393 #define __HAL_RCC_C2CRS_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1394 #endif 1395 #if defined(USB) 1396 #define __HAL_RCC_C2USB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB) 1397 #endif 1398 #define __HAL_RCC_C2LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1399 1400 #define __HAL_RCC_C2LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1401 #if defined(LPUART1) 1402 #define __HAL_RCC_C2LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1403 #endif 1404 1405 /** 1406 * @} 1407 */ 1408 1409 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1410 * @brief Enable or disable the APB2 peripheral clock. 1411 * @note After reset, the peripheral clock (used for registers read/write access) 1412 * is disabled and the application software has to enable this clock before 1413 * using it. 1414 * @{ 1415 */ 1416 1417 #if defined(ADC_SUPPORT_2_5_MSPS) 1418 #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC) 1419 #endif 1420 #define __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1421 #define __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1422 #define __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1423 #define __HAL_RCC_C2TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1424 #define __HAL_RCC_C2TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1425 #if defined(SAI1) 1426 #define __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1427 #endif 1428 1429 #if defined(ADC_SUPPORT_2_5_MSPS) 1430 #define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC) 1431 #endif 1432 #define __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1433 #define __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1434 #define __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1435 #define __HAL_RCC_C2TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1436 #define __HAL_RCC_C2TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1437 #if defined(SAI1) 1438 #define __HAL_RCC_C2SAI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1439 #endif 1440 1441 /** 1442 * @} 1443 */ 1444 1445 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1446 * @brief Enable or disable the APB3 peripheral clock. 1447 * @note After reset, the peripheral clock (used for registers read/write access) 1448 * is disabled and the application software has to enable this clock before 1449 * using it. 1450 * @{ 1451 */ 1452 1453 #define __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1454 #if defined(RCC_802_SUPPORT) 1455 #define __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802) 1456 #endif 1457 1458 #define __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1459 #if defined(RCC_802_SUPPORT) 1460 #define __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802) 1461 #endif 1462 1463 /** 1464 * @} 1465 */ 1466 1467 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1468 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1469 * @note After reset, the peripheral clock (used for registers read/write access) 1470 * is disabled and the application software has to enable this clock before 1471 * using it. 1472 * @{ 1473 */ 1474 1475 #define __HAL_RCC_C2DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1476 #if defined(DMA2) 1477 #define __HAL_RCC_C2DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1478 #endif 1479 #define __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1480 #define __HAL_RCC_C2SRAM1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1481 #define __HAL_RCC_C2CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1482 #if defined(TSC) 1483 #define __HAL_RCC_C2TSC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1484 #endif 1485 1486 #define __HAL_RCC_C2DMA1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)) 1487 #if defined(DMA2) 1488 #define __HAL_RCC_C2DMA2_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)) 1489 #endif 1490 #define __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)) 1491 #define __HAL_RCC_C2SRAM1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)) 1492 #define __HAL_RCC_C2CRC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)) 1493 #if defined(TSC) 1494 #define __HAL_RCC_C2TSC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)) 1495 #endif 1496 1497 /** 1498 * @} 1499 */ 1500 1501 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1502 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1503 * @note After reset, the peripheral clock (used for registers read/write access) 1504 * is disabled and the application software has to enable this clock before 1505 * using it. 1506 * @{ 1507 */ 1508 1509 #define __HAL_RCC_C2GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1510 #define __HAL_RCC_C2GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1511 #define __HAL_RCC_C2GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1512 #if defined(GPIOD) 1513 #define __HAL_RCC_C2GPIOD_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1514 #endif 1515 #define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1516 #define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1517 #if defined(ADC_SUPPORT_5_MSPS) 1518 #define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1519 #endif 1520 #if defined(AES1) 1521 #define __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1522 #endif 1523 1524 #define __HAL_RCC_C2GPIOA_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)) 1525 #define __HAL_RCC_C2GPIOB_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)) 1526 #define __HAL_RCC_C2GPIOC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)) 1527 #if defined(GPIOD) 1528 #define __HAL_RCC_C2GPIOD_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)) 1529 #endif 1530 #define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)) 1531 #define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)) 1532 #if defined(ADC_SUPPORT_5_MSPS) 1533 #define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)) 1534 #endif 1535 #if defined(AES1) 1536 #define __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)) 1537 #endif 1538 1539 /** 1540 * @} 1541 */ 1542 1543 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1544 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1545 * @note After reset, the peripheral clock (used for registers read/write access) 1546 * is disabled and the application software has to enable this clock before 1547 * using it. 1548 * @{ 1549 */ 1550 1551 #define __HAL_RCC_C2PKA_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1552 #define __HAL_RCC_C2AES2_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1553 #define __HAL_RCC_C2RNG_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1554 #define __HAL_RCC_C2HSEM_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1555 #define __HAL_RCC_C2IPCC_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1556 #define __HAL_RCC_C2FLASH_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1557 1558 #define __HAL_RCC_C2PKA_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)) 1559 #define __HAL_RCC_C2AES2_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2)) 1560 #define __HAL_RCC_C2RNG_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)) 1561 #define __HAL_RCC_C2HSEM_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)) 1562 #define __HAL_RCC_C2IPCC_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)) 1563 #define __HAL_RCC_C2FLASH_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)) 1564 1565 /** 1566 * @} 1567 */ 1568 1569 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1570 * @brief Check whether the APB1 peripheral clock is enabled or not. 1571 * @note After reset, the peripheral clock (used for registers read/write access) 1572 * is disabled and the application software has to enable this clock before 1573 * using it. 1574 * @{ 1575 */ 1576 1577 #define __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1578 #define __HAL_RCC_C2TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1579 #if defined(LCD) 1580 #define __HAL_RCC_C2LCD_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1581 #endif 1582 #if defined(SPI2) 1583 #define __HAL_RCC_C2SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1584 #endif 1585 #define __HAL_RCC_C2I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1586 #if defined(I2C3) 1587 #define __HAL_RCC_C2I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1588 #endif 1589 #if defined(CRS) 1590 #define __HAL_RCC_C2CRS_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1591 #endif 1592 #if defined(USB) 1593 #define __HAL_RCC_C2USB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB) 1594 #endif 1595 #define __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1596 1597 #define __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1598 #if defined(LPUART1) 1599 #define __HAL_RCC_C2LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1600 #endif 1601 1602 #define __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)) 1603 #define __HAL_RCC_C2TIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)) 1604 #if defined(LCD) 1605 #define __HAL_RCC_C2LCD_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)) 1606 #endif 1607 #if defined(SPI2) 1608 #define __HAL_RCC_C2SPI2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)) 1609 #endif 1610 #define __HAL_RCC_C2I2C1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)) 1611 #if defined(I2C3) 1612 #define __HAL_RCC_C2I2C3_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)) 1613 #endif 1614 #if defined(CRS) 1615 #define __HAL_RCC_C2CRS_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)) 1616 #endif 1617 #if defined(USB) 1618 #define __HAL_RCC_C2USB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)) 1619 #endif 1620 #define __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) 1621 1622 #define __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)) 1623 #if defined(LPUART1) 1624 #define __HAL_RCC_C2LPUART1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) 1625 #endif 1626 1627 /** 1628 * @} 1629 */ 1630 1631 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1632 * @brief Check whether the APB2 peripheral clock is enabled or not. 1633 * @note After reset, the peripheral clock (used for registers read/write access) 1634 * is disabled and the application software has to enable this clock before 1635 * using it. 1636 * @{ 1637 */ 1638 1639 #if defined(ADC_SUPPORT_2_5_MSPS) 1640 #define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC) 1641 #endif 1642 #define __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1643 #define __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1644 #define __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1645 #define __HAL_RCC_C2TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1646 #define __HAL_RCC_C2TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1647 #if defined(SAI1) 1648 #define __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1649 #endif 1650 1651 #if defined(ADC_SUPPORT_2_5_MSPS) 1652 #define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC)) 1653 #endif 1654 #define __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)) 1655 #define __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)) 1656 #define __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)) 1657 #define __HAL_RCC_C2TIM16_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)) 1658 #define __HAL_RCC_C2TIM17_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)) 1659 #if defined(SAI1) 1660 #define __HAL_RCC_C2SAI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)) 1661 #endif 1662 1663 /** 1664 * @} 1665 */ 1666 1667 1668 /** @defgroup RCC_APB3_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 1669 * @brief Check whether the APB3 peripheral clock is enabled or not. 1670 * @note After reset, the peripheral clock (used for registers read/write access) 1671 * is disabled and the application software has to enable this clock before 1672 * using it. 1673 * @{ 1674 */ 1675 1676 #define __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1677 #if defined(RCC_802_SUPPORT) 1678 #define __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802) 1679 #endif 1680 1681 #define __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)) 1682 #if defined(RCC_802_SUPPORT) 1683 #define __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)) 1684 #endif 1685 1686 /** 1687 * @} 1688 */ 1689 1690 1691 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1692 * @brief Force or release AHB1 peripheral reset. 1693 * @{ 1694 */ 1695 #define __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL) 1696 #define __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1) 1697 #if defined(DMA2) 1698 #define __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2) 1699 #endif 1700 #define __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1701 #define __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC) 1702 #if defined(TSC) 1703 #define __HAL_RCC_TSC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC) 1704 #endif 1705 1706 1707 #define __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL) 1708 #define __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1) 1709 #if defined(DMA2) 1710 #define __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2) 1711 #endif 1712 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1713 #define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC) 1714 #if defined(TSC) 1715 #define __HAL_RCC_TSC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC) 1716 #endif 1717 1718 1719 /** 1720 * @} 1721 */ 1722 1723 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1724 * @brief Force or release AHB2 peripheral reset. 1725 * @{ 1726 */ 1727 #define __HAL_RCC_AHB2_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) 1728 #define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1729 #define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1730 #define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1731 #if defined(GPIOD) 1732 #define __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD) 1733 #endif 1734 #define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE) 1735 #define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1736 #if defined(ADC_SUPPORT_5_MSPS) 1737 #define __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC) 1738 #endif 1739 #if defined(AES1) 1740 #define __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1) 1741 #endif 1742 1743 #define __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) 1744 #define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1745 #define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1746 #define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1747 #if defined(GPIOD) 1748 #define __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD) 1749 #endif 1750 #define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE) 1751 #define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1752 #if defined(ADC_SUPPORT_5_MSPS) 1753 #define __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC) 1754 #endif 1755 #if defined(AES1) 1756 #define __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1) 1757 #endif 1758 1759 /** 1760 * @} 1761 */ 1762 1763 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1764 * @brief Force or release AHB3 peripheral reset. 1765 * @{ 1766 */ 1767 #define __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) 1768 #if defined(QUADSPI) 1769 #define __HAL_RCC_QUADSPI_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI) 1770 #endif 1771 #define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) 1772 #define __HAL_RCC_AES2_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2) 1773 #define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) 1774 #define __HAL_RCC_HSEM_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM) 1775 #define __HAL_RCC_IPCC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC) 1776 #define __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH) 1777 1778 #define __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) 1779 #if defined(QUADSPI) 1780 #define __HAL_RCC_QUADSPI_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI) 1781 #endif 1782 #define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) 1783 #define __HAL_RCC_AES2_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2) 1784 #define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) 1785 #define __HAL_RCC_HSEM_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM) 1786 #define __HAL_RCC_IPCC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC) 1787 #define __HAL_RCC_FLASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH) 1788 /** 1789 * @} 1790 */ 1791 1792 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1793 * @brief Force or release APB1 peripheral reset. 1794 * @{ 1795 */ 1796 1797 #define __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL) 1798 #define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) 1799 #if defined(LCD) 1800 #define __HAL_RCC_LCD_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD) 1801 #endif 1802 #if defined(SPI2) 1803 #define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) 1804 #endif 1805 #define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) 1806 #if defined(I2C3) 1807 #define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) 1808 #endif 1809 #if defined(CRS) 1810 #define __HAL_RCC_CRS_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS) 1811 #endif 1812 #if defined(USB) 1813 #define __HAL_RCC_USB_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB) 1814 #endif 1815 #define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1816 1817 #define __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL) 1818 #if defined(LPUART1) 1819 #define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1) 1820 #endif 1821 #define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1822 1823 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 1824 __HAL_RCC_APB1L_FORCE_RESET();\ 1825 __HAL_RCC_APB1H_FORCE_RESET();\ 1826 } while(0U) 1827 1828 #define __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL) 1829 #define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) 1830 #if defined(LCD) 1831 #define __HAL_RCC_LCD_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD) 1832 #endif 1833 #if defined(SPI2) 1834 #define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) 1835 #endif 1836 #define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) 1837 #if defined(I2C3) 1838 #define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) 1839 #endif 1840 #if defined(CRS) 1841 #define __HAL_RCC_CRS_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS) 1842 #endif 1843 #if defined(USB) 1844 #define __HAL_RCC_USB_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB) 1845 #endif 1846 #define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1847 1848 #define __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL) 1849 #if defined(LPUART1) 1850 #define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1) 1851 #endif 1852 #define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1853 1854 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 1855 __HAL_RCC_APB1L_RELEASE_RESET();\ 1856 __HAL_RCC_APB1H_RELEASE_RESET();\ 1857 } while(0U) 1858 /** 1859 * @} 1860 */ 1861 1862 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1863 * @brief Force or release APB2 peripheral reset. 1864 * @{ 1865 */ 1866 #define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL) 1867 #if defined(ADC_SUPPORT_2_5_MSPS) 1868 #define __HAL_RCC_ADC_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC) 1869 #endif 1870 #define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) 1871 #define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) 1872 #define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) 1873 #define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) 1874 #define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) 1875 #if defined(SAI1) 1876 #define __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1) 1877 #endif 1878 1879 #define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) 1880 #if defined(ADC_SUPPORT_2_5_MSPS) 1881 #define __HAL_RCC_ADC_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC) 1882 #endif 1883 #define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) 1884 #define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) 1885 #define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) 1886 #define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) 1887 #define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) 1888 #if defined(SAI1) 1889 #define __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1) 1890 #endif 1891 /** 1892 * @} 1893 */ 1894 1895 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 1896 * @brief Force or release APB3 peripheral reset. 1897 * @{ 1898 */ 1899 #define __HAL_RCC_APB3_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL) 1900 #define __HAL_RCC_RF_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_RF) 1901 1902 #define __HAL_RCC_APB3_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL) 1903 #define __HAL_RCC_RF_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_RF) 1904 1905 /** 1906 * @} 1907 */ 1908 1909 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 1910 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1911 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1912 * power consumption. 1913 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1914 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1915 * @{ 1916 */ 1917 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1918 #if defined(DMA2) 1919 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1920 #endif 1921 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1922 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) 1923 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1924 #if defined(TSC) 1925 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) 1926 #endif 1927 1928 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1929 #if defined(DMA2) 1930 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1931 #endif 1932 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1933 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) 1934 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1935 #if defined(TSC) 1936 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) 1937 #endif 1938 1939 #define __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1940 #if defined(DMA2) 1941 #define __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1942 #endif 1943 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1944 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1945 #define __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1946 #if defined(TSC) 1947 #define __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) 1948 #endif 1949 1950 #define __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1951 #if defined(DMA2) 1952 #define __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1953 #endif 1954 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1955 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1956 1957 #define __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1958 #if defined(TSC) 1959 #define __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) 1960 #endif 1961 1962 /** 1963 * @} 1964 */ 1965 1966 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 1967 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 1968 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1969 * power consumption. 1970 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1971 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1972 * @{ 1973 */ 1974 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 1975 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 1976 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 1977 #if defined(GPIOD) 1978 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) 1979 #endif 1980 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) 1981 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 1982 #if defined(ADC_SUPPORT_5_MSPS) 1983 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) 1984 #endif 1985 #if defined(AES1) 1986 #define __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) 1987 #endif 1988 1989 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 1990 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 1991 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 1992 #if defined(GPIOD) 1993 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) 1994 #endif 1995 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) 1996 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 1997 #if defined(ADC_SUPPORT_5_MSPS) 1998 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) 1999 #endif 2000 #if defined(AES1) 2001 #define __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) 2002 #endif 2003 2004 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 2005 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 2006 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 2007 #if defined(GPIOD) 2008 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 2009 #endif 2010 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 2011 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 2012 #if defined(ADC_SUPPORT_5_MSPS) 2013 #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) 2014 #endif 2015 #if defined(AES1) 2016 #define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) 2017 #endif 2018 2019 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 2020 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 2021 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 2022 #if defined(GPIOD) 2023 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 2024 #endif 2025 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 2026 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 2027 #if defined(ADC_SUPPORT_5_MSPS) 2028 #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) 2029 #endif 2030 #if defined(AES1) 2031 #define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) 2032 #endif 2033 2034 /** 2035 * @} 2036 */ 2037 2038 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2039 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2040 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2041 * power consumption. 2042 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2043 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2044 * @{ 2045 */ 2046 #if defined(QUADSPI) 2047 #define __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) 2048 #endif 2049 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 2050 #define __HAL_RCC_AES2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) 2051 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 2052 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 2053 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 2054 2055 #if defined(QUADSPI) 2056 #define __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) 2057 #endif 2058 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 2059 #define __HAL_RCC_AES2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) 2060 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 2061 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 2062 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 2063 2064 #define __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 2065 #define __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2) 2066 #define __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 2067 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 2068 #define __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 2069 2070 #define __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 2071 #define __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2) 2072 #define __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 2073 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 2074 #define __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 2075 2076 /** 2077 * @} 2078 */ 2079 2080 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2081 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2082 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2083 * power consumption. 2084 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2085 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2086 * @{ 2087 */ 2088 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 2089 #if defined(LCD) 2090 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD) 2091 #endif 2092 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 2093 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 2094 #if defined(SPI2) 2095 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 2096 #endif 2097 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 2098 #if defined(I2C3) 2099 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 2100 #endif 2101 #if defined(CRS) 2102 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS) 2103 #endif 2104 #if defined(USB) 2105 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB) 2106 #endif 2107 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 2108 #if defined(LPUART1) 2109 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 2110 #endif 2111 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 2112 2113 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 2114 #if defined(LCD) 2115 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD) 2116 #endif 2117 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 2118 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 2119 #if defined(SPI2) 2120 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 2121 #endif 2122 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 2123 #if defined(I2C3) 2124 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 2125 #endif 2126 #if defined(CRS) 2127 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS) 2128 #endif 2129 #if defined(USB) 2130 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB) 2131 #endif 2132 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 2133 #if defined(LPUART1) 2134 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 2135 #endif 2136 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 2137 2138 #define __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 2139 #if defined(LCD) 2140 #define __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) 2141 #endif 2142 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 2143 #if defined(SPI2) 2144 #define __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 2145 #endif 2146 #define __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 2147 #if defined(I2C3) 2148 #define __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 2149 #endif 2150 #if defined(CRS) 2151 #define __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) 2152 #endif 2153 #if defined(USB) 2154 #define __HAL_RCC_C2USB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) 2155 #endif 2156 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 2157 #if defined(LPUART1) 2158 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 2159 #endif 2160 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 2161 2162 #define __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 2163 #if defined(LCD) 2164 #define __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) 2165 #endif 2166 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 2167 #if defined(SPI2) 2168 #define __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 2169 #endif 2170 #define __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 2171 #if defined(I2C3) 2172 #define __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 2173 #endif 2174 #if defined(CRS) 2175 #define __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) 2176 #endif 2177 #if defined(USB) 2178 #define __HAL_RCC_C2USB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) 2179 #endif 2180 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 2181 #if defined(LPUART1) 2182 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 2183 #endif 2184 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 2185 2186 /** 2187 * @} 2188 */ 2189 2190 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2191 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2192 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2193 * power consumption. 2194 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2195 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2196 * @{ 2197 */ 2198 #if defined(ADC_SUPPORT_2_5_MSPS) 2199 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC) 2200 #endif 2201 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 2202 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 2203 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 2204 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 2205 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 2206 #if defined(SAI1) 2207 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) 2208 #endif 2209 2210 #if defined(ADC_SUPPORT_2_5_MSPS) 2211 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC) 2212 #endif 2213 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 2214 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 2215 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 2216 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 2217 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 2218 #if defined(SAI1) 2219 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) 2220 #endif 2221 2222 #if defined(ADC_SUPPORT_2_5_MSPS) 2223 #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) 2224 #endif 2225 #define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 2226 #define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 2227 #define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 2228 #define __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 2229 #define __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 2230 #if defined(SAI1) 2231 #define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) 2232 #endif 2233 2234 #if defined(ADC_SUPPORT_2_5_MSPS) 2235 #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) 2236 #endif 2237 #define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 2238 #define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 2239 #define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 2240 #define __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 2241 #define __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 2242 #if defined(SAI1) 2243 #define __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) 2244 #endif 2245 /** 2246 * @} 2247 */ 2248 2249 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 2250 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2251 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2252 * power consumption. 2253 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2254 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2255 * @{ 2256 */ 2257 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) 2258 #if defined(DMA2) 2259 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) 2260 #endif 2261 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) 2262 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) 2263 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) 2264 #if defined(TSC) 2265 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) 2266 #endif 2267 2268 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) 2269 #if defined(DMA2) 2270 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) 2271 #endif 2272 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) 2273 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) 2274 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) 2275 #if defined(TSC) 2276 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) 2277 #endif 2278 2279 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET) 2280 #if defined(DMA2) 2281 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET) 2282 #endif 2283 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET) 2284 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET) 2285 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET) 2286 #if defined(TSC) 2287 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET) 2288 #endif 2289 2290 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET) 2291 #if defined(DMA2) 2292 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET) 2293 #endif 2294 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET) 2295 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET) 2296 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET) 2297 #if defined(TSC) 2298 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET) 2299 #endif 2300 /** 2301 * @} 2302 */ 2303 2304 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 2305 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2306 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2307 * power consumption. 2308 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2309 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2310 * @{ 2311 */ 2312 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) 2313 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) 2314 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) 2315 #if defined(GPIOD) 2316 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) 2317 #endif 2318 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) 2319 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) 2320 #if defined(ADC_SUPPORT_5_MSPS) 2321 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) 2322 #endif 2323 #if defined(AES1) 2324 #define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET) 2325 #endif 2326 2327 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) 2328 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) 2329 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) 2330 #if defined(GPIOD) 2331 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) 2332 #endif 2333 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) 2334 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) 2335 #if defined(ADC_SUPPORT_5_MSPS) 2336 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) 2337 #endif 2338 #if defined(AES1) 2339 #define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET) 2340 #endif 2341 2342 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET) 2343 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET) 2344 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET) 2345 #if defined(GPIOD) 2346 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET) 2347 #endif 2348 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET) 2349 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET) 2350 #if defined(ADC_SUPPORT_5_MSPS) 2351 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET) 2352 #endif 2353 #if defined(AES1) 2354 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET) 2355 #endif 2356 2357 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET) 2358 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET) 2359 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET) 2360 #if defined(GPIOD) 2361 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET) 2362 #endif 2363 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET) 2364 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET) 2365 #if defined(ADC_SUPPORT_5_MSPS) 2366 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET) 2367 #endif 2368 #if defined(AES1) 2369 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET) 2370 #endif 2371 /** 2372 * @} 2373 */ 2374 2375 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 2376 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2377 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2378 * power consumption. 2379 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2380 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2381 * @{ 2382 */ 2383 #if defined(QUADSPI) 2384 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET) 2385 #endif 2386 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET) 2387 #define __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET) 2388 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET) 2389 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET) 2390 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET) 2391 2392 #if defined(QUADSPI) 2393 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET) 2394 #endif 2395 #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET) 2396 #define __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET) 2397 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET) 2398 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) == RESET) 2399 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) == RESET) 2400 2401 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) != RESET) 2402 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) != RESET) 2403 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) != RESET) 2404 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) != RESET) 2405 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) != RESET) 2406 2407 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) == RESET) 2408 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) == RESET) 2409 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) == RESET) 2410 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) == RESET) 2411 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) == RESET) 2412 2413 /** 2414 * @} 2415 */ 2416 2417 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 2418 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2419 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2420 * power consumption. 2421 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2422 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2423 * @{ 2424 */ 2425 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) 2426 #if defined(LCD) 2427 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) 2428 #endif 2429 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) 2430 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) 2431 #if defined(SPI2) 2432 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) 2433 #endif 2434 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) 2435 #if defined(I2C3) 2436 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) 2437 #endif 2438 #if defined(CRS) 2439 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) 2440 #endif 2441 #if defined(USB) 2442 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != RESET) 2443 #endif 2444 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) 2445 #if defined(LPUART1) 2446 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) 2447 #endif 2448 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) 2449 2450 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) 2451 #if defined(LCD) 2452 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) 2453 #endif 2454 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) 2455 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) 2456 #if defined(SPI2) 2457 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) 2458 #endif 2459 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) 2460 #if defined(I2C3) 2461 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) 2462 #endif 2463 #if defined(CRS) 2464 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) 2465 #endif 2466 #if defined(USB) 2467 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == RESET) 2468 #endif 2469 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) 2470 #if defined(LPUART1) 2471 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) 2472 #endif 2473 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) 2474 2475 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET) 2476 #if defined(LCD) 2477 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) != RESET) 2478 #endif 2479 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) != RESET) 2480 #if defined(SPI2) 2481 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET) 2482 #endif 2483 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET) 2484 #if defined(I2C3) 2485 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET) 2486 #endif 2487 #if defined(CRS) 2488 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) != RESET) 2489 #endif 2490 #if defined(USB) 2491 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) != RESET) 2492 #endif 2493 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) != RESET) 2494 #if defined(LPUART1) 2495 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) != RESET) 2496 #endif 2497 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) != RESET) 2498 2499 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET) 2500 #if defined(LCD) 2501 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) == RESET) 2502 #endif 2503 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) == RESET) 2504 #if defined(SPI2) 2505 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET) 2506 #endif 2507 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET) 2508 #if defined(I2C3) 2509 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET) 2510 #endif 2511 #if defined(CRS) 2512 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) == RESET) 2513 #endif 2514 #if defined(USB) 2515 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) == RESET) 2516 #endif 2517 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) == RESET) 2518 #if defined(LPUART1) 2519 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) == RESET) 2520 #endif 2521 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) == RESET) 2522 /** 2523 * @} 2524 */ 2525 2526 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 2527 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2528 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2529 * power consumption. 2530 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2531 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2532 * @{ 2533 */ 2534 #if defined(ADC_SUPPORT_2_5_MSPS) 2535 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) != RESET) 2536 #endif 2537 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) 2538 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) 2539 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) 2540 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) 2541 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) 2542 #if defined(SAI1) 2543 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) 2544 #endif 2545 2546 #if defined(ADC_SUPPORT_2_5_MSPS) 2547 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) == RESET) 2548 #endif 2549 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) 2550 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) 2551 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) 2552 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) 2553 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) 2554 #if defined(SAI1) 2555 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) 2556 #endif 2557 2558 #if defined(ADC_SUPPORT_2_5_MSPS) 2559 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) != RESET) 2560 #endif 2561 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET) 2562 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET) 2563 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET) 2564 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET) 2565 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET) 2566 #if defined(SAI1) 2567 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET) 2568 #endif 2569 2570 #if defined(ADC_SUPPORT_2_5_MSPS) 2571 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) == RESET) 2572 #endif 2573 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET) 2574 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET) 2575 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET) 2576 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET) 2577 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET) 2578 #if defined(SAI1) 2579 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET) 2580 #endif 2581 /** 2582 * @} 2583 */ 2584 2585 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 2586 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. 2587 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2588 * power consumption. 2589 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2590 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2591 * @{ 2592 */ 2593 #define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) 2594 #if defined(RCC_802_SUPPORT) 2595 #define __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) 2596 #endif 2597 2598 #define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) 2599 #if defined(RCC_802_SUPPORT) 2600 #define __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) 2601 #endif 2602 /** 2603 * @} 2604 */ 2605 2606 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable_Status APB3 Peripheral Clock Sleep Enabled or Disabled Status 2607 * @brief Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2608 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2609 * power consumption. 2610 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2611 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2612 * @{ 2613 */ 2614 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET) 2615 #if defined(RCC_802_SUPPORT) 2616 #define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET) 2617 #endif 2618 2619 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET) 2620 #if defined(RCC_802_SUPPORT) 2621 #define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET) 2622 #endif 2623 /** 2624 * @} 2625 */ 2626 2627 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2628 * @{ 2629 */ 2630 2631 /** @brief Macros to force or release the Backup domain reset. 2632 * @note This function resets the RTC peripheral (including the backup registers) 2633 * and the RTC clock source selection in RCC_CSR register. 2634 * @note The BKPSRAM is not affected by this reset. 2635 * @retval None 2636 */ 2637 #define __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset() 2638 #define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset() 2639 2640 /** 2641 * @} 2642 */ 2643 2644 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2645 * @{ 2646 */ 2647 2648 /** @brief Macros to enable or disable the RTC clock. 2649 * @note As the RTC is in the Backup domain and write access is denied to 2650 * this domain after reset, you have to enable write access using 2651 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2652 * (to be done once after reset). 2653 * @note These macros must be used after the RTC clock source was selected. 2654 * @retval None 2655 */ 2656 #define __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC() 2657 #define __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC() 2658 2659 /** 2660 * @} 2661 */ 2662 2663 /** @brief Macros to enable the Internal High Speed oscillator (HSI). 2664 * @note The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes. 2665 * It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1 2666 * or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE 2667 * crystal oscillator and Security System CSS is enabled. 2668 * @note After enabling the HSI, the application software should wait on HSIRDY 2669 * flag to be set indicating that HSI clock is stable and can be used as 2670 * system clock source. 2671 * @retval None 2672 */ 2673 #define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() 2674 2675 /** @brief Macro to disable the Internal High Speed oscillator (HSI). 2676 * @note HSI can not be stopped if it is used as system clock source. In this case, 2677 * you have to select another source of the system clock then stop the HSI. 2678 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2679 * clock cycles. 2680 * @retval None 2681 */ 2682 #define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable() 2683 2684 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 2685 * @note The calibration is used to compensate for the variations in voltage 2686 * and temperature that influence the frequency of the internal HSI RC. 2687 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2688 * (default is RCC_HSICALIBRATION_DEFAULT). 2689 * This parameter must be a number between Min_data=0 and Max_Data=127. 2690 * @retval None 2691 */ 2692 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__) 2693 2694 /** 2695 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 2696 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 2697 * @note The enable of this function has not effect on the HSION bit. 2698 * This parameter can be: ENABLE or DISABLE. 2699 * @retval None 2700 */ 2701 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() LL_RCC_HSI_EnableAutoFromStop() 2702 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() LL_RCC_HSI_DisableAutoFromStop() 2703 2704 /** 2705 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2706 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2707 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2708 * speed because of the HSI startup time. 2709 * @note The enable of this function has not effect on the HSION bit. 2710 * @retval None 2711 */ 2712 #define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() 2713 #define __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode() 2714 2715 /** 2716 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 2717 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 2718 * It is used (enabled by hardware) as system clock source after 2719 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2720 * of failure of the HSE used directly or indirectly as system clock 2721 * (if the Clock Security System CSS is enabled). 2722 * @note MSI can not be stopped if it is used as system clock source. 2723 * In this case, you have to select another source of the system 2724 * clock then stop the MSI. 2725 * @note After enabling the MSI, the application software should wait on 2726 * MSIRDY flag to be set indicating that MSI clock is stable and can 2727 * be used as system clock source. 2728 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 2729 * clock cycles. 2730 * @retval None 2731 */ 2732 #define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() 2733 #define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() 2734 2735 /** @brief Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. 2736 * @note The calibration is used to compensate for the variations in voltage 2737 * and temperature that influence the frequency of the internal MSI RC. 2738 * Refer to the Application Note AN3300 for more details on how to 2739 * calibrate the MSI. 2740 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 2741 * (default is @ref RCC_MSICALIBRATION_DEFAULT). 2742 * This parameter must be a number between 0 and 255. 2743 * @retval None 2744 */ 2745 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__) 2746 2747 /** 2748 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 2749 * @note After restart from Reset , the MSI clock is around 4 MHz. 2750 * After stop the startup clock can be MSI (at any of its possible 2751 * frequencies, the one that was used before entering stop mode) or HSI. 2752 * After Standby its frequency can be selected between 4 possible values 2753 * (1, 2, 4 or 8 MHz). 2754 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 2755 * (MSIRDY=1). 2756 * @note The MSI clock range after reset can be modified on the fly. 2757 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 2758 * This parameter must be one of the following values: 2759 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 2760 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 2761 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 2762 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 2763 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2764 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz 2765 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset) 2766 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2767 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2768 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2769 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2770 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2771 * @retval None 2772 */ 2773 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) LL_RCC_MSI_SetRange(__MSIRANGEVALUE__) 2774 2775 2776 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 2777 * @retval MSI clock range. 2778 * This parameter must be one of the following values: 2779 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 2780 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 2781 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 2782 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 2783 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2784 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2785 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2786 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2787 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2788 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2789 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2790 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2791 */ 2792 #define __HAL_RCC_GET_MSI_RANGE() LL_RCC_MSI_GetRange() 2793 2794 2795 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI1). 2796 * @note After enabling the LSI1, the application software should wait on 2797 * LSI1RDY flag to be set indicating that LSI1 clock is stable and can 2798 * be used to clock the IWDG and/or the RTC. 2799 * @retval None 2800 */ 2801 #define __HAL_RCC_LSI1_ENABLE() LL_RCC_LSI1_Enable() 2802 #define __HAL_RCC_LSI1_DISABLE() LL_RCC_LSI1_Disable() 2803 2804 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI2). 2805 * @note After enabling the LSI2, the application software should wait on 2806 * LSI2RDY flag to be set indicating that LSI2 clock is stable and can 2807 * be used to clock the IWDG and/or the RTC. 2808 * @retval None 2809 */ 2810 #define __HAL_RCC_LSI2_ENABLE() LL_RCC_LSI2_Enable() 2811 #define __HAL_RCC_LSI2_DISABLE() LL_RCC_LSI2_Disable() 2812 2813 /** @brief Macro to adjust the Internal Low Speed oscillator (LSI2) calibration value. 2814 * @note The calibration is used to compensate for the variations in voltage 2815 * and temperature that influence the frequency of the internal HSI RC. 2816 * @param __LSI2TRIMMINGVALUE__ specifies the calibration trimming value 2817 * This parameter must be a number between Min_data=0 and Max_Data=15. 2818 * @retval None 2819 */ 2820 #define __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(__LSI2TRIMMINGVALUE__) LL_RCC_LSI2_SetTrimming(__LSI2TRIMMINGVALUE__) 2821 2822 /** 2823 * @brief Macro to configure the External High Speed oscillator (HSE). 2824 * @note After enabling the HSE (RCC_HSE_ON), the application 2825 * software should wait on HSERDY flag to be set indicating that HSE clock 2826 * is stable and can be used to clock the PLL and/or system clock. 2827 * @note HSE state can not be changed if it is used directly or through the 2828 * PLL as system clock. In this case, you have to select another source 2829 * of the system clock then change the HSE state (ex. disable it). 2830 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2831 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2832 * was previously enabled you have to enable it again after calling this 2833 * function. 2834 * @param __STATE__ specifies the new state of the HSE. 2835 * This parameter can be one of the following values: 2836 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2837 * 6 HSE oscillator clock cycles. 2838 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2839 * @note (*) Value not defined for all devices 2840 * @retval None 2841 */ 2842 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 2843 do { \ 2844 if((__STATE__) == RCC_HSE_ON) \ 2845 { \ 2846 LL_RCC_HSE_Enable(); \ 2847 } \ 2848 else \ 2849 { \ 2850 LL_RCC_HSE_Disable(); \ 2851 } \ 2852 } while(0U) 2853 2854 /** @brief Macros to enable or disable the HSE Prescaler 2855 * @note HSE div2 could be used as Sysclk or PLL entry in Range2 2856 * @retval None 2857 */ 2858 #define __HAL_RCC_HSE_DIV2_ENABLE() LL_RCC_HSE_EnableDiv2() 2859 #define __HAL_RCC_HSE_DIV2_DISABLE() LL_RCC_HSE_DisableDiv2() 2860 2861 /** 2862 * @brief Macro to configure the External Low Speed oscillator (LSE). 2863 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2864 * supported by this macro. User should request a transition to LSE Off 2865 * first and then LSE On or LSE Bypass. 2866 * @note As the LSE is in the Backup domain and write access is denied to 2867 * this domain after reset, you have to enable write access using 2868 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2869 * (to be done once after reset). 2870 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2871 * software should wait on LSERDY flag to be set indicating that LSE clock 2872 * is stable and can be used to clock the RTC. 2873 * @param __STATE__ specifies the new state of the LSE. 2874 * This parameter can be one of the following values: 2875 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2876 * 6 LSE oscillator clock cycles. 2877 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2878 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2879 * @retval None 2880 */ 2881 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 2882 do { \ 2883 if((__STATE__) == RCC_LSE_ON) \ 2884 { \ 2885 LL_RCC_LSE_Enable(); \ 2886 } \ 2887 else if((__STATE__) == RCC_LSE_BYPASS) \ 2888 { \ 2889 LL_RCC_LSE_EnableBypass(); \ 2890 LL_RCC_LSE_Enable(); \ 2891 } \ 2892 else \ 2893 { \ 2894 LL_RCC_LSE_Disable(); \ 2895 LL_RCC_LSE_DisableBypass(); \ 2896 } \ 2897 } while(0U) 2898 2899 2900 #if defined(RCC_HSI48_SUPPORT) 2901 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 2902 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 2903 * @note After enabling the HSI48, the application software should wait on HSI48RDY 2904 * flag to be set indicating that HSI48 clock is stable. 2905 * This parameter can be: ENABLE or DISABLE. 2906 * @retval None 2907 */ 2908 #define __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable() 2909 #define __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable() 2910 #endif 2911 2912 /** @brief Macros to configure HSE sense amplifier threshold. 2913 * @note to configure HSE sense amplifier, first disable HSE 2914 * using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2915 * 2916 * @param __HSE_AMPTHRES__ specifies the HSE sense amplifier threshold. 2917 * This parameter can be one of the following values: 2918 * @arg @ref RCC_HSEAMPTHRESHOLD_1_2 HSE bias current factor 1/2. 2919 * @arg @ref RCC_HSEAMPTHRESHOLD_3_4 HSE bias current factor 3/4. 2920 * @retval None 2921 */ 2922 #define __HAL_RCC_HSE_AMPCONFIG(__HSE_AMPTHRES__) LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__) 2923 2924 /** @brief Macros to configure HSE current control. 2925 * @note to configure HSE current control, first disable HSE 2926 * using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2927 * 2928 * @param __HSE_CURRENTMAX__ specifies the HSE current max limit. 2929 * This parameter can be one of the following values: 2930 * @arg @ref RCC_HSE_CURRENTMAX_0 HSE current max limit 0.18 mA/V. 2931 * @arg @ref RCC_HSE_CURRENTMAX_1 HSE current max limit 0.57 mA/V. 2932 * @arg @ref RCC_HSE_CURRENTMAX_2 HSE current max limit 0.78 mA/V. 2933 * @arg @ref RCC_HSE_CURRENTMAX_3 HSE current max limit 1.13 mA/V. 2934 * @arg @ref RCC_HSE_CURRENTMAX_4 HSE current max limit 0.61 mA/V. 2935 * @arg @ref RCC_HSE_CURRENTMAX_5 HSE current max limit 1.65 mA/V. 2936 * @arg @ref RCC_HSE_CURRENTMAX_6 HSE current max limit 2.12 mA/V. 2937 * @arg @ref RCC_HSE_CURRENTMAX_7 HSE current max limit 2.84 mA/V. 2938 * @retval None 2939 */ 2940 #define __HAL_RCC_HSE_CURRENTCONFIG(__HSE_CURRENTMAX__) LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__) 2941 2942 /** @brief Macros to configure HSE capacitor tuning. 2943 * @note to configure HSE current control, first disable HSE 2944 * using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2945 * 2946 * @param __HSE_LOAD_CAPACITANCE__ specifies the HSE capacitor value. 2947 * This Value Between Min_Data = 0 and Max_Data = 63 2948 * @retval None 2949 */ 2950 #define __HAL_RCC_HSE_CAPACITORTUNING(__HSE_LOAD_CAPACITANCE__) LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__) 2951 2952 2953 /** @brief Macros to configure the RTC clock (RTCCLK). 2954 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2955 * This parameter can be one of the following values: 2956 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 2957 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2958 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2959 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2960 * @note As the RTC clock configuration bits are in the Backup domain and write 2961 * access is denied to this domain after reset, you have to enable write 2962 * access using the Power Backup Access macro before to configure 2963 * the RTC clock source (to be done once after reset). 2964 * @note Once the RTC clock is configured it cannot be changed unless the 2965 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2966 * a Power On Reset (POR). 2967 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2968 * work in STOP and STANDBY modes, and can be used as wakeup source. 2969 * However, when the HSE clock is used as RTC clock source, the RTC 2970 * cannot be used in STOP and STANDBY modes. 2971 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2972 * RTC clock source). 2973 * @retval None 2974 */ 2975 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__) 2976 2977 /** @brief Macro to get the RTC clock source. 2978 * @retval The returned value can be one of the following: 2979 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 2980 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2981 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2982 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2983 */ 2984 #define __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource() 2985 2986 /** @brief Macros to enable or disable the main PLL. 2987 * @note After enabling the main PLL, the application software should wait on 2988 * PLLRDY flag to be set indicating that PLL clock is stable and can 2989 * be used as system clock source. 2990 * @note The main PLL can not be disabled if it is used as system clock source 2991 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 2992 * @retval None 2993 */ 2994 #define __HAL_RCC_PLL_ENABLE() LL_RCC_PLL_Enable() 2995 #define __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable() 2996 2997 /** @brief Macro to configure the PLL clock source. 2998 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2999 * This parameter can be one of the following values: 3000 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3001 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3002 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3003 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3004 * @note This function must be used only when the main PLL is disabled. 3005 * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). 3006 * @retval None 3007 * 3008 */ 3009 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 3010 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 3011 3012 /** @brief Macro to configure the PLL multiplication factor. 3013 * @note This function must be used only when the main PLL is disabled. 3014 * @param __PLLM__ specifies the division factor for PLL VCO input clock 3015 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 3016 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3017 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 3018 * of 16 MHz to limit PLL jitter. 3019 * @retval None 3020 * 3021 */ 3022 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 3023 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 3024 3025 /** 3026 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 3027 * @note This function must be used only when the main PLL is disabled. 3028 * 3029 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3030 * This parameter can be one of the following values: 3031 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3032 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3033 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3034 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3035 * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). 3036 * 3037 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 3038 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 3039 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3040 * frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency 3041 * of 16 MHz to limit PLL jitter. 3042 * 3043 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 3044 * This parameter must be a number between 6 and 127. 3045 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3046 * output frequency is between 96 and 344 MHz. 3047 * 3048 * @param __PLLP__ specifies the division factor for ADC and SAI1 clock. 3049 * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. 3050 * 3051 * @param __PLLQ__ specifies the division factor for USB and RNG clocks. 3052 * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider 3053 * @note If the USB FS is used in your application, you have to set the 3054 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 3055 * the RNG need a frequency lower than or equal to 48 MHz to work 3056 * correctly. 3057 * 3058 * @param __PLLR__ specifies the division factor for the main system clock. 3059 * This parameter must be a value of @ref RCC_PLLR_Clock_Divider 3060 * @note You have to set the PLLR parameter correctly to not exceed 48 MHZ. 3061 * @retval None 3062 */ 3063 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 3064 MODIFY_REG( RCC->PLLCFGR, \ 3065 (RCC_PLLCFGR_PLLSRC | \ 3066 RCC_PLLCFGR_PLLM | \ 3067 RCC_PLLCFGR_PLLN | \ 3068 RCC_PLLCFGR_PLLP | \ 3069 RCC_PLLCFGR_PLLQ | \ 3070 RCC_PLLCFGR_PLLR), \ 3071 ((uint32_t) (__PLLSOURCE__) | \ 3072 (uint32_t) (__PLLM__) | \ 3073 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 3074 (uint32_t) (__PLLP__) | \ 3075 (uint32_t) (__PLLQ__) | \ 3076 (uint32_t) (__PLLR__))) 3077 3078 /** @brief Macro to get the oscillator used as PLL clock source. 3079 * @retval The oscillator used as PLL clock source. The returned value can be one 3080 * of the following: 3081 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 3082 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3083 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3084 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3085 */ 3086 #define __HAL_RCC_GET_PLL_OSCSOURCE() LL_RCC_PLL_GetMainSource() 3087 3088 /** 3089 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK) 3090 * @note Enabling/disabling clock outputs RCC_PLL_SAI1CLK and RCC_PLL_USBCLK can be done at anytime 3091 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 3092 * be stopped if used as System Clock. 3093 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 3094 * This parameter can be one or a combination of the following values: 3095 * @arg @ref RCC_PLL_SAI1CLK This clock is used to generate the clock for SAI 3096 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate the clock for ADC 3097 * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) 3098 * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG 3099 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) 3100 * @retval None 3101 */ 3102 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3103 3104 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3105 3106 /** 3107 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK) 3108 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 3109 * This parameter can be one of the following values: 3110 * @arg @ref RCC_PLL_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 3111 * @arg @ref RCC_PLL_ADCCLK same 3112 * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) 3113 * @arg @ref RCC_PLL_RNGCLK same 3114 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) 3115 * @retval SET / RESET 3116 */ 3117 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3118 3119 /** 3120 * @brief Macro to configure the system clock source. 3121 * @param __SYSCLKSOURCE__ specifies the system clock source. 3122 * This parameter can be one of the following values: 3123 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 3124 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 3125 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 3126 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 3127 * @retval None 3128 */ 3129 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__) 3130 3131 /** @brief Macro to get the clock source used as system clock. 3132 * @retval The clock source used as system clock. The returned value can be one 3133 * of the following: 3134 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock. 3135 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 3136 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 3137 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. 3138 */ 3139 #define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource() 3140 3141 /** 3142 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3143 * @note As the LSE is in the Backup domain and write access is denied to 3144 * this domain after reset, you have to enable write access using 3145 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3146 * (to be done once after reset). 3147 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 3148 * This parameter can be one of the following values: 3149 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3150 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3151 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3152 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3153 * @retval None 3154 */ 3155 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__) 3156 3157 /** 3158 * @brief Macro to configure the wake up from stop clock. 3159 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 3160 * This parameter can be one of the following values: 3161 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 3162 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 3163 * @retval None 3164 */ 3165 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__) 3166 3167 3168 /** @brief Macro to configure the MCO clock. 3169 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 3170 * This parameter can be one of the following values: 3171 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 3172 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 3173 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 3174 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 3175 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 3176 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 3177 * @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source 3178 * @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source 3179 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3180 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source (*) 3181 * 3182 * @param __MCODIV__ specifies the MCO clock prescaler. 3183 * This parameter can be one of the following values: 3184 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3185 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3186 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3187 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3188 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3189 * 3190 * @note (*) Value not defined for all devices 3191 */ 3192 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__)) 3193 3194 3195 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3196 * @brief macros to manage the specified RCC Flags and interrupts. 3197 * @{ 3198 */ 3199 3200 /** @brief Enable RCC interrupt. 3201 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 3202 * This parameter can be any combination of the following values: 3203 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt enable 3204 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 3205 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 3206 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 3207 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 3208 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 3209 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable 3210 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 3211 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*) 3212 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable 3213 * 3214 * @note (*) Value not defined for all devices 3215 * 3216 * @retval None 3217 */ 3218 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3219 3220 /** @brief Disable RCC interrupt. 3221 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 3222 * This parameter can be any combination of the following values: 3223 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt enable 3224 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 3225 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 3226 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 3227 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 3228 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 3229 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable 3230 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 3231 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*) 3232 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable 3233 * 3234 * @note (*) Value not defined for all devices 3235 * 3236 * @retval None 3237 */ 3238 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3239 3240 /** @brief Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] 3241 * bits to clear the selected interrupt pending bits. 3242 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3243 * This parameter can be any combination of the following values: 3244 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt clear 3245 * @arg @ref RCC_IT_LSERDY LSE ready interrupt clear 3246 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt clear 3247 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt clear 3248 * @arg @ref RCC_IT_HSERDY HSE ready interrupt clear 3249 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt clear 3250 * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt clear 3251 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear 3252 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear 3253 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt clear (*) 3254 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt clear 3255 * 3256 * @note (*) Value not defined for all devices 3257 */ 3258 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 3259 3260 /** @brief Check whether the RCC interrupt has occurred or not. 3261 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 3262 * This parameter can be one of the following values: 3263 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt flag 3264 * @arg @ref RCC_IT_LSERDY LSE ready interrupt flag 3265 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt flag 3266 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt flag 3267 * @arg @ref RCC_IT_HSERDY HSE ready interrupt flag 3268 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt flag 3269 * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt flag 3270 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag 3271 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag 3272 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt flag (*) 3273 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt flag 3274 * 3275 * @note (*) Value not defined for all devices 3276 * 3277 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 3278 */ 3279 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 3280 3281 /** @brief Set RMVF bit to clear the reset flags. 3282 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3283 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3284 * @retval None 3285 */ 3286 #define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags() 3287 3288 /** @brief Check whether the selected RCC flag is set or not. 3289 * @param __FLAG__ specifies the flag to check. 3290 * This parameter can be one of the following values: 3291 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 3292 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3293 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3294 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 3295 * @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready 3296 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 (*) 3297 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3298 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3299 * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready 3300 * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready 3301 * @arg @ref RCC_FLAG_BORRST BOR reset 3302 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3303 * @arg @ref RCC_FLAG_PINRST Pin reset 3304 * @arg @ref RCC_FLAG_SFTRST Software reset 3305 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3306 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3307 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3308 * 3309 * @note (*) Value not defined for all devices 3310 * 3311 * @retval The new state of __FLAG__ (TRUE or FALSE). 3312 */ 3313 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 3314 ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ 3315 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 3316 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ 3317 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ 3318 ? 1U : 0U) 3319 3320 /** 3321 * @} 3322 */ 3323 3324 /** 3325 * @} 3326 */ 3327 3328 /* Include RCC HAL Extended module */ 3329 #include "stm32wbxx_hal_rcc_ex.h" 3330 3331 /* Exported functions --------------------------------------------------------*/ 3332 /** @addtogroup RCC_Exported_Functions 3333 * @{ 3334 */ 3335 3336 3337 /** @addtogroup RCC_Exported_Functions_Group1 3338 * @{ 3339 */ 3340 3341 /* Initialization and de-initialization functions ******************************/ 3342 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3343 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3344 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 3345 3346 /** 3347 * @} 3348 */ 3349 3350 /** @addtogroup RCC_Exported_Functions_Group2 3351 * @{ 3352 */ 3353 3354 /* Peripheral Control functions ************************************************/ 3355 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3356 void HAL_RCC_EnableCSS(void); 3357 uint32_t HAL_RCC_GetSysClockFreq(void); 3358 3359 uint32_t HAL_RCC_GetHCLKFreq(void); 3360 uint32_t HAL_RCC_GetHCLK2Freq(void); 3361 uint32_t HAL_RCC_GetHCLK4Freq(void); 3362 3363 uint32_t HAL_RCC_GetPCLK1Freq(void); 3364 uint32_t HAL_RCC_GetPCLK2Freq(void); 3365 3366 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3367 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3368 /* LSE & HSE CSS NMI IRQ handler */ 3369 void HAL_RCC_NMI_IRQHandler(void); 3370 /* User Callbacks in non blocking mode (IT mode) */ 3371 void HAL_RCC_CSSCallback(void); 3372 3373 uint32_t HAL_RCC_GetResetSource(void); 3374 /** 3375 * @} 3376 */ 3377 3378 /** 3379 * @} 3380 */ 3381 3382 /** 3383 * @} 3384 */ 3385 3386 /** 3387 * @} 3388 */ 3389 3390 #ifdef __cplusplus 3391 } 3392 #endif 3393 3394 #endif /* STM32WBxx_HAL_RCC_H */ 3395 3396 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3397 3398
