1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_RCC_EX_H 21 #define STM32U5xx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief PLL2 Clock structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. 49 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 50 51 uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. 52 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 53 54 uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. 55 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 56 57 uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. 58 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 59 60 uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. 61 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 62 63 uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 65 66 uint32_t PLL2RGE; /*!< PLL2RGE: PLL2 clock Input range 67 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 68 69 uint32_t PLL2FRACN; /*!< PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for 70 PLL2 VCO It should be a value between 0 and 8191 */ 71 72 uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled. 73 This parameter must be a value of @ref RCC_PLL2_Clock_Output */ 74 } RCC_PLL2InitTypeDef; 75 76 77 /** 78 * @brief PLL3 Clock structure definition 79 */ 80 typedef struct 81 { 82 uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source. 83 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 84 85 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. 86 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 87 88 uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. 89 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 90 91 uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. 92 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 93 94 uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. 95 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 96 97 uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. 98 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 99 100 uint32_t PLL3RGE; /*!< PLL3RGE: PLL3 clock Input range 101 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 102 103 uint32_t PLL3FRACN; /*!< PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for 104 PLL3 VCO It should be a value between 0 and 8191 */ 105 106 uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled. 107 This parameter must be a value of @ref RCC_PLL3_Clock_Output */ 108 } RCC_PLL3InitTypeDef; 109 110 /** 111 * @brief RCC PLL1 Clocks structure definition 112 */ 113 typedef struct 114 { 115 uint32_t PLL1_P_Frequency; 116 uint32_t PLL1_Q_Frequency; 117 uint32_t PLL1_R_Frequency; 118 } PLL1_ClocksTypeDef; 119 120 /** 121 * @brief RCC PLL2 Clocks structure definition 122 */ 123 typedef struct 124 { 125 uint32_t PLL2_P_Frequency; 126 uint32_t PLL2_Q_Frequency; 127 uint32_t PLL2_R_Frequency; 128 } PLL2_ClocksTypeDef; 129 130 /** 131 * @brief RCC PLL3 Clocks structure definition 132 */ 133 typedef struct 134 { 135 uint32_t PLL3_P_Frequency; 136 uint32_t PLL3_Q_Frequency; 137 uint32_t PLL3_R_Frequency; 138 } PLL3_ClocksTypeDef; 139 140 141 /** 142 * @brief RCC extended clocks structure definition 143 */ 144 typedef struct 145 { 146 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 147 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 148 149 RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. 150 This parameter will be used only when PLL2 is selected as kernel clock Source 151 for some peripherals */ 152 153 RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. 154 This parameter will be used only when PLL2 is selected as kernel clock Source 155 for some peripherals */ 156 157 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 158 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 159 160 #if defined(USART2) 161 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 162 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 163 #endif /* USART2 */ 164 165 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 166 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 167 168 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 169 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 170 171 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 172 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 173 174 #if defined(USART6) 175 uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. 176 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ 177 #endif /* USART6 */ 178 179 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 180 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 181 182 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 183 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 184 185 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 186 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 187 188 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 189 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 190 191 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 192 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 193 194 #if defined(I2C5) 195 uint32_t I2c5ClockSelection; /*!< Specifies I2C5 clock source. 196 This parameter can be a value of @ref RCCEx_I2C5_Clock_Source */ 197 #endif /* I2C5 */ 198 199 #if defined(I2C6) 200 uint32_t I2c6ClockSelection; /*!< Specifies I2C6 clock source. 201 This parameter can be a value of @ref RCCEx_I2C6_Clock_Source */ 202 #endif /* I2C6 */ 203 204 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 205 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 206 207 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 208 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 209 210 uint32_t Lptim34ClockSelection; /*!< Specifies LPTIM3 and LPTIM4 clock source. 211 This parameter can be a value of @ref RCCEx_LPTIM34_Clock_Source */ 212 213 uint32_t Fdcan1ClockSelection; /*!< Specifies FDCAN1 kernel clock source. 214 This parameter can be a value of @ref RCCEx_FDCAN1_Clock_Source */ 215 216 uint32_t Mdf1ClockSelection; /*!< Specifies MDF1 kernel clock source. 217 This parameter can be a value of @ref RCCEx_MDF1_Clock_Source */ 218 219 uint32_t Adf1ClockSelection; /*!< Specifies Adf1 kernel clock source. 220 This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ 221 222 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 223 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 224 225 #if defined (SAI2) 226 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 227 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 228 #endif /* SAI2 */ 229 230 uint32_t RngClockSelection; /*!< Specifies RNG clock source 231 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 232 233 #if defined(SAES) 234 uint32_t SaesClockSelection; /*!< Specifies SAES clock source 235 This parameter can be a value of @ref RCCEx_SAES_Clock_Source */ 236 #endif /* SAES */ 237 238 uint32_t IclkClockSelection; /*!< Specifies intermediate clock source used by USB, RNG and SDMMC1 239 This parameter can be a value of @ref RCCEx_ICLK_Clock_Source */ 240 241 uint32_t SdmmcClockSelection; /*!< Specifies SDMMC1/2 clock source. 242 This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ 243 244 uint32_t AdcDacClockSelection; /*!< Specifies ADC1, ADC4 and DAC interface clock source. 245 This parameter can be a value of @ref RCCEx_ADCDAC_Clock_Source */ 246 247 uint32_t Dac1ClockSelection; /*!< Specifies DAC1 interface clock source. 248 This parameter can be a value of @ref RCCEx_DAC1_Clock_Source */ 249 250 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 251 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 252 253 #if defined(HSPI1) 254 uint32_t HspiClockSelection; /*!< Specifies HexaSPI clock source. 255 This parameter can be a value of @ref RCCEx_HSPI_Clock_Source */ 256 #endif /* HSPI1 */ 257 258 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source 259 This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ 260 261 uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source 262 This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ 263 264 uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source 265 This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ 266 267 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 268 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 269 270 #if defined(LTDC) 271 uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. 272 This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ 273 #endif /* LTDC */ 274 275 #if defined(DSI) 276 uint32_t DsiClockSelection; /*!< Specifies DSI clock source. 277 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 278 #endif /* DSI */ 279 280 #if defined(USB_OTG_HS) 281 uint32_t UsbPhyClockSelection; /*!< Specifies USB PHY clock source. 282 This parameter can be a value of @ref RCCEx_USBPHY_Clock_Source */ 283 #endif /* USB_OTG_HS */ 284 285 } RCC_PeriphCLKInitTypeDef; 286 287 #if defined(CRS) 288 289 /** 290 * @brief RCC_CRS Init structure definition 291 */ 292 typedef struct 293 { 294 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 295 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 296 297 uint32_t Source; /*!< Specifies the SYNC signal source. 298 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 299 300 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 301 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 302 303 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC 304 event. It can be calculated in using macro 305 __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 306 This parameter must be a number between 0 and 0xFFFF or a value of 307 @ref RCCEx_CRS_ReloadValueDefault .*/ 308 309 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 310 This parameter must be a number between 0 and 0xFF or a value of 311 @ref RCCEx_CRS_ErrorLimitDefault */ 312 313 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 314 This parameter must be a number between 0 and 0x3F or a value of 315 @ref RCCEx_CRS_HSI48CalibrationDefault */ 316 317 } RCC_CRSInitTypeDef; 318 319 /** 320 * @brief RCC_CRS Synchronization structure definition 321 */ 322 typedef struct 323 { 324 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 325 This parameter must be a number between 0 and 0xFFFF */ 326 327 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 328 This parameter must be a number between 0 and 0x3F */ 329 330 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 331 value latched in the time of the last SYNC event. 332 This parameter must be a number between 0 and 0xFFFF */ 333 334 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 335 frequency error counter latched in the time of the last SYNC event. 336 It shows whether the actual frequency is below or above the target. 337 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 338 339 } RCC_CRSSynchroInfoTypeDef; 340 341 #endif /* CRS */ 342 /** 343 * @} 344 */ 345 346 347 /* Exported constants --------------------------------------------------------*/ 348 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 349 * @{ 350 */ 351 352 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 353 * @{ 354 */ 355 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 356 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 357 /** 358 * @} 359 */ 360 361 /** @defgroup RCCEx_MSI_Pll_Mode_Selection MSI Pll Mode Selection 362 * @{ 363 */ 364 #define RCC_MSIKPLL_MODE_SEL 0x00000000U /*!< PLL mode applied to MSIK (MSI kernel) clock output */ 365 #define RCC_MSISPLL_MODE_SEL RCC_CR_MSIPLLSEL /*!< PLL mode applied to MSIS (MSI system) clock output */ 366 /** 367 * @} 368 */ 369 370 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 371 * @{ 372 */ 373 #define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001U) 374 #if defined(USART2) 375 #define RCC_PERIPHCLK_USART2 ((uint64_t)0x00000002U) 376 #endif /* USART2 */ 377 #define RCC_PERIPHCLK_USART3 ((uint64_t)0x00000004U) 378 #define RCC_PERIPHCLK_UART4 ((uint64_t)0x00000008U) 379 #define RCC_PERIPHCLK_UART5 ((uint64_t)0x00000010U) 380 #define RCC_PERIPHCLK_LPUART1 ((uint64_t)0x00000020U) 381 #define RCC_PERIPHCLK_I2C1 ((uint64_t)0x00000040U) 382 #define RCC_PERIPHCLK_I2C2 ((uint64_t)0x00000080U) 383 #define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00000100U) 384 #define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00000200U) 385 #define RCC_PERIPHCLK_LPTIM2 ((uint64_t)0x00000400U) 386 #define RCC_PERIPHCLK_LPTIM34 ((uint64_t)0x00000800U) 387 #if defined(SAES) 388 #define RCC_PERIPHCLK_SAES ((uint64_t)0x00001000U) 389 #endif /* SAES */ 390 #define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00002000U) 391 #if defined(SAI2) 392 #define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00004000U) 393 #endif /* SAI2 */ 394 #define RCC_PERIPHCLK_ADCDAC ((uint64_t)0x00008000U) 395 #define RCC_PERIPHCLK_MDF1 ((uint64_t)0x00010000U) 396 #define RCC_PERIPHCLK_ADF1 ((uint64_t)0x00020000U) 397 #define RCC_PERIPHCLK_RTC ((uint64_t)0x00040000U) 398 #define RCC_PERIPHCLK_RNG ((uint64_t)0x00080000U) 399 #define RCC_PERIPHCLK_ICLK ((uint64_t)0x00100000U) 400 #define RCC_PERIPHCLK_SDMMC ((uint64_t)0x00200000U) 401 #define RCC_PERIPHCLK_I2C4 ((uint64_t)0x00400000U) 402 #define RCC_PERIPHCLK_SPI1 ((uint64_t)0x00800000U) 403 #define RCC_PERIPHCLK_SPI2 ((uint64_t)0x01000000U) 404 #define RCC_PERIPHCLK_SPI3 ((uint64_t)0x02000000U) 405 #define RCC_PERIPHCLK_OSPI ((uint64_t)0x04000000U) 406 #define RCC_PERIPHCLK_FDCAN1 ((uint64_t)0x08000000U) 407 #define RCC_PERIPHCLK_DAC1 ((uint64_t)0x10000000U) 408 #if defined(USART6) 409 #define RCC_PERIPHCLK_USART6 ((uint64_t)0x20000000U) 410 #endif /* USART6 */ 411 #if defined(I2C5) 412 #define RCC_PERIPHCLK_I2C5 ((uint64_t)0x40000000U) 413 #endif /* I2C5 */ 414 #if defined(I2C6) 415 #define RCC_PERIPHCLK_I2C6 ((uint64_t)0x80000000U) 416 #endif /* I2C6 */ 417 #if defined(HSPI1) 418 #define RCC_PERIPHCLK_HSPI ((uint64_t)0x100000000U) 419 #endif /* HSPI1 */ 420 #if defined(LTDC) 421 #define RCC_PERIPHCLK_LTDC ((uint64_t)0x200000000U) 422 #endif /* LTDC */ 423 #if defined(DSI) 424 #define RCC_PERIPHCLK_DSI ((uint64_t)0x400000000U) 425 #endif /* DSI */ 426 #if defined(USB_OTG_HS) 427 #define RCC_PERIPHCLK_USBPHY ((uint64_t)0x800000000U) 428 #endif /* USB_OTG_HS */ 429 #if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) 430 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 431 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 432 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 433 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ 434 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ 435 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ 436 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ 437 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ 438 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 439 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ 440 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ 441 RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY) 442 #elif defined (STM32U5G7xx) 443 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 444 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 445 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 446 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ 447 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ 448 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ 449 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ 450 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ 451 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 452 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ 453 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ 454 RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_SAES) 455 #elif defined (STM32U5F7xx) 456 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 457 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 458 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 459 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ 460 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ 461 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ 462 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ 463 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ 464 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 465 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ 466 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ 467 RCC_PERIPHCLK_USBPHY) 468 #elif (defined(STM32U595xx) || defined(STM32U5A5xx)) 469 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 470 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ 471 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ 472 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ 473 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ 474 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ 475 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ 476 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ 477 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ 478 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ 479 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY) 480 #elif defined(STM32U585xx) 481 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \ 482 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ 483 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 484 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ 485 RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 486 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ 487 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \ 488 RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ 489 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \ 490 RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) 491 #elif defined(STM32U575xx) 492 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \ 493 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ 494 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 495 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ 496 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 497 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ 498 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \ 499 RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ 500 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \ 501 RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) 502 #elif defined(STM32U535xx) 503 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ 504 RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \ 505 RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ 506 RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ 507 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ 508 RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ 509 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \ 510 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ 511 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) 512 #else 513 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ 514 RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \ 515 RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ 516 RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_SAES | \ 517 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ 518 RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ 519 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \ 520 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ 521 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) 522 #endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */ 523 /** 524 * @} 525 */ 526 527 528 /** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output 529 * @{ 530 */ 531 #define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN 532 #define RCC_PLL2_DIVQ RCC_PLL2CFGR_PLL2QEN 533 #define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN 534 /** 535 * @} 536 */ 537 538 /** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output 539 * @{ 540 */ 541 #define RCC_PLL3_DIVP RCC_PLL3CFGR_PLL3PEN 542 #define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN 543 #define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN 544 /** 545 * @} 546 */ 547 548 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 549 * @{ 550 */ 551 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 552 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 553 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 554 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) 555 /** 556 * @} 557 */ 558 559 #if defined(USART2) 560 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 561 * @{ 562 */ 563 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 564 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 565 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 566 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) 567 /** 568 * @} 569 */ 570 #endif /* USART2 */ 571 572 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 573 * @{ 574 */ 575 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 576 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR1_USART3SEL_0 577 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR1_USART3SEL_1 578 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) 579 /** 580 * @} 581 */ 582 583 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 584 * @{ 585 */ 586 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 587 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR1_UART4SEL_0 588 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR1_UART4SEL_1 589 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) 590 /** 591 * @} 592 */ 593 594 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 595 * @{ 596 */ 597 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 598 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR1_UART5SEL_0 599 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR1_UART5SEL_1 600 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) 601 /** 602 * @} 603 */ 604 605 #if defined(USART6) 606 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source 607 * @{ 608 */ 609 #define RCC_USART6CLKSOURCE_PCLK1 0x00000000U 610 #define RCC_USART6CLKSOURCE_SYSCLK RCC_CCIPR2_USART6SEL_0 611 #define RCC_USART6CLKSOURCE_HSI RCC_CCIPR2_USART6SEL_1 612 #define RCC_USART6CLKSOURCE_LSE (RCC_CCIPR2_USART6SEL_0 | RCC_CCIPR2_USART6SEL_1) 613 /** 614 * @} 615 */ 616 #endif /* USART6 */ 617 618 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 619 * @{ 620 */ 621 #define RCC_LPUART1CLKSOURCE_PCLK3 0x00000000U 622 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 623 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 624 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) 625 #define RCC_LPUART1CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 626 /** 627 * @} 628 */ 629 630 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 631 * @{ 632 */ 633 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 634 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 635 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 636 #define RCC_I2C1CLKSOURCE_MSIK (RCC_CCIPR1_I2C1SEL_1 | RCC_CCIPR1_I2C1SEL_0) 637 /** 638 * @} 639 */ 640 641 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 642 * @{ 643 */ 644 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 645 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR1_I2C2SEL_0 646 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR1_I2C2SEL_1 647 #define RCC_I2C2CLKSOURCE_MSIK (RCC_CCIPR1_I2C2SEL_1 | RCC_CCIPR1_I2C2SEL_0) 648 /** 649 * @} 650 */ 651 652 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 653 * @{ 654 */ 655 #define RCC_I2C3CLKSOURCE_PCLK3 0x00000000U 656 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR3_I2C3SEL_0 657 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR3_I2C3SEL_1 658 #define RCC_I2C3CLKSOURCE_MSIK (RCC_CCIPR3_I2C3SEL_0 | RCC_CCIPR3_I2C3SEL_1) 659 /** 660 * @} 661 */ 662 663 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 664 * @{ 665 */ 666 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 667 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR1_I2C4SEL_0 668 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR1_I2C4SEL_1 669 #define RCC_I2C4CLKSOURCE_MSIK (RCC_CCIPR1_I2C4SEL_1 | RCC_CCIPR1_I2C4SEL_0) 670 /** 671 * @} 672 */ 673 674 #if defined(I2C5) 675 /** @defgroup RCCEx_I2C5_Clock_Source I2C5 Clock Source 676 * @{ 677 */ 678 #define RCC_I2C5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 679 #define RCC_I2C5CLKSOURCE_SYSCLK RCC_CCIPR2_I2C5SEL_0 680 #define RCC_I2C5CLKSOURCE_HSI RCC_CCIPR2_I2C5SEL_1 681 #define RCC_I2C5CLKSOURCE_MSIK (RCC_CCIPR2_I2C5SEL_1 | RCC_CCIPR2_I2C5SEL_0) 682 /** 683 * @} 684 */ 685 #endif /* I2C5 */ 686 687 #if defined(I2C6) 688 /** @defgroup RCCEx_I2C6_Clock_Source I2C6 Clock Source 689 * @{ 690 */ 691 #define RCC_I2C6CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 692 #define RCC_I2C6CLKSOURCE_SYSCLK RCC_CCIPR2_I2C6SEL_0 693 #define RCC_I2C6CLKSOURCE_HSI RCC_CCIPR2_I2C6SEL_1 694 #define RCC_I2C6CLKSOURCE_MSIK (RCC_CCIPR2_I2C6SEL_1 | RCC_CCIPR2_I2C6SEL_0) 695 /** 696 * @} 697 */ 698 #endif /* I2C6 */ 699 700 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 701 * @{ 702 */ 703 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 704 #define RCC_RNGCLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 705 #define RCC_RNGCLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 706 /** 707 * @} 708 */ 709 710 #if defined(SAES) 711 /** @defgroup RCCEx_SAES_Clock_Source RCCEx SAES Clock Source 712 * @{ 713 */ 714 #define RCC_SAESCLKSOURCE_SHSI 0x00000000U 715 #define RCC_SAESCLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL 716 /** 717 * @} 718 */ 719 #endif /* SAES */ 720 721 /** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source 722 * @{ 723 */ 724 #define RCC_SPI1CLKSOURCE_PCLK2 0x00000000U 725 #define RCC_SPI1CLKSOURCE_SYSCLK RCC_CCIPR1_SPI1SEL_0 726 #define RCC_SPI1CLKSOURCE_HSI RCC_CCIPR1_SPI1SEL_1 727 #define RCC_SPI1CLKSOURCE_MSIK (RCC_CCIPR1_SPI1SEL_0 | RCC_CCIPR1_SPI1SEL_1) 728 /** 729 * @} 730 */ 731 732 /** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source 733 * @{ 734 */ 735 #define RCC_SPI2CLKSOURCE_PCLK1 0x00000000U 736 #define RCC_SPI2CLKSOURCE_SYSCLK RCC_CCIPR1_SPI2SEL_0 737 #define RCC_SPI2CLKSOURCE_HSI RCC_CCIPR1_SPI2SEL_1 738 #define RCC_SPI2CLKSOURCE_MSIK (RCC_CCIPR1_SPI2SEL_0 | RCC_CCIPR1_SPI2SEL_1) 739 /** 740 * @} 741 */ 742 743 /** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source 744 * @{ 745 */ 746 #define RCC_SPI3CLKSOURCE_PCLK3 0x00000000U 747 #define RCC_SPI3CLKSOURCE_SYSCLK RCC_CCIPR3_SPI3SEL_0 748 #define RCC_SPI3CLKSOURCE_HSI RCC_CCIPR3_SPI3SEL_1 749 #define RCC_SPI3CLKSOURCE_MSIK (RCC_CCIPR3_SPI3SEL_0 | RCC_CCIPR3_SPI3SEL_1) 750 /** 751 * @} 752 */ 753 754 /** @defgroup RCCEx_LPTIM34_Clock_Source LPTIM34 Clock Source 755 * @{ 756 */ 757 #define RCC_LPTIM34CLKSOURCE_MSIK 0x00000000U 758 #define RCC_LPTIM34CLKSOURCE_LSI RCC_CCIPR3_LPTIM34SEL_0 759 #define RCC_LPTIM34CLKSOURCE_HSI RCC_CCIPR3_LPTIM34SEL_1 760 #define RCC_LPTIM34CLKSOURCE_LSE (RCC_CCIPR3_LPTIM34SEL_0 | RCC_CCIPR3_LPTIM34SEL_1) 761 /** 762 * @} 763 */ 764 765 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 766 * @{ 767 */ 768 #define RCC_LPTIM1CLKSOURCE_MSIK 0x00000000U 769 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR3_LPTIM1SEL_0 770 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR3_LPTIM1SEL_1 771 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR3_LPTIM1SEL 772 /** 773 * @} 774 */ 775 776 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 777 * @{ 778 */ 779 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U 780 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 781 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 782 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL 783 /** 784 * @} 785 */ 786 787 /** @defgroup RCCEx_FDCAN1_Clock_Source FDCAN1 Kernel Clock Source 788 * @{ 789 */ 790 #define RCC_FDCAN1CLKSOURCE_HSE 0x00000000U 791 #define RCC_FDCAN1CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 792 #define RCC_FDCAN1CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 793 /** 794 * @} 795 */ 796 797 /** @defgroup RCCEx_ICLK_Clock_Source ICLK Clock Source 798 * @{ 799 */ 800 #define RCC_ICLK_CLKSOURCE_HSI48 0x00000000U 801 #define RCC_ICLK_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 802 #define RCC_ICLK_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 803 #define RCC_ICLK_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL 804 /** 805 * @} 806 */ 807 808 /** @defgroup RCCEx_ADCDAC_Clock_Source ADC1 Clock Source 809 * @{ 810 */ 811 #define RCC_ADCDACCLKSOURCE_HCLK 0x00000000U 812 #define RCC_ADCDACCLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 813 #define RCC_ADCDACCLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 814 #define RCC_ADCDACCLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_1) 815 #define RCC_ADCDACCLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 816 #define RCC_ADCDACCLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_2) 817 /** 818 * @} 819 */ 820 821 /** @defgroup RCCEx_MDF1_Clock_Source MDF1 Clock Source 822 * @{ 823 */ 824 #define RCC_MDF1CLKSOURCE_HCLK 0x00000000U 825 #define RCC_MDF1CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 826 #define RCC_MDF1CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 827 #define RCC_MDF1CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_0 | RCC_CCIPR2_MDF1SEL_1) 828 #define RCC_MDF1CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 829 /** 830 * @} 831 */ 832 833 /** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source 834 * @{ 835 */ 836 #define RCC_ADF1CLKSOURCE_HCLK 0x00000000U 837 #define RCC_ADF1CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 838 #define RCC_ADF1CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 839 #define RCC_ADF1CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_0 | RCC_CCIPR3_ADF1SEL_1) 840 #define RCC_ADF1CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 841 /** 842 * @} 843 */ 844 845 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 846 * @{ 847 */ 848 #define RCC_SAI1CLKSOURCE_PLL2 0x00000000U 849 #define RCC_SAI1CLKSOURCE_PLL3 RCC_CCIPR2_SAI1SEL_0 850 #define RCC_SAI1CLKSOURCE_PLL1 RCC_CCIPR2_SAI1SEL_1 851 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) 852 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 853 /** 854 * @} 855 */ 856 857 #if defined(SAI2) 858 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 859 * @{ 860 */ 861 #define RCC_SAI2CLKSOURCE_PLL2 0x00000000U 862 #define RCC_SAI2CLKSOURCE_PLL3 RCC_CCIPR2_SAI2SEL_0 863 #define RCC_SAI2CLKSOURCE_PLL1 RCC_CCIPR2_SAI2SEL_1 864 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) 865 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 866 /** 867 * @} 868 */ 869 #endif /* SAI2 */ 870 871 /** @defgroup RCCEx_SDMMC_Clock_Source SDMMC1/2 Clock Source 872 * @{ 873 */ 874 #define RCC_SDMMCCLKSOURCE_CLK48 0x00000000U 875 #define RCC_SDMMCCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL 876 /** 877 * @} 878 */ 879 880 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 881 * @{ 882 */ 883 #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U 884 #define RCC_OSPICLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 885 #define RCC_OSPICLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 886 #define RCC_OSPICLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) 887 /** 888 * @} 889 */ 890 891 #if defined(HSPI1) 892 /** @defgroup RCCEx_HSPI_Clock_Source HexaSPI Clock Source 893 * @{ 894 */ 895 #define RCC_HSPICLKSOURCE_SYSCLK ((uint32_t)0x00000000U) 896 #define RCC_HSPICLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0 897 #define RCC_HSPICLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1 898 #define RCC_HSPICLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL 899 /** 900 * @} 901 */ 902 #endif /* HSPI1 */ 903 904 /** @defgroup RCCEx_DAC1_Clock_Source DAC1 Clock Source 905 * @{ 906 */ 907 #define RCC_DAC1CLKSOURCE_LSE 0x00000000U 908 #define RCC_DAC1CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL 909 /** 910 * @} 911 */ 912 913 /** @defgroup RCC_Timicsel_items RCC timicsel items 914 * @brief RCC Timicsel items to configure timicsel 915 * @{ 916 */ 917 #define RCC_TIMIC_HSI_256 RCC_CCIPR1_TIMICSEL_2 /*!<HSI/256 selected for Timer16/17 and LPTimer2 */ 918 #define RCC_TIMIC_MSI_1024 RCC_CCIPR1_TIMICSEL_2 /*!<MSIS/1024 selected for Timer16/17 and LPTimer2*/ 919 #define RCC_TIMIC_MSI_4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1) /*!<MSIS/4 selected for Timer16/17 and LPTimer2*/ 920 #define RCC_TIMIC_MSIK_4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0) /*!<MSIK/1024 selected for Timer16/17 and LPTimer2*/ 921 #define RCC_TIMIC_MSIK_1024 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | RCC_CCIPR1_TIMICSEL_0) /*!<MSIK/4 selected for Timer16/17 and LPTimer2*/ 922 /** 923 * @} 924 */ 925 926 #if defined(LTDC) 927 /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source 928 * @{ 929 */ 930 #define RCC_LTDCCLKSOURCE_PLL3 ((uint32_t)0x00000000U) /*!< PLL3 divider R clock selected as LTDC kernel clock */ 931 #define RCC_LTDCCLKSOURCE_PLL2 RCC_CCIPR2_LTDCSEL /*!< PLL2 divider R clock selected as LTDC kernel clock */ 932 /** 933 * @} 934 */ 935 #endif /* LTDC */ 936 937 #if defined(DSI) 938 /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source 939 * @{ 940 */ 941 #define RCC_DSICLKSOURCE_DSIPHY RCC_CCIPR2_DSIHOSTSEL /*!< DSI-PHY is selected as DSI byte lane clock (usual case) */ 942 #define RCC_DSICLKSOURCE_PLL3 ((uint32_t)0x00000000U) /*!< PLL3 divider P clock selected as DSI byte lane clock (low power case) */ 943 /** 944 * @} 945 */ 946 #endif /* DSI */ 947 948 #if defined(USB_OTG_HS) 949 /** @defgroup RCCEx_USBPHY_Clock_Source USB-PHY Clock Source 950 * @{ 951 */ 952 #define RCC_USBPHYCLKSOURCE_HSE ((uint32_t)0x00000000U) /*!< HSE clock selected as USBPHYC clock */ 953 #define RCC_USBPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_USBPHYCSEL_1 /*!< HSE clock divided by 2 selected as USBPHYC clock */ 954 #define RCC_USBPHYCLKSOURCE_PLL1 RCC_CCIPR2_USBPHYCSEL_0 /*!< PLL1 divider P selected as USBPHYC clock */ 955 #define RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL1 divider P divided by 2 selected as USBPHYC clock */ 956 /** 957 * @} 958 */ 959 #endif /* USB_OTG_HS */ 960 961 #if defined(CRS) 962 963 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 964 * @{ 965 */ 966 #define RCC_CRS_NONE 0x00000000U 967 #define RCC_CRS_TIMEOUT 0x00000001U 968 #define RCC_CRS_SYNCOK 0x00000002U 969 #define RCC_CRS_SYNCWARN 0x00000004U 970 #define RCC_CRS_SYNCERR 0x00000008U 971 #define RCC_CRS_SYNCMISS 0x00000010U 972 #define RCC_CRS_TRIMOVF 0x00000020U 973 /** 974 * @} 975 */ 976 977 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 978 * @{ 979 */ 980 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 981 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 982 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 983 /** 984 * @} 985 */ 986 987 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 988 * @{ 989 */ 990 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 991 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 992 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 993 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 994 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 995 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 996 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 997 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 998 /** 999 * @} 1000 */ 1001 1002 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 1003 * @{ 1004 */ 1005 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 1006 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 1007 /** 1008 * @} 1009 */ 1010 1011 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 1012 * @{ 1013 */ 1014 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 1015 to a target frequency of 48 MHz and a synchronization 1016 signal frequency of 1 kHz (SOF signal from USB). */ 1017 /** 1018 * @} 1019 */ 1020 1021 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 1022 * @{ 1023 */ 1024 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 1025 /** 1026 * @} 1027 */ 1028 1029 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 1030 * @{ 1031 */ 1032 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to 1033 the middle of the trimming interval. 1034 The trimming step is around 67 kHz between two 1035 consecutive TRIM steps. A higher TRIM value 1036 corresponds to a higher output frequency */ 1037 /** 1038 * @} 1039 */ 1040 1041 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 1042 * @{ 1043 */ 1044 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 1045 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 1046 /** 1047 * @} 1048 */ 1049 1050 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 1051 * @{ 1052 */ 1053 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 1054 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 1055 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 1056 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 1057 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 1058 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 1059 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 1060 /** 1061 * @} 1062 */ 1063 1064 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 1065 * @{ 1066 */ 1067 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 1068 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 1069 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 1070 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 1071 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 1072 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 1073 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 1074 /** 1075 * @} 1076 */ 1077 /** 1078 * @} 1079 */ 1080 #endif /* CRS */ 1081 1082 /* Exported macros -----------------------------------------------------------*/ 1083 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1084 * @{ 1085 */ 1086 1087 /** @brief Macro to adjust the MSI oscillator calibration value. 1088 * @note The calibration is used to compensate for the variations in voltage 1089 * and temperature that influence the frequency of the internal MSI RC. 1090 * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value 1091 * This parameter must be a number between 0 and 0x1F. 1092 * @param __MSIRANGE__ : specifies the MSI Range value 1093 * This parameter can be one of the following values: 1094 * @arg RCC_MSIRANGE_0 1095 * @arg RCC_MSIRANGE_1 1096 * @arg RCC_MSIRANGE_2 1097 * @arg RCC_MSIRANGE_3 1098 * @arg RCC_MSIRANGE_4 1099 * @arg RCC_MSIRANGE_5 1100 * @arg RCC_MSIRANGE_6 1101 * @arg RCC_MSIRANGE_7 1102 * @arg RCC_MSIRANGE_8 1103 * @arg RCC_MSIRANGE_9 1104 * @arg RCC_MSIRANGE_10 1105 * @arg RCC_MSIRANGE_11 1106 * @arg RCC_MSIRANGE_12 1107 * @arg RCC_MSIRANGE_13 1108 * @arg RCC_MSIRANGE_14 1109 * @arg RCC_MSIRANGE_15 1110 * @retval None 1111 */ 1112 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__ , __MSIRANGE__) \ 1113 do \ 1114 { \ 1115 if(__MSIRANGE__ >= RCC_MSIRANGE_12) \ 1116 {\ 1117 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM3), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 1118 RCC_ICSCR2_MSITRIM3_Pos));\ 1119 }\ 1120 else if(__MSIRANGE__ >= RCC_MSIRANGE_8)\ 1121 {\ 1122 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM2), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 1123 RCC_ICSCR2_MSITRIM2_Pos));\ 1124 }\ 1125 else if(__MSIRANGE__ >= RCC_MSIRANGE_4)\ 1126 {\ 1127 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM1), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 1128 RCC_ICSCR2_MSITRIM1_Pos));\ 1129 } \ 1130 else /* if(__MSIRANGE__ >= RCC_MSIRANGE_0) */\ 1131 { \ 1132 MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM0), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ 1133 RCC_ICSCR2_MSITRIM0_Pos));\ 1134 } \ 1135 } while(0) 1136 1137 /** @brief Macro to configure timer input capture clock source. 1138 * @param __TIMICSOURCE__ : specifies the TIMIC clock source 1139 * This parameter can be one or a combination of the following values: 1140 * @arg RCC_TIMIC_HSI_256: HSI/256 selected for Timer16/17 and LPTimer2 1141 * @arg RCC_TIMIC_MSI_1024: MSIS/1024 selected for Timer16/17 and LPTimer2 1142 * @arg RCC_TIMIC_MSI_4: MSIS/4 selected for Timer16/17 and LPTimer2 1143 * @arg RCC_TIMIC_MSIK_1024: MSIK/1024 selected for Timer16/17 and LPTimer2 1144 * @arg RCC_TIMIC_MSIK_4 : MSIK/4 selected for Timer16/17 and LPTimer2 1145 * @note combination to be avoid : 1146 * RCC_TIMIC_MSI_1024 and RCC_TIMIC_MSIK_1024 1147 * RCC_TIMIC_MSI_4 and RCC_TIMIC_MSIK_4 1148 * @retval None 1149 */ 1150 #define __HAL_RCC_TIMIC_CLK_CONFIG(__TIMICSOURCE__) \ 1151 do \ 1152 { \ 1153 /*Disable All TIMIC SOURCE*/ \ 1154 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)); \ 1155 /*Select TIMIC clock SOURCE*/ \ 1156 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(uint32_t)(__TIMICSOURCE__));\ 1157 } while(0) 1158 1159 /** @brief Macro to disable timer input capture clock source. 1160 * @retval None 1161 */ 1162 #define __HAL_RCC_TIMIC_CLK_DISABLE() MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)) 1163 1164 /** @brief Macros to enable or disable the PLL2. 1165 * @note After enabling PLL2, the application software should wait on 1166 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1167 * be used as kernel clock source. 1168 * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1169 * @retval None 1170 */ 1171 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 1172 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 1173 1174 /** @brief Macro to configure the PLL2 clock source. 1175 * @note This function must be used only when all PLL2 is disabled. 1176 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1177 * This parameter can be one of the following values: 1178 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL2 clock entry 1179 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry 1180 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry 1181 */ 1182 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC,\ 1183 (__PLL2SOURCE__)) 1184 1185 /** @brief Macro to get the oscillator used as PLL2 clock source. 1186 * @retval The oscillator used as PLL2 clock source. The returned value can be one 1187 * of the following: 1188 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 1189 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 1190 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 1191 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 1192 */ 1193 #define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) 1194 1195 /** @brief Macro to configures the PLL2 source, multiplication and division factors. 1196 * @note This function must be used only when PLL2 is disabled. 1197 * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. 1198 * This parameter can be one of the following values: 1199 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL2 clock entry 1200 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL2 clock entry 1201 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL2 clock entry 1202 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL2 clock entry 1203 * @param __PLL2M__ specifies the division factor of PLL2 input clock. 1204 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 1205 * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock 1206 * This parameter must be a number between 4 and 512. 1207 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 1208 * output frequency is between 64 and 344 MHz. 1209 * PLL2 clock frequency = f(PLL2) multiplied by PLL2N 1210 * @param __PLL2P__: specifies the division factor for peripheral kernel clocks 1211 * This parameter must be a number between 1 and 128 1212 * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks 1213 * This parameter must be a number between 1 and 128 1214 * @param __PLL2R__: specifies the division factor for peripheral kernel clocks 1215 * This parameter must be a number between 1 and 128 1216 * @retval None 1217 */ 1218 #define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ 1219 do \ 1220 { \ 1221 MODIFY_REG(RCC->PLL2CFGR,(RCC_PLL2CFGR_PLL2SRC|RCC_PLL2CFGR_PLL2M), ((__PLL2SOURCE__)<< RCC_PLL2CFGR_PLL2SRC_Pos) |\ 1222 (((__PLL2M__) - 1U) << RCC_PLL2CFGR_PLL2M_Pos));\ 1223 MODIFY_REG(RCC->PLL2DIVR ,(RCC_PLL2DIVR_PLL2N|RCC_PLL2DIVR_PLL2P|RCC_PLL2DIVR_PLL2Q|\ 1224 RCC_PLL2DIVR_PLL2R), ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | ((((__PLL2P__) -1U)<< \ 1225 RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) |\ 1226 ((((__PLL2Q__) -1U) << RCC_PLL2DIVR_PLL2Q_Pos)& \ 1227 RCC_PLL2DIVR_PLL2Q) | ((((__PLL2R__)- 1U) << \ 1228 RCC_PLL2DIVR_PLL2R_Pos) & \ 1229 RCC_PLL2DIVR_PLL2R))); \ 1230 } while(0) 1231 1232 /** 1233 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) 1234 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL2, 1235 * This is mainly used to save Power. 1236 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock outputted. 1237 * This parameter can be one or a combination of the following values: 1238 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve 1239 * high-quality audio performance on SAI interface. 1240 * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), 1241 * the random number generator (<=48 MHz). 1242 * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. 1243 * @retval None 1244 */ 1245 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1246 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1247 1248 /** 1249 * @brief Macro to get the PLL2 clock output enable status. 1250 * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be outputted. 1251 * This parameter can be one of the following values: 1252 * This parameter can be one or a combination of the following values: 1253 * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve 1254 * high-quality audio performance on SAI interface. 1255 * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), 1256 * the random number generator (<=48 MHz). 1257 * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. 1258 * @retval SET / RESET 1259 */ 1260 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) 1261 1262 /** 1263 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 1264 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 1265 * @retval None 1266 */ 1267 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1268 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) 1269 1270 /** 1271 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 1272 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 1273 * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 1274 * It should be a value between 0 and 8191 1275 * @note Warning: the software has to set correctly these bits to insure that the VCO 1276 * output frequency is between its valid frequency range, which is: 1277 * 192 to 836 MHz if PLL2VCOSEL = 0 1278 * 150 to 420 MHz if PLL2VCOSEL = 1 1279 * @retval None 1280 */ 1281 #define __HAL_RCC_PLL2FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN,\ 1282 (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) 1283 1284 /** @brief Macro to select the PLL2 reference frequency range. 1285 * @param __PLL2VCIRange__: specifies the PLL2 input frequency range 1286 * This parameter can be one of the following values: 1287 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 1288 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 1289 * @retval None 1290 */ 1291 #define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ 1292 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) 1293 1294 /** @brief Macros to enable or disable the main PLL3. 1295 * @note After enabling PLL3, the application software should wait on 1296 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 1297 * be used as kernel clock source. 1298 * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. 1299 */ 1300 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 1301 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 1302 1303 /** @brief Macro to configure the PLL3 clock source. 1304 * @note This function must be used only when all PLL3 is disabled. 1305 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1306 * This parameter can be one of the following values: 1307 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL3 clock entry 1308 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry 1309 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry 1310 * 1311 */ 1312 #define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ 1313 (__PLL3SOURCE__)) 1314 1315 /** @brief Macro to get the oscillator used as PLL3 clock source. 1316 * @retval The oscillator used as PLL3 clock source. The returned value can be one 1317 * of the following: 1318 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 1319 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 1320 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 1321 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 1322 */ 1323 #define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) 1324 1325 /** @brief Macro to configures the PLL3 source, multiplication and division factors. 1326 * @note This function must be used only when PLL3 is disabled. 1327 * 1328 * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. 1329 * This parameter can be one of the following values: 1330 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL3 clock entry 1331 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL3 clock entry 1332 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL3 clock entry 1333 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL3 clock entry 1334 * @param __PLL3M__ specifies the division factor of PLL3 input clock. 1335 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 1336 * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock 1337 * This parameter must be a number between 4 and 512. 1338 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 1339 * output frequency is between 64 and 344 MHz. 1340 * PLL3 clock frequency = f(PLL3) multiplied by PLL3N 1341 * @param __PLL3P__: specifies the division factor for peripheral kernel clocks 1342 * This parameter must be a number between 1 and 128 1343 * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks 1344 * This parameter must be a number between 1 and 128 1345 * @param __PLL3R__: specifies the division factor for peripheral kernel clocks 1346 * This parameter must be a number between 1 and 128 1347 * @retval None 1348 */ 1349 #define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ 1350 do\ 1351 {\ 1352 MODIFY_REG(RCC->PLL3CFGR,(RCC_PLL3CFGR_PLL3SRC|RCC_PLL3CFGR_PLL3M), ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos)|\ 1353 (((__PLL3M__) - 1U) << RCC_PLL3CFGR_PLL3M_Pos));\ 1354 MODIFY_REG(RCC->PLL3DIVR ,(RCC_PLL3DIVR_PLL3N|RCC_PLL3DIVR_PLL3P|RCC_PLL3DIVR_PLL3Q|RCC_PLL3DIVR_PLL3R),\ 1355 ((((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | ((((__PLL3P__) -1U) << RCC_PLL3DIVR_PLL3P_Pos) &\ 1356 RCC_PLL3DIVR_PLL3P) | ((((__PLL3Q__) -1U) << \ 1357 RCC_PLL3DIVR_PLL3Q_Pos) & \ 1358 RCC_PLL3DIVR_PLL3Q) | \ 1359 ((((__PLL3R__)- 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ 1360 } while(0) 1361 1362 /** 1363 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 1364 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 1365 * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 1366 * It should be a value between 0 and 8191 1367 * @note Warning: the software has to set correctly these bits to insure that the VCO 1368 * output frequency is between its valid frequency range, which is: 1369 * 192 to 836 MHz if PLL3VCOSEL = 0 1370 * 150 to 420 MHz if PLL3VCOSEL = 1 1371 * @retval None 1372 */ 1373 #define __HAL_RCC_PLL3FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ 1374 (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) 1375 1376 /** @brief Macro to select the PLL3 reference frequency range. 1377 * @param __PLL3VCIRange__: specifies the PLL1 input frequency range 1378 * This parameter can be one of the following values: 1379 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 1380 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 1381 * @retval None 1382 */ 1383 #define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ 1384 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) 1385 1386 /** 1387 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 1388 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 1389 * @retval None 1390 */ 1391 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1392 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) 1393 1394 /** 1395 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) 1396 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, 1397 * This is mainly used to save Power. 1398 * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted 1399 * This parameter can be one of the following values: 1400 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1401 * high-quality audio performance on SAI interface. 1402 * @retval None 1403 */ 1404 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1405 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1406 1407 /** 1408 * @brief Macro to get clock output enable status (PLL3_SAI2). 1409 * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be outputted. 1410 * This parameter can be one of the following values: 1411 * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve 1412 * high-quality audio performance on SAI interface. 1413 * @retval SET / RESET 1414 */ 1415 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) 1416 1417 /** @brief Macro to configure the ADC1, ADC2, ADC4 and DAC interface clock. 1418 * @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source. 1419 * This parameter can be one of the following values: 1420 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC2, ADC4 and DAC clock 1421 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC2 ADC4 and DAC clock 1422 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC2 ADC4 and DAC clock 1423 * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC2 ADC4 and DAC clock 1424 * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC2 ADC4 and DAC clock 1425 * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC2 ADC4 and DAC clock 1426 * @retval None 1427 */ 1428 #define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ 1429 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) 1430 1431 /** @brief Macro to get the ADCDAC clock source. 1432 * @retval The clock source can be one of the following values: 1433 * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC2, ADC4 and DAC clock 1434 * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC2, ADC4 and DAC clock 1435 * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC2, ADC4 and DAC clock 1436 * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC2, ADC4 and DAC clock 1437 * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC2, ADC4 and DAC clock 1438 * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC2, ADC4 and DAC clock 1439 */ 1440 #define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL))) 1441 1442 /** @brief Macro to configure the CLK48 source (CLK48CLK). 1443 * @param __CLK48_SOURCE__: specifies the CLK48 clock source. 1444 * This parameter can be one of the following values: 1445 * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 selected as CLK48 source 1446 * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 selected as CLK48 source 1447 * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 selected as CLK48 source 1448 * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source 1449 */ 1450 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ 1451 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, (uint32_t)(__CLK48_SOURCE__)) 1452 1453 /** @brief macro to get the CLK48 source. 1454 * @retval The clock source can be one of the following values: 1455 * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 used as CLK48 source 1456 * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 used as CLK48 source 1457 * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source 1458 * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source 1459 */ 1460 #define __HAL_RCC_GET_ICLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL))) 1461 1462 /** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK). 1463 * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source. 1464 * This parameter can be one of the following values: 1465 * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock 1466 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock 1467 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock 1468 * @retval None 1469 */ 1470 #define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \ 1471 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN1_CLKSOURCE__)) 1472 1473 /** @brief Macro to get the FDCAN1 clock source. 1474 * @retval The clock source can be one of the following values: 1475 * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock 1476 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock 1477 * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock 1478 */ 1479 #define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL))) 1480 1481 /** @brief Macro to configure the LPTIM34 clock (LPTIM34CLK). 1482 * @param __LPTIM34_CLKSOURCE__ specifies the LPTIM34 clock source. 1483 * This parameter can be one of the following values: 1484 * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock 1485 * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock 1486 * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock 1487 * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock 1488 * @retval None 1489 */ 1490 #define __HAL_RCC_LPTIM34_CONFIG(__LPTIM34_CLKSOURCE__) \ 1491 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL, (uint32_t)(__LPTIM34_CLKSOURCE__)) 1492 1493 /** @brief Macro to get the LPTIM34 clock source. 1494 * @retval The clock source can be one of the following values: 1495 * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock 1496 * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock 1497 * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock 1498 * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock 1499 */ 1500 #define __HAL_RCC_GET_LPTIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL))) 1501 1502 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1503 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1504 * This parameter can be one of the following values: 1505 * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock 1506 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1507 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1508 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1509 * @retval None 1510 */ 1511 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1512 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1513 1514 /** @brief Macro to get the LPTIM1 clock source. 1515 * @retval The clock source can be one of the following values: 1516 * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock 1517 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1518 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1519 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1520 */ 1521 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL))) 1522 1523 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1524 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1525 * This parameter can be one of the following values: 1526 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1527 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1528 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1529 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1530 * @retval None 1531 */ 1532 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1533 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 1534 1535 /** @brief Macro to get the LPTIM2 clock source. 1536 * @retval The clock source can be one of the following values: 1537 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1538 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1539 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1540 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1541 */ 1542 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL))) 1543 1544 /** @brief macro to configure the SPI1 clock source. 1545 * @retval The clock source can be one of the following values: 1546 * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI1 clock 1547 * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI1 clock 1548 * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock selected as SPI1 clock 1549 * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock selected as SPI1 clock 1550 */ 1551 1552 #define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ 1553 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) 1554 1555 /** @brief macro to get the SPI1 clock source. 1556 * @retval The clock source can be one of the following values: 1557 * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI1 clock 1558 * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI1 clock 1559 * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock used as SPI1 clock 1560 * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock used as SPI1 clock 1561 */ 1562 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL))) 1563 1564 /** @brief macro to configure the SPI2 clock source. 1565 * @retval The clock source can be one of the following values: 1566 * @arg RCC_SPI2CLKSOURCE_PCLK3 : PCLK3 selected as SPI2 clock 1567 * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI2 clock 1568 * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock selected as SPI2 clock 1569 * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock selected as SPI2 clock 1570 */ 1571 1572 #define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ 1573 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) 1574 1575 /** @brief macro to get the SPI2 clock source. 1576 * @retval The clock source can be one of the following values: 1577 * @arg RCC_SPI2CLKSOURCE_PCLK1 : PCLK1 Clock used as SPI2 clock 1578 * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI2 clock 1579 * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock used as SPI2 clock 1580 * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock used as SPI2 clock 1581 */ 1582 #define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL))) 1583 1584 /** @brief macro to configure the SPI3 clock source. 1585 * @retval The clock source can be one of the following values: 1586 * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 selected as SPI3 clock 1587 * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock 1588 * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock 1589 * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock selected as SPI3 clock 1590 */ 1591 #define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ 1592 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) 1593 1594 /** @brief macro to get the SPI3 clock source. 1595 * @retval The clock source can be one of the following values: 1596 * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 used as SPI3 clock 1597 * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI3 clock 1598 * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock used as SPI3 clock 1599 * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock used as SPI3 clock 1600 */ 1601 #define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) 1602 1603 1604 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1605 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1606 * This parameter can be one of the following values: 1607 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1608 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1609 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1610 * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock 1611 * @retval None 1612 */ 1613 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1614 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1615 1616 /** @brief Macro to get the I2C1 clock source. 1617 * @retval The clock source can be one of the following values: 1618 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1619 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1620 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1621 * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock 1622 */ 1623 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL))) 1624 1625 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 1626 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 1627 * This parameter can be one of the following values: 1628 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1629 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1630 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1631 * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock 1632 * @retval None 1633 */ 1634 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 1635 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 1636 1637 /** @brief Macro to get the I2C2 clock source. 1638 * @retval The clock source can be one of the following values: 1639 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1640 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1641 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1642 * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock 1643 */ 1644 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL))) 1645 1646 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1647 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1648 * This parameter can be one of the following values: 1649 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 selected as I2C3 clock 1650 * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI selected as I2C3 clock 1651 * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK selected as I2C3 clock 1652 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock selected as I2C3 clock 1653 * @retval None 1654 */ 1655 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1656 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 1657 1658 /** @brief Macro to get the I2C3 clock source. 1659 * @retval The clock source can be one of the following values: 1660 * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 used as I2C3 clock 1661 * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI used as I2C3 clock 1662 * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK used as I2C3 clock 1663 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock used as I2C3 clock 1664 */ 1665 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL))) 1666 1667 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 1668 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 1669 * This parameter can be one of the following values: 1670 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1671 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1672 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1673 * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock 1674 * @retval None 1675 */ 1676 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 1677 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 1678 1679 /** @brief Macro to get the I2C4 clock source. 1680 * @retval The clock source can be one of the following values: 1681 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1682 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1683 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1684 * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock 1685 */ 1686 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL))) 1687 1688 #if defined(I2C5) 1689 /** @brief Macro to configure the I2C5 clock (I2C5CLK). 1690 * 1691 * @param __I2C5_CLKSOURCE__ specifies the I2C5 clock source. 1692 * This parameter can be one of the following values: 1693 * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock 1694 * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock 1695 * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock 1696 * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock 1697 * @retval None 1698 */ 1699 #define __HAL_RCC_I2C5_CONFIG(__I2C5_CLKSOURCE__) \ 1700 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL, (uint32_t)(__I2C5_CLKSOURCE__)) 1701 1702 /** @brief Macro to get the I2C5 clock source. 1703 * @retval The clock source can be one of the following values: 1704 * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock 1705 * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock 1706 * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock 1707 * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock 1708 */ 1709 #define __HAL_RCC_GET_I2C5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL))) 1710 #endif /* I2C5 */ 1711 1712 #if defined(I2C6) 1713 /** @brief Macro to configure the I2C6 clock (I2C6CLK). 1714 * 1715 * @param __I2C6_CLKSOURCE__ specifies the I2C6 clock source. 1716 * This parameter can be one of the following values: 1717 * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock 1718 * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock 1719 * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock 1720 * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock 1721 * @retval None 1722 */ 1723 #define __HAL_RCC_I2C6_CONFIG(__I2C6_CLKSOURCE__) \ 1724 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL, (uint32_t)(__I2C6_CLKSOURCE__)) 1725 1726 /** @brief Macro to get the I2C6 clock source. 1727 * @retval The clock source can be one of the following values: 1728 * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock 1729 * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock 1730 * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock 1731 * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock 1732 */ 1733 #define __HAL_RCC_GET_I2C6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL))) 1734 #endif /* I2C6 */ 1735 1736 /** @brief Macro to configure the USART1 clock (USART1CLK). 1737 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1738 * This parameter can be one of the following values: 1739 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock 1740 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1741 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1742 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 1743 * @retval None 1744 */ 1745 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1746 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 1747 1748 /** @brief Macro to get the USART1 clock source. 1749 * @retval The clock source can be one of the following values: 1750 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock 1751 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1752 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1753 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1754 */ 1755 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) 1756 1757 #if defined(USART2) 1758 /** @brief Macro to configure the USART2 clock (USART2CLK). 1759 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1760 * This parameter can be one of the following values: 1761 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1762 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1763 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1764 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1765 * @retval None 1766 */ 1767 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1768 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 1769 1770 /** @brief Macro to get the USART2 clock source. 1771 * @retval The clock source can be one of the following values: 1772 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1773 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1774 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1775 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1776 */ 1777 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) 1778 #endif /* USART2 */ 1779 1780 /** @brief Macro to configure the USART3 clock (USART3CLK). 1781 * 1782 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 1783 * This parameter can be one of the following values: 1784 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1785 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1786 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1787 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1788 * @retval None 1789 */ 1790 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 1791 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 1792 1793 /** @brief Macro to get the USART3 clock source. 1794 * @retval The clock source can be one of the following values: 1795 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1796 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1797 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1798 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1799 */ 1800 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) 1801 1802 /** @brief Macro to configure the UART4 clock (UART4CLK). 1803 * 1804 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 1805 * This parameter can be one of the following values: 1806 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1807 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1808 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1809 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1810 * @retval None 1811 */ 1812 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 1813 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 1814 1815 /** @brief Macro to get the UART4 clock source. 1816 * @retval The clock source can be one of the following values: 1817 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1818 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1819 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1820 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1821 */ 1822 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) 1823 1824 /** @brief Macro to configure the UART5 clock (UART5CLK). 1825 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 1826 * This parameter can be one of the following values: 1827 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1828 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1829 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1830 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1831 * @retval None 1832 */ 1833 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 1834 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 1835 1836 /** @brief Macro to get the UART5 clock source. 1837 * @retval The clock source can be one of the following values: 1838 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1839 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1840 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1841 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1842 */ 1843 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) 1844 1845 #if defined(USART6) 1846 /** @brief Macro to configure the USART6 clock (USART6CLK). 1847 * 1848 * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. 1849 * This parameter can be one of the following values: 1850 * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock 1851 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 1852 * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock 1853 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 1854 * @retval None 1855 */ 1856 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ 1857 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) 1858 1859 /** @brief Macro to get the USART6 clock source. 1860 * @retval The clock source can be one of the following values: 1861 * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock 1862 * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock 1863 * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock 1864 * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock 1865 */ 1866 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART6SEL))) 1867 #endif /* USART6 */ 1868 1869 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1870 * 1871 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1872 * This parameter can be one of the following values: 1873 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 1874 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1875 * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock 1876 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1877 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1878 * @retval None 1879 */ 1880 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1881 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 1882 1883 /** @brief Macro to get the LPUART1 clock source. 1884 * @retval The clock source can be one of the following values: 1885 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock 1886 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1887 * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock 1888 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1889 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1890 */ 1891 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) 1892 1893 /** @brief Macro to configure the OctoSPI clock. 1894 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 1895 * This parameter can be one of the following values: 1896 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1897 * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock 1898 * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock 1899 * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock 1900 * @retval None 1901 */ 1902 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 1903 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) 1904 1905 /** @brief Macro to get the OctoSPI clock source. 1906 * @retval The clock source can be one of the following values: 1907 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1908 * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock 1909 * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock 1910 * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock 1911 */ 1912 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL))) 1913 1914 #if defined(HSPI1) 1915 /** @brief Macro to configure the HexaSPI clock. 1916 * @param __HSPI_CLKSOURCE__ specifies the HexaSPI clock source. 1917 * This parameter can be one of the following values: 1918 * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock 1919 * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock 1920 * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock 1921 * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock 1922 * @retval None 1923 */ 1924 #define __HAL_RCC_HSPI_CONFIG(__HSPI_CLKSOURCE__) \ 1925 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, (uint32_t)(__HSPI_CLKSOURCE__)) 1926 1927 /** @brief Macro to get the HexaSPI clock source. 1928 * @retval The clock source can be one of the following values: 1929 * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock 1930 * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock 1931 * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock 1932 * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock 1933 */ 1934 #define __HAL_RCC_GET_HSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_HSPISEL))) 1935 #endif /* HSPI1 */ 1936 1937 /** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK). 1938 * @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source. 1939 * This parameter can be one of the following values: 1940 * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock 1941 * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock 1942 */ 1943 #define __HAL_RCC_SDMMC_CONFIG(__SDMMC_CLKSOURCE__) \ 1944 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, (uint32_t)(__SDMMC_CLKSOURCE__)) 1945 1946 /** @brief macro to get the SDMMC1/2 clock source. 1947 * @retval The clock source can be one of the following values: 1948 * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock 1949 * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock 1950 */ 1951 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL))) 1952 1953 /** @brief macro to configure the RNG clock (RNGCLK). 1954 * @param __RNG_CLKSource__: specifies the RNG clock source. 1955 * This parameter can be one of the following values: 1956 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 1957 * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock 1958 * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock 1959 */ 1960 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSource__) \ 1961 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, (uint32_t)(__RNG_CLKSource__)) 1962 1963 /** @brief macro to get the RNG clock source. 1964 * @retval The clock source can be one of the following values: 1965 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock 1966 * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock 1967 * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock 1968 */ 1969 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL))) 1970 1971 #if defined(SAES) 1972 /** @brief macro to configure the SAES clock (SAESCLK). 1973 * @param __SAES_CLKSource__: specifies the SAES clock source. 1974 * This parameter can be one of the following values: 1975 * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock 1976 * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock 1977 */ 1978 #define __HAL_RCC_SAES_CONFIG(__SAES_CLKSource__) \ 1979 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, (uint32_t)(__SAES_CLKSource__)) 1980 1981 /** @brief macro to get the SAES clock source. 1982 * @retval The clock source can be one of the following values: 1983 * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock 1984 * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock 1985 */ 1986 #define __HAL_RCC_GET_SAES_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAESSEL))) 1987 #endif /* SAES */ 1988 1989 /** 1990 * @brief Macro to configure the SAI1 clock source. 1991 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 1992 * from the PLL2, system PLL or external clock (through a dedicated pin). 1993 * This parameter can be one of the following values: 1994 * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) 1995 * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) 1996 * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL1 "P" clock (PLL1CLK) 1997 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 1998 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 1999 * 2000 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLL3. 2001 * @retval None 2002 */ 2003 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 2004 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) 2005 2006 /** @brief Macro to get the SAI1 clock source. 2007 * @retval The clock source can be one of the following values: 2008 * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) 2009 * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) 2010 * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL "P" clock (PLL1CLK) 2011 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 2012 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 2013 * @note Despite returned values RCC_SAI1CLKSOURCE_PLL2 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 2014 * clock source when PLLs are disabled for devices without PLL3. 2015 */ 2016 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) 2017 2018 #if defined(SAI2) 2019 /** 2020 * @brief Macro to configure the SAI2 clock source. 2021 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 2022 * from the PLL3, system PLL or external clock (through a dedicated pin). 2023 * This parameter can be one of the following values: 2024 * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) 2025 * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) 2026 * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) 2027 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 2028 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 2029 * @retval None 2030 */ 2031 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 2032 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) 2033 2034 /** @brief Macro to get the SAI2 clock source. 2035 * @retval The clock source can be one of the following values: 2036 * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) 2037 * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) 2038 * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) 2039 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 2040 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 2041 */ 2042 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) 2043 #endif /* SAI2 */ 2044 2045 /** @brief Macro to configure the MDF1 clock. 2046 * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. 2047 * This parameter can be one of the following values: 2048 * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock 2049 * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 P Clock selected as MDF1 clock 2050 * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Q Clock selected as MDF1 clock 2051 * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as MDF1 clock 2052 * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock selected as MDF1 clock 2053 * @retval None 2054 */ 2055 #define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \ 2056 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, (uint32_t)(__MDF1_CLKSOURCE__)) 2057 2058 /** @brief Macro to get the MDF1 clock source. 2059 * @retval The clock source can be one of the following values: 2060 * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock used as MDF1 clock 2061 * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 Clock used as MDF1 clock 2062 * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Clock used as MDF1 clock 2063 * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as MDF1 clock 2064 * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock used as MDF1 clock 2065 */ 2066 #define __HAL_RCC_GET_MDF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL))) 2067 2068 /** @brief Macro to configure the ADF1 clock. 2069 * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. 2070 * This parameter can be one of the following values: 2071 * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock 2072 * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock selected as ADF1 clock 2073 * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock selected as ADF1 clock 2074 * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as ADF1 clock 2075 * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock selected as ADF1 clock 2076 * @retval None 2077 */ 2078 #define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ 2079 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, (uint32_t)(__ADF1_CLKSOURCE__)) 2080 2081 /** @brief Macro to get the ADF1 clock source. 2082 * @retval The clock source can be one of the following values: 2083 * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock used as ADF1 clock 2084 * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock used as ADF1 clock 2085 * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock used as ADF1 clock 2086 * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as ADF1 clock 2087 * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock used as ADF1 clock 2088 */ 2089 #define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL))) 2090 2091 /** @brief Macro to configure the DAC1 interface clock. 2092 * @param __DAC1_CLKSOURCE__ specifies the DAC1 digital interface clock source. 2093 * This parameter can be one of the following values: 2094 * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock 2095 * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock 2096 * @retval None 2097 */ 2098 #define __HAL_RCC_DAC1_CONFIG(__DAC1_CLKSOURCE__) \ 2099 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, (uint32_t)(__DAC1_CLKSOURCE__)) 2100 2101 /** @brief Macro to get the DAC1 clock source. 2102 * @retval The clock source can be one of the following values: 2103 * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock 2104 * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock 2105 */ 2106 #define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL))) 2107 2108 #if defined(LTDC) 2109 2110 /** @brief Macro to configure the LTDC clock. 2111 * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. 2112 * This parameter can be one of the following values: 2113 * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock 2114 * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock 2115 * @retval None 2116 */ 2117 #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ 2118 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, (__LTDC_CLKSOURCE__)) 2119 2120 /** @brief Macro to get the LTDC clock source. 2121 * @retval The clock source can be one of the following values: 2122 * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock 2123 * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock 2124 */ 2125 #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL)) 2126 2127 #endif /* LTDC */ 2128 2129 #if defined(DSI) 2130 2131 /** @brief Macro to configure the DSI clock. 2132 * @param __DSI_CLKSOURCE__ specifies the DSI clock source. 2133 * This parameter can be one of the following values: 2134 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 2135 * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) 2136 * @retval None 2137 */ 2138 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ 2139 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, (__DSI_CLKSOURCE__)) 2140 2141 /** @brief Macro to get the DSI clock source. 2142 * @retval The clock source can be one of the following values: 2143 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 2144 * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) 2145 */ 2146 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL)) 2147 2148 #endif /* DSI */ 2149 2150 #if defined(USB_OTG_HS) 2151 2152 /** @brief Macro to configure the USB PHY clock. 2153 * @param __USBPHY_CLKSOURCE__ specifies the USB PHY clock source. 2154 * This parameter can be one of the following values: 2155 * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock 2156 * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock 2157 * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock 2158 * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock 2159 * @retval None 2160 */ 2161 #define __HAL_RCC_USBPHY_CONFIG(__USBPHY_CLKSOURCE__) \ 2162 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, (__USBPHY_CLKSOURCE__)) 2163 2164 /** @brief Macro to get the USB PHY clock source. 2165 * @retval The clock source can be one of the following values: 2166 * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock 2167 * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock 2168 * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock 2169 * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock 2170 */ 2171 #define __HAL_RCC_GET_USBPHY_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL)) 2172 2173 #endif /* USB_OTG_HS */ 2174 2175 #if defined(RCC_CFGR2_PPRE_DPHY) 2176 2177 /** @brief Macro to configure the DPHY clock. 2178 * @param __PRESCALER__ specifies the DPHY clock source prescaler. 2179 * This parameter can be one of the following values: 2180 * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock 2181 * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock 2182 * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock 2183 * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock 2184 * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock 2185 * @retval None 2186 */ 2187 #define __HAL_RCC_DPHY_CONFIG(__PRESCALER__) \ 2188 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, (__PRESCALER__) << 8UL) 2189 2190 /** @brief Macro to get the DPHY clock prescaler configuration. 2191 * @retval The clock source prescaler can be one of the following values: 2192 * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock 2193 * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock 2194 * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock 2195 * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock 2196 * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock 2197 * @retval None 2198 */ 2199 #define __HAL_RCC_GET_DPHY_CONFIG() (READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY) >> 8UL) 2200 2201 #endif /* defined(RCC_CFGR2_PPRE_DPHY) */ 2202 2203 #if defined(CRS) 2204 2205 /** 2206 * @brief Enable the specified CRS interrupts. 2207 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 2208 * This parameter can be any combination of the following values: 2209 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2210 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2211 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2212 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2213 * @retval None 2214 */ 2215 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 2216 2217 /** 2218 * @brief Disable the specified CRS interrupts. 2219 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 2220 * This parameter can be any combination of the following values: 2221 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2222 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2223 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2224 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2225 * @retval None 2226 */ 2227 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 2228 2229 /** @brief Check whether the CRS interrupt has occurred or not. 2230 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 2231 * This parameter can be one of the following values: 2232 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2233 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2234 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2235 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2236 * @retval The new state of __INTERRUPT__ (SET or RESET). 2237 */ 2238 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) 2239 2240 /** @brief Clear the CRS interrupt pending bits 2241 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2242 * This parameter can be any combination of the following values: 2243 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2244 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2245 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2246 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2247 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 2248 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 2249 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 2250 */ 2251 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 2252 2253 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 2254 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 2255 { \ 2256 WRITE_REG(CRS->ICR, CRS_ICR_ERRC |\ 2257 ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 2258 } \ 2259 else \ 2260 { \ 2261 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 2262 } \ 2263 } while(0) 2264 2265 /** 2266 * @brief Check whether the specified CRS flag is set or not. 2267 * @param __FLAG__ specifies the flag to check. 2268 * This parameter can be one of the following values: 2269 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2270 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2271 * @arg @ref RCC_CRS_FLAG_ERR Error 2272 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2273 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2274 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2275 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2276 * @retval The new state of _FLAG_ (TRUE or FALSE). 2277 */ 2278 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 2279 2280 /** 2281 * @brief Clear the CRS specified FLAG. 2282 * @param __FLAG__ specifies the flag to clear. 2283 * This parameter can be one of the following values: 2284 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2285 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2286 * @arg @ref RCC_CRS_FLAG_ERR Error 2287 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2288 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2289 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2290 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2291 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently 2292 * RCC_CRS_FLAG_ERR 2293 * @retval None 2294 */ 2295 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | \ 2296 RCC_CRS_FLAG_SYNCMISS)) 2297 2298 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 2299 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 2300 { \ 2301 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ 2302 ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 2303 } \ 2304 else \ 2305 { \ 2306 WRITE_REG(CRS->ICR, (__FLAG__)); \ 2307 } \ 2308 } while(0) 2309 2310 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 2311 * @{ 2312 */ 2313 /** 2314 * @brief Enable the oscillator clock for frequency error counter. 2315 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 2316 * @retval None 2317 */ 2318 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 2319 2320 /** 2321 * @brief Disable the oscillator clock for frequency error counter. 2322 * @retval None 2323 */ 2324 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 2325 2326 /** 2327 * @brief Enable the automatic hardware adjustment of TRIM bits. 2328 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 2329 * @retval None 2330 */ 2331 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2332 2333 /** 2334 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 2335 * @retval None 2336 */ 2337 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2338 2339 /** 2340 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 2341 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 2342 * of the synchronization source after prescaling. It is then decreased by one in order to 2343 * reach the expected synchronization on the zero value. The formula is the following: 2344 * RELOAD = (fTARGET / fSYNC) -1 2345 * @param __FTARGET__ Target frequency (value in Hz) 2346 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 2347 * @retval None 2348 */ 2349 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 2350 2351 2352 /** 2353 * @} 2354 */ 2355 2356 #endif /* CRS */ 2357 2358 /** 2359 * @} 2360 */ 2361 2362 /* Exported functions --------------------------------------------------------*/ 2363 /** @addtogroup RCCEx_Exported_Functions 2364 * @{ 2365 */ 2366 2367 /** @addtogroup RCCEx_Exported_Functions_Group1 2368 * @{ 2369 */ 2370 2371 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 2372 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); 2373 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 2374 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); 2375 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); 2376 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); 2377 /** 2378 * @} 2379 */ 2380 2381 /** @addtogroup RCCEx_Exported_Functions_Group2 2382 * @{ 2383 */ 2384 2385 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init); 2386 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 2387 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init); 2388 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); 2389 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void); 2390 HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void); 2391 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection); 2392 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 2393 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); 2394 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 2395 void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange); 2396 void HAL_RCCEx_EnableLSECSS(void); 2397 void HAL_RCCEx_DisableLSECSS(void); 2398 void HAL_RCCEx_EnableLSECSS_IT(void); 2399 void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void); 2400 void HAL_RCCEx_LSECSS_IRQHandler(void); 2401 void HAL_RCCEx_LSECSS_Callback(void); 2402 void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void); 2403 void HAL_RCCEx_MSIPLLUNLCK_Callback(void); 2404 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 2405 void HAL_RCCEx_DisableLSCO(void); 2406 void HAL_RCCEx_EnableMSIPLLMode(void); 2407 void HAL_RCCEx_DisableMSIPLLMode(void); 2408 /** 2409 * @} 2410 */ 2411 2412 #if defined(CRS) 2413 2414 /** @addtogroup RCCEx_Exported_Functions_Group3 2415 * @{ 2416 */ 2417 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit); 2418 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 2419 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 2420 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 2421 void HAL_RCCEx_CRS_IRQHandler(void); 2422 void HAL_RCCEx_CRS_SyncOkCallback(void); 2423 void HAL_RCCEx_CRS_SyncWarnCallback(void); 2424 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 2425 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 2426 /** 2427 * @} 2428 */ 2429 2430 #endif /* CRS */ 2431 2432 /** 2433 * @} 2434 */ 2435 2436 /** 2437 * @} 2438 */ 2439 2440 /** 2441 * @} 2442 */ 2443 2444 #ifdef __cplusplus 2445 } 2446 #endif 2447 2448 #endif /* STM32U5xx_HAL_RCC_EX_H */ 2449
