1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F7xx_HAL_RCC_EX_H 20 #define __STM32F7xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f7xx_hal_def.h" 28 29 /** @addtogroup STM32F7xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 55 56 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 57 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 58 59 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). 60 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 61 62 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. 63 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ 64 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 65 uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. 66 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ 67 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 68 69 }RCC_PLLInitTypeDef; 70 71 /** 72 * @brief PLLI2S Clock structure definition 73 */ 74 typedef struct 75 { 76 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 77 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 78 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 79 80 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 81 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 82 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 83 84 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. 85 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 86 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 87 88 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ 89 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 90 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. 91 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. 92 This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ 93 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 94 }RCC_PLLI2SInitTypeDef; 95 96 /** 97 * @brief PLLSAI Clock structure definition 98 */ 99 typedef struct 100 { 101 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 102 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 103 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 104 105 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. 106 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 107 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 108 109 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ 110 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 111 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock 112 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 113 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ 114 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 115 116 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. 117 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider 118 This parameter will be used only when PLLSAI is disabled */ 119 }RCC_PLLSAIInitTypeDef; 120 121 /** 122 * @brief RCC extended clocks structure definition 123 */ 124 typedef struct 125 { 126 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 127 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 128 129 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 130 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 131 132 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 133 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 134 135 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 136 This parameter must be a number between Min_Data = 1 and Max_Data = 32 137 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 138 139 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 140 This parameter must be a number between Min_Data = 1 and Max_Data = 32 141 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 142 143 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. 144 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ 145 146 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. 147 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 148 149 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. 150 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 151 152 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 153 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ 154 155 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection 156 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 157 158 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection 159 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 160 161 uint32_t Usart1ClockSelection; /*!< USART1 clock source 162 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 163 164 uint32_t Usart2ClockSelection; /*!< USART2 clock source 165 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 166 167 uint32_t Usart3ClockSelection; /*!< USART3 clock source 168 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 169 170 uint32_t Uart4ClockSelection; /*!< UART4 clock source 171 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 172 173 uint32_t Uart5ClockSelection; /*!< UART5 clock source 174 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 175 176 uint32_t Usart6ClockSelection; /*!< USART6 clock source 177 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ 178 179 uint32_t Uart7ClockSelection; /*!< UART7 clock source 180 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ 181 182 uint32_t Uart8ClockSelection; /*!< UART8 clock source 183 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ 184 185 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 186 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 187 188 uint32_t I2c2ClockSelection; /*!< I2C2 clock source 189 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 190 191 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 192 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 193 194 uint32_t I2c4ClockSelection; /*!< I2C4 clock source 195 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 196 197 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 198 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 199 200 uint32_t CecClockSelection; /*!< CEC clock source 201 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 202 203 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC 204 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 205 206 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source 207 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 208 209 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 210 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 211 uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source 212 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ 213 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 214 215 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 216 uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source 217 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ 218 219 uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source 220 This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ 221 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 222 }RCC_PeriphCLKInitTypeDef; 223 /** 224 * @} 225 */ 226 227 /* Exported constants --------------------------------------------------------*/ 228 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 229 * @{ 230 */ 231 232 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection 233 * @{ 234 */ 235 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) 236 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 237 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) 238 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 239 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) 240 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) 241 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) 242 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) 243 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) 244 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) 245 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) 246 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) 247 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) 248 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) 249 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) 250 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) 251 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) 252 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) 253 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) 254 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) 255 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) 256 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) 257 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) 258 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) 259 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) 260 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) 261 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 262 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 263 #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) 264 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 265 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 266 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) 267 #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) 268 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 269 270 /** 271 * @} 272 */ 273 274 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ 275 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 276 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider 277 * @{ 278 */ 279 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) 280 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) 281 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) 282 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) 283 /** 284 * @} 285 */ 286 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 287 288 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider 289 * @{ 290 */ 291 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) 292 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) 293 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) 294 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) 295 /** 296 * @} 297 */ 298 299 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR 300 * @{ 301 */ 302 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) 303 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 304 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 305 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR 306 /** 307 * @} 308 */ 309 310 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source 311 * @{ 312 */ 313 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) 314 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC 315 316 /** 317 * @} 318 */ 319 320 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source 321 * @{ 322 */ 323 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) 324 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 325 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 326 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 327 #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL 328 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 329 /** 330 * @} 331 */ 332 333 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source 334 * @{ 335 */ 336 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) 337 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 338 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 339 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 340 #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL 341 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source 347 * @{ 348 */ 349 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) 350 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ 351 /** 352 * @} 353 */ 354 355 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source 356 * @{ 357 */ 358 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 359 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 360 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 361 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL 362 /** 363 * @} 364 */ 365 366 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 367 * @{ 368 */ 369 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 370 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 371 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 372 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL 373 /** 374 * @} 375 */ 376 377 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source 378 * @{ 379 */ 380 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 381 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 382 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 383 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL 384 /** 385 * @} 386 */ 387 388 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source 389 * @{ 390 */ 391 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 392 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 393 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 394 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL 395 /** 396 * @} 397 */ 398 399 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source 400 * @{ 401 */ 402 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 403 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 404 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 405 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL 406 /** 407 * @} 408 */ 409 410 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source 411 * @{ 412 */ 413 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 414 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 415 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 416 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL 417 /** 418 * @} 419 */ 420 421 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source 422 * @{ 423 */ 424 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 425 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 426 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 427 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL 428 /** 429 * @} 430 */ 431 432 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source 433 * @{ 434 */ 435 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 436 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 437 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 438 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL 439 /** 440 * @} 441 */ 442 443 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source 444 * @{ 445 */ 446 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 447 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 448 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 449 /** 450 * @} 451 */ 452 453 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source 454 * @{ 455 */ 456 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 457 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 458 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 459 460 /** 461 * @} 462 */ 463 464 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source 465 * @{ 466 */ 467 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 468 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 469 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 470 /** 471 * @} 472 */ 473 474 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source 475 * @{ 476 */ 477 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 478 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 479 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 480 /** 481 * @} 482 */ 483 484 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source 485 * @{ 486 */ 487 #define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) 488 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 489 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 490 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL 491 492 /** 493 * @} 494 */ 495 496 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source 497 * @{ 498 */ 499 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) 500 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL 501 /** 502 * @} 503 */ 504 505 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection 506 * @{ 507 */ 508 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) 509 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE 510 /** 511 * @} 512 */ 513 514 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source 515 * @{ 516 */ 517 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) 518 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL 519 /** 520 * @} 521 */ 522 523 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 524 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 525 /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source 526 * @{ 527 */ 528 #define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) 529 #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL 530 /** 531 * @} 532 */ 533 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 534 535 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 536 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source 537 * @{ 538 */ 539 #define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) 540 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL 541 /** 542 * @} 543 */ 544 545 /** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source 546 * @{ 547 */ 548 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) 549 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL 550 /** 551 * @} 552 */ 553 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 554 555 #if defined (STM32F769xx) || defined (STM32F779xx) 556 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source 557 * @{ 558 */ 559 #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) 560 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) 561 /** 562 * @} 563 */ 564 #endif /* STM32F769xx || STM32F779xx */ 565 566 /** 567 * @} 568 */ 569 570 /* Exported macro ------------------------------------------------------------*/ 571 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 572 * @{ 573 */ 574 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable 575 * @brief Enables or disables the AHB/APB peripheral clock. 576 * @note After reset, the peripheral clock (used for registers read/write access) 577 * is disabled and the application software has to enable this clock before 578 * using it. 579 * @{ 580 */ 581 582 /** @brief Enables or disables the AHB1 peripheral clock. 583 * @note After reset, the peripheral clock (used for registers read/write access) 584 * is disabled and the application software has to enable this clock before 585 * using it. 586 */ 587 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 588 __IO uint32_t tmpreg; \ 589 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 590 /* Delay after an RCC peripheral clock enabling */ \ 591 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 592 UNUSED(tmpreg); \ 593 } while(0) 594 595 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ 596 __IO uint32_t tmpreg; \ 597 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ 598 /* Delay after an RCC peripheral clock enabling */ \ 599 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ 600 UNUSED(tmpreg); \ 601 } while(0) 602 603 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 604 __IO uint32_t tmpreg; \ 605 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 606 /* Delay after an RCC peripheral clock enabling */ \ 607 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 608 UNUSED(tmpreg); \ 609 } while(0) 610 611 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 612 __IO uint32_t tmpreg; \ 613 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 614 /* Delay after an RCC peripheral clock enabling */ \ 615 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 616 UNUSED(tmpreg); \ 617 } while(0) 618 619 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 620 __IO uint32_t tmpreg; \ 621 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 622 /* Delay after an RCC peripheral clock enabling */ \ 623 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 624 UNUSED(tmpreg); \ 625 } while(0) 626 627 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 628 __IO uint32_t tmpreg; \ 629 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 630 /* Delay after an RCC peripheral clock enabling */ \ 631 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 632 UNUSED(tmpreg); \ 633 } while(0) 634 635 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 636 __IO uint32_t tmpreg; \ 637 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 638 /* Delay after an RCC peripheral clock enabling */ \ 639 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 640 UNUSED(tmpreg); \ 641 } while(0) 642 643 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 644 __IO uint32_t tmpreg; \ 645 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 646 /* Delay after an RCC peripheral clock enabling */ \ 647 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 648 UNUSED(tmpreg); \ 649 } while(0) 650 651 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 652 __IO uint32_t tmpreg; \ 653 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 654 /* Delay after an RCC peripheral clock enabling */ \ 655 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 656 UNUSED(tmpreg); \ 657 } while(0) 658 659 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 660 __IO uint32_t tmpreg; \ 661 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 662 /* Delay after an RCC peripheral clock enabling */ \ 663 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 664 UNUSED(tmpreg); \ 665 } while(0) 666 667 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 668 __IO uint32_t tmpreg; \ 669 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 670 /* Delay after an RCC peripheral clock enabling */ \ 671 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 672 UNUSED(tmpreg); \ 673 } while(0) 674 675 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 676 __IO uint32_t tmpreg; \ 677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 678 /* Delay after an RCC peripheral clock enabling */ \ 679 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 680 UNUSED(tmpreg); \ 681 } while(0) 682 683 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 684 __IO uint32_t tmpreg; \ 685 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 686 /* Delay after an RCC peripheral clock enabling */ \ 687 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 688 UNUSED(tmpreg); \ 689 } while(0) 690 691 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 692 __IO uint32_t tmpreg; \ 693 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 694 /* Delay after an RCC peripheral clock enabling */ \ 695 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 696 UNUSED(tmpreg); \ 697 } while(0) 698 699 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 700 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 701 defined (STM32F750xx) 702 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 703 __IO uint32_t tmpreg; \ 704 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 705 /* Delay after an RCC peripheral clock enabling */ \ 706 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 707 UNUSED(tmpreg); \ 708 } while(0) 709 710 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 711 __IO uint32_t tmpreg; \ 712 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 713 /* Delay after an RCC peripheral clock enabling */ \ 714 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 715 UNUSED(tmpreg); \ 716 } while(0) 717 718 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 719 __IO uint32_t tmpreg; \ 720 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 721 /* Delay after an RCC peripheral clock enabling */ \ 722 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 723 UNUSED(tmpreg); \ 724 } while(0) 725 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 726 727 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 728 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) 729 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) 730 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 731 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 732 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) 733 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) 734 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) 735 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 736 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 737 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 738 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 739 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) 740 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 741 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 742 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 743 defined (STM32F750xx) 744 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) 745 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) 746 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) 747 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 748 749 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 750 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 751 defined (STM32F750xx) 752 /** 753 * @brief Enable ETHERNET clock. 754 */ 755 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 756 __IO uint32_t tmpreg; \ 757 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 758 /* Delay after an RCC peripheral clock enabling */ \ 759 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 760 UNUSED(tmpreg); \ 761 } while(0) 762 763 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 764 __IO uint32_t tmpreg; \ 765 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 766 /* Delay after an RCC peripheral clock enabling */ \ 767 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 768 UNUSED(tmpreg); \ 769 } while(0) 770 771 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 772 __IO uint32_t tmpreg; \ 773 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 774 /* Delay after an RCC peripheral clock enabling */ \ 775 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 776 UNUSED(tmpreg); \ 777 } while(0) 778 779 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 780 __IO uint32_t tmpreg; \ 781 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 782 /* Delay after an RCC peripheral clock enabling */ \ 783 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 784 UNUSED(tmpreg); \ 785 } while(0) 786 787 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 788 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 789 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 790 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 791 } while(0) 792 /** 793 * @brief Disable ETHERNET clock. 794 */ 795 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 796 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 797 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 798 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 799 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 800 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 801 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 802 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 803 } while(0) 804 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 805 806 /** @brief Enable or disable the AHB2 peripheral clock. 807 * @note After reset, the peripheral clock (used for registers read/write access) 808 * is disabled and the application software has to enable this clock before 809 * using it. 810 */ 811 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 812 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 813 defined (STM32F750xx) 814 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 815 __IO uint32_t tmpreg; \ 816 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 817 /* Delay after an RCC peripheral clock enabling */ \ 818 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 819 UNUSED(tmpreg); \ 820 } while(0) 821 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 822 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 823 824 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 825 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ 826 __IO uint32_t tmpreg; \ 827 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ 828 /* Delay after an RCC peripheral clock enabling */ \ 829 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ 830 UNUSED(tmpreg); \ 831 } while(0) 832 #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) 833 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 834 835 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 836 __IO uint32_t tmpreg; \ 837 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 838 /* Delay after an RCC peripheral clock enabling */ \ 839 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 840 UNUSED(tmpreg); \ 841 } while(0) 842 843 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 844 __IO uint32_t tmpreg; \ 845 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ 846 /* Delay after an RCC peripheral clock enabling */ \ 847 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ 848 UNUSED(tmpreg); \ 849 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 850 } while(0) 851 852 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 853 854 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 855 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 856 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 857 __IO uint32_t tmpreg; \ 858 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 859 /* Delay after an RCC peripheral clock enabling */ \ 860 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 861 UNUSED(tmpreg); \ 862 } while(0) 863 864 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 865 __IO uint32_t tmpreg; \ 866 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 867 /* Delay after an RCC peripheral clock enabling */ \ 868 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 869 UNUSED(tmpreg); \ 870 } while(0) 871 872 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 873 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 874 #endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ 875 876 #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) 877 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 878 __IO uint32_t tmpreg; \ 879 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 880 /* Delay after an RCC peripheral clock enabling */ \ 881 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 882 UNUSED(tmpreg); \ 883 } while(0) 884 885 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) 886 #endif /* STM32F732xx || STM32F733xx || STM32F730xx */ 887 888 /** @brief Enables or disables the AHB3 peripheral clock. 889 * @note After reset, the peripheral clock (used for registers read/write access) 890 * is disabled and the application software has to enable this clock before 891 * using it. 892 */ 893 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 894 __IO uint32_t tmpreg; \ 895 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 896 /* Delay after an RCC peripheral clock enabling */ \ 897 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 898 UNUSED(tmpreg); \ 899 } while(0) 900 901 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 902 __IO uint32_t tmpreg; \ 903 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 904 /* Delay after an RCC peripheral clock enabling */ \ 905 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 906 UNUSED(tmpreg); \ 907 } while(0) 908 909 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 910 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 911 912 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 913 * @note After reset, the peripheral clock (used for registers read/write access) 914 * is disabled and the application software has to enable this clock before 915 * using it. 916 */ 917 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 918 __IO uint32_t tmpreg; \ 919 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 920 /* Delay after an RCC peripheral clock enabling */ \ 921 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 922 UNUSED(tmpreg); \ 923 } while(0) 924 925 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 926 __IO uint32_t tmpreg; \ 927 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 928 /* Delay after an RCC peripheral clock enabling */ \ 929 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 930 UNUSED(tmpreg); \ 931 } while(0) 932 933 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 934 __IO uint32_t tmpreg; \ 935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 936 /* Delay after an RCC peripheral clock enabling */ \ 937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 938 UNUSED(tmpreg); \ 939 } while(0) 940 941 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 942 __IO uint32_t tmpreg; \ 943 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 944 /* Delay after an RCC peripheral clock enabling */ \ 945 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 946 UNUSED(tmpreg); \ 947 } while(0) 948 949 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 950 __IO uint32_t tmpreg; \ 951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 952 /* Delay after an RCC peripheral clock enabling */ \ 953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 954 UNUSED(tmpreg); \ 955 } while(0) 956 957 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 958 __IO uint32_t tmpreg; \ 959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 960 /* Delay after an RCC peripheral clock enabling */ \ 961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 962 UNUSED(tmpreg); \ 963 } while(0) 964 965 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 966 __IO uint32_t tmpreg; \ 967 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 968 /* Delay after an RCC peripheral clock enabling */ \ 969 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 970 UNUSED(tmpreg); \ 971 } while(0) 972 973 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 974 __IO uint32_t tmpreg; \ 975 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 976 /* Delay after an RCC peripheral clock enabling */ \ 977 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 978 UNUSED(tmpreg); \ 979 } while(0) 980 981 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 982 __IO uint32_t tmpreg; \ 983 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 984 /* Delay after an RCC peripheral clock enabling */ \ 985 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 986 UNUSED(tmpreg); \ 987 } while(0) 988 989 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 990 __IO uint32_t tmpreg; \ 991 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 992 /* Delay after an RCC peripheral clock enabling */ \ 993 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 994 UNUSED(tmpreg); \ 995 } while(0) 996 997 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ 998 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ 999 defined (STM32F779xx) || defined (STM32F730xx) 1000 #define __HAL_RCC_RTC_CLK_ENABLE() do { \ 1001 __IO uint32_t tmpreg; \ 1002 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ 1003 /* Delay after an RCC peripheral clock enabling */ \ 1004 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ 1005 UNUSED(tmpreg); \ 1006 } while(0) 1007 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || 1008 STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 1009 1010 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1011 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ 1012 __IO uint32_t tmpreg; \ 1013 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 1014 /* Delay after an RCC peripheral clock enabling */ \ 1015 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 1016 UNUSED(tmpreg); \ 1017 } while(0) 1018 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1019 1020 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1021 __IO uint32_t tmpreg; \ 1022 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 1023 /* Delay after an RCC peripheral clock enabling */ \ 1024 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 1025 UNUSED(tmpreg); \ 1026 } while(0) 1027 1028 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1029 __IO uint32_t tmpreg; \ 1030 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1031 /* Delay after an RCC peripheral clock enabling */ \ 1032 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1033 UNUSED(tmpreg); \ 1034 } while(0) 1035 1036 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1037 __IO uint32_t tmpreg; \ 1038 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 1039 /* Delay after an RCC peripheral clock enabling */ \ 1040 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 1041 UNUSED(tmpreg); \ 1042 } while(0) 1043 1044 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1045 __IO uint32_t tmpreg; \ 1046 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1047 /* Delay after an RCC peripheral clock enabling */ \ 1048 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1049 UNUSED(tmpreg); \ 1050 } while(0) 1051 1052 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1053 __IO uint32_t tmpreg; \ 1054 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1055 /* Delay after an RCC peripheral clock enabling */ \ 1056 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1057 UNUSED(tmpreg); \ 1058 } while(0) 1059 1060 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1061 __IO uint32_t tmpreg; \ 1062 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1063 /* Delay after an RCC peripheral clock enabling */ \ 1064 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1065 UNUSED(tmpreg); \ 1066 } while(0) 1067 1068 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1069 __IO uint32_t tmpreg; \ 1070 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 1071 /* Delay after an RCC peripheral clock enabling */ \ 1072 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 1073 UNUSED(tmpreg); \ 1074 } while(0) 1075 1076 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1077 __IO uint32_t tmpreg; \ 1078 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 1079 /* Delay after an RCC peripheral clock enabling */ \ 1080 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 1081 UNUSED(tmpreg); \ 1082 } while(0) 1083 1084 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1085 __IO uint32_t tmpreg; \ 1086 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1087 /* Delay after an RCC peripheral clock enabling */ \ 1088 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1089 UNUSED(tmpreg); \ 1090 } while(0) 1091 1092 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1093 __IO uint32_t tmpreg; \ 1094 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1095 /* Delay after an RCC peripheral clock enabling */ \ 1096 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1097 UNUSED(tmpreg); \ 1098 } while(0) 1099 1100 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 1101 __IO uint32_t tmpreg; \ 1102 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1103 /* Delay after an RCC peripheral clock enabling */ \ 1104 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1105 UNUSED(tmpreg); \ 1106 } while(0) 1107 1108 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1109 __IO uint32_t tmpreg; \ 1110 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1111 /* Delay after an RCC peripheral clock enabling */ \ 1112 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1113 UNUSED(tmpreg); \ 1114 } while(0) 1115 1116 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1117 __IO uint32_t tmpreg; \ 1118 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1119 /* Delay after an RCC peripheral clock enabling */ \ 1120 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1121 UNUSED(tmpreg); \ 1122 } while(0) 1123 1124 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1125 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1126 defined (STM32F750xx) 1127 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 1128 __IO uint32_t tmpreg; \ 1129 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 1130 /* Delay after an RCC peripheral clock enabling */ \ 1131 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 1132 UNUSED(tmpreg); \ 1133 } while(0) 1134 1135 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1136 __IO uint32_t tmpreg; \ 1137 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ 1138 /* Delay after an RCC peripheral clock enabling */ \ 1139 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ 1140 UNUSED(tmpreg); \ 1141 } while(0) 1142 1143 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1144 __IO uint32_t tmpreg; \ 1145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1146 /* Delay after an RCC peripheral clock enabling */ \ 1147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1148 UNUSED(tmpreg); \ 1149 } while(0) 1150 1151 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1152 __IO uint32_t tmpreg; \ 1153 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 1154 /* Delay after an RCC peripheral clock enabling */ \ 1155 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 1156 UNUSED(tmpreg); \ 1157 } while(0) 1158 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1159 1160 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 1161 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 1162 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 1163 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 1164 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 1165 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 1166 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1167 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1168 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1169 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 1170 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ 1171 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ 1172 defined (STM32F779xx) || defined (STM32F730xx) 1173 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) 1174 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || 1175 STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 1176 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1177 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) 1178 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1179 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 1180 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 1181 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 1182 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 1183 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 1184 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 1185 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 1186 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 1187 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 1188 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 1189 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 1190 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 1191 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 1192 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1193 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1194 defined (STM32F750xx) 1195 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) 1196 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) 1197 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 1198 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 1199 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ 1200 1201 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. 1202 * @note After reset, the peripheral clock (used for registers read/write access) 1203 * is disabled and the application software has to enable this clock before 1204 * using it. 1205 */ 1206 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1207 __IO uint32_t tmpreg; \ 1208 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 1209 /* Delay after an RCC peripheral clock enabling */ \ 1210 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 1211 UNUSED(tmpreg); \ 1212 } while(0) 1213 1214 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1215 __IO uint32_t tmpreg; \ 1216 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1217 /* Delay after an RCC peripheral clock enabling */ \ 1218 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1219 UNUSED(tmpreg); \ 1220 } while(0) 1221 1222 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1223 __IO uint32_t tmpreg; \ 1224 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 1225 /* Delay after an RCC peripheral clock enabling */ \ 1226 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 1227 UNUSED(tmpreg); \ 1228 } while(0) 1229 1230 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1231 __IO uint32_t tmpreg; \ 1232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 1233 /* Delay after an RCC peripheral clock enabling */ \ 1234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 1235 UNUSED(tmpreg); \ 1236 } while(0) 1237 1238 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 1239 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 1240 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 1241 __IO uint32_t tmpreg; \ 1242 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ 1243 /* Delay after an RCC peripheral clock enabling */ \ 1244 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ 1245 UNUSED(tmpreg); \ 1246 } while(0) 1247 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ 1248 1249 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 1250 __IO uint32_t tmpreg; \ 1251 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 1252 /* Delay after an RCC peripheral clock enabling */ \ 1253 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 1254 UNUSED(tmpreg); \ 1255 } while(0) 1256 1257 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 1258 __IO uint32_t tmpreg; \ 1259 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1260 /* Delay after an RCC peripheral clock enabling */ \ 1261 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1262 UNUSED(tmpreg); \ 1263 } while(0) 1264 1265 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 1266 __IO uint32_t tmpreg; \ 1267 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1268 /* Delay after an RCC peripheral clock enabling */ \ 1269 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1270 UNUSED(tmpreg); \ 1271 } while(0) 1272 1273 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1274 __IO uint32_t tmpreg; \ 1275 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ 1276 /* Delay after an RCC peripheral clock enabling */ \ 1277 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ 1278 UNUSED(tmpreg); \ 1279 } while(0) 1280 1281 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1282 __IO uint32_t tmpreg; \ 1283 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 1284 /* Delay after an RCC peripheral clock enabling */ \ 1285 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 1286 UNUSED(tmpreg); \ 1287 } while(0) 1288 1289 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1290 __IO uint32_t tmpreg; \ 1291 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1292 /* Delay after an RCC peripheral clock enabling */ \ 1293 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1294 UNUSED(tmpreg); \ 1295 } while(0) 1296 1297 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 1298 __IO uint32_t tmpreg; \ 1299 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 1300 /* Delay after an RCC peripheral clock enabling */ \ 1301 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 1302 UNUSED(tmpreg); \ 1303 } while(0) 1304 1305 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 1306 __IO uint32_t tmpreg; \ 1307 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1308 /* Delay after an RCC peripheral clock enabling */ \ 1309 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1310 UNUSED(tmpreg); \ 1311 } while(0) 1312 1313 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 1314 __IO uint32_t tmpreg; \ 1315 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 1316 /* Delay after an RCC peripheral clock enabling */ \ 1317 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 1318 UNUSED(tmpreg); \ 1319 } while(0) 1320 1321 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1322 __IO uint32_t tmpreg; \ 1323 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1324 /* Delay after an RCC peripheral clock enabling */ \ 1325 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1326 UNUSED(tmpreg); \ 1327 } while(0) 1328 1329 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1330 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1331 defined (STM32F750xx) 1332 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1333 __IO uint32_t tmpreg; \ 1334 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1335 /* Delay after an RCC peripheral clock enabling */ \ 1336 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1337 UNUSED(tmpreg); \ 1338 } while(0) 1339 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1340 1341 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1342 __IO uint32_t tmpreg; \ 1343 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1344 /* Delay after an RCC peripheral clock enabling */ \ 1345 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1346 UNUSED(tmpreg); \ 1347 } while(0) 1348 1349 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1350 __IO uint32_t tmpreg; \ 1351 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 1352 /* Delay after an RCC peripheral clock enabling */ \ 1353 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 1354 UNUSED(tmpreg); \ 1355 } while(0) 1356 1357 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1358 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1359 __IO uint32_t tmpreg; \ 1360 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1361 /* Delay after an RCC peripheral clock enabling */ \ 1362 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1363 UNUSED(tmpreg); \ 1364 } while(0) 1365 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1366 1367 #if defined (STM32F769xx) || defined (STM32F779xx) 1368 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1369 __IO uint32_t tmpreg; \ 1370 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1371 /* Delay after an RCC peripheral clock enabling */ \ 1372 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1373 UNUSED(tmpreg); \ 1374 } while(0) 1375 #endif /* STM32F769xx || STM32F779xx */ 1376 1377 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1378 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 1379 __IO uint32_t tmpreg; \ 1380 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 1381 /* Delay after an RCC peripheral clock enabling */ \ 1382 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 1383 UNUSED(tmpreg); \ 1384 } while(0) 1385 1386 #define __HAL_RCC_MDIO_CLK_ENABLE() do { \ 1387 __IO uint32_t tmpreg; \ 1388 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ 1389 /* Delay after an RCC peripheral clock enabling */ \ 1390 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ 1391 UNUSED(tmpreg); \ 1392 } while(0) 1393 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1394 #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) 1395 #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ 1396 __IO uint32_t tmpreg; \ 1397 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ 1398 /* Delay after an RCC peripheral clock enabling */ \ 1399 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ 1400 UNUSED(tmpreg); \ 1401 } while(0) 1402 #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ 1403 1404 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 1405 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 1406 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 1407 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) 1408 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 1409 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 1410 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) 1411 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 1412 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 1413 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 1414 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 1415 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) 1416 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 1417 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 1418 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 1419 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 1420 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 1421 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 1422 1423 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1424 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1425 defined (STM32F750xx) 1426 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) 1427 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1428 1429 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 1430 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) 1431 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1432 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) 1433 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1434 #if defined (STM32F769xx) || defined (STM32F779xx) 1435 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) 1436 #endif /* STM32F769xx || STM32F779xx */ 1437 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1438 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) 1439 #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) 1440 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1441 #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) 1442 #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) 1443 #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ 1444 1445 /** 1446 * @} 1447 */ 1448 1449 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status 1450 * @brief Get the enable or disable status of the AHB/APB peripheral clock. 1451 * @note After reset, the peripheral clock (used for registers read/write access) 1452 * is disabled and the application software has to enable this clock before 1453 * using it. 1454 * @{ 1455 */ 1456 1457 /** @brief Get the enable or disable status of the AHB1 peripheral clock. 1458 * @note After reset, the peripheral clock (used for registers read/write access) 1459 * is disabled and the application software has to enable this clock before 1460 * using it. 1461 */ 1462 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 1463 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) 1464 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) 1465 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 1466 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 1467 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) 1468 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) 1469 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) 1470 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 1471 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 1472 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 1473 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 1474 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) 1475 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 1476 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1477 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1478 defined (STM32F750xx) 1479 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 1480 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) 1481 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 1482 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1483 1484 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 1485 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) 1486 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) 1487 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 1488 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 1489 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) 1490 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) 1491 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) 1492 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 1493 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 1494 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 1495 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 1496 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) 1497 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 1498 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1499 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1500 defined (STM32F750xx) 1501 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 1502 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) 1503 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 1504 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1505 1506 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1507 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1508 defined (STM32F750xx) 1509 /** 1510 * @brief Enable ETHERNET clock. 1511 */ 1512 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 1513 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 1514 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 1515 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 1516 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 1517 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 1518 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 1519 1520 /** 1521 * @brief Disable ETHERNET clock. 1522 */ 1523 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 1524 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 1525 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 1526 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 1527 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 1528 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 1529 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 1530 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1531 1532 /** @brief Get the enable or disable status of the AHB2 peripheral clock. 1533 * @note After reset, the peripheral clock (used for registers read/write access) 1534 * is disabled and the application software has to enable this clock before 1535 * using it. 1536 */ 1537 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 1538 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 1539 1540 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 1541 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 1542 1543 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1544 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 1545 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 1546 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 1547 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 1548 #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1549 1550 #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) 1551 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) 1552 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) 1553 #endif /* STM32F732xx || STM32F733xx || STM32F730xx */ 1554 1555 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1556 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1557 defined (STM32F750xx) 1558 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 1559 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 1560 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1561 1562 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1563 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) 1564 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) 1565 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1566 1567 /** @brief Get the enable or disable status of the AHB3 peripheral clock. 1568 * @note After reset, the peripheral clock (used for registers read/write access) 1569 * is disabled and the application software has to enable this clock before 1570 * using it. 1571 */ 1572 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 1573 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 1574 1575 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 1576 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 1577 1578 /** @brief Get the enable or disable status of the APB1 peripheral clock. 1579 * @note After reset, the peripheral clock (used for registers read/write access) 1580 * is disabled and the application software has to enable this clock before 1581 * using it. 1582 */ 1583 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 1584 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 1585 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 1586 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 1587 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1588 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1589 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1590 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1591 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1592 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 1593 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1594 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) 1595 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1596 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 1597 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1598 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 1599 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1600 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1601 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1602 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 1603 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 1604 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 1605 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 1606 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1607 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 1608 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 1609 1610 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 1611 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 1612 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 1613 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 1614 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1615 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1616 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1617 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1618 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1619 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 1620 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1621 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) 1622 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1623 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 1624 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1625 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 1626 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1627 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1628 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1629 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 1630 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 1631 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 1632 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 1633 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1634 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 1635 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 1636 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1637 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1638 defined (STM32F750xx) 1639 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) 1640 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 1641 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 1642 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) 1643 1644 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) 1645 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 1646 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 1647 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) 1648 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1649 1650 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ 1651 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ 1652 defined (STM32F779xx) || defined (STM32F730xx) 1653 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) 1654 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) 1655 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || 1656 STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 1657 1658 /** @brief Get the enable or disable status of the APB2 peripheral clock. 1659 * @note After reset, the peripheral clock (used for registers read/write access) 1660 * is disabled and the application software has to enable this clock before 1661 * using it. 1662 */ 1663 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 1664 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 1665 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 1666 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) 1667 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 1668 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 1669 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 1670 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) 1671 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 1672 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 1673 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 1674 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 1675 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 1676 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 1677 1678 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1679 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1680 defined (STM32F750xx) 1681 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 1682 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1683 1684 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 1685 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) 1686 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1687 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) 1688 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1689 #if defined (STM32F769xx) || defined (STM32F779xx) 1690 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) 1691 #endif /* STM32F769xx || STM32F779xx */ 1692 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 1693 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 1694 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) 1695 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 1696 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1697 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) 1698 #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) 1699 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1700 #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) 1701 #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) 1702 #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ 1703 1704 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 1705 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 1706 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 1707 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) 1708 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 1709 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 1710 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 1711 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) 1712 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 1713 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 1714 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 1715 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 1716 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 1717 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 1718 1719 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1720 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1721 defined (STM32F750xx) 1722 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) 1723 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1724 1725 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 1726 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 1727 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1728 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) 1729 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1730 #if defined (STM32F769xx) || defined (STM32F779xx) 1731 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) 1732 #endif /* STM32F769xx || STM32F779xx */ 1733 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 1734 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 1735 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) 1736 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 1737 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1738 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) 1739 #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) 1740 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1741 #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) 1742 #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) 1743 #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ 1744 1745 /** 1746 * @} 1747 */ 1748 1749 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset 1750 * @brief Forces or releases AHB/APB peripheral reset. 1751 * @{ 1752 */ 1753 1754 /** @brief Force or release AHB1 peripheral reset. 1755 */ 1756 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) 1757 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 1758 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) 1759 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) 1760 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) 1761 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 1762 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 1763 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 1764 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 1765 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) 1766 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 1767 1768 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) 1769 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 1770 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) 1771 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) 1772 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) 1773 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 1774 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 1775 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 1776 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 1777 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) 1778 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 1779 1780 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1781 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1782 defined (STM32F750xx) 1783 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) 1784 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 1785 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) 1786 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) 1787 1788 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) 1789 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 1790 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) 1791 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) 1792 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1793 1794 /** @brief Force or release AHB2 peripheral reset. 1795 */ 1796 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 1797 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 1798 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 1799 1800 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 1801 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 1802 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 1803 1804 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1805 #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) 1806 #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) 1807 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1808 1809 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1810 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 1811 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 1812 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 1813 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 1814 #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1815 1816 #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) 1817 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) 1818 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) 1819 #endif /* STM32F732xx || STM32F733xx || STM32F730xx */ 1820 1821 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1822 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1823 defined (STM32F750xx) 1824 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 1825 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 1826 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1827 1828 /** @brief Force or release AHB3 peripheral reset 1829 */ 1830 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 1831 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 1832 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 1833 1834 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 1835 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 1836 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 1837 1838 /** @brief Force or release APB1 peripheral reset. 1839 */ 1840 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 1841 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 1842 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 1843 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 1844 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1845 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1846 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1847 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1848 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1849 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 1850 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1851 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) 1852 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1853 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 1854 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1855 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 1856 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1857 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1858 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1859 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 1860 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 1861 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 1862 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 1863 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1864 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 1865 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 1866 1867 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 1868 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 1869 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 1870 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 1871 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1872 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1873 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1874 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1875 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1876 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 1877 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1878 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) 1879 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1880 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 1881 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1882 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 1883 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1884 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1885 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1886 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 1887 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 1888 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 1889 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 1890 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1891 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 1892 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 1893 1894 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1895 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1896 defined (STM32F750xx) 1897 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) 1898 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) 1899 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 1900 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 1901 1902 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) 1903 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) 1904 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 1905 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 1906 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1907 1908 /** @brief Force or release APB2 peripheral reset. 1909 */ 1910 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 1911 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 1912 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 1913 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) 1914 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) 1915 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) 1916 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 1917 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 1918 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 1919 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1920 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 1921 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 1922 1923 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1924 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1925 defined (STM32F750xx) 1926 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) 1927 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1928 1929 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 1930 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) 1931 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1932 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) 1933 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1934 #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) 1935 #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) 1936 #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ 1937 1938 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 1939 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 1940 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 1941 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) 1942 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) 1943 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) 1944 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 1945 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 1946 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 1947 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1948 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 1949 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 1950 1951 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 1952 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 1953 defined (STM32F750xx) 1954 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) 1955 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1956 1957 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 1958 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 1959 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 1960 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) 1961 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 1962 #if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) 1963 #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) 1964 #endif /* STM32F723xx || STM32F733xx || STM32F730xx */ 1965 1966 #if defined (STM32F769xx) || defined (STM32F779xx) 1967 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) 1968 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) 1969 #endif /* STM32F769xx || STM32F779xx */ 1970 1971 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 1972 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 1973 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) 1974 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) 1975 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 1976 1977 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 1978 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) 1979 #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) 1980 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) 1981 #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) 1982 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 1983 /** 1984 * @} 1985 */ 1986 1987 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable 1988 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. 1989 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1990 * power consumption. 1991 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1992 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1993 * @{ 1994 */ 1995 1996 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1997 */ 1998 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 1999 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) 2000 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 2001 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 2002 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 2003 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) 2004 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 2005 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 2006 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 2007 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) 2008 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) 2009 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) 2010 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 2011 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 2012 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 2013 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 2014 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) 2015 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 2016 2017 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 2018 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) 2019 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 2020 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 2021 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 2022 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) 2023 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) 2024 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 2025 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 2026 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) 2027 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) 2028 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) 2029 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 2030 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 2031 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 2032 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 2033 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) 2034 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 2035 2036 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2037 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2038 defined (STM32F750xx) 2039 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) 2040 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 2041 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 2042 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 2043 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 2044 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) 2045 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) 2046 2047 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) 2048 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 2049 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 2050 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 2051 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 2052 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) 2053 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) 2054 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2055 2056 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2057 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2058 * power consumption. 2059 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2060 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2061 */ 2062 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2063 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2064 defined (STM32F750xx) 2065 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 2066 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 2067 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2068 2069 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2070 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) 2071 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) 2072 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2073 2074 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 2075 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 2076 2077 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 2078 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 2079 2080 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 2081 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 2082 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 2083 2084 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 2085 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 2086 #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2087 2088 #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) 2089 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) 2090 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) 2091 #endif /* STM32F732xx || STM32F733xx || STM32F730xx */ 2092 2093 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2094 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2095 * power consumption. 2096 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2097 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2098 */ 2099 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 2100 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 2101 2102 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 2103 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 2104 2105 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2106 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2107 * power consumption. 2108 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2109 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2110 */ 2111 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 2112 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 2113 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 2114 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) 2115 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 2116 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 2117 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 2118 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 2119 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 2120 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 2121 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2122 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) 2123 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2124 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) 2125 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 2126 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) 2127 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 2128 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 2129 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 2130 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) 2131 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) 2132 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 2133 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 2134 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 2135 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 2136 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 2137 2138 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 2139 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 2140 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 2141 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) 2142 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 2143 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 2144 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 2145 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 2146 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 2147 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 2148 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2149 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) 2150 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2151 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) 2152 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 2153 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) 2154 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 2155 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 2156 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 2157 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) 2158 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) 2159 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 2160 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 2161 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 2162 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 2163 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 2164 2165 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ 2166 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ 2167 defined (STM32F779xx) || defined (STM32F730xx) 2168 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) 2169 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) 2170 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || 2171 STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 2172 2173 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2174 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2175 defined (STM32F750xx) 2176 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) 2177 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) 2178 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 2179 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) 2180 2181 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) 2182 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) 2183 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 2184 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) 2185 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2186 2187 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2188 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2189 * power consumption. 2190 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2191 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2192 */ 2193 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) 2194 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 2195 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) 2196 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) 2197 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) 2198 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 2199 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 2200 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) 2201 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) 2202 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 2203 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) 2204 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 2205 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) 2206 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 2207 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 2208 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) 2209 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 2210 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) 2211 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2212 2213 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) 2214 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 2215 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) 2216 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) 2217 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) 2218 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 2219 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 2220 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) 2221 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) 2222 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 2223 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) 2224 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 2225 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) 2226 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 2227 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 2228 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) 2229 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) 2230 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) 2231 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2232 #if defined (STM32F769xx) || defined (STM32F779xx) 2233 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) 2234 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) 2235 #endif /* STM32F769xx || STM32F779xx */ 2236 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2237 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) 2238 #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) 2239 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) 2240 #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) 2241 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2242 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 2243 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 2244 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) 2245 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) 2246 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 2247 2248 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2249 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2250 defined (STM32F750xx) 2251 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) 2252 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) 2253 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2254 /** 2255 * @} 2256 */ 2257 2258 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status 2259 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. 2260 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2261 * power consumption. 2262 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2263 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2264 * @{ 2265 */ 2266 2267 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. 2268 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2269 * power consumption. 2270 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2271 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2272 */ 2273 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) 2274 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) 2275 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) 2276 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) 2277 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) 2278 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) 2279 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) 2280 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) 2281 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) 2282 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) 2283 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) 2284 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) 2285 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) 2286 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) 2287 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) 2288 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) 2289 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) 2290 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) 2291 2292 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) 2293 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) 2294 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) 2295 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) 2296 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) 2297 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) 2298 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) 2299 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) 2300 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) 2301 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) 2302 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) 2303 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) 2304 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) 2305 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) 2306 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) 2307 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) 2308 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) 2309 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) 2310 2311 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2312 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2313 defined (STM32F750xx) 2314 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) 2315 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) 2316 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) 2317 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) 2318 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) 2319 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) 2320 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) 2321 2322 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) 2323 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) 2324 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) 2325 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) 2326 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) 2327 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) 2328 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) 2329 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2330 2331 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. 2332 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2333 * power consumption. 2334 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2335 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2336 */ 2337 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2338 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2339 defined (STM32F750xx) 2340 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) 2341 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) 2342 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2343 2344 #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2345 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) 2346 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) 2347 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2348 2349 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) 2350 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) 2351 2352 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) 2353 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) 2354 2355 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 2356 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) 2357 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) 2358 2359 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) 2360 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) 2361 #endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2362 2363 #if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) 2364 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) 2365 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) 2366 #endif /* STM32F732xx || STM32F733xx || STM32F730xx */ 2367 2368 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. 2369 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2370 * power consumption. 2371 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2372 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2373 */ 2374 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) 2375 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) 2376 2377 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) 2378 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) 2379 2380 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. 2381 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2382 * power consumption. 2383 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2384 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2385 */ 2386 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) 2387 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) 2388 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) 2389 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) 2390 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) 2391 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) 2392 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) 2393 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) 2394 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) 2395 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) 2396 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ 2397 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ 2398 defined (STM32F779xx) || defined (STM32F730xx) 2399 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) 2400 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || 2401 STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 2402 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2403 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) 2404 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2405 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) 2406 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) 2407 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) 2408 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) 2409 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) 2410 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) 2411 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) 2412 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) 2413 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) 2414 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) 2415 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) 2416 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) 2417 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) 2418 2419 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) 2420 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) 2421 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) 2422 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) 2423 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) 2424 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) 2425 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) 2426 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) 2427 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) 2428 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) 2429 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ 2430 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ 2431 defined (STM32F779xx) || defined (STM32F730xx) 2432 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) 2433 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || 2434 STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 2435 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2436 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) 2437 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2438 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) 2439 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) 2440 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) 2441 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) 2442 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) 2443 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) 2444 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) 2445 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) 2446 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) 2447 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) 2448 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) 2449 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) 2450 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) 2451 2452 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2453 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2454 defined (STM32F750xx) 2455 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) 2456 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) 2457 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) 2458 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) 2459 2460 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) 2461 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) 2462 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) 2463 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) 2464 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2465 2466 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. 2467 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2468 * power consumption. 2469 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2470 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2471 */ 2472 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) 2473 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) 2474 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) 2475 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) 2476 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) 2477 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) 2478 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) 2479 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) 2480 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) 2481 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) 2482 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) 2483 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) 2484 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) 2485 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) 2486 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) 2487 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) 2488 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 2489 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) 2490 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2491 #if defined (STM32F769xx) || defined (STM32F779xx) 2492 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) 2493 #endif /* STM32F769xx || STM32F779xx */ 2494 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 2495 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 2496 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) 2497 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 2498 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2499 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) 2500 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) 2501 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2502 2503 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) 2504 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) 2505 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) 2506 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) 2507 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) 2508 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) 2509 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) 2510 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) 2511 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) 2512 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) 2513 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) 2514 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) 2515 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) 2516 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) 2517 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) 2518 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) 2519 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 2520 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) 2521 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2522 #if defined (STM32F769xx) || defined (STM32F779xx) 2523 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) 2524 #endif /* STM32F769xx || STM32F779xx */ 2525 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 2526 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 2527 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) 2528 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 2529 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2530 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) 2531 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) 2532 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2533 2534 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2535 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2536 defined (STM32F750xx) 2537 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) 2538 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) 2539 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2540 /** 2541 * @} 2542 */ 2543 2544 /*------------------------------- PLL Configuration --------------------------*/ 2545 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 2546 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 2547 * @note This function must be used only when the main PLL is disabled. 2548 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 2549 * This parameter can be one of the following values: 2550 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 2551 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 2552 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 2553 * @param __PLLM__ specifies the division factor for PLL VCO input clock 2554 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 2555 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2556 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 2557 * of 2 MHz to limit PLL jitter. 2558 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 2559 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 2560 * @note You have to set the PLLN parameter correctly to ensure that the VCO 2561 * output frequency is between 100 and 432 MHz. 2562 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 2563 * This parameter must be a number in the range {2, 4, 6, or 8}. 2564 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on 2565 * the System clock frequency. 2566 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks 2567 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 2568 * @note If the USB OTG FS is used in your application, you have to set the 2569 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 2570 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work 2571 * correctly. 2572 * @param __PLLR__ specifies the division factor for DSI clock 2573 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 2574 */ 2575 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ 2576 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ 2577 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 2578 ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ 2579 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ 2580 ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) 2581 #else 2582 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 2583 * @note This function must be used only when the main PLL is disabled. 2584 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 2585 * This parameter can be one of the following values: 2586 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 2587 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 2588 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 2589 * @param __PLLM__ specifies the division factor for PLL VCO input clock 2590 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 2591 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2592 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 2593 * of 2 MHz to limit PLL jitter. 2594 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 2595 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 2596 * @note You have to set the PLLN parameter correctly to ensure that the VCO 2597 * output frequency is between 100 and 432 MHz. 2598 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 2599 * This parameter must be a number in the range {2, 4, 6, or 8}. 2600 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on 2601 * the System clock frequency. 2602 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks 2603 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 2604 * @note If the USB OTG FS is used in your application, you have to set the 2605 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 2606 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work 2607 * correctly. 2608 */ 2609 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ 2610 (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ 2611 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 2612 ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ 2613 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) 2614 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 2615 /*---------------------------------------------------------------------------------------------*/ 2616 2617 /** @brief Macro to configure the Timers clocks prescalers 2618 * @param __PRESC__ specifies the Timers clocks prescalers selection 2619 * This parameter can be one of the following values: 2620 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 2621 * equal to HPRE if PPREx is corresponding to division by 1 or 2, 2622 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 2623 * division by 4 or more. 2624 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 2625 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 2626 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 2627 * to division by 8 or more. 2628 */ 2629 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ 2630 RCC->DCKCFGR1 |= (__PRESC__); \ 2631 }while(0) 2632 2633 /** @brief Macros to Enable or Disable the PLLISAI. 2634 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 2635 */ 2636 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) 2637 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) 2638 2639 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) 2640 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 2641 * @note This function must be used only when the PLLSAI is disabled. 2642 * @note PLLSAI clock source is common with the main PLL (configured in 2643 * RCC_PLLConfig function ) 2644 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 2645 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 2646 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 2647 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 2648 * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks 2649 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. 2650 * @param __PLLSAIQ__ specifies the division factor for SAI clock 2651 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 2652 */ 2653 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ 2654 (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ 2655 ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ 2656 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)) 2657 2658 /** @brief Macro to configure the PLLI2S clock multiplication and division factors. 2659 * @note This macro must be used only when the PLLI2S is disabled. 2660 * @note PLLI2S clock source is common with the main PLL (configured in 2661 * HAL_RCC_ClockConfig() API) 2662 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. 2663 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 2664 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 2665 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 2666 * @param __PLLI2SQ__ specifies the division factor for SAI clock. 2667 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 2668 * @param __PLLI2SR__ specifies the division factor for I2S clock 2669 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 2670 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 2671 * on the I2S clock frequency. 2672 */ 2673 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ 2674 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 2675 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 2676 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) 2677 #else 2678 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 2679 * @note This function must be used only when the PLLSAI is disabled. 2680 * @note PLLSAI clock source is common with the main PLL (configured in 2681 * RCC_PLLConfig function ) 2682 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 2683 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 2684 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 2685 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 2686 * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks 2687 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. 2688 * @param __PLLSAIQ__ specifies the division factor for SAI clock 2689 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 2690 * @param __PLLSAIR__ specifies the division factor for LTDC clock 2691 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 2692 */ 2693 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 2694 (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ 2695 ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ 2696 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ 2697 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)) 2698 2699 /** @brief Macro to configure the PLLI2S clock multiplication and division factors. 2700 * @note This macro must be used only when the PLLI2S is disabled. 2701 * @note PLLI2S clock source is common with the main PLL (configured in 2702 * HAL_RCC_ClockConfig() API) 2703 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. 2704 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 2705 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 2706 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 2707 * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. 2708 * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. 2709 * @param __PLLI2SQ__ specifies the division factor for SAI clock. 2710 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 2711 * @param __PLLI2SR__ specifies the division factor for I2S clock 2712 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 2713 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 2714 * on the I2S clock frequency. 2715 */ 2716 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ 2717 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 2718 ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ 2719 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 2720 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) 2721 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ 2722 2723 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 2724 * @note This function must be called before enabling the PLLI2S. 2725 * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . 2726 * This parameter must be a number between 1 and 32. 2727 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 2728 */ 2729 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) 2730 2731 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. 2732 * @note This function must be called before enabling the PLLSAI. 2733 * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . 2734 * This parameter must be a number between Min_Data = 1 and Max_Data = 32. 2735 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ 2736 */ 2737 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) 2738 2739 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ 2740 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ 2741 defined (STM32F750xx) 2742 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. 2743 * @note This function must be called before enabling the PLLSAI. 2744 * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . 2745 * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. 2746 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 2747 */ 2748 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ 2749 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) 2750 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 2751 2752 /** @brief Macro to configure SAI1 clock source selection. 2753 * @note This function must be called before enabling PLLSAI, PLLI2S and 2754 * the SAI clock. 2755 * @param __SOURCE__ specifies the SAI1 clock source. 2756 * This parameter can be one of the following values: 2757 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 2758 * as SAI1 clock. 2759 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 2760 * as SAI1 clock. 2761 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin 2762 * used as SAI1 clock. 2763 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock 2764 * used as SAI1 clock. 2765 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices 2766 */ 2767 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ 2768 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) 2769 2770 /** @brief Macro to get the SAI1 clock source. 2771 * @retval The clock source can be one of the following values: 2772 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 2773 * as SAI1 clock. 2774 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 2775 * as SAI1 clock. 2776 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin 2777 * used as SAI1 clock. 2778 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock 2779 * used as SAI1 clock. 2780 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices 2781 */ 2782 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) 2783 2784 /** @brief Macro to configure SAI2 clock source selection. 2785 * @note This function must be called before enabling PLLSAI, PLLI2S and 2786 * the SAI clock. 2787 * @param __SOURCE__ specifies the SAI2 clock source. 2788 * This parameter can be one of the following values: 2789 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 2790 * as SAI2 clock. 2791 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 2792 * as SAI2 clock. 2793 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin 2794 * used as SAI2 clock. 2795 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock 2796 * used as SAI2 clock. 2797 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices 2798 */ 2799 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ 2800 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) 2801 2802 2803 /** @brief Macro to get the SAI2 clock source. 2804 * @retval The clock source can be one of the following values: 2805 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 2806 * as SAI2 clock. 2807 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 2808 * as SAI2 clock. 2809 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin 2810 * used as SAI2 clock. 2811 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock 2812 * used as SAI2 clock. 2813 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices 2814 */ 2815 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) 2816 2817 2818 /** @brief Enable PLLSAI_RDY interrupt. 2819 */ 2820 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) 2821 2822 /** @brief Disable PLLSAI_RDY interrupt. 2823 */ 2824 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) 2825 2826 /** @brief Clear the PLLSAI RDY interrupt pending bits. 2827 */ 2828 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) 2829 2830 /** @brief Check the PLLSAI RDY interrupt has occurred or not. 2831 * @retval The new state (TRUE or FALSE). 2832 */ 2833 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) 2834 2835 /** @brief Check PLLSAI RDY flag is set or not. 2836 * @retval The new state (TRUE or FALSE). 2837 */ 2838 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) 2839 2840 /** @brief Macro to Get I2S clock source selection. 2841 * @retval The clock source can be one of the following values: 2842 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 2843 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source 2844 */ 2845 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) 2846 2847 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 2848 * 2849 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 2850 * This parameter can be one of the following values: 2851 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock 2852 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 2853 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock 2854 */ 2855 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 2856 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 2857 2858 /** @brief Macro to get the I2C1 clock source. 2859 * @retval The clock source can be one of the following values: 2860 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock 2861 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock 2862 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock 2863 */ 2864 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) 2865 2866 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 2867 * 2868 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 2869 * This parameter can be one of the following values: 2870 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock 2871 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 2872 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock 2873 */ 2874 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 2875 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 2876 2877 /** @brief Macro to get the I2C2 clock source. 2878 * @retval The clock source can be one of the following values: 2879 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock 2880 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock 2881 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock 2882 */ 2883 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) 2884 2885 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 2886 * 2887 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 2888 * This parameter can be one of the following values: 2889 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock 2890 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 2891 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock 2892 */ 2893 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 2894 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 2895 2896 /** @brief macro to get the I2C3 clock source. 2897 * @retval The clock source can be one of the following values: 2898 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock 2899 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock 2900 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock 2901 */ 2902 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) 2903 2904 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 2905 * 2906 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 2907 * This parameter can be one of the following values: 2908 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock 2909 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 2910 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock 2911 */ 2912 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 2913 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 2914 2915 /** @brief macro to get the I2C4 clock source. 2916 * @retval The clock source can be one of the following values: 2917 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock 2918 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock 2919 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock 2920 */ 2921 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) 2922 2923 /** @brief Macro to configure the USART1 clock (USART1CLK). 2924 * 2925 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 2926 * This parameter can be one of the following values: 2927 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock 2928 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 2929 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock 2930 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 2931 */ 2932 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 2933 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 2934 2935 /** @brief macro to get the USART1 clock source. 2936 * @retval The clock source can be one of the following values: 2937 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock 2938 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock 2939 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock 2940 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock 2941 */ 2942 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) 2943 2944 /** @brief Macro to configure the USART2 clock (USART2CLK). 2945 * 2946 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 2947 * This parameter can be one of the following values: 2948 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock 2949 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 2950 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock 2951 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 2952 */ 2953 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 2954 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 2955 2956 /** @brief macro to get the USART2 clock source. 2957 * @retval The clock source can be one of the following values: 2958 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock 2959 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock 2960 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock 2961 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock 2962 */ 2963 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) 2964 2965 /** @brief Macro to configure the USART3 clock (USART3CLK). 2966 * 2967 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 2968 * This parameter can be one of the following values: 2969 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock 2970 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 2971 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock 2972 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 2973 */ 2974 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 2975 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 2976 2977 /** @brief macro to get the USART3 clock source. 2978 * @retval The clock source can be one of the following values: 2979 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock 2980 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock 2981 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock 2982 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock 2983 */ 2984 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) 2985 2986 /** @brief Macro to configure the UART4 clock (UART4CLK). 2987 * 2988 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 2989 * This parameter can be one of the following values: 2990 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock 2991 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 2992 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock 2993 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 2994 */ 2995 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 2996 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 2997 2998 /** @brief macro to get the UART4 clock source. 2999 * @retval The clock source can be one of the following values: 3000 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock 3001 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock 3002 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock 3003 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock 3004 */ 3005 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) 3006 3007 /** @brief Macro to configure the UART5 clock (UART5CLK). 3008 * 3009 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 3010 * This parameter can be one of the following values: 3011 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock 3012 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 3013 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock 3014 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 3015 */ 3016 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 3017 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 3018 3019 /** @brief macro to get the UART5 clock source. 3020 * @retval The clock source can be one of the following values: 3021 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock 3022 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock 3023 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock 3024 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock 3025 */ 3026 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) 3027 3028 /** @brief Macro to configure the USART6 clock (USART6CLK). 3029 * 3030 * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. 3031 * This parameter can be one of the following values: 3032 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock 3033 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 3034 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock 3035 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 3036 */ 3037 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ 3038 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) 3039 3040 /** @brief macro to get the USART6 clock source. 3041 * @retval The clock source can be one of the following values: 3042 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock 3043 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 3044 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock 3045 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock 3046 */ 3047 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) 3048 3049 /** @brief Macro to configure the UART7 clock (UART7CLK). 3050 * 3051 * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. 3052 * This parameter can be one of the following values: 3053 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock 3054 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 3055 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock 3056 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 3057 */ 3058 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ 3059 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) 3060 3061 /** @brief macro to get the UART7 clock source. 3062 * @retval The clock source can be one of the following values: 3063 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock 3064 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock 3065 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock 3066 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock 3067 */ 3068 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) 3069 3070 /** @brief Macro to configure the UART8 clock (UART8CLK). 3071 * 3072 * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. 3073 * This parameter can be one of the following values: 3074 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock 3075 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 3076 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock 3077 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 3078 */ 3079 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ 3080 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) 3081 3082 /** @brief macro to get the UART8 clock source. 3083 * @retval The clock source can be one of the following values: 3084 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock 3085 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock 3086 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock 3087 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock 3088 */ 3089 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) 3090 3091 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 3092 * 3093 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 3094 * This parameter can be one of the following values: 3095 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 3096 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock 3097 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 3098 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 3099 */ 3100 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 3101 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 3102 3103 /** @brief macro to get the LPTIM1 clock source. 3104 * @retval The clock source can be one of the following values: 3105 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 3106 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock 3107 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 3108 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 3109 */ 3110 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) 3111 3112 /** @brief Macro to configure the CEC clock (CECCLK). 3113 * 3114 * @param __CEC_CLKSOURCE__ specifies the CEC clock source. 3115 * This parameter can be one of the following values: 3116 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 3117 * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock 3118 */ 3119 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ 3120 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) 3121 3122 /** @brief macro to get the CEC clock source. 3123 * @retval The clock source can be one of the following values: 3124 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 3125 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock 3126 */ 3127 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) 3128 3129 /** @brief Macro to configure the CLK48 source (CLK48CLK). 3130 * 3131 * @param __CLK48_SOURCE__ specifies the CLK48 clock source. 3132 * This parameter can be one of the following values: 3133 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source 3134 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source 3135 */ 3136 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ 3137 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) 3138 3139 /** @brief macro to get the CLK48 source. 3140 * @retval The clock source can be one of the following values: 3141 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source 3142 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source 3143 */ 3144 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) 3145 3146 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). 3147 * 3148 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. 3149 * This parameter can be one of the following values: 3150 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock 3151 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock 3152 */ 3153 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 3154 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) 3155 3156 /** @brief macro to get the SDMMC1 clock source. 3157 * @retval The clock source can be one of the following values: 3158 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock 3159 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock 3160 */ 3161 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) 3162 3163 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 3164 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 3165 /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). 3166 * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. 3167 * This parameter can be one of the following values: 3168 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock 3169 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock 3170 */ 3171 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ 3172 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) 3173 3174 /** @brief macro to get the SDMMC2 clock source. 3175 * @retval The clock source can be one of the following values: 3176 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock 3177 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock 3178 */ 3179 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) 3180 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 3181 3182 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 3183 /** @brief Macro to configure the DFSDM1 clock 3184 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 3185 * This parameter can be one of the following values: 3186 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock 3187 * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock 3188 */ 3189 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 3190 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) 3191 3192 /** @brief Macro to get the DFSDM1 clock source. 3193 * @retval The clock source can be one of the following values: 3194 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock 3195 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock 3196 */ 3197 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) 3198 3199 /** @brief Macro to configure the DFSDM1 Audio clock 3200 * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. 3201 * This parameter can be one of the following values: 3202 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock 3203 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock 3204 */ 3205 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ 3206 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) 3207 3208 /** @brief Macro to get the DFSDM1 Audio clock source. 3209 * @retval The clock source can be one of the following values: 3210 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock 3211 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock 3212 */ 3213 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) 3214 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 3215 3216 #if defined (STM32F769xx) || defined (STM32F779xx) 3217 /** @brief Macro to configure the DSI clock. 3218 * @param __DSI_CLKSOURCE__ specifies the DSI clock source. 3219 * This parameter can be one of the following values: 3220 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 3221 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 3222 */ 3223 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) 3224 3225 /** @brief Macro to Get the DSI clock. 3226 * @retval The clock source can be one of the following values: 3227 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 3228 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 3229 */ 3230 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) 3231 #endif /* STM32F769xx || STM32F779xx */ 3232 /** 3233 * @} 3234 */ 3235 3236 /* Exported functions --------------------------------------------------------*/ 3237 /** @addtogroup RCCEx_Exported_Functions_Group1 3238 * @{ 3239 */ 3240 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3241 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 3242 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 3243 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 3244 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 3245 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); 3246 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); 3247 /** 3248 * @} 3249 */ 3250 /* Private macros ------------------------------------------------------------*/ 3251 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros 3252 * @{ 3253 */ 3254 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 3255 * @{ 3256 */ 3257 #if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) 3258 #define IS_RCC_PERIPHCLOCK(SELECTION) \ 3259 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 3260 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 3261 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ 3262 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 3263 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 3264 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 3265 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 3266 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 3267 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 3268 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ 3269 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ 3270 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 3271 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 3272 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 3273 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 3274 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 3275 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 3276 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 3277 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ 3278 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 3279 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 3280 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ 3281 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 3282 #elif defined(STM32F745xx) 3283 #define IS_RCC_PERIPHCLOCK(SELECTION) \ 3284 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 3285 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ 3286 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 3287 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 3288 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 3289 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 3290 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 3291 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 3292 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ 3293 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ 3294 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 3295 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 3296 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 3297 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 3298 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 3299 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 3300 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 3301 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ 3302 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 3303 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 3304 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ 3305 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 3306 #elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 3307 #define IS_RCC_PERIPHCLOCK(SELECTION) \ 3308 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 3309 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 3310 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ 3311 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 3312 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 3313 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 3314 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 3315 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 3316 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 3317 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ 3318 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ 3319 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 3320 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 3321 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 3322 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 3323 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 3324 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 3325 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 3326 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ 3327 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 3328 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 3329 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ 3330 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 3331 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ 3332 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ 3333 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 3334 #elif defined (STM32F765xx) 3335 #define IS_RCC_PERIPHCLOCK(SELECTION) \ 3336 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 3337 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ 3338 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 3339 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 3340 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 3341 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 3342 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 3343 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 3344 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ 3345 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ 3346 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 3347 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 3348 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 3349 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 3350 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 3351 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 3352 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 3353 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ 3354 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 3355 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 3356 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ 3357 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 3358 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ 3359 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ 3360 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 3361 #elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) 3362 #define IS_RCC_PERIPHCLOCK(SELECTION) \ 3363 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 3364 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ 3365 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 3366 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 3367 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 3368 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 3369 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 3370 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 3371 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ 3372 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ 3373 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 3374 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 3375 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 3376 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 3377 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 3378 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 3379 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ 3380 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 3381 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ 3382 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 3383 #endif /* STM32F746xx || STM32F756xx || STM32F750xx */ 3384 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 3385 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ 3386 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) 3387 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ 3388 ((VALUE) == RCC_PLLI2SP_DIV4) ||\ 3389 ((VALUE) == RCC_PLLI2SP_DIV6) ||\ 3390 ((VALUE) == RCC_PLLI2SP_DIV8)) 3391 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ 3392 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 3393 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 3394 3395 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 3396 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 3397 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 3398 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 3399 ((VALUE) == RCC_PLLSAIP_DIV8)) 3400 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 3401 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 3402 3403 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 3404 3405 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 3406 3407 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ 3408 ((VALUE) == RCC_PLLSAIDIVR_4) ||\ 3409 ((VALUE) == RCC_PLLSAIDIVR_8) ||\ 3410 ((VALUE) == RCC_PLLSAIDIVR_16)) 3411 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ 3412 ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) 3413 3414 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ 3415 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) 3416 3417 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ 3418 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 3419 #define IS_RCC_USART1CLKSOURCE(SOURCE) \ 3420 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ 3421 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ 3422 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ 3423 ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) 3424 3425 #define IS_RCC_USART2CLKSOURCE(SOURCE) \ 3426 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ 3427 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ 3428 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ 3429 ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) 3430 #define IS_RCC_USART3CLKSOURCE(SOURCE) \ 3431 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ 3432 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ 3433 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ 3434 ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) 3435 3436 #define IS_RCC_UART4CLKSOURCE(SOURCE) \ 3437 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ 3438 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ 3439 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ 3440 ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) 3441 3442 #define IS_RCC_UART5CLKSOURCE(SOURCE) \ 3443 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ 3444 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ 3445 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ 3446 ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) 3447 3448 #define IS_RCC_USART6CLKSOURCE(SOURCE) \ 3449 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ 3450 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ 3451 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ 3452 ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) 3453 3454 #define IS_RCC_UART7CLKSOURCE(SOURCE) \ 3455 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ 3456 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ 3457 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ 3458 ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) 3459 3460 #define IS_RCC_UART8CLKSOURCE(SOURCE) \ 3461 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ 3462 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ 3463 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ 3464 ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) 3465 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \ 3466 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ 3467 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 3468 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) 3469 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \ 3470 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ 3471 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 3472 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) 3473 3474 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \ 3475 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ 3476 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 3477 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) 3478 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \ 3479 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ 3480 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 3481 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) 3482 #define IS_RCC_LPTIM1CLK(SOURCE) \ 3483 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 3484 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ 3485 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ 3486 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 3487 #define IS_RCC_CLK48SOURCE(SOURCE) \ 3488 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ 3489 ((SOURCE) == RCC_CLK48SOURCE_PLL)) 3490 #define IS_RCC_TIMPRES(VALUE) \ 3491 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ 3492 ((VALUE) == RCC_TIMPRES_ACTIVATED)) 3493 3494 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ 3495 defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) 3496 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ 3497 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ 3498 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) 3499 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ 3500 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ 3501 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) 3502 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ 3503 3504 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 3505 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 3506 3507 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ 3508 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ 3509 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ 3510 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) 3511 3512 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ 3513 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ 3514 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ 3515 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) 3516 3517 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 3518 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 3519 3520 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ 3521 ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) 3522 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 3523 3524 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ 3525 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) 3526 #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ 3527 ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) 3528 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ 3529 3530 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) 3531 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ 3532 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) 3533 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ 3534 3535 /** 3536 * @} 3537 */ 3538 3539 /** 3540 * @} 3541 */ 3542 3543 /** 3544 * @} 3545 */ 3546 3547 /** 3548 * @} 3549 */ 3550 #ifdef __cplusplus 3551 } 3552 #endif 3553 3554 #endif /* __STM32F7xx_HAL_RCC_EX_H */ 3555 3556
