1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F4xx_HAL_RCC_EX_H 20 #define __STM32F4xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f4xx_hal_def.h" 28 29 /** @addtogroup STM32F4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 55 56 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 57 This parameter must be a number between Min_Data = 50 and Max_Data = 432 58 except for STM32F411xE devices where the Min_Data = 192 */ 59 60 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). 61 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 62 63 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. 64 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ 65 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 66 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 67 defined(STM32F413xx) || defined(STM32F423xx) 68 uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 69 This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx 70 and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 71 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ 72 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 73 } RCC_PLLInitTypeDef; 74 75 #if defined(STM32F446xx) 76 /** 77 * @brief PLLI2S Clock structure definition 78 */ 79 typedef struct 80 { 81 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 82 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 83 84 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 85 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 86 87 uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. 88 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ 89 90 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 91 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 92 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 93 94 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 95 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 96 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 97 } RCC_PLLI2SInitTypeDef; 98 99 /** 100 * @brief PLLSAI Clock structure definition 101 */ 102 typedef struct 103 { 104 uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. 105 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 106 107 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 108 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 109 110 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. 111 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 112 113 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. 114 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 116 } RCC_PLLSAIInitTypeDef; 117 118 /** 119 * @brief RCC extended clocks structure definition 120 */ 121 typedef struct 122 { 123 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 124 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 125 126 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 127 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 128 129 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 130 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 131 132 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 133 This parameter must be a number between Min_Data = 1 and Max_Data = 32 134 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 135 136 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 137 This parameter must be a number between Min_Data = 1 and Max_Data = 32 138 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 139 140 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. 141 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 142 143 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. 144 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 145 146 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 147 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 148 149 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 150 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 151 152 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 153 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 154 155 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 156 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 157 158 uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. 159 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 160 161 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 162 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 163 164 uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. 165 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 166 167 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 168 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 169 170 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 171 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 172 } RCC_PeriphCLKInitTypeDef; 173 #endif /* STM32F446xx */ 174 175 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 176 /** 177 * @brief RCC extended clocks structure definition 178 */ 179 typedef struct 180 { 181 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 182 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 183 184 uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. 185 This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ 186 187 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 188 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 189 190 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 191 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 192 193 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 194 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 195 196 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 197 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 198 } RCC_PeriphCLKInitTypeDef; 199 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 200 201 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 202 /** 203 * @brief PLLI2S Clock structure definition 204 */ 205 typedef struct 206 { 207 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 208 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 209 210 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 211 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 212 213 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 214 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 215 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 216 217 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 218 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 219 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 220 } RCC_PLLI2SInitTypeDef; 221 222 /** 223 * @brief RCC extended clocks structure definition 224 */ 225 typedef struct 226 { 227 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 228 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 229 230 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 231 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 232 233 #if defined(STM32F413xx) || defined(STM32F423xx) 234 uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. 235 This parameter must be a number between Min_Data = 1 and Max_Data = 32 236 This parameter will be used only when PLL is selected as Clock Source SAI */ 237 238 uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. 239 This parameter must be a number between Min_Data = 1 and Max_Data = 32 240 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 241 #endif /* STM32F413xx || STM32F423xx */ 242 243 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 244 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 245 246 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 247 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 248 249 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 250 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 251 252 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 253 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 254 255 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 256 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 257 258 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 259 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 260 261 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. 262 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ 263 264 uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. 265 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 266 267 #if defined(STM32F413xx) || defined(STM32F423xx) 268 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. 269 This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ 270 271 uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. 272 This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ 273 274 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 275 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 276 277 uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection 278 This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ 279 280 uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection 281 This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ 282 #endif /* STM32F413xx || STM32F423xx */ 283 284 uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. 285 This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ 286 287 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 288 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 289 } RCC_PeriphCLKInitTypeDef; 290 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 291 292 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 293 294 /** 295 * @brief PLLI2S Clock structure definition 296 */ 297 typedef struct 298 { 299 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 300 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 301 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 302 303 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 304 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 305 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 306 307 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. 308 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 309 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 310 } RCC_PLLI2SInitTypeDef; 311 312 /** 313 * @brief PLLSAI Clock structure definition 314 */ 315 typedef struct 316 { 317 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 318 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 319 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 320 #if defined(STM32F469xx) || defined(STM32F479xx) 321 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. 322 This parameter is only available in STM32F469xx/STM32F479xx devices. 323 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 324 #endif /* STM32F469xx || STM32F479xx */ 325 326 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. 327 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 328 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 329 330 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock 331 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 332 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ 333 334 } RCC_PLLSAIInitTypeDef; 335 336 /** 337 * @brief RCC extended clocks structure definition 338 */ 339 typedef struct 340 { 341 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 342 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 343 344 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 345 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 346 347 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 348 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 349 350 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 351 This parameter must be a number between Min_Data = 1 and Max_Data = 32 352 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 353 354 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 355 This parameter must be a number between Min_Data = 1 and Max_Data = 32 356 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 357 358 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. 359 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ 360 361 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 362 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 363 364 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 365 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 366 #if defined(STM32F469xx) || defined(STM32F479xx) 367 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 368 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 369 370 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 371 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 372 #endif /* STM32F469xx || STM32F479xx */ 373 } RCC_PeriphCLKInitTypeDef; 374 375 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 376 377 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 378 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 379 /** 380 * @brief PLLI2S Clock structure definition 381 */ 382 typedef struct 383 { 384 #if defined(STM32F411xE) 385 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. 386 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ 387 #endif /* STM32F411xE */ 388 389 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 390 This parameter must be a number between Min_Data = 50 and Max_Data = 432 391 Except for STM32F411xE devices where the Min_Data = 192. 392 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 393 394 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 395 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 396 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 397 398 } RCC_PLLI2SInitTypeDef; 399 400 /** 401 * @brief RCC extended clocks structure definition 402 */ 403 typedef struct 404 { 405 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 406 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 407 408 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 409 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 410 411 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 412 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 413 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 414 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 415 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 416 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 417 } RCC_PeriphCLKInitTypeDef; 418 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 419 /** 420 * @} 421 */ 422 423 /* Exported constants --------------------------------------------------------*/ 424 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 425 * @{ 426 */ 427 428 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection 429 * @{ 430 */ 431 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ 432 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 433 defined(STM32F413xx) || defined(STM32F423xx) 434 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 435 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 436 #define RCC_PERIPHCLK_TIM 0x00000004U 437 #define RCC_PERIPHCLK_RTC 0x00000008U 438 #define RCC_PERIPHCLK_FMPI2C1 0x00000010U 439 #define RCC_PERIPHCLK_CLK48 0x00000020U 440 #define RCC_PERIPHCLK_SDIO 0x00000040U 441 #define RCC_PERIPHCLK_PLLI2S 0x00000080U 442 #define RCC_PERIPHCLK_DFSDM1 0x00000100U 443 #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U 444 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ 445 #if defined(STM32F413xx) || defined(STM32F423xx) 446 #define RCC_PERIPHCLK_DFSDM2 0x00000400U 447 #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U 448 #define RCC_PERIPHCLK_LPTIM1 0x00001000U 449 #define RCC_PERIPHCLK_SAIA 0x00002000U 450 #define RCC_PERIPHCLK_SAIB 0x00004000U 451 #endif /* STM32F413xx || STM32F423xx */ 452 /*----------------------------------------------------------------------------*/ 453 454 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/ 455 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 456 #define RCC_PERIPHCLK_I2S 0x00000001U 457 #define RCC_PERIPHCLK_TIM 0x00000002U 458 #define RCC_PERIPHCLK_RTC 0x00000004U 459 #define RCC_PERIPHCLK_FMPI2C1 0x00000008U 460 #define RCC_PERIPHCLK_LPTIM1 0x00000010U 461 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 462 /*----------------------------------------------------------------------------*/ 463 464 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/ 465 #if defined(STM32F446xx) 466 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 467 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 468 #define RCC_PERIPHCLK_SAI1 0x00000004U 469 #define RCC_PERIPHCLK_SAI2 0x00000008U 470 #define RCC_PERIPHCLK_TIM 0x00000010U 471 #define RCC_PERIPHCLK_RTC 0x00000020U 472 #define RCC_PERIPHCLK_CEC 0x00000040U 473 #define RCC_PERIPHCLK_FMPI2C1 0x00000080U 474 #define RCC_PERIPHCLK_CLK48 0x00000100U 475 #define RCC_PERIPHCLK_SDIO 0x00000200U 476 #define RCC_PERIPHCLK_SPDIFRX 0x00000400U 477 #define RCC_PERIPHCLK_PLLI2S 0x00000800U 478 #endif /* STM32F446xx */ 479 /*-----------------------------------------------------------------------------*/ 480 481 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ 482 #if defined(STM32F469xx) || defined(STM32F479xx) 483 #define RCC_PERIPHCLK_I2S 0x00000001U 484 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 485 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 486 #define RCC_PERIPHCLK_LTDC 0x00000008U 487 #define RCC_PERIPHCLK_TIM 0x00000010U 488 #define RCC_PERIPHCLK_RTC 0x00000020U 489 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 490 #define RCC_PERIPHCLK_CLK48 0x00000080U 491 #define RCC_PERIPHCLK_SDIO 0x00000100U 492 #endif /* STM32F469xx || STM32F479xx */ 493 /*----------------------------------------------------------------------------*/ 494 495 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ 496 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 497 #define RCC_PERIPHCLK_I2S 0x00000001U 498 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 499 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 500 #define RCC_PERIPHCLK_LTDC 0x00000008U 501 #define RCC_PERIPHCLK_TIM 0x00000010U 502 #define RCC_PERIPHCLK_RTC 0x00000020U 503 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 504 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 505 /*----------------------------------------------------------------------------*/ 506 507 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ 508 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ 509 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 510 #define RCC_PERIPHCLK_I2S 0x00000001U 511 #define RCC_PERIPHCLK_RTC 0x00000002U 512 #define RCC_PERIPHCLK_PLLI2S 0x00000004U 513 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 514 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 515 #define RCC_PERIPHCLK_TIM 0x00000008U 516 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 517 /*----------------------------------------------------------------------------*/ 518 /** 519 * @} 520 */ 521 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 522 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 523 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ 524 defined(STM32F479xx) 525 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 526 * @{ 527 */ 528 #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U 529 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC 530 /** 531 * @} 532 */ 533 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 534 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 535 536 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR 537 * @{ 538 */ 539 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 540 defined(STM32F469xx) || defined(STM32F479xx) 541 #define RCC_PLLSAIDIVR_2 0x00000000U 542 #define RCC_PLLSAIDIVR_4 0x00010000U 543 #define RCC_PLLSAIDIVR_8 0x00020000U 544 #define RCC_PLLSAIDIVR_16 0x00030000U 545 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 546 /** 547 * @} 548 */ 549 550 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider 551 * @{ 552 */ 553 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 554 defined(STM32F412Rx) || defined(STM32F412Cx) 555 #define RCC_PLLI2SP_DIV2 0x00000002U 556 #define RCC_PLLI2SP_DIV4 0x00000004U 557 #define RCC_PLLI2SP_DIV6 0x00000006U 558 #define RCC_PLLI2SP_DIV8 0x00000008U 559 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 560 /** 561 * @} 562 */ 563 564 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider 565 * @{ 566 */ 567 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 568 #define RCC_PLLSAIP_DIV2 0x00000002U 569 #define RCC_PLLSAIP_DIV4 0x00000004U 570 #define RCC_PLLSAIP_DIV6 0x00000006U 571 #define RCC_PLLSAIP_DIV8 0x00000008U 572 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ 573 /** 574 * @} 575 */ 576 577 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 578 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source 579 * @{ 580 */ 581 #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U 582 #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U 583 #define RCC_SAIACLKSOURCE_EXT 0x00200000U 584 /** 585 * @} 586 */ 587 588 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source 589 * @{ 590 */ 591 #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U 592 #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U 593 #define RCC_SAIBCLKSOURCE_EXT 0x00800000U 594 /** 595 * @} 596 */ 597 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 598 599 #if defined(STM32F469xx) || defined(STM32F479xx) 600 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 601 * @{ 602 */ 603 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 604 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) 605 /** 606 * @} 607 */ 608 609 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 610 * @{ 611 */ 612 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 613 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) 614 /** 615 * @} 616 */ 617 618 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source 619 * @{ 620 */ 621 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 622 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) 623 /** 624 * @} 625 */ 626 #endif /* STM32F469xx || STM32F479xx */ 627 628 #if defined(STM32F446xx) 629 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 630 * @{ 631 */ 632 #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U 633 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 634 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 635 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) 636 /** 637 * @} 638 */ 639 640 /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source 641 * @{ 642 */ 643 #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U 644 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) 645 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) 646 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) 647 /** 648 * @} 649 */ 650 651 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 652 * @{ 653 */ 654 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 655 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 656 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 657 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 658 /** 659 * @} 660 */ 661 662 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 663 * @{ 664 */ 665 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 666 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 667 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 668 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 669 /** 670 * @} 671 */ 672 673 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 674 * @{ 675 */ 676 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 677 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 678 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 679 /** 680 * @} 681 */ 682 683 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source 684 * @{ 685 */ 686 #define RCC_CECCLKSOURCE_HSI 0x00000000U 687 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) 688 /** 689 * @} 690 */ 691 692 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 693 * @{ 694 */ 695 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 696 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 697 /** 698 * @} 699 */ 700 701 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 702 * @{ 703 */ 704 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 705 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 706 /** 707 * @} 708 */ 709 710 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source 711 * @{ 712 */ 713 #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U 714 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) 715 /** 716 * @} 717 */ 718 719 #endif /* STM32F446xx */ 720 721 #if defined(STM32F413xx) || defined(STM32F423xx) 722 /** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source 723 * @{ 724 */ 725 #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U 726 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) 727 #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) 728 #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) 729 /** 730 * @} 731 */ 732 733 /** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source 734 * @{ 735 */ 736 #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U 737 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) 738 #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) 739 #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) 740 /** 741 * @} 742 */ 743 744 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 745 * @{ 746 */ 747 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 748 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 749 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 750 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 751 /** 752 * @} 753 */ 754 755 756 /** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source 757 * @{ 758 */ 759 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U 760 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) 761 /** 762 * @} 763 */ 764 765 /** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source 766 * @{ 767 */ 768 #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U 769 #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 770 /** 771 * @} 772 */ 773 774 #endif /* STM32F413xx || STM32F423xx */ 775 776 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 777 /** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source 778 * @{ 779 */ 780 #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U 781 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) 782 /** 783 * @} 784 */ 785 786 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source 787 * @{ 788 */ 789 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U 790 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) 791 /** 792 * @} 793 */ 794 795 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source 796 * @{ 797 */ 798 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 799 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 800 /** 801 * @} 802 */ 803 804 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 805 * @{ 806 */ 807 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 808 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 809 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 810 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 811 /** 812 * @} 813 */ 814 815 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 816 * @{ 817 */ 818 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 819 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 820 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 821 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 822 /** 823 * @} 824 */ 825 826 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 827 * @{ 828 */ 829 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 830 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 831 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 832 /** 833 * @} 834 */ 835 836 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 837 * @{ 838 */ 839 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 840 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 841 /** 842 * @} 843 */ 844 845 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 846 * @{ 847 */ 848 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 849 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 850 /** 851 * @} 852 */ 853 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 854 855 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 856 857 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source 858 * @{ 859 */ 860 #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U 861 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 862 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 863 /** 864 * @} 865 */ 866 867 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 868 * @{ 869 */ 870 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 871 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 872 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 873 /** 874 * @} 875 */ 876 877 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 878 * @{ 879 */ 880 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 881 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 882 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 883 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 884 /** 885 * @} 886 */ 887 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 888 889 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 890 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 891 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 892 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 893 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 894 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection 895 * @{ 896 */ 897 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 898 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 899 /** 900 * @} 901 */ 902 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ 903 STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 904 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 905 906 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 907 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 908 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 909 defined(STM32F423xx) 910 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection 911 * @{ 912 */ 913 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 914 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 915 /** 916 * @} 917 */ 918 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ 919 STM32F412Rx || STM32F412Cx */ 920 921 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 922 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 923 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 924 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 925 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 926 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 927 * @{ 928 */ 929 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 930 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 931 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 932 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 933 /** 934 * @} 935 */ 936 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 937 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 938 STM32F412Rx || STM32F413xx | STM32F423xx */ 939 940 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 941 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 942 * @{ 943 */ 944 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 945 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 946 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 947 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 948 /** 949 * @} 950 */ 951 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 952 953 /** 954 * @} 955 */ 956 957 /* Exported macro ------------------------------------------------------------*/ 958 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 959 * @{ 960 */ 961 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ 962 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 963 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 964 * @brief Enables or disables the AHB1 peripheral clock. 965 * @note After reset, the peripheral clock (used for registers read/write access) 966 * is disabled and the application software has to enable this clock before 967 * using it. 968 * @{ 969 */ 970 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 971 __IO uint32_t tmpreg = 0x00U; \ 972 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 973 /* Delay after an RCC peripheral clock enabling */ \ 974 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 975 UNUSED(tmpreg); \ 976 } while(0U) 977 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 978 __IO uint32_t tmpreg = 0x00U; \ 979 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 980 /* Delay after an RCC peripheral clock enabling */ \ 981 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 982 UNUSED(tmpreg); \ 983 } while(0U) 984 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 985 __IO uint32_t tmpreg = 0x00U; \ 986 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 987 /* Delay after an RCC peripheral clock enabling */ \ 988 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 989 UNUSED(tmpreg); \ 990 } while(0U) 991 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 992 __IO uint32_t tmpreg = 0x00U; \ 993 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 994 /* Delay after an RCC peripheral clock enabling */ \ 995 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 996 UNUSED(tmpreg); \ 997 } while(0U) 998 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 999 __IO uint32_t tmpreg = 0x00U; \ 1000 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 1001 /* Delay after an RCC peripheral clock enabling */ \ 1002 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 1003 UNUSED(tmpreg); \ 1004 } while(0U) 1005 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 1006 __IO uint32_t tmpreg = 0x00U; \ 1007 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 1008 /* Delay after an RCC peripheral clock enabling */ \ 1009 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 1010 UNUSED(tmpreg); \ 1011 } while(0U) 1012 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1013 __IO uint32_t tmpreg = 0x00U; \ 1014 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 1015 /* Delay after an RCC peripheral clock enabling */ \ 1016 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 1017 UNUSED(tmpreg); \ 1018 } while(0U) 1019 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1020 __IO uint32_t tmpreg = 0x00U; \ 1021 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 1022 /* Delay after an RCC peripheral clock enabling */ \ 1023 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 1024 UNUSED(tmpreg); \ 1025 } while(0U) 1026 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 1027 __IO uint32_t tmpreg = 0x00U; \ 1028 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 1029 /* Delay after an RCC peripheral clock enabling */ \ 1030 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 1031 UNUSED(tmpreg); \ 1032 } while(0U) 1033 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 1034 __IO uint32_t tmpreg = 0x00U; \ 1035 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 1036 /* Delay after an RCC peripheral clock enabling */ \ 1037 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 1038 UNUSED(tmpreg); \ 1039 } while(0U) 1040 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 1041 __IO uint32_t tmpreg = 0x00U; \ 1042 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 1043 /* Delay after an RCC peripheral clock enabling */ \ 1044 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 1045 UNUSED(tmpreg); \ 1046 } while(0U) 1047 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 1048 __IO uint32_t tmpreg = 0x00U; \ 1049 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 1050 /* Delay after an RCC peripheral clock enabling */ \ 1051 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 1052 UNUSED(tmpreg); \ 1053 } while(0U) 1054 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 1055 __IO uint32_t tmpreg = 0x00U; \ 1056 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 1057 /* Delay after an RCC peripheral clock enabling */ \ 1058 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 1059 UNUSED(tmpreg); \ 1060 } while(0U) 1061 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 1062 __IO uint32_t tmpreg = 0x00U; \ 1063 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 1064 /* Delay after an RCC peripheral clock enabling */ \ 1065 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 1066 UNUSED(tmpreg); \ 1067 } while(0U) 1068 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 1069 __IO uint32_t tmpreg = 0x00U; \ 1070 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 1071 /* Delay after an RCC peripheral clock enabling */ \ 1072 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 1073 UNUSED(tmpreg); \ 1074 } while(0U) 1075 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 1076 __IO uint32_t tmpreg = 0x00U; \ 1077 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 1078 /* Delay after an RCC peripheral clock enabling */ \ 1079 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 1080 UNUSED(tmpreg); \ 1081 } while(0U) 1082 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 1083 __IO uint32_t tmpreg = 0x00U; \ 1084 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 1085 /* Delay after an RCC peripheral clock enabling */ \ 1086 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 1087 UNUSED(tmpreg); \ 1088 } while(0U) 1089 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 1090 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 1091 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 1092 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 1093 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 1094 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) 1095 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) 1096 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) 1097 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 1098 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 1099 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 1100 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 1101 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 1102 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 1103 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 1104 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 1105 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 1106 1107 /** 1108 * @brief Enable ETHERNET clock. 1109 */ 1110 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 1111 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 1112 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 1113 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 1114 } while(0U) 1115 /** 1116 * @brief Disable ETHERNET clock. 1117 */ 1118 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 1119 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 1120 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 1121 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 1122 } while(0U) 1123 /** 1124 * @} 1125 */ 1126 1127 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 1128 * @brief Get the enable or disable status of the AHB1 peripheral clock. 1129 * @note After reset, the peripheral clock (used for registers read/write access) 1130 * is disabled and the application software has to enable this clock before 1131 * using it. 1132 * @{ 1133 */ 1134 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 1135 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 1136 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 1137 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 1138 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 1139 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 1140 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) 1141 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 1142 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 1143 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 1144 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 1145 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 1146 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 1147 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 1148 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 1149 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 1150 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 1151 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 1152 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 1153 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 1154 1155 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 1156 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 1157 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 1158 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 1159 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 1160 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 1161 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) 1162 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 1163 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 1164 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 1165 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 1166 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 1167 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 1168 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 1169 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 1170 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 1171 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 1172 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 1173 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 1174 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 1175 /** 1176 * @} 1177 */ 1178 1179 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 1180 * @brief Enable or disable the AHB2 peripheral clock. 1181 * @note After reset, the peripheral clock (used for registers read/write access) 1182 * is disabled and the application software has to enable this clock before 1183 * using it. 1184 * @{ 1185 */ 1186 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 1187 __IO uint32_t tmpreg = 0x00U; \ 1188 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1189 /* Delay after an RCC peripheral clock enabling */ \ 1190 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 1191 UNUSED(tmpreg); \ 1192 } while(0U) 1193 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 1194 1195 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1196 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 1197 __IO uint32_t tmpreg = 0x00U; \ 1198 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1199 /* Delay after an RCC peripheral clock enabling */ \ 1200 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 1201 UNUSED(tmpreg); \ 1202 } while(0U) 1203 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1204 __IO uint32_t tmpreg = 0x00U; \ 1205 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1206 /* Delay after an RCC peripheral clock enabling */ \ 1207 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 1208 UNUSED(tmpreg); \ 1209 } while(0U) 1210 1211 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 1212 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 1213 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1214 1215 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 1216 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 1217 }while(0U) 1218 1219 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 1220 1221 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1222 __IO uint32_t tmpreg = 0x00U; \ 1223 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1224 /* Delay after an RCC peripheral clock enabling */ \ 1225 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 1226 UNUSED(tmpreg); \ 1227 } while(0U) 1228 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 1229 /** 1230 * @} 1231 */ 1232 1233 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 1234 * @brief Get the enable or disable status of the AHB1 peripheral clock. 1235 * @note After reset, the peripheral clock (used for registers read/write access) 1236 * is disabled and the application software has to enable this clock before 1237 * using it. 1238 * @{ 1239 */ 1240 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 1241 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 1242 1243 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1244 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 1245 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 1246 1247 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 1248 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 1249 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1250 1251 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 1252 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 1253 1254 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 1255 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 1256 /** 1257 * @} 1258 */ 1259 1260 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 1261 * @brief Enables or disables the AHB3 peripheral clock. 1262 * @note After reset, the peripheral clock (used for registers read/write access) 1263 * is disabled and the application software has to enable this clock before 1264 * using it. 1265 * @{ 1266 */ 1267 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1268 __IO uint32_t tmpreg = 0x00U; \ 1269 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 1270 /* Delay after an RCC peripheral clock enabling */ \ 1271 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 1272 UNUSED(tmpreg); \ 1273 } while(0U) 1274 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 1275 #if defined(STM32F469xx) || defined(STM32F479xx) 1276 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 1277 __IO uint32_t tmpreg = 0x00U; \ 1278 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 1279 /* Delay after an RCC peripheral clock enabling */ \ 1280 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 1281 UNUSED(tmpreg); \ 1282 } while(0U) 1283 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 1284 #endif /* STM32F469xx || STM32F479xx */ 1285 /** 1286 * @} 1287 */ 1288 1289 1290 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 1291 * @brief Get the enable or disable status of the AHB3 peripheral clock. 1292 * @note After reset, the peripheral clock (used for registers read/write access) 1293 * is disabled and the application software has to enable this clock before 1294 * using it. 1295 * @{ 1296 */ 1297 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 1298 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 1299 #if defined(STM32F469xx) || defined(STM32F479xx) 1300 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 1301 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 1302 #endif /* STM32F469xx || STM32F479xx */ 1303 /** 1304 * @} 1305 */ 1306 1307 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1308 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 1309 * @note After reset, the peripheral clock (used for registers read/write access) 1310 * is disabled and the application software has to enable this clock before 1311 * using it. 1312 * @{ 1313 */ 1314 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1315 __IO uint32_t tmpreg = 0x00U; \ 1316 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1317 /* Delay after an RCC peripheral clock enabling */ \ 1318 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1319 UNUSED(tmpreg); \ 1320 } while(0U) 1321 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1322 __IO uint32_t tmpreg = 0x00U; \ 1323 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1324 /* Delay after an RCC peripheral clock enabling */ \ 1325 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1326 UNUSED(tmpreg); \ 1327 } while(0U) 1328 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1329 __IO uint32_t tmpreg = 0x00U; \ 1330 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1331 /* Delay after an RCC peripheral clock enabling */ \ 1332 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1333 UNUSED(tmpreg); \ 1334 } while(0U) 1335 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1336 __IO uint32_t tmpreg = 0x00U; \ 1337 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1338 /* Delay after an RCC peripheral clock enabling */ \ 1339 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1340 UNUSED(tmpreg); \ 1341 } while(0U) 1342 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1343 __IO uint32_t tmpreg = 0x00U; \ 1344 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1345 /* Delay after an RCC peripheral clock enabling */ \ 1346 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1347 UNUSED(tmpreg); \ 1348 } while(0U) 1349 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1350 __IO uint32_t tmpreg = 0x00U; \ 1351 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1352 /* Delay after an RCC peripheral clock enabling */ \ 1353 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1354 UNUSED(tmpreg); \ 1355 } while(0U) 1356 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1357 __IO uint32_t tmpreg = 0x00U; \ 1358 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1359 /* Delay after an RCC peripheral clock enabling */ \ 1360 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1361 UNUSED(tmpreg); \ 1362 } while(0U) 1363 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1364 __IO uint32_t tmpreg = 0x00U; \ 1365 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1366 /* Delay after an RCC peripheral clock enabling */ \ 1367 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 1368 UNUSED(tmpreg); \ 1369 } while(0U) 1370 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1371 __IO uint32_t tmpreg = 0x00U; \ 1372 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1373 /* Delay after an RCC peripheral clock enabling */ \ 1374 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1375 UNUSED(tmpreg); \ 1376 } while(0U) 1377 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1378 __IO uint32_t tmpreg = 0x00U; \ 1379 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1380 /* Delay after an RCC peripheral clock enabling */ \ 1381 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 1382 UNUSED(tmpreg); \ 1383 } while(0U) 1384 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1385 __IO uint32_t tmpreg = 0x00U; \ 1386 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1387 /* Delay after an RCC peripheral clock enabling */ \ 1388 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1389 UNUSED(tmpreg); \ 1390 } while(0U) 1391 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 1392 __IO uint32_t tmpreg = 0x00U; \ 1393 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1394 /* Delay after an RCC peripheral clock enabling */ \ 1395 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1396 UNUSED(tmpreg); \ 1397 } while(0U) 1398 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1399 __IO uint32_t tmpreg = 0x00U; \ 1400 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1401 /* Delay after an RCC peripheral clock enabling */ \ 1402 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 1403 UNUSED(tmpreg); \ 1404 } while(0U) 1405 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1406 __IO uint32_t tmpreg = 0x00U; \ 1407 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1408 /* Delay after an RCC peripheral clock enabling */ \ 1409 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 1410 UNUSED(tmpreg); \ 1411 } while(0U) 1412 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1413 __IO uint32_t tmpreg = 0x00U; \ 1414 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1415 /* Delay after an RCC peripheral clock enabling */ \ 1416 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1417 UNUSED(tmpreg); \ 1418 } while(0U) 1419 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1420 __IO uint32_t tmpreg = 0x00U; \ 1421 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 1422 /* Delay after an RCC peripheral clock enabling */ \ 1423 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 1424 UNUSED(tmpreg); \ 1425 } while(0U) 1426 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1427 __IO uint32_t tmpreg = 0x00U; \ 1428 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 1429 /* Delay after an RCC peripheral clock enabling */ \ 1430 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 1431 UNUSED(tmpreg); \ 1432 } while(0U) 1433 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1434 __IO uint32_t tmpreg = 0x00U; \ 1435 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1436 /* Delay after an RCC peripheral clock enabling */ \ 1437 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 1438 UNUSED(tmpreg); \ 1439 } while(0U) 1440 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1441 __IO uint32_t tmpreg = 0x00U; \ 1442 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1443 /* Delay after an RCC peripheral clock enabling */ \ 1444 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 1445 UNUSED(tmpreg); \ 1446 } while(0U) 1447 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 1448 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 1449 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 1450 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 1451 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 1452 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 1453 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 1454 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1455 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1456 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1457 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 1458 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 1459 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 1460 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 1461 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 1462 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 1463 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 1464 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 1465 /** 1466 * @} 1467 */ 1468 1469 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 1470 * @brief Get the enable or disable status of the APB1 peripheral clock. 1471 * @note After reset, the peripheral clock (used for registers read/write access) 1472 * is disabled and the application software has to enable this clock before 1473 * using it. 1474 * @{ 1475 */ 1476 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 1477 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 1478 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 1479 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1480 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 1481 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1482 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1483 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1484 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1485 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1486 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1487 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1488 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1489 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 1490 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 1491 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1492 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 1493 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 1494 1495 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 1496 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 1497 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 1498 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1499 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 1500 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1501 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1502 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1503 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1504 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1505 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1506 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1507 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1508 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 1509 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 1510 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1511 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 1512 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 1513 /** 1514 * @} 1515 */ 1516 1517 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1518 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 1519 * @note After reset, the peripheral clock (used for registers read/write access) 1520 * is disabled and the application software has to enable this clock before 1521 * using it. 1522 * @{ 1523 */ 1524 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1525 __IO uint32_t tmpreg = 0x00U; \ 1526 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1527 /* Delay after an RCC peripheral clock enabling */ \ 1528 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1529 UNUSED(tmpreg); \ 1530 } while(0U) 1531 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 1532 __IO uint32_t tmpreg = 0x00U; \ 1533 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1534 /* Delay after an RCC peripheral clock enabling */ \ 1535 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1536 UNUSED(tmpreg); \ 1537 } while(0U) 1538 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 1539 __IO uint32_t tmpreg = 0x00U; \ 1540 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1541 /* Delay after an RCC peripheral clock enabling */ \ 1542 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1543 UNUSED(tmpreg); \ 1544 } while(0U) 1545 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1546 __IO uint32_t tmpreg = 0x00U; \ 1547 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1548 /* Delay after an RCC peripheral clock enabling */ \ 1549 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1550 UNUSED(tmpreg); \ 1551 } while(0U) 1552 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1553 __IO uint32_t tmpreg = 0x00U; \ 1554 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1555 /* Delay after an RCC peripheral clock enabling */ \ 1556 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 1557 UNUSED(tmpreg); \ 1558 } while(0U) 1559 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1560 __IO uint32_t tmpreg = 0x00U; \ 1561 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1562 /* Delay after an RCC peripheral clock enabling */ \ 1563 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1564 UNUSED(tmpreg); \ 1565 } while(0U) 1566 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 1567 __IO uint32_t tmpreg = 0x00U; \ 1568 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 1569 /* Delay after an RCC peripheral clock enabling */ \ 1570 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 1571 UNUSED(tmpreg); \ 1572 } while(0U) 1573 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1574 __IO uint32_t tmpreg = 0x00U; \ 1575 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1576 /* Delay after an RCC peripheral clock enabling */ \ 1577 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1578 UNUSED(tmpreg); \ 1579 } while(0U) 1580 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 1581 __IO uint32_t tmpreg = 0x00U; \ 1582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1583 /* Delay after an RCC peripheral clock enabling */ \ 1584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1585 UNUSED(tmpreg); \ 1586 } while(0U) 1587 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 1588 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 1589 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 1590 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 1591 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 1592 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 1593 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 1594 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) 1595 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 1596 1597 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1598 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1599 __IO uint32_t tmpreg = 0x00U; \ 1600 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1601 /* Delay after an RCC peripheral clock enabling */ \ 1602 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 1603 UNUSED(tmpreg); \ 1604 } while(0U) 1605 1606 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) 1607 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1608 1609 #if defined(STM32F469xx) || defined(STM32F479xx) 1610 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1611 __IO uint32_t tmpreg = 0x00U; \ 1612 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1613 /* Delay after an RCC peripheral clock enabling */ \ 1614 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 1615 UNUSED(tmpreg); \ 1616 } while(0U) 1617 1618 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) 1619 #endif /* STM32F469xx || STM32F479xx */ 1620 /** 1621 * @} 1622 */ 1623 1624 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 1625 * @brief Get the enable or disable status of the APB2 peripheral clock. 1626 * @note After reset, the peripheral clock (used for registers read/write access) 1627 * is disabled and the application software has to enable this clock before 1628 * using it. 1629 * @{ 1630 */ 1631 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 1632 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 1633 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 1634 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 1635 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 1636 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 1637 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 1638 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 1639 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) 1640 1641 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 1642 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 1643 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) 1644 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 1645 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 1646 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 1647 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 1648 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) 1649 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 1650 1651 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1652 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) 1653 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) 1654 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 1655 1656 #if defined(STM32F469xx) || defined(STM32F479xx) 1657 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) 1658 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) 1659 #endif /* STM32F469xx || STM32F479xx */ 1660 /** 1661 * @} 1662 */ 1663 1664 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 1665 * @brief Force or release AHB1 peripheral reset. 1666 * @{ 1667 */ 1668 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x22E017FFU) 1669 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 1670 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 1671 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 1672 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 1673 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 1674 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 1675 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 1676 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) 1677 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) 1678 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) 1679 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 1680 1681 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 1682 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 1683 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 1684 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 1685 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 1686 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 1687 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 1688 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) 1689 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) 1690 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) 1691 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 1692 /** 1693 * @} 1694 */ 1695 1696 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 1697 * @brief Force or release AHB2 peripheral reset. 1698 * @{ 1699 */ 1700 #if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F469xx) 1701 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) 1702 #endif /* STM32F427xx || STM32F429xx || STM32F469xx */ 1703 #if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) 1704 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) 1705 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1706 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 1707 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 1708 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 1709 1710 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 1711 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 1712 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 1713 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 1714 1715 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1716 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 1717 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 1718 1719 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 1720 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 1721 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1722 /** 1723 * @} 1724 */ 1725 1726 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 1727 * @brief Force or release AHB3 peripheral reset. 1728 * @{ 1729 */ 1730 #if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) 1731 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) 1732 #endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx */ 1733 #if defined(STM32F469xx) || defined(STM32F479xx) 1734 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) 1735 #endif /* STM32F469xx || STM32F479xx */ 1736 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 1737 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 1738 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 1739 1740 #if defined(STM32F469xx) || defined(STM32F479xx) 1741 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 1742 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 1743 #endif /* STM32F469xx || STM32F479xx */ 1744 /** 1745 * @} 1746 */ 1747 1748 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 1749 * @brief Force or release APB1 peripheral reset. 1750 * @{ 1751 */ 1752 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) 1753 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1754 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1755 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1756 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1757 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1758 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1759 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1760 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1761 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 1762 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 1763 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1764 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 1765 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 1766 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 1767 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 1768 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 1769 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1770 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 1771 1772 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 1773 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 1774 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 1775 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1776 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 1777 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1778 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1779 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1780 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1781 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1782 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1783 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1784 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1785 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 1786 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 1787 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1788 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 1789 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 1790 /** 1791 * @} 1792 */ 1793 1794 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 1795 * @brief Force or release APB2 peripheral reset. 1796 * @{ 1797 */ 1798 #if defined(STM32F469xx) || defined(STM32F479xx) 1799 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x0C777933U) 1800 #endif /* STM32F469xx || STM32F479xx */ 1801 #if defined(STM32F429xx) || defined(STM32F439xx) 1802 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) 1803 #endif /* STM32F429xx || STM32F439xx */ 1804 #if defined(STM32F427xx) || defined(STM32F437xx) 1805 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00777933U) 1806 #endif /* STM32F427xx || STM32F437xx */ 1807 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 1808 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 1809 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) 1810 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 1811 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 1812 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 1813 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1814 1815 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 1816 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 1817 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1818 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 1819 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 1820 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) 1821 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 1822 1823 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 1824 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) 1825 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) 1826 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 1827 1828 #if defined(STM32F469xx) || defined(STM32F479xx) 1829 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) 1830 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) 1831 #endif /* STM32F469xx || STM32F479xx */ 1832 /** 1833 * @} 1834 */ 1835 1836 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 1837 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1838 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1839 * power consumption. 1840 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1841 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1842 * @{ 1843 */ 1844 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 1845 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 1846 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 1847 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 1848 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 1849 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 1850 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 1851 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 1852 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 1853 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 1854 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 1855 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 1856 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) 1857 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) 1858 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) 1859 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) 1860 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 1861 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 1862 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 1863 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 1864 1865 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 1866 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 1867 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 1868 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 1869 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 1870 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 1871 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 1872 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 1873 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 1874 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 1875 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 1876 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 1877 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) 1878 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) 1879 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) 1880 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 1881 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 1882 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 1883 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 1884 /** 1885 * @} 1886 */ 1887 1888 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 1889 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 1890 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1891 * power consumption. 1892 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 1893 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1894 * @{ 1895 */ 1896 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 1897 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 1898 1899 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 1900 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 1901 1902 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 1903 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 1904 1905 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 1906 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 1907 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 1908 1909 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 1910 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 1911 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 1912 /** 1913 * @} 1914 */ 1915 1916 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 1917 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 1918 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1919 * power consumption. 1920 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1921 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1922 * @{ 1923 */ 1924 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 1925 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 1926 1927 #if defined(STM32F469xx) || defined(STM32F479xx) 1928 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 1929 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 1930 #endif /* STM32F469xx || STM32F479xx */ 1931 /** 1932 * @} 1933 */ 1934 1935 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 1936 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1937 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1938 * power consumption. 1939 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1940 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1941 * @{ 1942 */ 1943 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 1944 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 1945 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 1946 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 1947 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 1948 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 1949 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 1950 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 1951 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 1952 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 1953 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 1954 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 1955 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 1956 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 1957 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 1958 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 1959 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 1960 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 1961 1962 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 1963 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 1964 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 1965 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 1966 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 1967 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 1968 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 1969 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 1970 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 1971 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 1972 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 1973 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 1974 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 1975 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 1976 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 1977 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 1978 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 1979 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 1980 /** 1981 * @} 1982 */ 1983 1984 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 1985 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1986 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1987 * power consumption. 1988 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1989 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1990 * @{ 1991 */ 1992 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 1993 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 1994 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 1995 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 1996 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) 1997 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 1998 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 1999 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 2000 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 2001 2002 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 2003 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 2004 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 2005 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 2006 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 2007 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 2008 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 2009 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) 2010 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 2011 2012 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 2013 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) 2014 2015 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) 2016 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 2017 2018 #if defined(STM32F469xx) || defined(STM32F479xx) 2019 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) 2020 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) 2021 #endif /* STM32F469xx || STM32F479xx */ 2022 /** 2023 * @} 2024 */ 2025 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 2026 /*----------------------------------------------------------------------------*/ 2027 2028 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ 2029 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 2030 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 2031 * @brief Enables or disables the AHB1 peripheral clock. 2032 * @note After reset, the peripheral clock (used for registers read/write access) 2033 * is disabled and the application software has to enable this clock before 2034 * using it. 2035 * @{ 2036 */ 2037 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 2038 __IO uint32_t tmpreg = 0x00U; \ 2039 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 2040 /* Delay after an RCC peripheral clock enabling */ \ 2041 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 2042 UNUSED(tmpreg); \ 2043 } while(0U) 2044 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 2045 __IO uint32_t tmpreg = 0x00U; \ 2046 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2047 /* Delay after an RCC peripheral clock enabling */ \ 2048 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2049 UNUSED(tmpreg); \ 2050 } while(0U) 2051 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 2052 __IO uint32_t tmpreg = 0x00U; \ 2053 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2054 /* Delay after an RCC peripheral clock enabling */ \ 2055 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2056 UNUSED(tmpreg); \ 2057 } while(0U) 2058 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 2059 __IO uint32_t tmpreg = 0x00U; \ 2060 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2061 /* Delay after an RCC peripheral clock enabling */ \ 2062 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2063 UNUSED(tmpreg); \ 2064 } while(0U) 2065 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 2066 __IO uint32_t tmpreg = 0x00U; \ 2067 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2068 /* Delay after an RCC peripheral clock enabling */ \ 2069 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2070 UNUSED(tmpreg); \ 2071 } while(0U) 2072 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 2073 __IO uint32_t tmpreg = 0x00U; \ 2074 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 2075 /* Delay after an RCC peripheral clock enabling */ \ 2076 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 2077 UNUSED(tmpreg); \ 2078 } while(0U) 2079 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 2080 __IO uint32_t tmpreg = 0x00U; \ 2081 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 2082 /* Delay after an RCC peripheral clock enabling */ \ 2083 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 2084 UNUSED(tmpreg); \ 2085 } while(0U) 2086 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 2087 __IO uint32_t tmpreg = 0x00U; \ 2088 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 2089 /* Delay after an RCC peripheral clock enabling */ \ 2090 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 2091 UNUSED(tmpreg); \ 2092 } while(0U) 2093 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 2094 __IO uint32_t tmpreg = 0x00U; \ 2095 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 2096 /* Delay after an RCC peripheral clock enabling */ \ 2097 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 2098 UNUSED(tmpreg); \ 2099 } while(0U) 2100 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 2101 __IO uint32_t tmpreg = 0x00U; \ 2102 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 2103 /* Delay after an RCC peripheral clock enabling */ \ 2104 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 2105 UNUSED(tmpreg); \ 2106 } while(0U) 2107 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 2108 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 2109 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 2110 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 2111 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 2112 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 2113 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 2114 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 2115 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 2116 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 2117 #if defined(STM32F407xx)|| defined(STM32F417xx) 2118 /** 2119 * @brief Enable ETHERNET clock. 2120 */ 2121 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 2122 __IO uint32_t tmpreg = 0x00U; \ 2123 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 2124 /* Delay after an RCC peripheral clock enabling */ \ 2125 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 2126 UNUSED(tmpreg); \ 2127 } while(0U) 2128 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 2129 __IO uint32_t tmpreg = 0x00U; \ 2130 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 2131 /* Delay after an RCC peripheral clock enabling */ \ 2132 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 2133 UNUSED(tmpreg); \ 2134 } while(0U) 2135 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 2136 __IO uint32_t tmpreg = 0x00U; \ 2137 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 2138 /* Delay after an RCC peripheral clock enabling */ \ 2139 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 2140 UNUSED(tmpreg); \ 2141 } while(0U) 2142 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 2143 __IO uint32_t tmpreg = 0x00U; \ 2144 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 2145 /* Delay after an RCC peripheral clock enabling */ \ 2146 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 2147 UNUSED(tmpreg); \ 2148 } while(0U) 2149 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 2150 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 2151 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 2152 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 2153 } while(0U) 2154 2155 /** 2156 * @brief Disable ETHERNET clock. 2157 */ 2158 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 2159 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 2160 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 2161 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 2162 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 2163 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 2164 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 2165 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 2166 } while(0U) 2167 #endif /* STM32F407xx || STM32F417xx */ 2168 /** 2169 * @} 2170 */ 2171 2172 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 2173 * @brief Get the enable or disable status of the AHB1 peripheral clock. 2174 * @note After reset, the peripheral clock (used for registers read/write access) 2175 * is disabled and the application software has to enable this clock before 2176 * using it. 2177 * @{ 2178 */ 2179 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 2180 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 2181 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 2182 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 2183 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 2184 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 2185 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 2186 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 2187 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 2188 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 2189 2190 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 2191 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 2192 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 2193 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 2194 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 2195 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 2196 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) 2197 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 2198 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 2199 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 2200 #if defined(STM32F407xx)|| defined(STM32F417xx) 2201 /** 2202 * @brief Enable ETHERNET clock. 2203 */ 2204 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 2205 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 2206 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 2207 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 2208 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 2209 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 2210 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 2211 /** 2212 * @brief Disable ETHERNET clock. 2213 */ 2214 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 2215 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 2216 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 2217 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 2218 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 2219 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 2220 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 2221 #endif /* STM32F407xx || STM32F417xx */ 2222 /** 2223 * @} 2224 */ 2225 2226 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 2227 * @brief Enable or disable the AHB2 peripheral clock. 2228 * @note After reset, the peripheral clock (used for registers read/write access) 2229 * is disabled and the application software has to enable this clock before 2230 * using it. 2231 * @{ 2232 */ 2233 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 2234 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 2235 }while(0U) 2236 2237 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 2238 2239 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 2240 __IO uint32_t tmpreg = 0x00U; \ 2241 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2242 /* Delay after an RCC peripheral clock enabling */ \ 2243 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 2244 UNUSED(tmpreg); \ 2245 } while(0U) 2246 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 2247 2248 #if defined(STM32F407xx)|| defined(STM32F417xx) 2249 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 2250 __IO uint32_t tmpreg = 0x00U; \ 2251 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2252 /* Delay after an RCC peripheral clock enabling */ \ 2253 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 2254 UNUSED(tmpreg); \ 2255 } while(0U) 2256 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 2257 #endif /* STM32F407xx || STM32F417xx */ 2258 2259 #if defined(STM32F415xx) || defined(STM32F417xx) 2260 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 2261 __IO uint32_t tmpreg = 0x00U; \ 2262 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2263 /* Delay after an RCC peripheral clock enabling */ \ 2264 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 2265 UNUSED(tmpreg); \ 2266 } while(0U) 2267 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 2268 __IO uint32_t tmpreg = 0x00U; \ 2269 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2270 /* Delay after an RCC peripheral clock enabling */ \ 2271 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 2272 UNUSED(tmpreg); \ 2273 } while(0U) 2274 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 2275 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 2276 #endif /* STM32F415xx || STM32F417xx */ 2277 /** 2278 * @} 2279 */ 2280 2281 2282 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 2283 * @brief Get the enable or disable status of the AHB2 peripheral clock. 2284 * @note After reset, the peripheral clock (used for registers read/write access) 2285 * is disabled and the application software has to enable this clock before 2286 * using it. 2287 * @{ 2288 */ 2289 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 2290 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 2291 2292 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 2293 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 2294 2295 #if defined(STM32F407xx)|| defined(STM32F417xx) 2296 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 2297 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 2298 #endif /* STM32F407xx || STM32F417xx */ 2299 2300 #if defined(STM32F415xx) || defined(STM32F417xx) 2301 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 2302 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 2303 2304 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 2305 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 2306 #endif /* STM32F415xx || STM32F417xx */ 2307 /** 2308 * @} 2309 */ 2310 2311 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 2312 * @brief Enables or disables the AHB3 peripheral clock. 2313 * @note After reset, the peripheral clock (used for registers read/write access) 2314 * is disabled and the application software has to enable this clock before 2315 * using it. 2316 * @{ 2317 */ 2318 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 2319 __IO uint32_t tmpreg = 0x00U; \ 2320 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 2321 /* Delay after an RCC peripheral clock enabling */ \ 2322 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 2323 UNUSED(tmpreg); \ 2324 } while(0U) 2325 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 2326 /** 2327 * @} 2328 */ 2329 2330 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 2331 * @brief Get the enable or disable status of the AHB3 peripheral clock. 2332 * @note After reset, the peripheral clock (used for registers read/write access) 2333 * is disabled and the application software has to enable this clock before 2334 * using it. 2335 * @{ 2336 */ 2337 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 2338 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 2339 /** 2340 * @} 2341 */ 2342 2343 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 2344 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 2345 * @note After reset, the peripheral clock (used for registers read/write access) 2346 * is disabled and the application software has to enable this clock before 2347 * using it. 2348 * @{ 2349 */ 2350 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 2351 __IO uint32_t tmpreg = 0x00U; \ 2352 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 2353 /* Delay after an RCC peripheral clock enabling */ \ 2354 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 2355 UNUSED(tmpreg); \ 2356 } while(0U) 2357 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 2358 __IO uint32_t tmpreg = 0x00U; \ 2359 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2360 /* Delay after an RCC peripheral clock enabling */ \ 2361 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 2362 UNUSED(tmpreg); \ 2363 } while(0U) 2364 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 2365 __IO uint32_t tmpreg = 0x00U; \ 2366 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2367 /* Delay after an RCC peripheral clock enabling */ \ 2368 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 2369 UNUSED(tmpreg); \ 2370 } while(0U) 2371 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 2372 __IO uint32_t tmpreg = 0x00U; \ 2373 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2374 /* Delay after an RCC peripheral clock enabling */ \ 2375 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 2376 UNUSED(tmpreg); \ 2377 } while(0U) 2378 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 2379 __IO uint32_t tmpreg = 0x00U; \ 2380 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2381 /* Delay after an RCC peripheral clock enabling */ \ 2382 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 2383 UNUSED(tmpreg); \ 2384 } while(0U) 2385 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 2386 __IO uint32_t tmpreg = 0x00U; \ 2387 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 2388 /* Delay after an RCC peripheral clock enabling */ \ 2389 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 2390 UNUSED(tmpreg); \ 2391 } while(0U) 2392 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 2393 __IO uint32_t tmpreg = 0x00U; \ 2394 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2395 /* Delay after an RCC peripheral clock enabling */ \ 2396 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 2397 UNUSED(tmpreg); \ 2398 } while(0U) 2399 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 2400 __IO uint32_t tmpreg = 0x00U; \ 2401 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2402 /* Delay after an RCC peripheral clock enabling */ \ 2403 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 2404 UNUSED(tmpreg); \ 2405 } while(0U) 2406 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 2407 __IO uint32_t tmpreg = 0x00U; \ 2408 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 2409 /* Delay after an RCC peripheral clock enabling */ \ 2410 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 2411 UNUSED(tmpreg); \ 2412 } while(0U) 2413 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 2414 __IO uint32_t tmpreg = 0x00U; \ 2415 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 2416 /* Delay after an RCC peripheral clock enabling */ \ 2417 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 2418 UNUSED(tmpreg); \ 2419 } while(0U) 2420 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 2421 __IO uint32_t tmpreg = 0x00U; \ 2422 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 2423 /* Delay after an RCC peripheral clock enabling */ \ 2424 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 2425 UNUSED(tmpreg); \ 2426 } while(0U) 2427 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 2428 __IO uint32_t tmpreg = 0x00U; \ 2429 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2430 /* Delay after an RCC peripheral clock enabling */ \ 2431 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 2432 UNUSED(tmpreg); \ 2433 } while(0U) 2434 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 2435 __IO uint32_t tmpreg = 0x00U; \ 2436 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2437 /* Delay after an RCC peripheral clock enabling */ \ 2438 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 2439 UNUSED(tmpreg); \ 2440 } while(0U) 2441 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 2442 __IO uint32_t tmpreg = 0x00U; \ 2443 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2444 /* Delay after an RCC peripheral clock enabling */ \ 2445 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 2446 UNUSED(tmpreg); \ 2447 } while(0U) 2448 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 2449 __IO uint32_t tmpreg = 0x00U; \ 2450 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2451 /* Delay after an RCC peripheral clock enabling */ \ 2452 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 2453 UNUSED(tmpreg); \ 2454 } while(0U) 2455 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 2456 __IO uint32_t tmpreg = 0x00U; \ 2457 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2458 /* Delay after an RCC peripheral clock enabling */ \ 2459 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 2460 UNUSED(tmpreg); \ 2461 } while(0U) 2462 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 2463 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 2464 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 2465 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 2466 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 2467 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 2468 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 2469 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 2470 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 2471 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 2472 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 2473 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 2474 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 2475 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 2476 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 2477 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 2478 /** 2479 * @} 2480 */ 2481 2482 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 2483 * @brief Get the enable or disable status of the APB1 peripheral clock. 2484 * @note After reset, the peripheral clock (used for registers read/write access) 2485 * is disabled and the application software has to enable this clock before 2486 * using it. 2487 * @{ 2488 */ 2489 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 2490 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 2491 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 2492 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 2493 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 2494 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 2495 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 2496 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 2497 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 2498 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 2499 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 2500 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 2501 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 2502 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 2503 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 2504 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 2505 2506 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 2507 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 2508 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 2509 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 2510 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 2511 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 2512 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 2513 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 2514 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 2515 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 2516 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 2517 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 2518 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 2519 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 2520 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 2521 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 2522 /** 2523 * @} 2524 */ 2525 2526 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 2527 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 2528 * @note After reset, the peripheral clock (used for registers read/write access) 2529 * is disabled and the application software has to enable this clock before 2530 * using it. 2531 * @{ 2532 */ 2533 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 2534 __IO uint32_t tmpreg = 0x00U; \ 2535 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2536 /* Delay after an RCC peripheral clock enabling */ \ 2537 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 2538 UNUSED(tmpreg); \ 2539 } while(0U) 2540 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 2541 __IO uint32_t tmpreg = 0x00U; \ 2542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 2543 /* Delay after an RCC peripheral clock enabling */ \ 2544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 2545 UNUSED(tmpreg); \ 2546 } while(0U) 2547 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 2548 __IO uint32_t tmpreg = 0x00U; \ 2549 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 2550 /* Delay after an RCC peripheral clock enabling */ \ 2551 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 2552 UNUSED(tmpreg); \ 2553 } while(0U) 2554 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 2555 __IO uint32_t tmpreg = 0x00U; \ 2556 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 2557 /* Delay after an RCC peripheral clock enabling */ \ 2558 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 2559 UNUSED(tmpreg); \ 2560 } while(0U) 2561 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 2562 __IO uint32_t tmpreg = 0x00U; \ 2563 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2564 /* Delay after an RCC peripheral clock enabling */ \ 2565 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 2566 UNUSED(tmpreg); \ 2567 } while(0U) 2568 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 2569 __IO uint32_t tmpreg = 0x00U; \ 2570 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 2571 /* Delay after an RCC peripheral clock enabling */ \ 2572 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 2573 UNUSED(tmpreg); \ 2574 } while(0U) 2575 2576 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 2577 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 2578 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 2579 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 2580 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 2581 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 2582 /** 2583 * @} 2584 */ 2585 2586 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 2587 * @brief Get the enable or disable status of the APB2 peripheral clock. 2588 * @note After reset, the peripheral clock (used for registers read/write access) 2589 * is disabled and the application software has to enable this clock before 2590 * using it. 2591 * @{ 2592 */ 2593 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 2594 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 2595 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 2596 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 2597 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 2598 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 2599 2600 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 2601 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 2602 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 2603 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 2604 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 2605 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 2606 /** 2607 * @} 2608 */ 2609 2610 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 2611 * @brief Force or release AHB1 peripheral reset. 2612 * @{ 2613 */ 2614 #if defined (STM32F405xx) || defined (STM32F415xx) 2615 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206011FFU) 2616 #endif /* STM32F405xx || STM32F415xx */ 2617 #if defined (STM32F407xx) || defined (STM32F417xx) 2618 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x226011FFU) 2619 #endif /* STM32F407xx || STM32F417xx */ 2620 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 2621 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 2622 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 2623 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 2624 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 2625 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 2626 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 2627 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 2628 2629 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 2630 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 2631 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 2632 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 2633 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 2634 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 2635 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 2636 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 2637 /** 2638 * @} 2639 */ 2640 2641 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 2642 * @brief Force or release AHB2 peripheral reset. 2643 * @{ 2644 */ 2645 #if defined (STM32F415xx) || defined (STM32F417xx) 2646 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) 2647 #endif /* STM32F415xx || STM32F417xx */ 2648 #if defined (STM32F405xx) || defined (STM32F407xx) 2649 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) 2650 #endif /* STM32F405xx || STM32F407xx */ 2651 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 2652 2653 #if defined(STM32F407xx)|| defined(STM32F417xx) 2654 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 2655 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 2656 #endif /* STM32F407xx || STM32F417xx */ 2657 2658 #if defined(STM32F415xx) || defined(STM32F417xx) 2659 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 2660 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 2661 2662 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 2663 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 2664 #endif /* STM32F415xx || STM32F417xx */ 2665 2666 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 2667 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 2668 2669 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 2670 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 2671 /** 2672 * @} 2673 */ 2674 2675 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 2676 * @brief Force or release AHB3 peripheral reset. 2677 * @{ 2678 */ 2679 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) 2680 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 2681 2682 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 2683 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 2684 /** 2685 * @} 2686 */ 2687 2688 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 2689 * @brief Force or release APB1 peripheral reset. 2690 * @{ 2691 */ 2692 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) 2693 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 2694 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 2695 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 2696 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 2697 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 2698 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 2699 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 2700 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 2701 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 2702 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 2703 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 2704 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 2705 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 2706 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 2707 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 2708 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 2709 2710 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 2711 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 2712 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 2713 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 2714 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 2715 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 2716 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 2717 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 2718 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 2719 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 2720 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 2721 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 2722 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 2723 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 2724 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 2725 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 2726 /** 2727 * @} 2728 */ 2729 2730 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 2731 * @brief Force or release APB2 peripheral reset. 2732 * @{ 2733 */ 2734 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) 2735 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 2736 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 2737 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 2738 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 2739 2740 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 2741 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 2742 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 2743 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 2744 /** 2745 * @} 2746 */ 2747 2748 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 2749 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2750 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2751 * power consumption. 2752 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2753 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2754 * @{ 2755 */ 2756 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 2757 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 2758 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 2759 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 2760 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 2761 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 2762 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 2763 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 2764 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 2765 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 2766 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 2767 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 2768 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 2769 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 2770 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 2771 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 2772 2773 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 2774 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 2775 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 2776 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 2777 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 2778 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 2779 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 2780 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 2781 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 2782 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 2783 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 2784 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 2785 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 2786 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 2787 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 2788 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 2789 /** 2790 * @} 2791 */ 2792 2793 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 2794 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2795 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2796 * power consumption. 2797 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 2798 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2799 * @{ 2800 */ 2801 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 2802 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 2803 2804 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 2805 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 2806 2807 #if defined(STM32F407xx)|| defined(STM32F417xx) 2808 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 2809 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 2810 #endif /* STM32F407xx || STM32F417xx */ 2811 2812 #if defined(STM32F415xx) || defined(STM32F417xx) 2813 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 2814 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 2815 2816 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 2817 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 2818 #endif /* STM32F415xx || STM32F417xx */ 2819 /** 2820 * @} 2821 */ 2822 2823 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 2824 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2825 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2826 * power consumption. 2827 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2828 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2829 * @{ 2830 */ 2831 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 2832 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 2833 /** 2834 * @} 2835 */ 2836 2837 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 2838 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2839 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2840 * power consumption. 2841 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2842 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2843 * @{ 2844 */ 2845 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 2846 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 2847 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 2848 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 2849 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 2850 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 2851 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 2852 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 2853 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 2854 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 2855 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 2856 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 2857 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 2858 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 2859 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 2860 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 2861 2862 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 2863 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 2864 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 2865 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 2866 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 2867 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 2868 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 2869 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 2870 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 2871 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 2872 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 2873 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 2874 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 2875 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 2876 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 2877 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 2878 /** 2879 * @} 2880 */ 2881 2882 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 2883 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2884 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2885 * power consumption. 2886 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2887 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2888 * @{ 2889 */ 2890 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 2891 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 2892 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 2893 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 2894 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 2895 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 2896 2897 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 2898 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 2899 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 2900 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 2901 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 2902 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 2903 /** 2904 * @} 2905 */ 2906 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 2907 /*----------------------------------------------------------------------------*/ 2908 2909 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/ 2910 #if defined(STM32F401xC) || defined(STM32F401xE) 2911 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 2912 * @brief Enable or disable the AHB1 peripheral clock. 2913 * @note After reset, the peripheral clock (used for registers read/write access) 2914 * is disabled and the application software has to enable this clock before 2915 * using it. 2916 * @{ 2917 */ 2918 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 2919 __IO uint32_t tmpreg = 0x00U; \ 2920 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2921 /* Delay after an RCC peripheral clock enabling */ \ 2922 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 2923 UNUSED(tmpreg); \ 2924 } while(0U) 2925 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 2926 __IO uint32_t tmpreg = 0x00U; \ 2927 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2928 /* Delay after an RCC peripheral clock enabling */ \ 2929 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 2930 UNUSED(tmpreg); \ 2931 } while(0U) 2932 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 2933 __IO uint32_t tmpreg = 0x00U; \ 2934 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2935 /* Delay after an RCC peripheral clock enabling */ \ 2936 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 2937 UNUSED(tmpreg); \ 2938 } while(0U) 2939 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 2940 __IO uint32_t tmpreg = 0x00U; \ 2941 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2942 /* Delay after an RCC peripheral clock enabling */ \ 2943 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 2944 UNUSED(tmpreg); \ 2945 } while(0U) 2946 2947 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 2948 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 2949 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 2950 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 2951 /** 2952 * @} 2953 */ 2954 2955 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 2956 * @brief Get the enable or disable status of the AHB1 peripheral clock. 2957 * @note After reset, the peripheral clock (used for registers read/write access) 2958 * is disabled and the application software has to enable this clock before 2959 * using it. 2960 * @{ 2961 */ 2962 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 2963 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 2964 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 2965 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 2966 2967 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 2968 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 2969 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 2970 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 2971 /** 2972 * @} 2973 */ 2974 2975 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 2976 * @brief Enable or disable the AHB2 peripheral clock. 2977 * @note After reset, the peripheral clock (used for registers read/write access) 2978 * is disabled and the application software has to enable this clock before 2979 * using it. 2980 * @{ 2981 */ 2982 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 2983 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 2984 }while(0U) 2985 2986 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 2987 /** 2988 * @} 2989 */ 2990 2991 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 2992 * @brief Get the enable or disable status of the AHB2 peripheral clock. 2993 * @note After reset, the peripheral clock (used for registers read/write access) 2994 * is disabled and the application software has to enable this clock before 2995 * using it. 2996 * @{ 2997 */ 2998 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 2999 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 3000 /** 3001 * @} 3002 */ 3003 3004 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 3005 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 3006 * @note After reset, the peripheral clock (used for registers read/write access) 3007 * is disabled and the application software has to enable this clock before 3008 * using it. 3009 * @{ 3010 */ 3011 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 3012 __IO uint32_t tmpreg = 0x00U; \ 3013 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3014 /* Delay after an RCC peripheral clock enabling */ \ 3015 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3016 UNUSED(tmpreg); \ 3017 } while(0U) 3018 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 3019 __IO uint32_t tmpreg = 0x00U; \ 3020 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3021 /* Delay after an RCC peripheral clock enabling */ \ 3022 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3023 UNUSED(tmpreg); \ 3024 } while(0U) 3025 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 3026 __IO uint32_t tmpreg = 0x00U; \ 3027 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3028 /* Delay after an RCC peripheral clock enabling */ \ 3029 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3030 UNUSED(tmpreg); \ 3031 } while(0U) 3032 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 3033 __IO uint32_t tmpreg = 0x00U; \ 3034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3035 /* Delay after an RCC peripheral clock enabling */ \ 3036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3037 UNUSED(tmpreg); \ 3038 } while(0U) 3039 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 3040 __IO uint32_t tmpreg = 0x00U; \ 3041 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3042 /* Delay after an RCC peripheral clock enabling */ \ 3043 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3044 UNUSED(tmpreg); \ 3045 } while(0U) 3046 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 3047 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 3048 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 3049 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 3050 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 3051 /** 3052 * @} 3053 */ 3054 3055 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3056 * @brief Get the enable or disable status of the APB1 peripheral clock. 3057 * @note After reset, the peripheral clock (used for registers read/write access) 3058 * is disabled and the application software has to enable this clock before 3059 * using it. 3060 * @{ 3061 */ 3062 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 3063 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 3064 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 3065 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 3066 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 3067 3068 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 3069 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 3070 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 3071 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 3072 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 3073 /** 3074 * @} 3075 */ 3076 3077 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3078 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3079 * @note After reset, the peripheral clock (used for registers read/write access) 3080 * is disabled and the application software has to enable this clock before 3081 * using it. 3082 * @{ 3083 */ 3084 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 3085 __IO uint32_t tmpreg = 0x00U; \ 3086 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3087 /* Delay after an RCC peripheral clock enabling */ \ 3088 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3089 UNUSED(tmpreg); \ 3090 } while(0U) 3091 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 3092 __IO uint32_t tmpreg = 0x00U; \ 3093 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3094 /* Delay after an RCC peripheral clock enabling */ \ 3095 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3096 UNUSED(tmpreg); \ 3097 } while(0U) 3098 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 3099 __IO uint32_t tmpreg = 0x00U; \ 3100 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3101 /* Delay after an RCC peripheral clock enabling */ \ 3102 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3103 UNUSED(tmpreg); \ 3104 } while(0U) 3105 3106 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 3107 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 3108 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 3109 /** 3110 * @} 3111 */ 3112 3113 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3114 * @brief Get the enable or disable status of the APB2 peripheral clock. 3115 * @note After reset, the peripheral clock (used for registers read/write access) 3116 * is disabled and the application software has to enable this clock before 3117 * using it. 3118 * @{ 3119 */ 3120 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 3121 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 3122 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 3123 3124 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 3125 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 3126 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 3127 /** 3128 * @} 3129 */ 3130 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3131 * @brief Force or release AHB1 peripheral reset. 3132 * @{ 3133 */ 3134 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) 3135 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 3136 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 3137 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3138 3139 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 3140 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 3141 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 3142 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3143 /** 3144 * @} 3145 */ 3146 3147 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3148 * @brief Force or release AHB2 peripheral reset. 3149 * @{ 3150 */ 3151 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) 3152 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 3153 3154 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 3155 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 3156 /** 3157 * @} 3158 */ 3159 3160 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3161 * @brief Force or release APB1 peripheral reset. 3162 * @{ 3163 */ 3164 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) 3165 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 3166 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 3167 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 3168 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 3169 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 3170 3171 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 3172 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 3173 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 3174 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 3175 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 3176 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 3177 /** 3178 * @} 3179 */ 3180 3181 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3182 * @brief Force or release APB2 peripheral reset. 3183 * @{ 3184 */ 3185 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00077931U) 3186 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 3187 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 3188 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 3189 3190 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 3191 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 3192 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 3193 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 3194 /** 3195 * @} 3196 */ 3197 3198 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3199 * @brief Force or release AHB3 peripheral reset. 3200 * @{ 3201 */ 3202 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 3203 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 3204 /** 3205 * @} 3206 */ 3207 3208 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3209 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3210 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3211 * power consumption. 3212 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3213 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3214 * @{ 3215 */ 3216 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 3217 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 3218 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3219 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3220 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3221 3222 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 3223 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 3224 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3225 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3226 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3227 /** 3228 * @} 3229 */ 3230 3231 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 3232 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3233 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3234 * power consumption. 3235 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3236 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3237 * @{ 3238 */ 3239 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 3240 3241 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 3242 /** 3243 * @} 3244 */ 3245 3246 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3247 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3248 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3249 * power consumption. 3250 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3251 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3252 * @{ 3253 */ 3254 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 3255 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 3256 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 3257 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 3258 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 3259 3260 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 3261 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 3262 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 3263 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 3264 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 3265 /** 3266 * @} 3267 */ 3268 3269 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3270 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3271 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3272 * power consumption. 3273 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3274 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3275 * @{ 3276 */ 3277 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 3278 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 3279 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 3280 3281 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 3282 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 3283 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 3284 /** 3285 * @} 3286 */ 3287 #endif /* STM32F401xC || STM32F401xE*/ 3288 /*----------------------------------------------------------------------------*/ 3289 3290 /*-------------------------------- STM32F410xx -------------------------------*/ 3291 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 3292 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3293 * @brief Enables or disables the AHB1 peripheral clock. 3294 * @note After reset, the peripheral clock (used for registers read/write access) 3295 * is disabled and the application software has to enable this clock before 3296 * using it. 3297 * @{ 3298 */ 3299 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3300 __IO uint32_t tmpreg = 0x00U; \ 3301 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3302 /* Delay after an RCC peripheral clock enabling */ \ 3303 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3304 UNUSED(tmpreg); \ 3305 } while(0U) 3306 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 3307 __IO uint32_t tmpreg = 0x00U; \ 3308 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 3309 /* Delay after an RCC peripheral clock enabling */ \ 3310 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 3311 UNUSED(tmpreg); \ 3312 } while(0U) 3313 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3314 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) 3315 /** 3316 * @} 3317 */ 3318 3319 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3320 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3321 * @note After reset, the peripheral clock (used for registers read/write access) 3322 * is disabled and the application software has to enable this clock before 3323 * using it. 3324 * @{ 3325 */ 3326 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 3327 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) 3328 3329 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 3330 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) 3331 /** 3332 * @} 3333 */ 3334 3335 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 3336 * @brief Enable or disable the High Speed APB (APB1) peripheral clock. 3337 * @{ 3338 */ 3339 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 3340 __IO uint32_t tmpreg = 0x00U; \ 3341 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 3342 /* Delay after an RCC peripheral clock enabling */ \ 3343 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 3344 UNUSED(tmpreg); \ 3345 } while(0U) 3346 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 3347 __IO uint32_t tmpreg = 0x00U; \ 3348 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 3349 /* Delay after an RCC peripheral clock enabling */ \ 3350 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 3351 UNUSED(tmpreg); \ 3352 } while(0U) 3353 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 3354 __IO uint32_t tmpreg = 0x00U; \ 3355 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 3356 /* Delay after an RCC peripheral clock enabling */ \ 3357 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 3358 UNUSED(tmpreg); \ 3359 } while(0U) 3360 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 3361 __IO uint32_t tmpreg = 0x00U; \ 3362 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 3363 /* Delay after an RCC peripheral clock enabling */ \ 3364 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 3365 UNUSED(tmpreg); \ 3366 } while(0U) 3367 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 3368 __IO uint32_t tmpreg = 0x00U; \ 3369 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 3370 /* Delay after an RCC peripheral clock enabling */ \ 3371 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 3372 UNUSED(tmpreg); \ 3373 } while(0U) 3374 3375 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 3376 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 3377 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 3378 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 3379 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 3380 /** 3381 * @} 3382 */ 3383 3384 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3385 * @brief Get the enable or disable status of the APB1 peripheral clock. 3386 * @note After reset, the peripheral clock (used for registers read/write access) 3387 * is disabled and the application software has to enable this clock before 3388 * using it. 3389 * @{ 3390 */ 3391 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 3392 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 3393 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 3394 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 3395 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 3396 3397 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 3398 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 3399 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 3400 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 3401 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 3402 /** 3403 * @} 3404 */ 3405 3406 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3407 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3408 * @{ 3409 */ 3410 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 3411 __IO uint32_t tmpreg = 0x00U; \ 3412 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3413 /* Delay after an RCC peripheral clock enabling */ \ 3414 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3415 UNUSED(tmpreg); \ 3416 } while(0U) 3417 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 3418 __IO uint32_t tmpreg = 0x00U; \ 3419 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 3420 /* Delay after an RCC peripheral clock enabling */ \ 3421 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 3422 UNUSED(tmpreg); \ 3423 } while(0U) 3424 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 3425 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 3426 /** 3427 * @} 3428 */ 3429 3430 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3431 * @brief Get the enable or disable status of the APB2 peripheral clock. 3432 * @note After reset, the peripheral clock (used for registers read/write access) 3433 * is disabled and the application software has to enable this clock before 3434 * using it. 3435 * @{ 3436 */ 3437 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 3438 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 3439 3440 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 3441 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 3442 /** 3443 * @} 3444 */ 3445 3446 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3447 * @brief Force or release AHB1 peripheral reset. 3448 * @{ 3449 */ 3450 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x80601087U) 3451 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3452 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) 3453 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3454 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) 3455 /** 3456 * @} 3457 */ 3458 3459 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3460 * @brief Force or release AHB2 peripheral reset. 3461 * @{ 3462 */ 3463 #define __HAL_RCC_AHB2_FORCE_RESET() 3464 #define __HAL_RCC_AHB2_RELEASE_RESET() 3465 /** 3466 * @} 3467 */ 3468 3469 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3470 * @brief Force or release AHB3 peripheral reset. 3471 * @{ 3472 */ 3473 #define __HAL_RCC_AHB3_FORCE_RESET() 3474 #define __HAL_RCC_AHB3_RELEASE_RESET() 3475 /** 3476 * @} 3477 */ 3478 3479 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3480 * @brief Force or release APB1 peripheral reset. 3481 * @{ 3482 */ 3483 #if defined (STM32F410Rx) || defined (STM32F410Cx) 3484 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31624A18U) 3485 #endif /* STM32F410Rx || STM32F410Cx */ 3486 #if defined (STM32F410Tx) 3487 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31620A18U) 3488 #endif /* STM32F410Tx */ 3489 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 3490 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 3491 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 3492 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 3493 3494 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 3495 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 3496 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 3497 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 3498 /** 3499 * @} 3500 */ 3501 3502 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3503 * @brief Force or release APB2 peripheral reset. 3504 * @{ 3505 */ 3506 #if defined (STM32F410Rx) || defined (STM32F410Cx) 3507 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00155131U) 3508 #endif /* STM32F410Rx || STM32F410Cx */ 3509 #if defined (STM32F410Tx) 3510 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00055111U) 3511 #endif /* STM32F410Tx */ 3512 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 3513 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 3514 /** 3515 * @} 3516 */ 3517 3518 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3519 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3520 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3521 * power consumption. 3522 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3523 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3524 * @{ 3525 */ 3526 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) 3527 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3528 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3529 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3530 3531 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) 3532 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3533 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3534 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3535 /** 3536 * @} 3537 */ 3538 3539 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3540 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3541 * @{ 3542 */ 3543 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 3544 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 3545 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 3546 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 3547 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 3548 3549 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 3550 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 3551 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 3552 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 3553 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 3554 /** 3555 * @} 3556 */ 3557 3558 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3559 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3560 * @{ 3561 */ 3562 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 3563 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 3564 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 3565 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 3566 /** 3567 * @} 3568 */ 3569 3570 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 3571 /*----------------------------------------------------------------------------*/ 3572 3573 /*-------------------------------- STM32F411xx -------------------------------*/ 3574 #if defined(STM32F411xE) 3575 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3576 * @brief Enables or disables the AHB1 peripheral clock. 3577 * @note After reset, the peripheral clock (used for registers read/write access) 3578 * is disabled and the application software has to enable this clock before 3579 * using it. 3580 * @{ 3581 */ 3582 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 3583 __IO uint32_t tmpreg = 0x00U; \ 3584 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3585 /* Delay after an RCC peripheral clock enabling */ \ 3586 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3587 UNUSED(tmpreg); \ 3588 } while(0U) 3589 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 3590 __IO uint32_t tmpreg = 0x00U; \ 3591 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3592 /* Delay after an RCC peripheral clock enabling */ \ 3593 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3594 UNUSED(tmpreg); \ 3595 } while(0U) 3596 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 3597 __IO uint32_t tmpreg = 0x00U; \ 3598 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3599 /* Delay after an RCC peripheral clock enabling */ \ 3600 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3601 UNUSED(tmpreg); \ 3602 } while(0U) 3603 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3604 __IO uint32_t tmpreg = 0x00U; \ 3605 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3606 /* Delay after an RCC peripheral clock enabling */ \ 3607 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3608 UNUSED(tmpreg); \ 3609 } while(0U) 3610 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 3611 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 3612 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 3613 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 3614 /** 3615 * @} 3616 */ 3617 3618 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 3619 * @brief Get the enable or disable status of the AHB1 peripheral clock. 3620 * @note After reset, the peripheral clock (used for registers read/write access) 3621 * is disabled and the application software has to enable this clock before 3622 * using it. 3623 * @{ 3624 */ 3625 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 3626 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 3627 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 3628 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 3629 3630 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 3631 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 3632 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 3633 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 3634 /** 3635 * @} 3636 */ 3637 3638 /** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 3639 * @brief Enable or disable the AHB2 peripheral clock. 3640 * @note After reset, the peripheral clock (used for registers read/write access) 3641 * is disabled and the application software has to enable this clock before 3642 * using it. 3643 * @{ 3644 */ 3645 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 3646 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 3647 }while(0U) 3648 3649 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 3650 /** 3651 * @} 3652 */ 3653 3654 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 3655 * @brief Get the enable or disable status of the AHB2 peripheral clock. 3656 * @note After reset, the peripheral clock (used for registers read/write access) 3657 * is disabled and the application software has to enable this clock before 3658 * using it. 3659 * @{ 3660 */ 3661 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 3662 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 3663 /** 3664 * @} 3665 */ 3666 3667 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 3668 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 3669 * @note After reset, the peripheral clock (used for registers read/write access) 3670 * is disabled and the application software has to enable this clock before 3671 * using it. 3672 * @{ 3673 */ 3674 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 3675 __IO uint32_t tmpreg = 0x00U; \ 3676 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3677 /* Delay after an RCC peripheral clock enabling */ \ 3678 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 3679 UNUSED(tmpreg); \ 3680 } while(0U) 3681 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 3682 __IO uint32_t tmpreg = 0x00U; \ 3683 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3684 /* Delay after an RCC peripheral clock enabling */ \ 3685 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 3686 UNUSED(tmpreg); \ 3687 } while(0U) 3688 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 3689 __IO uint32_t tmpreg = 0x00U; \ 3690 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3691 /* Delay after an RCC peripheral clock enabling */ \ 3692 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 3693 UNUSED(tmpreg); \ 3694 } while(0U) 3695 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 3696 __IO uint32_t tmpreg = 0x00U; \ 3697 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3698 /* Delay after an RCC peripheral clock enabling */ \ 3699 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 3700 UNUSED(tmpreg); \ 3701 } while(0U) 3702 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 3703 __IO uint32_t tmpreg = 0x00U; \ 3704 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3705 /* Delay after an RCC peripheral clock enabling */ \ 3706 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 3707 UNUSED(tmpreg); \ 3708 } while(0U) 3709 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 3710 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 3711 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 3712 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 3713 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 3714 /** 3715 * @} 3716 */ 3717 3718 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 3719 * @brief Get the enable or disable status of the APB1 peripheral clock. 3720 * @note After reset, the peripheral clock (used for registers read/write access) 3721 * is disabled and the application software has to enable this clock before 3722 * using it. 3723 * @{ 3724 */ 3725 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 3726 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 3727 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 3728 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 3729 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 3730 3731 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 3732 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 3733 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 3734 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 3735 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 3736 /** 3737 * @} 3738 */ 3739 3740 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 3741 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 3742 * @{ 3743 */ 3744 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 3745 __IO uint32_t tmpreg = 0x00U; \ 3746 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3747 /* Delay after an RCC peripheral clock enabling */ \ 3748 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 3749 UNUSED(tmpreg); \ 3750 } while(0U) 3751 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 3752 __IO uint32_t tmpreg = 0x00U; \ 3753 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3754 /* Delay after an RCC peripheral clock enabling */ \ 3755 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 3756 UNUSED(tmpreg); \ 3757 } while(0U) 3758 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 3759 __IO uint32_t tmpreg = 0x00U; \ 3760 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3761 /* Delay after an RCC peripheral clock enabling */ \ 3762 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 3763 UNUSED(tmpreg); \ 3764 } while(0U) 3765 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 3766 __IO uint32_t tmpreg = 0x00U; \ 3767 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3768 /* Delay after an RCC peripheral clock enabling */ \ 3769 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 3770 UNUSED(tmpreg); \ 3771 } while(0U) 3772 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 3773 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 3774 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 3775 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 3776 /** 3777 * @} 3778 */ 3779 3780 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 3781 * @brief Get the enable or disable status of the APB2 peripheral clock. 3782 * @note After reset, the peripheral clock (used for registers read/write access) 3783 * is disabled and the application software has to enable this clock before 3784 * using it. 3785 * @{ 3786 */ 3787 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 3788 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 3789 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 3790 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 3791 3792 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 3793 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 3794 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 3795 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 3796 /** 3797 * @} 3798 */ 3799 3800 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 3801 * @brief Force or release AHB1 peripheral reset. 3802 * @{ 3803 */ 3804 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) 3805 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 3806 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 3807 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 3808 3809 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 3810 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 3811 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 3812 /** 3813 * @} 3814 */ 3815 3816 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 3817 * @brief Force or release AHB2 peripheral reset. 3818 * @{ 3819 */ 3820 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) 3821 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 3822 3823 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 3824 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 3825 /** 3826 * @} 3827 */ 3828 3829 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 3830 * @brief Force or release AHB3 peripheral reset. 3831 * @{ 3832 */ 3833 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 3834 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 3835 /** 3836 * @} 3837 */ 3838 3839 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 3840 * @brief Force or release APB1 peripheral reset. 3841 * @{ 3842 */ 3843 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) 3844 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 3845 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 3846 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 3847 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 3848 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 3849 3850 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 3851 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 3852 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 3853 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 3854 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 3855 /** 3856 * @} 3857 */ 3858 3859 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 3860 * @brief Force or release APB2 peripheral reset. 3861 * @{ 3862 */ 3863 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00177931U) 3864 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 3865 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 3866 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 3867 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 3868 3869 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 3870 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 3871 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 3872 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 3873 /** 3874 * @} 3875 */ 3876 3877 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 3878 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3879 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3880 * power consumption. 3881 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3882 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3883 * @{ 3884 */ 3885 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 3886 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 3887 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 3888 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 3889 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 3890 3891 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 3892 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 3893 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 3894 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 3895 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 3896 /** 3897 * @} 3898 */ 3899 3900 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 3901 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3902 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3903 * power consumption. 3904 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 3905 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3906 * @{ 3907 */ 3908 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 3909 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 3910 /** 3911 * @} 3912 */ 3913 3914 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 3915 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3916 * @{ 3917 */ 3918 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 3919 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 3920 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 3921 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 3922 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 3923 3924 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 3925 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 3926 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 3927 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 3928 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 3929 /** 3930 * @} 3931 */ 3932 3933 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 3934 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3935 * @{ 3936 */ 3937 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 3938 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 3939 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 3940 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 3941 3942 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 3943 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 3944 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 3945 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 3946 /** 3947 * @} 3948 */ 3949 #endif /* STM32F411xE */ 3950 /*----------------------------------------------------------------------------*/ 3951 3952 /*---------------------------------- STM32F446xx -----------------------------*/ 3953 #if defined(STM32F446xx) 3954 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 3955 * @brief Enables or disables the AHB1 peripheral clock. 3956 * @note After reset, the peripheral clock (used for registers read/write access) 3957 * is disabled and the application software has to enable this clock before 3958 * using it. 3959 * @{ 3960 */ 3961 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 3962 __IO uint32_t tmpreg = 0x00U; \ 3963 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 3964 /* Delay after an RCC peripheral clock enabling */ \ 3965 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 3966 UNUSED(tmpreg); \ 3967 } while(0U) 3968 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 3969 __IO uint32_t tmpreg = 0x00U; \ 3970 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3971 /* Delay after an RCC peripheral clock enabling */ \ 3972 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 3973 UNUSED(tmpreg); \ 3974 } while(0U) 3975 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 3976 __IO uint32_t tmpreg = 0x00U; \ 3977 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3978 /* Delay after an RCC peripheral clock enabling */ \ 3979 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 3980 UNUSED(tmpreg); \ 3981 } while(0U) 3982 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 3983 __IO uint32_t tmpreg = 0x00U; \ 3984 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3985 /* Delay after an RCC peripheral clock enabling */ \ 3986 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 3987 UNUSED(tmpreg); \ 3988 } while(0U) 3989 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 3990 __IO uint32_t tmpreg = 0x00U; \ 3991 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3992 /* Delay after an RCC peripheral clock enabling */ \ 3993 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 3994 UNUSED(tmpreg); \ 3995 } while(0U) 3996 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 3997 __IO uint32_t tmpreg = 0x00U; \ 3998 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 3999 /* Delay after an RCC peripheral clock enabling */ \ 4000 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 4001 UNUSED(tmpreg); \ 4002 } while(0U) 4003 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 4004 __IO uint32_t tmpreg = 0x00U; \ 4005 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4006 /* Delay after an RCC peripheral clock enabling */ \ 4007 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4008 UNUSED(tmpreg); \ 4009 } while(0U) 4010 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 4011 __IO uint32_t tmpreg = 0x00U; \ 4012 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 4013 /* Delay after an RCC peripheral clock enabling */ \ 4014 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 4015 UNUSED(tmpreg); \ 4016 } while(0U) 4017 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 4018 __IO uint32_t tmpreg = 0x00U; \ 4019 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 4020 /* Delay after an RCC peripheral clock enabling */ \ 4021 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 4022 UNUSED(tmpreg); \ 4023 } while(0U) 4024 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 4025 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 4026 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 4027 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 4028 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 4029 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 4030 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 4031 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 4032 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 4033 /** 4034 * @} 4035 */ 4036 4037 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 4038 * @brief Get the enable or disable status of the AHB1 peripheral clock. 4039 * @note After reset, the peripheral clock (used for registers read/write access) 4040 * is disabled and the application software has to enable this clock before 4041 * using it. 4042 * @{ 4043 */ 4044 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 4045 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 4046 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 4047 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 4048 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 4049 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 4050 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 4051 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) 4052 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 4053 4054 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 4055 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 4056 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 4057 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 4058 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 4059 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 4060 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 4061 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 4062 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 4063 /** 4064 * @} 4065 */ 4066 4067 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 4068 * @brief Enable or disable the AHB2 peripheral clock. 4069 * @note After reset, the peripheral clock (used for registers read/write access) 4070 * is disabled and the application software has to enable this clock before 4071 * using it. 4072 * @{ 4073 */ 4074 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 4075 __IO uint32_t tmpreg = 0x00U; \ 4076 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 4077 /* Delay after an RCC peripheral clock enabling */ \ 4078 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 4079 UNUSED(tmpreg); \ 4080 } while(0U) 4081 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 4082 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 4083 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 4084 }while(0U) 4085 4086 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 4087 4088 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 4089 __IO uint32_t tmpreg = 0x00U; \ 4090 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4091 /* Delay after an RCC peripheral clock enabling */ \ 4092 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4093 UNUSED(tmpreg); \ 4094 } while(0U) 4095 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 4096 /** 4097 * @} 4098 */ 4099 4100 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 4101 * @brief Get the enable or disable status of the AHB2 peripheral clock. 4102 * @note After reset, the peripheral clock (used for registers read/write access) 4103 * is disabled and the application software has to enable this clock before 4104 * using it. 4105 * @{ 4106 */ 4107 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 4108 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 4109 4110 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 4111 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 4112 4113 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 4114 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 4115 /** 4116 * @} 4117 */ 4118 4119 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 4120 * @brief Enables or disables the AHB3 peripheral clock. 4121 * @note After reset, the peripheral clock (used for registers read/write access) 4122 * is disabled and the application software has to enable this clock before 4123 * using it. 4124 * @{ 4125 */ 4126 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 4127 __IO uint32_t tmpreg = 0x00U; \ 4128 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 4129 /* Delay after an RCC peripheral clock enabling */ \ 4130 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 4131 UNUSED(tmpreg); \ 4132 } while(0U) 4133 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 4134 __IO uint32_t tmpreg = 0x00U; \ 4135 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4136 /* Delay after an RCC peripheral clock enabling */ \ 4137 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4138 UNUSED(tmpreg); \ 4139 } while(0U) 4140 4141 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 4142 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 4143 /** 4144 * @} 4145 */ 4146 4147 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 4148 * @brief Get the enable or disable status of the AHB3 peripheral clock. 4149 * @note After reset, the peripheral clock (used for registers read/write access) 4150 * is disabled and the application software has to enable this clock before 4151 * using it. 4152 * @{ 4153 */ 4154 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 4155 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 4156 4157 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 4158 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 4159 /** 4160 * @} 4161 */ 4162 4163 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 4164 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 4165 * @note After reset, the peripheral clock (used for registers read/write access) 4166 * is disabled and the application software has to enable this clock before 4167 * using it. 4168 * @{ 4169 */ 4170 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 4171 __IO uint32_t tmpreg = 0x00U; \ 4172 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4173 /* Delay after an RCC peripheral clock enabling */ \ 4174 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4175 UNUSED(tmpreg); \ 4176 } while(0U) 4177 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 4178 __IO uint32_t tmpreg = 0x00U; \ 4179 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4180 /* Delay after an RCC peripheral clock enabling */ \ 4181 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4182 UNUSED(tmpreg); \ 4183 } while(0U) 4184 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 4185 __IO uint32_t tmpreg = 0x00U; \ 4186 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4187 /* Delay after an RCC peripheral clock enabling */ \ 4188 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4189 UNUSED(tmpreg); \ 4190 } while(0U) 4191 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 4192 __IO uint32_t tmpreg = 0x00U; \ 4193 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4194 /* Delay after an RCC peripheral clock enabling */ \ 4195 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4196 UNUSED(tmpreg); \ 4197 } while(0U) 4198 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 4199 __IO uint32_t tmpreg = 0x00U; \ 4200 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4201 /* Delay after an RCC peripheral clock enabling */ \ 4202 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 4203 UNUSED(tmpreg); \ 4204 } while(0U) 4205 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 4206 __IO uint32_t tmpreg = 0x00U; \ 4207 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 4208 /* Delay after an RCC peripheral clock enabling */ \ 4209 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 4210 UNUSED(tmpreg); \ 4211 } while(0U) 4212 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 4213 __IO uint32_t tmpreg = 0x00U; \ 4214 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4215 /* Delay after an RCC peripheral clock enabling */ \ 4216 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 4217 UNUSED(tmpreg); \ 4218 } while(0U) 4219 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 4220 __IO uint32_t tmpreg = 0x00U; \ 4221 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4222 /* Delay after an RCC peripheral clock enabling */ \ 4223 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 4224 UNUSED(tmpreg); \ 4225 } while(0U) 4226 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 4227 __IO uint32_t tmpreg = 0x00U; \ 4228 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4229 /* Delay after an RCC peripheral clock enabling */ \ 4230 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 4231 UNUSED(tmpreg); \ 4232 } while(0U) 4233 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 4234 __IO uint32_t tmpreg = 0x00U; \ 4235 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 4236 /* Delay after an RCC peripheral clock enabling */ \ 4237 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 4238 UNUSED(tmpreg); \ 4239 } while(0U) 4240 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 4241 __IO uint32_t tmpreg = 0x00U; \ 4242 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 4243 /* Delay after an RCC peripheral clock enabling */ \ 4244 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 4245 UNUSED(tmpreg); \ 4246 } while(0U) 4247 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 4248 __IO uint32_t tmpreg = 0x00U; \ 4249 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 4250 /* Delay after an RCC peripheral clock enabling */ \ 4251 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 4252 UNUSED(tmpreg); \ 4253 } while(0U) 4254 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 4255 __IO uint32_t tmpreg = 0x00U; \ 4256 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 4257 /* Delay after an RCC peripheral clock enabling */ \ 4258 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 4259 UNUSED(tmpreg); \ 4260 } while(0U) 4261 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 4262 __IO uint32_t tmpreg = 0x00U; \ 4263 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 4264 /* Delay after an RCC peripheral clock enabling */ \ 4265 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 4266 UNUSED(tmpreg); \ 4267 } while(0U) 4268 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 4269 __IO uint32_t tmpreg = 0x00U; \ 4270 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 4271 /* Delay after an RCC peripheral clock enabling */ \ 4272 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 4273 UNUSED(tmpreg); \ 4274 } while(0U) 4275 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 4276 __IO uint32_t tmpreg = 0x00U; \ 4277 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 4278 /* Delay after an RCC peripheral clock enabling */ \ 4279 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 4280 UNUSED(tmpreg); \ 4281 } while(0U) 4282 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 4283 __IO uint32_t tmpreg = 0x00U; \ 4284 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 4285 /* Delay after an RCC peripheral clock enabling */ \ 4286 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 4287 UNUSED(tmpreg); \ 4288 } while(0U) 4289 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 4290 __IO uint32_t tmpreg = 0x00U; \ 4291 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 4292 /* Delay after an RCC peripheral clock enabling */ \ 4293 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 4294 UNUSED(tmpreg); \ 4295 } while(0U) 4296 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 4297 __IO uint32_t tmpreg = 0x00U; \ 4298 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 4299 /* Delay after an RCC peripheral clock enabling */ \ 4300 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 4301 UNUSED(tmpreg); \ 4302 } while(0U) 4303 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 4304 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 4305 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 4306 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 4307 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 4308 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 4309 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 4310 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 4311 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 4312 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 4313 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) 4314 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 4315 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 4316 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 4317 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 4318 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 4319 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 4320 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 4321 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 4322 /** 4323 * @} 4324 */ 4325 4326 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 4327 * @brief Get the enable or disable status of the APB1 peripheral clock. 4328 * @note After reset, the peripheral clock (used for registers read/write access) 4329 * is disabled and the application software has to enable this clock before 4330 * using it. 4331 * @{ 4332 */ 4333 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 4334 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 4335 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 4336 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 4337 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 4338 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 4339 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 4340 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 4341 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 4342 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 4343 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) 4344 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 4345 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 4346 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 4347 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 4348 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 4349 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 4350 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 4351 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 4352 4353 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 4354 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 4355 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 4356 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 4357 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 4358 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 4359 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 4360 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 4361 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 4362 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 4363 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) 4364 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 4365 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 4366 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 4367 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 4368 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 4369 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 4370 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 4371 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 4372 /** 4373 * @} 4374 */ 4375 4376 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 4377 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 4378 * @note After reset, the peripheral clock (used for registers read/write access) 4379 * is disabled and the application software has to enable this clock before 4380 * using it. 4381 * @{ 4382 */ 4383 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 4384 __IO uint32_t tmpreg = 0x00U; \ 4385 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4386 /* Delay after an RCC peripheral clock enabling */ \ 4387 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 4388 UNUSED(tmpreg); \ 4389 } while(0U) 4390 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 4391 __IO uint32_t tmpreg = 0x00U; \ 4392 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 4393 /* Delay after an RCC peripheral clock enabling */ \ 4394 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 4395 UNUSED(tmpreg); \ 4396 } while(0U) 4397 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 4398 __IO uint32_t tmpreg = 0x00U; \ 4399 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 4400 /* Delay after an RCC peripheral clock enabling */ \ 4401 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 4402 UNUSED(tmpreg); \ 4403 } while(0U) 4404 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 4405 __IO uint32_t tmpreg = 0x00U; \ 4406 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4407 /* Delay after an RCC peripheral clock enabling */ \ 4408 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 4409 UNUSED(tmpreg); \ 4410 } while(0U) 4411 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 4412 __IO uint32_t tmpreg = 0x00U; \ 4413 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4414 /* Delay after an RCC peripheral clock enabling */ \ 4415 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 4416 UNUSED(tmpreg); \ 4417 } while(0U) 4418 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 4419 __IO uint32_t tmpreg = 0x00U; \ 4420 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 4421 /* Delay after an RCC peripheral clock enabling */ \ 4422 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 4423 UNUSED(tmpreg); \ 4424 } while(0U) 4425 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 4426 __IO uint32_t tmpreg = 0x00U; \ 4427 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4428 /* Delay after an RCC peripheral clock enabling */ \ 4429 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 4430 UNUSED(tmpreg); \ 4431 } while(0U) 4432 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 4433 __IO uint32_t tmpreg = 0x00U; \ 4434 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 4435 /* Delay after an RCC peripheral clock enabling */ \ 4436 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 4437 UNUSED(tmpreg); \ 4438 } while(0U) 4439 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 4440 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 4441 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 4442 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 4443 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 4444 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 4445 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 4446 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) 4447 /** 4448 * @} 4449 */ 4450 4451 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 4452 * @brief Get the enable or disable status of the APB2 peripheral clock. 4453 * @note After reset, the peripheral clock (used for registers read/write access) 4454 * is disabled and the application software has to enable this clock before 4455 * using it. 4456 * @{ 4457 */ 4458 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 4459 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 4460 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 4461 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 4462 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 4463 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 4464 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 4465 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) 4466 4467 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 4468 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 4469 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 4470 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 4471 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 4472 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 4473 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 4474 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 4475 /** 4476 * @} 4477 */ 4478 4479 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 4480 * @brief Force or release AHB1 peripheral reset. 4481 * @{ 4482 */ 4483 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206010FFU) 4484 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 4485 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 4486 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 4487 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 4488 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 4489 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 4490 4491 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 4492 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 4493 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 4494 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 4495 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 4496 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 4497 /** 4498 * @} 4499 */ 4500 4501 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 4502 * @brief Force or release AHB2 peripheral reset. 4503 * @{ 4504 */ 4505 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000081U) 4506 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 4507 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 4508 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 4509 4510 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 4511 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 4512 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 4513 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 4514 /** 4515 * @} 4516 */ 4517 4518 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 4519 * @brief Force or release AHB3 peripheral reset. 4520 * @{ 4521 */ 4522 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) 4523 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 4524 4525 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 4526 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 4527 4528 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 4529 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 4530 /** 4531 * @} 4532 */ 4533 4534 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 4535 * @brief Force or release APB1 peripheral reset. 4536 * @{ 4537 */ 4538 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x3FFFC9FFU) 4539 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 4540 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 4541 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 4542 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 4543 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 4544 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) 4545 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 4546 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 4547 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 4548 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 4549 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 4550 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 4551 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 4552 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 4553 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 4554 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 4555 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 4556 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 4557 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 4558 4559 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 4560 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 4561 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 4562 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 4563 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 4564 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 4565 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 4566 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 4567 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 4568 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 4569 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) 4570 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 4571 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 4572 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 4573 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 4574 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 4575 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 4576 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 4577 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 4578 /** 4579 * @} 4580 */ 4581 4582 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 4583 * @brief Force or release APB2 peripheral reset. 4584 * @{ 4585 */ 4586 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00C77933U) 4587 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 4588 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 4589 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) 4590 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 4591 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 4592 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 4593 4594 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 4595 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 4596 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 4597 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 4598 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 4599 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 4600 /** 4601 * @} 4602 */ 4603 4604 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 4605 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 4606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4607 * power consumption. 4608 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4609 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4610 * @{ 4611 */ 4612 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 4613 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 4614 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 4615 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 4616 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 4617 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 4618 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 4619 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 4620 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 4621 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 4622 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 4623 4624 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 4625 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 4626 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 4627 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 4628 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 4629 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 4630 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 4631 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 4632 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 4633 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 4634 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 4635 /** 4636 * @} 4637 */ 4638 4639 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 4640 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 4641 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4642 * power consumption. 4643 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 4644 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4645 * @{ 4646 */ 4647 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 4648 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 4649 4650 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 4651 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 4652 4653 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 4654 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 4655 /** 4656 * @} 4657 */ 4658 4659 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 4660 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 4661 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4662 * power consumption. 4663 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4664 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4665 * @{ 4666 */ 4667 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 4668 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 4669 4670 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 4671 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 4672 /** 4673 * @} 4674 */ 4675 4676 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 4677 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 4678 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4679 * power consumption. 4680 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4681 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4682 * @{ 4683 */ 4684 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 4685 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 4686 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 4687 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 4688 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 4689 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) 4690 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 4691 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 4692 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 4693 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 4694 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 4695 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 4696 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) 4697 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 4698 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 4699 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 4700 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 4701 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 4702 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 4703 4704 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 4705 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 4706 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 4707 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 4708 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 4709 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 4710 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 4711 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 4712 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 4713 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 4714 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) 4715 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 4716 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 4717 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 4718 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 4719 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 4720 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 4721 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) 4722 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 4723 /** 4724 * @} 4725 */ 4726 4727 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 4728 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 4729 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 4730 * power consumption. 4731 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4732 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4733 * @{ 4734 */ 4735 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 4736 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 4737 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 4738 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 4739 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) 4740 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 4741 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 4742 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 4743 4744 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 4745 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 4746 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 4747 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 4748 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 4749 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 4750 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 4751 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) 4752 /** 4753 * @} 4754 */ 4755 4756 #endif /* STM32F446xx */ 4757 /*----------------------------------------------------------------------------*/ 4758 4759 /*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ 4760 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 4761 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 4762 * @brief Enables or disables the AHB1 peripheral clock. 4763 * @note After reset, the peripheral clock (used for registers read/write access) 4764 * is disabled and the application software has to enable this clock before 4765 * using it. 4766 * @{ 4767 */ 4768 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4769 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 4770 __IO uint32_t tmpreg = 0x00U; \ 4771 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 4772 /* Delay after an RCC peripheral clock enabling */ \ 4773 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 4774 UNUSED(tmpreg); \ 4775 } while(0U) 4776 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4777 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4778 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 4779 __IO uint32_t tmpreg = 0x00U; \ 4780 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 4781 /* Delay after an RCC peripheral clock enabling */ \ 4782 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 4783 UNUSED(tmpreg); \ 4784 } while(0U) 4785 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4786 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4787 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 4788 __IO uint32_t tmpreg = 0x00U; \ 4789 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 4790 /* Delay after an RCC peripheral clock enabling */ \ 4791 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 4792 UNUSED(tmpreg); \ 4793 } while(0U) 4794 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 4795 __IO uint32_t tmpreg = 0x00U; \ 4796 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4797 /* Delay after an RCC peripheral clock enabling */ \ 4798 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 4799 UNUSED(tmpreg); \ 4800 } while(0U) 4801 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4802 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 4803 __IO uint32_t tmpreg = 0x00U; \ 4804 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 4805 /* Delay after an RCC peripheral clock enabling */ \ 4806 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 4807 UNUSED(tmpreg); \ 4808 } while(0U) 4809 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4810 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 4811 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4812 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4813 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 4814 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4815 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4816 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 4817 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 4818 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4819 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 4820 /** 4821 * @} 4822 */ 4823 4824 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 4825 * @brief Get the enable or disable status of the AHB1 peripheral clock. 4826 * @note After reset, the peripheral clock (used for registers read/write access) 4827 * is disabled and the application software has to enable this clock before 4828 * using it. 4829 * @{ 4830 */ 4831 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4832 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 4833 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4834 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4835 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 4836 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4837 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4838 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 4839 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 4840 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4841 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 4842 4843 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4844 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 4845 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4846 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4847 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 4848 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 4849 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 4850 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 4851 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 4852 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 4853 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 4854 /** 4855 * @} 4856 */ 4857 4858 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 4859 * @brief Enable or disable the AHB2 peripheral clock. 4860 * @note After reset, the peripheral clock (used for registers read/write access) 4861 * is disabled and the application software has to enable this clock before 4862 * using it. 4863 * @{ 4864 */ 4865 #if defined(STM32F423xx) 4866 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 4867 __IO uint32_t tmpreg = 0x00U; \ 4868 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 4869 /* Delay after an RCC peripheral clock enabling */ \ 4870 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 4871 UNUSED(tmpreg); \ 4872 } while(0U) 4873 4874 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) 4875 #endif /* STM32F423xx */ 4876 4877 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 4878 __IO uint32_t tmpreg = 0x00U; \ 4879 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4880 /* Delay after an RCC peripheral clock enabling */ \ 4881 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 4882 UNUSED(tmpreg); \ 4883 } while(0U) 4884 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 4885 4886 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 4887 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 4888 }while(0U) 4889 4890 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 4891 /** 4892 * @} 4893 */ 4894 4895 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 4896 * @brief Get the enable or disable status of the AHB2 peripheral clock. 4897 * @note After reset, the peripheral clock (used for registers read/write access) 4898 * is disabled and the application software has to enable this clock before 4899 * using it. 4900 * @{ 4901 */ 4902 #if defined(STM32F423xx) 4903 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) 4904 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) 4905 #endif /* STM32F423xx */ 4906 4907 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 4908 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 4909 4910 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 4911 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 4912 /** 4913 * @} 4914 */ 4915 4916 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 4917 * @brief Enables or disables the AHB3 peripheral clock. 4918 * @note After reset, the peripheral clock (used for registers read/write access) 4919 * is disabled and the application software has to enable this clock before 4920 * using it. 4921 * @{ 4922 */ 4923 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 4924 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 4925 __IO uint32_t tmpreg = 0x00U; \ 4926 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 4927 /* Delay after an RCC peripheral clock enabling */ \ 4928 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 4929 UNUSED(tmpreg); \ 4930 } while(0U) 4931 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 4932 __IO uint32_t tmpreg = 0x00U; \ 4933 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4934 /* Delay after an RCC peripheral clock enabling */ \ 4935 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 4936 UNUSED(tmpreg); \ 4937 } while(0U) 4938 4939 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 4940 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 4941 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 4942 /** 4943 * @} 4944 */ 4945 4946 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 4947 * @brief Get the enable or disable status of the AHB3 peripheral clock. 4948 * @note After reset, the peripheral clock (used for registers read/write access) 4949 * is disabled and the application software has to enable this clock before 4950 * using it. 4951 * @{ 4952 */ 4953 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 4954 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 4955 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 4956 4957 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 4958 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 4959 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 4960 4961 /** 4962 * @} 4963 */ 4964 4965 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 4966 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 4967 * @note After reset, the peripheral clock (used for registers read/write access) 4968 * is disabled and the application software has to enable this clock before 4969 * using it. 4970 * @{ 4971 */ 4972 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 4973 __IO uint32_t tmpreg = 0x00U; \ 4974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4975 /* Delay after an RCC peripheral clock enabling */ \ 4976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 4977 UNUSED(tmpreg); \ 4978 } while(0U) 4979 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 4980 __IO uint32_t tmpreg = 0x00U; \ 4981 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4982 /* Delay after an RCC peripheral clock enabling */ \ 4983 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 4984 UNUSED(tmpreg); \ 4985 } while(0U) 4986 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 4987 __IO uint32_t tmpreg = 0x00U; \ 4988 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4989 /* Delay after an RCC peripheral clock enabling */ \ 4990 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 4991 UNUSED(tmpreg); \ 4992 } while(0U) 4993 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 4994 __IO uint32_t tmpreg = 0x00U; \ 4995 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4996 /* Delay after an RCC peripheral clock enabling */ \ 4997 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 4998 UNUSED(tmpreg); \ 4999 } while(0U) 5000 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 5001 __IO uint32_t tmpreg = 0x00U; \ 5002 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 5003 /* Delay after an RCC peripheral clock enabling */ \ 5004 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 5005 UNUSED(tmpreg); \ 5006 } while(0U) 5007 #if defined(STM32F413xx) || defined(STM32F423xx) 5008 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 5009 __IO uint32_t tmpreg = 0x00U; \ 5010 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 5011 /* Delay after an RCC peripheral clock enabling */ \ 5012 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 5013 UNUSED(tmpreg); \ 5014 } while(0U) 5015 #endif /* STM32F413xx || STM32F423xx */ 5016 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 5017 __IO uint32_t tmpreg = 0x00U; \ 5018 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 5019 /* Delay after an RCC peripheral clock enabling */ \ 5020 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 5021 UNUSED(tmpreg); \ 5022 } while(0U) 5023 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 5024 __IO uint32_t tmpreg = 0x00U; \ 5025 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 5026 /* Delay after an RCC peripheral clock enabling */ \ 5027 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 5028 UNUSED(tmpreg); \ 5029 } while(0U) 5030 5031 #if defined(STM32F413xx) || defined(STM32F423xx) 5032 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 5033 __IO uint32_t tmpreg = 0x00U; \ 5034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 5035 /* Delay after an RCC peripheral clock enabling */ \ 5036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 5037 UNUSED(tmpreg); \ 5038 } while(0U) 5039 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 5040 __IO uint32_t tmpreg = 0x00U; \ 5041 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 5042 /* Delay after an RCC peripheral clock enabling */ \ 5043 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 5044 UNUSED(tmpreg); \ 5045 } while(0U) 5046 #endif /* STM32F413xx || STM32F423xx */ 5047 5048 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 5049 __IO uint32_t tmpreg = 0x00U; \ 5050 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 5051 /* Delay after an RCC peripheral clock enabling */ \ 5052 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 5053 UNUSED(tmpreg); \ 5054 } while(0U) 5055 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 5056 __IO uint32_t tmpreg = 0x00U; \ 5057 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 5058 /* Delay after an RCC peripheral clock enabling */ \ 5059 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 5060 UNUSED(tmpreg); \ 5061 } while(0U) 5062 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 5063 __IO uint32_t tmpreg = 0x00U; \ 5064 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 5065 /* Delay after an RCC peripheral clock enabling */ \ 5066 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 5067 UNUSED(tmpreg); \ 5068 } while(0U) 5069 #if defined(STM32F413xx) || defined(STM32F423xx) 5070 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ 5071 __IO uint32_t tmpreg = 0x00U; \ 5072 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 5073 /* Delay after an RCC peripheral clock enabling */ \ 5074 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 5075 UNUSED(tmpreg); \ 5076 } while(0U) 5077 #endif /* STM32F413xx || STM32F423xx */ 5078 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 5079 __IO uint32_t tmpreg = 0x00U; \ 5080 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 5081 /* Delay after an RCC peripheral clock enabling */ \ 5082 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 5083 UNUSED(tmpreg); \ 5084 } while(0U) 5085 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 5086 __IO uint32_t tmpreg = 0x00U; \ 5087 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 5088 /* Delay after an RCC peripheral clock enabling */ \ 5089 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 5090 UNUSED(tmpreg); \ 5091 } while(0U) 5092 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 5093 __IO uint32_t tmpreg = 0x00U; \ 5094 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 5095 /* Delay after an RCC peripheral clock enabling */ \ 5096 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 5097 UNUSED(tmpreg); \ 5098 } while(0U) 5099 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 5100 __IO uint32_t tmpreg = 0x00U; \ 5101 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 5102 /* Delay after an RCC peripheral clock enabling */ \ 5103 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 5104 UNUSED(tmpreg); \ 5105 } while(0U) 5106 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 5107 __IO uint32_t tmpreg = 0x00U; \ 5108 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 5109 /* Delay after an RCC peripheral clock enabling */ \ 5110 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 5111 UNUSED(tmpreg); \ 5112 } while(0U) 5113 #if defined(STM32F413xx) || defined(STM32F423xx) 5114 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 5115 __IO uint32_t tmpreg = 0x00U; \ 5116 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 5117 /* Delay after an RCC peripheral clock enabling */ \ 5118 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 5119 UNUSED(tmpreg); \ 5120 } while(0U) 5121 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 5122 __IO uint32_t tmpreg = 0x00U; \ 5123 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 5124 /* Delay after an RCC peripheral clock enabling */ \ 5125 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 5126 UNUSED(tmpreg); \ 5127 } while(0U) 5128 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 5129 __IO uint32_t tmpreg = 0x00U; \ 5130 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 5131 /* Delay after an RCC peripheral clock enabling */ \ 5132 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 5133 UNUSED(tmpreg); \ 5134 } while(0U) 5135 #endif /* STM32F413xx || STM32F423xx */ 5136 5137 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 5138 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 5139 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 5140 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 5141 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 5142 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 5143 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 5144 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 5145 #if defined(STM32F413xx) || defined(STM32F423xx) 5146 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 5147 #endif /* STM32F413xx || STM32F423xx */ 5148 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 5149 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 5150 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 5151 #if defined(STM32F413xx) || defined(STM32F423xx) 5152 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 5153 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 5154 #endif /* STM32F413xx || STM32F423xx */ 5155 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 5156 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 5157 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 5158 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 5159 #if defined(STM32F413xx) || defined(STM32F423xx) 5160 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) 5161 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 5162 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 5163 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 5164 #endif /* STM32F413xx || STM32F423xx */ 5165 5166 /** 5167 * @} 5168 */ 5169 5170 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 5171 * @brief Get the enable or disable status of the APB1 peripheral clock. 5172 * @note After reset, the peripheral clock (used for registers read/write access) 5173 * is disabled and the application software has to enable this clock before 5174 * using it. 5175 * @{ 5176 */ 5177 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 5178 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 5179 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 5180 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 5181 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 5182 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 5183 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 5184 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 5185 #if defined(STM32F413xx) || defined(STM32F423xx) 5186 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 5187 #endif /* STM32F413xx || STM32F423xx */ 5188 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 5189 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 5190 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 5191 #if defined(STM32F413xx) || defined(STM32F423xx) 5192 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 5193 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 5194 #endif /* STM32F413xx || STM32F423xx */ 5195 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 5196 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 5197 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) 5198 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 5199 #if defined(STM32F413xx) || defined(STM32F423xx) 5200 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) 5201 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 5202 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 5203 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 5204 #endif /* STM32F413xx || STM32F423xx */ 5205 5206 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 5207 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 5208 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 5209 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 5210 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 5211 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 5212 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 5213 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 5214 #if defined(STM32F413xx) || defined(STM32F423xx) 5215 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 5216 #endif /* STM32F413xx || STM32F423xx */ 5217 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 5218 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 5219 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 5220 #if defined(STM32F413xx) || defined(STM32F423xx) 5221 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 5222 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 5223 #endif /* STM32F413xx || STM32F423xx */ 5224 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 5225 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 5226 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 5227 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 5228 #if defined(STM32F413xx) || defined(STM32F423xx) 5229 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) 5230 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 5231 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 5232 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 5233 #endif /* STM32F413xx || STM32F423xx */ 5234 /** 5235 * @} 5236 */ 5237 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 5238 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 5239 * @note After reset, the peripheral clock (used for registers read/write access) 5240 * is disabled and the application software has to enable this clock before 5241 * using it. 5242 * @{ 5243 */ 5244 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 5245 __IO uint32_t tmpreg = 0x00U; \ 5246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 5247 /* Delay after an RCC peripheral clock enabling */ \ 5248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 5249 UNUSED(tmpreg); \ 5250 } while(0U) 5251 #if defined(STM32F413xx) || defined(STM32F423xx) 5252 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 5253 __IO uint32_t tmpreg = 0x00U; \ 5254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 5255 /* Delay after an RCC peripheral clock enabling */ \ 5256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 5257 UNUSED(tmpreg); \ 5258 } while(0U) 5259 #define __HAL_RCC_UART10_CLK_ENABLE() do { \ 5260 __IO uint32_t tmpreg = 0x00U; \ 5261 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 5262 /* Delay after an RCC peripheral clock enabling */ \ 5263 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 5264 UNUSED(tmpreg); \ 5265 } while(0U) 5266 #endif /* STM32F413xx || STM32F423xx */ 5267 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 5268 __IO uint32_t tmpreg = 0x00U; \ 5269 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 5270 /* Delay after an RCC peripheral clock enabling */ \ 5271 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 5272 UNUSED(tmpreg); \ 5273 } while(0U) 5274 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 5275 __IO uint32_t tmpreg = 0x00U; \ 5276 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 5277 /* Delay after an RCC peripheral clock enabling */ \ 5278 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 5279 UNUSED(tmpreg); \ 5280 } while(0U) 5281 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 5282 __IO uint32_t tmpreg = 0x00U; \ 5283 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 5284 /* Delay after an RCC peripheral clock enabling */ \ 5285 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 5286 UNUSED(tmpreg); \ 5287 } while(0U) 5288 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 5289 __IO uint32_t tmpreg = 0x00U; \ 5290 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 5291 /* Delay after an RCC peripheral clock enabling */ \ 5292 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 5293 UNUSED(tmpreg); \ 5294 } while(0U) 5295 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 5296 __IO uint32_t tmpreg = 0x00U; \ 5297 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 5298 /* Delay after an RCC peripheral clock enabling */ \ 5299 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 5300 UNUSED(tmpreg); \ 5301 } while(0U) 5302 #if defined(STM32F413xx) || defined(STM32F423xx) 5303 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 5304 __IO uint32_t tmpreg = 0x00U; \ 5305 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 5306 /* Delay after an RCC peripheral clock enabling */ \ 5307 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 5308 UNUSED(tmpreg); \ 5309 } while(0U) 5310 #endif /* STM32F413xx || STM32F423xx */ 5311 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 5312 __IO uint32_t tmpreg = 0x00U; \ 5313 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 5314 /* Delay after an RCC peripheral clock enabling */ \ 5315 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 5316 UNUSED(tmpreg); \ 5317 } while(0U) 5318 #if defined(STM32F413xx) || defined(STM32F423xx) 5319 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ 5320 __IO uint32_t tmpreg = 0x00U; \ 5321 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 5322 /* Delay after an RCC peripheral clock enabling */ \ 5323 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 5324 UNUSED(tmpreg); \ 5325 } while(0U) 5326 #endif /* STM32F413xx || STM32F423xx */ 5327 5328 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 5329 #if defined(STM32F413xx) || defined(STM32F423xx) 5330 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) 5331 #define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) 5332 #endif /* STM32F413xx || STM32F423xx */ 5333 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 5334 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 5335 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 5336 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 5337 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 5338 #if defined(STM32F413xx) || defined(STM32F423xx) 5339 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 5340 #endif /* STM32F413xx || STM32F423xx */ 5341 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) 5342 #if defined(STM32F413xx) || defined(STM32F423xx) 5343 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) 5344 #endif /* STM32F413xx || STM32F423xx */ 5345 /** 5346 * @} 5347 */ 5348 5349 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 5350 * @brief Get the enable or disable status of the APB2 peripheral clock. 5351 * @note After reset, the peripheral clock (used for registers read/write access) 5352 * is disabled and the application software has to enable this clock before 5353 * using it. 5354 * @{ 5355 */ 5356 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 5357 #if defined(STM32F413xx) || defined(STM32F423xx) 5358 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) 5359 #define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) 5360 #endif /* STM32F413xx || STM32F423xx */ 5361 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 5362 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 5363 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 5364 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 5365 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 5366 #if defined(STM32F413xx) || defined(STM32F423xx) 5367 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 5368 #endif /* STM32F413xx || STM32F423xx */ 5369 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) 5370 #if defined(STM32F413xx) || defined(STM32F423xx) 5371 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) 5372 #endif /* STM32F413xx || STM32F423xx */ 5373 5374 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 5375 #if defined(STM32F413xx) || defined(STM32F423xx) 5376 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 5377 #define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) 5378 #endif /* STM32F413xx || STM32F423xx */ 5379 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 5380 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 5381 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 5382 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 5383 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 5384 #if defined(STM32F413xx) || defined(STM32F423xx) 5385 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 5386 #endif /* STM32F413xx || STM32F423xx */ 5387 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) 5388 #if defined(STM32F413xx) || defined(STM32F423xx) 5389 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) 5390 #endif /* STM32F413xx || STM32F423xx */ 5391 /** 5392 * @} 5393 */ 5394 5395 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 5396 * @brief Force or release AHB1 peripheral reset. 5397 * @{ 5398 */ 5399 #if defined (STM32F412Zx) || defined(STM32F413xx) || defined (STM32F423xx) 5400 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x006010FFU) 5401 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 5402 #if defined (STM32F412Cx) 5403 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x00601087U) 5404 #endif /* STM32F412Cx */ 5405 #if defined (STM32F412Vx) 5406 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) 5407 #endif /* STM32F412Vx */ 5408 #if defined (STM32F412Rx) 5409 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060108FU) 5410 #endif /* STM32F412Rx */ 5411 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5412 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 5413 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5414 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5415 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 5416 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5417 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5418 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 5419 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 5420 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 5421 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 5422 5423 #if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5424 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 5425 #endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5426 #if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5427 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 5428 #endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 5429 #if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 5430 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 5431 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 5432 #endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ 5433 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 5434 /** 5435 * @} 5436 */ 5437 5438 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 5439 * @brief Force or release AHB2 peripheral reset. 5440 * @{ 5441 */ 5442 #if defined(STM32F423xx) 5443 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000D0U) 5444 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) 5445 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) 5446 #else 5447 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C0U) 5448 #endif /* STM32F423xx */ 5449 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 5450 5451 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 5452 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 5453 5454 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 5455 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 5456 /** 5457 * @} 5458 */ 5459 5460 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 5461 * @brief Force or release AHB3 peripheral reset. 5462 * @{ 5463 */ 5464 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 5465 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) 5466 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 5467 5468 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 5469 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 5470 5471 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 5472 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 5473 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 5474 #if defined(STM32F412Cx) 5475 #define __HAL_RCC_AHB3_FORCE_RESET() 5476 #define __HAL_RCC_AHB3_RELEASE_RESET() 5477 5478 #define __HAL_RCC_FSMC_FORCE_RESET() 5479 #define __HAL_RCC_QSPI_FORCE_RESET() 5480 5481 #define __HAL_RCC_FSMC_RELEASE_RESET() 5482 #define __HAL_RCC_QSPI_RELEASE_RESET() 5483 #endif /* STM32F412Cx */ 5484 /** 5485 * @} 5486 */ 5487 5488 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 5489 * @brief Force or release APB1 peripheral reset. 5490 * @{ 5491 */ 5492 #if defined(STM32F413xx) || defined(STM32F423xx) 5493 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFECBFFU) 5494 #endif /* STM32F413xx || STM32F423xx */ 5495 #if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) 5496 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x17E6C9FFU) 5497 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 5498 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 5499 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 5500 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 5501 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 5502 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 5503 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 5504 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 5505 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 5506 #if defined(STM32F413xx) || defined(STM32F423xx) 5507 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 5508 #endif /* STM32F413xx || STM32F423xx */ 5509 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 5510 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 5511 #if defined(STM32F413xx) || defined(STM32F423xx) 5512 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 5513 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 5514 #endif /* STM32F413xx || STM32F423xx */ 5515 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 5516 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 5517 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 5518 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 5519 #if defined(STM32F413xx) || defined(STM32F423xx) 5520 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) 5521 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 5522 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 5523 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 5524 #endif /* STM32F413xx || STM32F423xx */ 5525 5526 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 5527 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 5528 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 5529 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 5530 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 5531 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 5532 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 5533 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 5534 #if defined(STM32F413xx) || defined(STM32F423xx) 5535 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 5536 #endif /* STM32F413xx || STM32F423xx */ 5537 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 5538 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 5539 #if defined(STM32F413xx) || defined(STM32F423xx) 5540 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 5541 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 5542 #endif /* STM32F413xx || STM32F423xx */ 5543 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 5544 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 5545 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 5546 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 5547 #if defined(STM32F413xx) || defined(STM32F423xx) 5548 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) 5549 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 5550 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 5551 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 5552 #endif /* STM32F413xx || STM32F423xx */ 5553 /** 5554 * @} 5555 */ 5556 5557 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 5558 * @brief Force or release APB2 peripheral reset. 5559 * @{ 5560 */ 5561 #if defined(STM32F413xx)|| defined(STM32F423xx) 5562 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x035779F3U) 5563 #endif /* STM32F413xx || STM32F423xx */ 5564 #if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) 5565 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x01177933U) 5566 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 5567 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 5568 #if defined(STM32F413xx) || defined(STM32F423xx) 5569 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) 5570 #define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) 5571 #endif /* STM32F413xx || STM32F423xx */ 5572 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 5573 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 5574 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 5575 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 5576 #if defined(STM32F413xx) || defined(STM32F423xx) 5577 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 5578 #endif /* STM32F413xx || STM32F423xx */ 5579 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) 5580 #if defined(STM32F413xx) || defined(STM32F423xx) 5581 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) 5582 #endif /* STM32F413xx || STM32F423xx */ 5583 5584 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 5585 #if defined(STM32F413xx) || defined(STM32F423xx) 5586 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) 5587 #define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) 5588 #endif /* STM32F413xx || STM32F423xx */ 5589 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 5590 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 5591 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 5592 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 5593 #if defined(STM32F413xx) || defined(STM32F423xx) 5594 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 5595 #endif /* STM32F413xx || STM32F423xx */ 5596 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) 5597 #if defined(STM32F413xx) || defined(STM32F423xx) 5598 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) 5599 #endif /* STM32F413xx || STM32F423xx */ 5600 /** 5601 * @} 5602 */ 5603 5604 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 5605 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 5606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5607 * power consumption. 5608 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5609 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5610 * @{ 5611 */ 5612 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 5613 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 5614 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 5615 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 5616 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 5617 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 5618 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 5619 #if defined(STM32F413xx) || defined(STM32F423xx) 5620 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 5621 #endif /* STM32F413xx || STM32F423xx */ 5622 5623 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 5624 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 5625 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 5626 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 5627 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 5628 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 5629 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 5630 #if defined(STM32F413xx) || defined(STM32F423xx) 5631 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 5632 #endif /* STM32F413xx || STM32F423xx */ 5633 /** 5634 * @} 5635 */ 5636 5637 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 5638 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 5639 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5640 * power consumption. 5641 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 5642 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5643 * @{ 5644 */ 5645 #if defined(STM32F423xx) 5646 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) 5647 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) 5648 #endif /* STM32F423xx */ 5649 5650 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 5651 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 5652 5653 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 5654 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 5655 /** 5656 * @} 5657 */ 5658 5659 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 5660 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 5661 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5662 * power consumption. 5663 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5664 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5665 * @{ 5666 */ 5667 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 5668 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 5669 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 5670 5671 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 5672 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 5673 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 5674 5675 /** 5676 * @} 5677 */ 5678 5679 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 5680 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 5681 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5682 * power consumption. 5683 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5684 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5685 * @{ 5686 */ 5687 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 5688 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 5689 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 5690 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 5691 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 5692 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 5693 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 5694 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 5695 #if defined(STM32F413xx) || defined(STM32F423xx) 5696 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 5697 #endif /* STM32F413xx || STM32F423xx */ 5698 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 5699 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 5700 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 5701 #if defined(STM32F413xx) || defined(STM32F423xx) 5702 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 5703 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 5704 #endif /* STM32F413xx || STM32F423xx */ 5705 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 5706 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 5707 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 5708 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 5709 #if defined(STM32F413xx) || defined(STM32F423xx) 5710 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) 5711 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 5712 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 5713 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 5714 #endif /* STM32F413xx || STM32F423xx */ 5715 5716 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 5717 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 5718 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 5719 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 5720 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 5721 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 5722 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 5723 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 5724 #if defined(STM32F413xx) || defined(STM32F423xx) 5725 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 5726 #endif /* STM32F413xx || STM32F423xx */ 5727 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 5728 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 5729 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 5730 #if defined(STM32F413xx) || defined(STM32F423xx) 5731 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 5732 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 5733 #endif /* STM32F413xx || STM32F423xx */ 5734 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 5735 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 5736 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 5737 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 5738 #if defined(STM32F413xx) || defined(STM32F423xx) 5739 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) 5740 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 5741 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 5742 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 5743 #endif /* STM32F413xx || STM32F423xx */ 5744 /** 5745 * @} 5746 */ 5747 5748 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 5749 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 5750 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 5751 * power consumption. 5752 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 5753 * @note By default, all peripheral clocks are enabled during SLEEP mode. 5754 * @{ 5755 */ 5756 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 5757 #if defined(STM32F413xx) || defined(STM32F423xx) 5758 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) 5759 #define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) 5760 #endif /* STM32F413xx || STM32F423xx */ 5761 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 5762 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 5763 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 5764 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 5765 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 5766 #if defined(STM32F413xx) || defined(STM32F423xx) 5767 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 5768 #endif /* STM32F413xx || STM32F423xx */ 5769 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) 5770 #if defined(STM32F413xx) || defined(STM32F423xx) 5771 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) 5772 #endif /* STM32F413xx || STM32F423xx */ 5773 5774 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 5775 #if defined(STM32F413xx) || defined(STM32F423xx) 5776 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) 5777 #define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) 5778 #endif /* STM32F413xx || STM32F423xx */ 5779 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 5780 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 5781 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 5782 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 5783 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 5784 #if defined(STM32F413xx) || defined(STM32F423xx) 5785 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 5786 #endif /* STM32F413xx || STM32F423xx */ 5787 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) 5788 #if defined(STM32F413xx) || defined(STM32F423xx) 5789 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) 5790 #endif /* STM32F413xx || STM32F423xx */ 5791 /** 5792 * @} 5793 */ 5794 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 5795 /*----------------------------------------------------------------------------*/ 5796 5797 /*------------------------------- PLL Configuration --------------------------*/ 5798 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ 5799 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 5800 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 5801 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 5802 * @note This function must be used only when the main PLL is disabled. 5803 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 5804 * This parameter can be one of the following values: 5805 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 5806 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 5807 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 5808 * @param __PLLM__ specifies the division factor for PLL VCO input clock 5809 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5810 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 5811 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5812 * of 2 MHz to limit PLL jitter. 5813 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 5814 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5815 * @note You have to set the PLLN parameter correctly to ensure that the VCO 5816 * output frequency is between 100 and 432 MHz. 5817 * 5818 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 5819 * This parameter must be a number in the range {2, 4, 6, or 8}. 5820 * 5821 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 5822 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5823 * @note If the USB OTG FS is used in your application, you have to set the 5824 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 5825 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 5826 * correctly. 5827 * 5828 * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 5829 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5830 * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ 5831 STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 5832 * 5833 */ 5834 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ 5835 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ 5836 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 5837 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 5838 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ 5839 ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) 5840 #else 5841 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 5842 * @note This function must be used only when the main PLL is disabled. 5843 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 5844 * This parameter can be one of the following values: 5845 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 5846 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 5847 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 5848 * @param __PLLM__ specifies the division factor for PLL VCO input clock 5849 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5850 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 5851 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5852 * of 2 MHz to limit PLL jitter. 5853 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 5854 * This parameter must be a number between Min_Data = 50 and Max_Data = 432 5855 * Except for STM32F411xE devices where Min_Data = 192. 5856 * @note You have to set the PLLN parameter correctly to ensure that the VCO 5857 * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices 5858 * where frequency is between 192 and 432 MHz. 5859 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 5860 * This parameter must be a number in the range {2, 4, 6, or 8}. 5861 * 5862 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 5863 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5864 * @note If the USB OTG FS is used in your application, you have to set the 5865 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 5866 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 5867 * correctly. 5868 * 5869 */ 5870 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ 5871 (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ 5872 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 5873 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 5874 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) 5875 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 5876 /*----------------------------------------------------------------------------*/ 5877 5878 /*----------------------------PLLI2S Configuration ---------------------------*/ 5879 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 5880 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 5881 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 5882 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 5883 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 5884 5885 /** @brief Macros to enable or disable the PLLI2S. 5886 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 5887 */ 5888 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 5889 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 5890 5891 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 5892 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 5893 STM32F412Rx || STM32F412Cx */ 5894 #if defined(STM32F446xx) 5895 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5896 * @note This macro must be used only when the PLLI2S is disabled. 5897 * @note PLLI2S clock source is common with the main PLL (configured in 5898 * HAL_RCC_ClockConfig() API). 5899 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5900 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5901 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5902 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5903 * of 1 MHz to limit PLLI2S jitter. 5904 * 5905 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5906 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5907 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5908 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5909 * 5910 * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. 5911 * This parameter must be a number in the range {2, 4, 6, or 8}. 5912 * @note the PLLI2SP parameter is only available with STM32F446xx Devices 5913 * 5914 * @param __PLLI2SR__ specifies the division factor for I2S clock 5915 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5916 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5917 * on the I2S clock frequency. 5918 * 5919 * @param __PLLI2SQ__ specifies the division factor for SAI clock 5920 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5921 */ 5922 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ 5923 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5924 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5925 ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ 5926 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 5927 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5928 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 5929 defined(STM32F413xx) || defined(STM32F423xx) 5930 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5931 * @note This macro must be used only when the PLLI2S is disabled. 5932 * @note PLLI2S clock source is common with the main PLL (configured in 5933 * HAL_RCC_ClockConfig() API). 5934 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5935 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5936 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5937 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5938 * of 1 MHz to limit PLLI2S jitter. 5939 * 5940 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5941 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5942 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5943 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5944 * 5945 * @param __PLLI2SR__ specifies the division factor for I2S clock 5946 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5947 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5948 * on the I2S clock frequency. 5949 * 5950 * @param __PLLI2SQ__ specifies the division factor for SAI clock 5951 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 5952 */ 5953 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ 5954 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 5955 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5956 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 5957 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5958 #else 5959 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5960 * @note This macro must be used only when the PLLI2S is disabled. 5961 * @note PLLI2S clock source is common with the main PLL (configured in 5962 * HAL_RCC_ClockConfig() API). 5963 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5964 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 5965 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5966 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 5967 * 5968 * @param __PLLI2SR__ specifies the division factor for I2S clock 5969 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5970 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5971 * on the I2S clock frequency. 5972 * 5973 */ 5974 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ 5975 (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 5976 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 5977 #endif /* STM32F446xx */ 5978 5979 #if defined(STM32F411xE) 5980 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 5981 * @note This macro must be used only when the PLLI2S is disabled. 5982 * @note This macro must be used only when the PLLI2S is disabled. 5983 * @note PLLI2S clock source is common with the main PLL (configured in 5984 * HAL_RCC_ClockConfig() API). 5985 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 5986 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 5987 * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices 5988 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 5989 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 5990 * of 2 MHz to limit PLLI2S jitter. 5991 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 5992 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. 5993 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 5994 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. 5995 * @param __PLLI2SR__ specifies the division factor for I2S clock 5996 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 5997 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 5998 * on the I2S clock frequency. 5999 */ 6000 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 6001 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 6002 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 6003 #endif /* STM32F411xE */ 6004 6005 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 6006 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. 6007 * @note This macro must be used only when the PLLI2S is disabled. 6008 * @note PLLI2S clock source is common with the main PLL (configured in 6009 * HAL_RCC_ClockConfig() API) 6010 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. 6011 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 6012 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 6013 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6014 * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. 6015 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6016 * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 6017 * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro 6018 * @param __PLLI2SR__ specifies the division factor for I2S clock 6019 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6020 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 6021 * on the I2S clock frequency. 6022 */ 6023 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ 6024 ((__PLLI2SQ__) << 24U) |\ 6025 ((__PLLI2SR__) << 28U)) 6026 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 6027 /*----------------------------------------------------------------------------*/ 6028 6029 /*------------------------------ PLLSAI Configuration ------------------------*/ 6030 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6031 /** @brief Macros to Enable or Disable the PLLISAI. 6032 * @note The PLLSAI is only available with STM32F429x/439x Devices. 6033 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 6034 */ 6035 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) 6036 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) 6037 6038 #if defined(STM32F446xx) 6039 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 6040 * 6041 * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock 6042 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 6043 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input 6044 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 6045 * of 1 MHz to limit PLLI2S jitter. 6046 * @note The PLLSAIM parameter is only used with STM32F446xx Devices 6047 * 6048 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 6049 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 6050 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 6051 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6052 * 6053 * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. 6054 * This parameter must be a number in the range {2, 4, 6, or 8}. 6055 * @note the PLLSAIP parameter is only available with STM32F446xx Devices 6056 * 6057 * @param __PLLSAIQ__ specifies the division factor for SAI clock 6058 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6059 * 6060 * @param __PLLSAIR__ specifies the division factor for LTDC clock 6061 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6062 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 6063 */ 6064 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 6065 (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ 6066 ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 6067 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ 6068 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 6069 #endif /* STM32F446xx */ 6070 6071 #if defined(STM32F469xx) || defined(STM32F479xx) 6072 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 6073 * 6074 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 6075 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 6076 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 6077 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6078 * 6079 * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. 6080 * This parameter must be a number in the range {2, 4, 6, or 8}. 6081 * 6082 * @param __PLLSAIQ__ specifies the division factor for SAI clock 6083 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6084 * 6085 * @param __PLLSAIR__ specifies the division factor for LTDC clock 6086 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6087 */ 6088 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 6089 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ 6090 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ 6091 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ 6092 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 6093 #endif /* STM32F469xx || STM32F479xx */ 6094 6095 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 6096 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 6097 * 6098 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 6099 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 6100 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 6101 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 6102 * 6103 * @param __PLLSAIQ__ specifies the division factor for SAI clock 6104 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 6105 * 6106 * @param __PLLSAIR__ specifies the division factor for LTDC clock 6107 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 6108 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 6109 */ 6110 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ 6111 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 6112 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ 6113 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 6114 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 6115 6116 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6117 /*----------------------------------------------------------------------------*/ 6118 6119 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ 6120 #if defined(STM32F413xx) || defined(STM32F423xx) 6121 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 6122 * @note This function must be called before enabling the PLLI2S. 6123 * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. 6124 * This parameter must be a number between 1 and 32. 6125 * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 6126 */ 6127 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) 6128 6129 /** @brief Macro to configure the SAI clock Divider coming from PLL. 6130 * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. 6131 * This parameter must be a number between 1 and 32. 6132 * SAI1 clock frequency = f(PLLR) / __PLLDivR__ 6133 */ 6134 #define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) 6135 #endif /* STM32F413xx || STM32F423xx */ 6136 6137 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 6138 defined(STM32F469xx) || defined(STM32F479xx) 6139 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 6140 * @note This function must be called before enabling the PLLI2S. 6141 * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. 6142 * This parameter must be a number between 1 and 32. 6143 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 6144 */ 6145 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) 6146 6147 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. 6148 * @note This function must be called before enabling the PLLSAI. 6149 * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . 6150 * This parameter must be a number between Min_Data = 1 and Max_Data = 32. 6151 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ 6152 */ 6153 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) 6154 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6155 6156 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 6157 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. 6158 * 6159 * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6160 * @note This function must be called before enabling the PLLSAI. 6161 * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . 6162 * This parameter must be a number between Min_Data = 2 and Max_Data = 16. 6163 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 6164 */ 6165 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) 6166 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 6167 /*----------------------------------------------------------------------------*/ 6168 6169 /*------------------------- Peripheral Clock selection -----------------------*/ 6170 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 6171 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6172 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ 6173 defined(STM32F479xx) 6174 /** @brief Macro to configure the I2S clock source (I2SCLK). 6175 * @note This function must be called before enabling the I2S APB clock. 6176 * @param __SOURCE__ specifies the I2S clock source. 6177 * This parameter can be one of the following values: 6178 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 6179 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 6180 * used as I2S clock source. 6181 */ 6182 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (__SOURCE__))) 6183 6184 6185 /** @brief Macro to get the I2S clock source (I2SCLK). 6186 * @retval The clock source can be one of the following values: 6187 * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 6188 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 6189 * used as I2S clock source 6190 */ 6191 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) 6192 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ 6193 6194 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 6195 6196 /** @brief Macro to configure SAI1BlockA clock source selection. 6197 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6198 * @note This function must be called before enabling PLLSAI, PLLI2S and 6199 * the SAI clock. 6200 * @param __SOURCE__ specifies the SAI Block A clock source. 6201 * This parameter can be one of the following values: 6202 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 6203 * as SAI1 Block A clock. 6204 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 6205 * as SAI1 Block A clock. 6206 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 6207 * used as SAI1 Block A clock. 6208 */ 6209 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 6210 6211 /** @brief Macro to configure SAI1BlockB clock source selection. 6212 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 6213 * @note This function must be called before enabling PLLSAI, PLLI2S and 6214 * the SAI clock. 6215 * @param __SOURCE__ specifies the SAI Block B clock source. 6216 * This parameter can be one of the following values: 6217 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 6218 * as SAI1 Block B clock. 6219 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 6220 * as SAI1 Block B clock. 6221 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 6222 * used as SAI1 Block B clock. 6223 */ 6224 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 6225 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 6226 6227 #if defined(STM32F446xx) 6228 /** @brief Macro to configure SAI1 clock source selection. 6229 * @note This configuration is only available with STM32F446xx Devices. 6230 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 6231 * the SAI clock. 6232 * @param __SOURCE__ specifies the SAI1 clock source. 6233 * This parameter can be one of the following values: 6234 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 6235 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 6236 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 6237 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 6238 */ 6239 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) 6240 6241 /** @brief Macro to Get SAI1 clock source selection. 6242 * @note This configuration is only available with STM32F446xx Devices. 6243 * @retval The clock source can be one of the following values: 6244 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 6245 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 6246 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 6247 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 6248 */ 6249 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) 6250 6251 /** @brief Macro to configure SAI2 clock source selection. 6252 * @note This configuration is only available with STM32F446xx Devices. 6253 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 6254 * the SAI clock. 6255 * @param __SOURCE__ specifies the SAI2 clock source. 6256 * This parameter can be one of the following values: 6257 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 6258 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 6259 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 6260 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 6261 */ 6262 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) 6263 6264 /** @brief Macro to Get SAI2 clock source selection. 6265 * @note This configuration is only available with STM32F446xx Devices. 6266 * @retval The clock source can be one of the following values: 6267 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 6268 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 6269 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 6270 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 6271 */ 6272 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) 6273 6274 /** @brief Macro to configure I2S APB1 clock source selection. 6275 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 6276 * @param __SOURCE__ specifies the I2S APB1 clock source. 6277 * This parameter can be one of the following values: 6278 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6279 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 6280 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 6281 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6282 */ 6283 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 6284 6285 /** @brief Macro to Get I2S APB1 clock source selection. 6286 * @retval The clock source can be one of the following values: 6287 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6288 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 6289 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 6290 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6291 */ 6292 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 6293 6294 /** @brief Macro to configure I2S APB2 clock source selection. 6295 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 6296 * @param __SOURCE__ specifies the SAI Block A clock source. 6297 * This parameter can be one of the following values: 6298 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6299 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 6300 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 6301 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6302 */ 6303 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 6304 6305 /** @brief Macro to Get I2S APB2 clock source selection. 6306 * @retval The clock source can be one of the following values: 6307 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 6308 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 6309 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 6310 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6311 */ 6312 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 6313 6314 /** @brief Macro to configure the CEC clock. 6315 * @param __SOURCE__ specifies the CEC clock source. 6316 * This parameter can be one of the following values: 6317 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock 6318 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 6319 */ 6320 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) 6321 6322 /** @brief Macro to Get the CEC clock. 6323 * @retval The clock source can be one of the following values: 6324 * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock 6325 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 6326 */ 6327 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) 6328 6329 /** @brief Macro to configure the FMPI2C1 clock. 6330 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6331 * This parameter can be one of the following values: 6332 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6333 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6334 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6335 */ 6336 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6337 6338 /** @brief Macro to Get the FMPI2C1 clock. 6339 * @retval The clock source can be one of the following values: 6340 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6341 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6342 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6343 */ 6344 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6345 6346 /** @brief Macro to configure the CLK48 clock. 6347 * @param __SOURCE__ specifies the CLK48 clock source. 6348 * This parameter can be one of the following values: 6349 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6350 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6351 */ 6352 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 6353 6354 /** @brief Macro to Get the CLK48 clock. 6355 * @retval The clock source can be one of the following values: 6356 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6357 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6358 */ 6359 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 6360 6361 /** @brief Macro to configure the SDIO clock. 6362 * @param __SOURCE__ specifies the SDIO clock source. 6363 * This parameter can be one of the following values: 6364 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6365 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6366 */ 6367 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 6368 6369 /** @brief Macro to Get the SDIO clock. 6370 * @retval The clock source can be one of the following values: 6371 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6372 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6373 */ 6374 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 6375 6376 /** @brief Macro to configure the SPDIFRX clock. 6377 * @param __SOURCE__ specifies the SPDIFRX clock source. 6378 * This parameter can be one of the following values: 6379 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 6380 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 6381 */ 6382 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) 6383 6384 /** @brief Macro to Get the SPDIFRX clock. 6385 * @retval The clock source can be one of the following values: 6386 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 6387 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 6388 */ 6389 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) 6390 #endif /* STM32F446xx */ 6391 6392 #if defined(STM32F469xx) || defined(STM32F479xx) 6393 6394 /** @brief Macro to configure the CLK48 clock. 6395 * @param __SOURCE__ specifies the CLK48 clock source. 6396 * This parameter can be one of the following values: 6397 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6398 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6399 */ 6400 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) 6401 6402 /** @brief Macro to Get the CLK48 clock. 6403 * @retval The clock source can be one of the following values: 6404 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6405 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 6406 */ 6407 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) 6408 6409 /** @brief Macro to configure the SDIO clock. 6410 * @param __SOURCE__ specifies the SDIO clock source. 6411 * This parameter can be one of the following values: 6412 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6413 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6414 */ 6415 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) 6416 6417 /** @brief Macro to Get the SDIO clock. 6418 * @retval The clock source can be one of the following values: 6419 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6420 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6421 */ 6422 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) 6423 6424 /** @brief Macro to configure the DSI clock. 6425 * @param __SOURCE__ specifies the DSI clock source. 6426 * This parameter can be one of the following values: 6427 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 6428 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 6429 */ 6430 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) 6431 6432 /** @brief Macro to Get the DSI clock. 6433 * @retval The clock source can be one of the following values: 6434 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 6435 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 6436 */ 6437 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) 6438 6439 #endif /* STM32F469xx || STM32F479xx */ 6440 6441 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 6442 defined(STM32F413xx) || defined(STM32F423xx) 6443 /** @brief Macro to configure the DFSDM1 clock. 6444 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 6445 * This parameter can be one of the following values: 6446 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6447 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 6448 * @retval None 6449 */ 6450 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 6451 6452 /** @brief Macro to get the DFSDM1 clock source. 6453 * @retval The clock source can be one of the following values: 6454 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6455 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. 6456 */ 6457 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 6458 6459 /** @brief Macro to configure DFSDM1 Audio clock source selection. 6460 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 6461 STM32F413xx/STM32F423xx Devices. 6462 * @param __SOURCE__ specifies the DFSDM1 Audio clock source. 6463 * This parameter can be one of the following values: 6464 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6465 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6466 */ 6467 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) 6468 6469 /** @brief Macro to Get DFSDM1 Audio clock source selection. 6470 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 6471 STM32F413xx/STM32F423xx Devices. 6472 * @retval The clock source can be one of the following values: 6473 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6474 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6475 */ 6476 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) 6477 6478 #if defined(STM32F413xx) || defined(STM32F423xx) 6479 /** @brief Macro to configure the DFSDM2 clock. 6480 * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. 6481 * This parameter can be one of the following values: 6482 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6483 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 6484 * @retval None 6485 */ 6486 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) 6487 6488 /** @brief Macro to get the DFSDM2 clock source. 6489 * @retval The clock source can be one of the following values: 6490 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 6491 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. 6492 */ 6493 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 6494 6495 /** @brief Macro to configure DFSDM1 Audio clock source selection. 6496 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6497 * @param __SOURCE__ specifies the DFSDM2 Audio clock source. 6498 * This parameter can be one of the following values: 6499 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6500 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6501 */ 6502 #define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) 6503 6504 /** @brief Macro to Get DFSDM2 Audio clock source selection. 6505 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6506 * @retval The clock source can be one of the following values: 6507 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 6508 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 6509 */ 6510 #define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) 6511 6512 /** @brief Macro to configure SAI1BlockA clock source selection. 6513 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 6514 * @note This function must be called before enabling PLLSAI, PLLI2S and 6515 * the SAI clock. 6516 * @param __SOURCE__ specifies the SAI Block A clock source. 6517 * This parameter can be one of the following values: 6518 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6519 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 6520 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6521 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6522 */ 6523 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 6524 6525 /** @brief Macro to Get SAI1 BlockA clock source selection. 6526 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6527 * @retval The clock source can be one of the following values: 6528 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6529 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 6530 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6531 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6532 */ 6533 #define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) 6534 6535 /** @brief Macro to configure SAI1 BlockB clock source selection. 6536 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 6537 * @note This function must be called before enabling PLLSAI, PLLI2S and 6538 * the SAI clock. 6539 * @param __SOURCE__ specifies the SAI Block B clock source. 6540 * This parameter can be one of the following values: 6541 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6542 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 6543 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6544 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6545 */ 6546 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 6547 6548 /** @brief Macro to Get SAI1 BlockB clock source selection. 6549 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 6550 * @retval The clock source can be one of the following values: 6551 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 6552 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 6553 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 6554 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6555 */ 6556 #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) 6557 6558 /** @brief Macro to configure the LPTIM1 clock. 6559 * @param __SOURCE__ specifies the LPTIM1 clock source. 6560 * This parameter can be one of the following values: 6561 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 6562 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6563 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6564 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6565 */ 6566 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 6567 6568 /** @brief Macro to Get the LPTIM1 clock. 6569 * @retval The clock source can be one of the following values: 6570 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 6571 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6572 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6573 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6574 */ 6575 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 6576 #endif /* STM32F413xx || STM32F423xx */ 6577 6578 /** @brief Macro to configure I2S APB1 clock source selection. 6579 * @param __SOURCE__ specifies the I2S APB1 clock source. 6580 * This parameter can be one of the following values: 6581 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6582 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6583 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6584 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6585 */ 6586 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 6587 6588 /** @brief Macro to Get I2S APB1 clock source selection. 6589 * @retval The clock source can be one of the following values: 6590 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6591 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6592 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6593 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6594 */ 6595 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 6596 6597 /** @brief Macro to configure I2S APB2 clock source selection. 6598 * @param __SOURCE__ specifies the I2S APB2 clock source. 6599 * This parameter can be one of the following values: 6600 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6601 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6602 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6603 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6604 */ 6605 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 6606 6607 /** @brief Macro to Get I2S APB2 clock source selection. 6608 * @retval The clock source can be one of the following values: 6609 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 6610 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6611 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 6612 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6613 */ 6614 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 6615 6616 /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). 6617 * @note This macro must be called before enabling the I2S APB clock. 6618 * @param __SOURCE__ specifies the I2S clock source. 6619 * This parameter can be one of the following values: 6620 * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 6621 * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 6622 * used as I2S clock source. 6623 */ 6624 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) 6625 6626 /** @brief Macro to configure the FMPI2C1 clock. 6627 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6628 * This parameter can be one of the following values: 6629 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6630 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6631 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6632 */ 6633 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6634 6635 /** @brief Macro to Get the FMPI2C1 clock. 6636 * @retval The clock source can be one of the following values: 6637 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6638 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6639 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6640 */ 6641 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6642 6643 /** @brief Macro to configure the CLK48 clock. 6644 * @param __SOURCE__ specifies the CLK48 clock source. 6645 * This parameter can be one of the following values: 6646 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6647 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. 6648 */ 6649 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 6650 6651 /** @brief Macro to Get the CLK48 clock. 6652 * @retval The clock source can be one of the following values: 6653 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 6654 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock 6655 */ 6656 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 6657 6658 /** @brief Macro to configure the SDIO clock. 6659 * @param __SOURCE__ specifies the SDIO clock source. 6660 * This parameter can be one of the following values: 6661 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6662 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6663 */ 6664 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 6665 6666 /** @brief Macro to Get the SDIO clock. 6667 * @retval The clock source can be one of the following values: 6668 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 6669 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 6670 */ 6671 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 6672 6673 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 6674 6675 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6676 /** @brief Macro to configure I2S clock source selection. 6677 * @param __SOURCE__ specifies the I2S clock source. 6678 * This parameter can be one of the following values: 6679 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 6680 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6681 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 6682 */ 6683 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) 6684 6685 /** @brief Macro to Get I2S clock source selection. 6686 * @retval The clock source can be one of the following values: 6687 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 6688 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 6689 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 6690 */ 6691 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) 6692 6693 /** @brief Macro to configure the FMPI2C1 clock. 6694 * @param __SOURCE__ specifies the FMPI2C1 clock source. 6695 * This parameter can be one of the following values: 6696 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6697 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6698 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6699 */ 6700 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 6701 6702 /** @brief Macro to Get the FMPI2C1 clock. 6703 * @retval The clock source can be one of the following values: 6704 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 6705 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 6706 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 6707 */ 6708 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 6709 6710 /** @brief Macro to configure the LPTIM1 clock. 6711 * @param __SOURCE__ specifies the LPTIM1 clock source. 6712 * This parameter can be one of the following values: 6713 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 6714 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6715 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6716 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6717 */ 6718 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 6719 6720 /** @brief Macro to Get the LPTIM1 clock. 6721 * @retval The clock source can be one of the following values: 6722 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 6723 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 6724 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 6725 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 6726 */ 6727 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 6728 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6729 6730 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6731 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 6732 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 6733 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 6734 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6735 /** @brief Macro to configure the Timers clocks prescalers 6736 * @note This feature is only available with STM32F429x/439x Devices. 6737 * @param __PRESC__ specifies the Timers clocks prescalers selection 6738 * This parameter can be one of the following values: 6739 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 6740 * equal to HPRE if PPREx is corresponding to division by 1 or 2, 6741 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 6742 * division by 4 or more. 6743 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 6744 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 6745 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 6746 * to division by 8 or more. 6747 */ 6748 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) 6749 6750 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ 6751 STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ 6752 STM32F423xx */ 6753 6754 /*----------------------------------------------------------------------------*/ 6755 6756 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6757 /** @brief Enable PLLSAI_RDY interrupt. 6758 */ 6759 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) 6760 6761 /** @brief Disable PLLSAI_RDY interrupt. 6762 */ 6763 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) 6764 6765 /** @brief Clear the PLLSAI RDY interrupt pending bits. 6766 */ 6767 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) 6768 6769 /** @brief Check the PLLSAI RDY interrupt has occurred or not. 6770 * @retval The new state (TRUE or FALSE). 6771 */ 6772 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) 6773 6774 /** @brief Check PLLSAI RDY flag is set or not. 6775 * @retval The new state (TRUE or FALSE). 6776 */ 6777 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) 6778 6779 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6780 6781 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6782 /** @brief Macros to enable or disable the RCC MCO1 feature. 6783 */ 6784 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) 6785 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) 6786 6787 /** @brief Macros to enable or disable the RCC MCO2 feature. 6788 */ 6789 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) 6790 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) 6791 6792 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6793 6794 /** 6795 * @} 6796 */ 6797 6798 /* Exported functions --------------------------------------------------------*/ 6799 /** @addtogroup RCCEx_Exported_Functions 6800 * @{ 6801 */ 6802 6803 /** @addtogroup RCCEx_Exported_Functions_Group1 6804 * @{ 6805 */ 6806 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 6807 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 6808 6809 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 6810 6811 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 6812 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 6813 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 6814 defined(STM32F423xx) 6815 void HAL_RCCEx_SelectLSEMode(uint8_t Mode); 6816 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6817 #if defined(RCC_PLLI2S_SUPPORT) 6818 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 6819 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 6820 #endif /* RCC_PLLI2S_SUPPORT */ 6821 #if defined(RCC_PLLSAI_SUPPORT) 6822 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); 6823 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); 6824 #endif /* RCC_PLLSAI_SUPPORT */ 6825 /** 6826 * @} 6827 */ 6828 6829 /** 6830 * @} 6831 */ 6832 /* Private types -------------------------------------------------------------*/ 6833 /* Private variables ---------------------------------------------------------*/ 6834 /* Private constants ---------------------------------------------------------*/ 6835 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants 6836 * @{ 6837 */ 6838 6839 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion 6840 * @brief RCC registers bit address in the alias region 6841 * @{ 6842 */ 6843 /* --- CR Register ---*/ 6844 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6845 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6846 /* Alias word address of PLLSAION bit */ 6847 #define RCC_PLLSAION_BIT_NUMBER 0x1CU 6848 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) 6849 6850 #define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6851 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6852 6853 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 6854 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 6855 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 6856 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 6857 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6858 /* Alias word address of PLLI2SON bit */ 6859 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU 6860 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) 6861 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 6862 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 6863 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6864 6865 /* --- DCKCFGR Register ---*/ 6866 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 6867 defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ 6868 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 6869 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 6870 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6871 /* Alias word address of TIMPRE bit */ 6872 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) 6873 #define RCC_TIMPRE_BIT_NUMBER 0x18U 6874 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) 6875 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ 6876 STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 6877 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6878 6879 /* --- CFGR Register ---*/ 6880 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 6881 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 6882 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 6883 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 6884 defined(STM32F469xx) || defined(STM32F479xx) 6885 /* Alias word address of I2SSRC bit */ 6886 #define RCC_I2SSRC_BIT_NUMBER 0x17U 6887 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) 6888 6889 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6890 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 6891 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ 6892 6893 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 6894 defined(STM32F413xx) || defined(STM32F423xx) 6895 /* --- PLLI2SCFGR Register ---*/ 6896 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) 6897 /* Alias word address of PLLI2SSRC bit */ 6898 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16U 6899 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE\ 6900 + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) 6901 6902 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 6903 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ 6904 6905 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6906 /* Alias word address of MCO1EN bit */ 6907 #define RCC_MCO1EN_BIT_NUMBER 0x8U 6908 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) 6909 6910 /* Alias word address of MCO2EN bit */ 6911 #define RCC_MCO2EN_BIT_NUMBER 0x9U 6912 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) 6913 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6914 6915 #define PLL_TIMEOUT_VALUE 2U /* 2 ms */ 6916 /** 6917 * @} 6918 */ 6919 6920 /** 6921 * @} 6922 */ 6923 6924 /* Private macros ------------------------------------------------------------*/ 6925 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 6926 * @{ 6927 */ 6928 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 6929 * @{ 6930 */ 6931 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6932 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6933 6934 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 6935 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) 6936 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 6937 6938 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 6939 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) 6940 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 6941 6942 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 6943 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) 6944 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 6945 6946 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6947 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) 6948 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 6949 6950 #if defined(STM32F446xx) 6951 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) 6952 #endif /* STM32F446xx */ 6953 6954 #if defined(STM32F469xx) || defined(STM32F479xx) 6955 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) 6956 #endif /* STM32F469xx || STM32F479xx */ 6957 6958 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 6959 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) 6960 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 6961 6962 #if defined(STM32F413xx) || defined(STM32F423xx) 6963 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) 6964 #endif /* STM32F413xx || STM32F423xx */ 6965 6966 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6967 6968 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ 6969 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 6970 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 6971 6972 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 6973 6974 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 6975 6976 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6977 6978 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 6979 6980 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 6981 6982 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ 6983 ((VALUE) == RCC_PLLSAIDIVR_4) ||\ 6984 ((VALUE) == RCC_PLLSAIDIVR_8) ||\ 6985 ((VALUE) == RCC_PLLSAIDIVR_16)) 6986 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 6987 6988 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 6989 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 6990 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) 6991 6992 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 6993 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 6994 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 6995 6996 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 6997 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 6998 6999 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 7000 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 7001 7002 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 7003 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 7004 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 7005 7006 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 7007 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 7008 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 7009 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 7010 7011 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ 7012 ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ 7013 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 7014 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 7015 7016 #if defined(STM32F446xx) 7017 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 7018 7019 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ 7020 ((VALUE) == RCC_PLLI2SP_DIV4) ||\ 7021 ((VALUE) == RCC_PLLI2SP_DIV6) ||\ 7022 ((VALUE) == RCC_PLLI2SP_DIV8)) 7023 7024 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) 7025 7026 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 7027 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 7028 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 7029 ((VALUE) == RCC_PLLSAIP_DIV8)) 7030 7031 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ 7032 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ 7033 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ 7034 ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) 7035 7036 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ 7037 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ 7038 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ 7039 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) 7040 7041 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 7042 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 7043 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 7044 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 7045 7046 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 7047 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 7048 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 7049 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 7050 7051 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 7052 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 7053 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 7054 7055 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ 7056 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 7057 7058 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 7059 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 7060 7061 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 7062 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 7063 7064 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ 7065 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 7066 #endif /* STM32F446xx */ 7067 7068 #if defined(STM32F469xx) || defined(STM32F479xx) 7069 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 7070 7071 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 7072 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 7073 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 7074 ((VALUE) == RCC_PLLSAIP_DIV8)) 7075 7076 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 7077 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 7078 7079 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 7080 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 7081 7082 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ 7083 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) 7084 7085 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 7086 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 7087 #endif /* STM32F469xx || STM32F479xx */ 7088 7089 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 7090 defined(STM32F413xx) || defined(STM32F423xx) 7091 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 7092 7093 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 7094 7095 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ 7096 ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) 7097 7098 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 7099 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 7100 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 7101 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 7102 7103 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 7104 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 7105 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 7106 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 7107 7108 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 7109 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 7110 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 7111 7112 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 7113 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) 7114 7115 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 7116 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 7117 7118 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 7119 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 7120 7121 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ 7122 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) 7123 7124 #if defined(STM32F413xx) || defined(STM32F423xx) 7125 #define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ 7126 ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) 7127 7128 #define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ 7129 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) 7130 7131 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 7132 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 7133 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 7134 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 7135 7136 #define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ 7137 ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ 7138 ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ 7139 ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) 7140 7141 #define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ 7142 ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ 7143 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ 7144 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) 7145 7146 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 7147 7148 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 7149 7150 #endif /* STM32F413xx || STM32F423xx */ 7151 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 7152 7153 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 7154 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 7155 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 7156 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 7157 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 7158 7159 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ 7160 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 7161 7162 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 7163 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ 7164 STM32F412Rx */ 7165 7166 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 7167 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ 7168 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 7169 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 7170 /** 7171 * @} 7172 */ 7173 7174 /** 7175 * @} 7176 */ 7177 7178 /** 7179 * @} 7180 */ 7181 7182 /** 7183 * @} 7184 */ 7185 #ifdef __cplusplus 7186 } 7187 #endif 7188 7189 #endif /* __STM32F4xx_HAL_RCC_EX_H */ 7190 7191
