1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32U5xx_HAL_RCC_H 22 #define STM32U5xx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_def.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCC_Exported_Types RCC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLLState; /*!< The new state of the PLL. 50 This parameter can be a value of @ref RCC_PLL_Config */ 51 52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 53 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 54 55 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 56 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 57 58 uint32_t PLLMBOOST; /*!< PLLMBOOST: Prescaler for EPOD booster input clock. 59 This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider */ 60 61 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 62 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 63 64 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 65 This parameter must be a number between Min_Data = 1 and Max_Data = 128 66 odd division factors are not allowed */ 67 68 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 69 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 70 71 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 72 This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ 73 74 uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range 75 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 76 77 uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 78 PLL1 VCO It should be a value between 0 and 32767 */ 79 80 } RCC_PLLInitTypeDef; 81 82 /** 83 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 84 */ 85 typedef struct 86 { 87 uint32_t OscillatorType; /*!< The oscillators to be configured. 88 This parameter can be a value of @ref RCC_Oscillator_Type */ 89 90 uint32_t HSEState; /*!< The new state of the HSE. 91 This parameter can be a value of @ref RCC_HSE_Config */ 92 93 uint32_t LSEState; /*!< The new state of the LSE. 94 This parameter can be a value of @ref RCC_LSE_Config */ 95 96 uint32_t HSIState; /*!< The new state of the HSI. 97 This parameter can be a value of @ref RCC_HSI_Config */ 98 99 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 101 on the other devices */ 102 103 uint32_t LSIState; /*!< The new state of the LSI. 104 This parameter can be a value of @ref RCC_LSI_Config */ 105 106 uint32_t LSIDiv; /*!< The division factor of the LSI. 107 This parameter can be a value of @ref RCC_LSI_Div */ 108 109 uint32_t MSIState; /*!< The new state of the MSI. 110 This parameter can be a value of @ref RCC_MSI_Config */ 111 112 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 114 115 uint32_t MSIClockRange; /*!< The MSI frequency range. 116 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 117 118 uint32_t MSIKClockRange; /*!< The MSIK frequency range. 119 This parameter can be a value of @ref RCC_MSIk_Clock_Range */ 120 121 uint32_t HSI48State; /*!< The new state of the HSI48. 122 This parameter can be a value of @ref RCC_HSI48_Config */ 123 124 uint32_t SHSIState; /*!< The new state of the SHSI. 125 This parameter can be a value of @ref RCC_SHSI_Config */ 126 127 uint32_t MSIKState; /*!< The new state of the MSIK. 128 This parameter can be a value of @ref RCC_MSIK_Config */ 129 130 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 131 132 } RCC_OscInitTypeDef; 133 134 /** 135 * @brief RCC System, AHB and APB busses clock configuration structure definition 136 */ 137 typedef struct 138 { 139 uint32_t ClockType; /*!< The clock to be configured. 140 This parameter can be a value of @ref RCC_System_Clock_Type */ 141 142 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 143 This parameter can be a value of @ref RCC_System_Clock_Source */ 144 145 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock 146 (SYSCLK). 147 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 148 149 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 150 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 151 152 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 153 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 154 155 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 156 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 157 } RCC_ClkInitTypeDef; 158 159 /** 160 * @} 161 */ 162 163 /* Exported constants --------------------------------------------------------*/ 164 /** @defgroup RCC_Exported_Constants RCC Exported Constants 165 * @{ 166 */ 167 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 168 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 169 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 170 171 /* Defines used for Flags */ 172 #define CR_REG_INDEX (1U) 173 #define BDCR_REG_INDEX (2U) 174 #define CSR_REG_INDEX (3U) 175 #define CRRCR_REG_INDEX (4U) 176 177 #define RCC_FLAG_MASK (0x1FU) 178 /** 179 * @} 180 */ 181 182 /** @defgroup RCC_Reset_Flag Reset Flag 183 * @{ 184 */ 185 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 186 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 187 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 188 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 189 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 190 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 191 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 192 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 193 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 194 RCC_RESET_FLAG_LPWR) 195 /** 196 * @} 197 */ 198 199 /** @defgroup RCC_Timeout_Value Timeout Values 200 * @{ 201 */ 202 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 203 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 204 /** 205 * @} 206 */ 207 208 /** @defgroup RCC_Oscillator_Type Oscillator Type 209 * @{ 210 */ 211 #define RCC_OSCILLATORTYPE_NONE 0x0UL /*!< Oscillator configuration unchanged */ 212 #define RCC_OSCILLATORTYPE_HSE 0x1UL /*!< HSE to configure */ 213 #define RCC_OSCILLATORTYPE_HSI 0x2UL /*!< HSI to configure */ 214 #define RCC_OSCILLATORTYPE_LSE 0x4UL /*!< LSE to configure */ 215 #define RCC_OSCILLATORTYPE_LSI 0x8UL /*!< LSI to configure */ 216 #define RCC_OSCILLATORTYPE_MSI 0x10UL /*!< MSI to configure */ 217 #define RCC_OSCILLATORTYPE_HSI48 0x20UL /*!< HSI48 to configure */ 218 #define RCC_OSCILLATORTYPE_MSIK 0x040U /*!< MSIK to configure */ 219 #define RCC_OSCILLATORTYPE_SHSI 0x80UL /*!< SHSI to configure */ 220 /* Defines Oscillator Masks */ 221 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | \ 222 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_MSIK | \ 223 RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_SHSI) /*!< All Oscillator to configure */ 224 /** 225 * @} 226 */ 227 228 /** @defgroup RCC_HSE_Config HSE Config 229 * @{ 230 */ 231 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 232 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 233 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 234 #define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) 235 /** 236 * @} 237 */ 238 239 /** @defgroup RCC_LSE_Config LSE Config 240 * @{ 241 */ 242 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 243 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 244 #define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */ 245 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 246 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 247 /** 248 * @} 249 */ 250 251 /** @defgroup RCC_HSI_Config HSI Config 252 * @{ 253 */ 254 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 255 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 256 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 257 /** 258 * @} 259 */ 260 261 /** @defgroup RCC_LSI_Config LSI Config 262 * @{ 263 */ 264 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 265 #define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ 266 /** 267 * @} 268 */ 269 270 /** @defgroup RCC_LSI_Div LSI Div 271 * @{ 272 */ 273 #define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ 274 #define RCC_LSI_DIV128 RCC_BDCR_LSIPREDIV /*!< LSI clock is divided by 128 */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup RCC_MSI_Config MSI Config 280 * @{ 281 */ 282 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 283 #define RCC_MSI_ON RCC_CR_MSISON /*!< MSI clock activation */ 284 285 #define RCC_MSICALIBRATION_DEFAULT 0x10U /*!< Default MSI calibration trimming value */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup RCC_HSI48_Config HSI48 Config 291 * @{ 292 */ 293 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 294 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup RCC_MSIK_Config MSIK Config 300 * @{ 301 */ 302 #define RCC_MSIK_OFF 0x00000000U /*!< MSIK clock deactivation */ 303 #define RCC_MSIK_ON RCC_CR_MSIKON /*!< MSIK clock activation */ 304 /** 305 * @} 306 */ 307 308 /** @defgroup RCC_SHSI_Config SHSI Config 309 * @{ 310 */ 311 #define RCC_SHSI_OFF 0x00000000U /*!< SHSI clock deactivation */ 312 #define RCC_SHSI_ON RCC_CR_SHSION /*!< SHSI clock activation */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup RCC_PLL_Config RCC PLL Config 318 * @{ 319 */ 320 #define RCC_PLL_NONE 0x00000000U 321 #define RCC_PLL_OFF 0x00000001U 322 #define RCC_PLL_ON 0x00000002U 323 /** 324 * @} 325 */ 326 327 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output 328 * @{ 329 */ 330 #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN 331 #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN 332 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN 333 /** 334 * @} 335 */ 336 337 /** @defgroup RCC_PLLMBOOST_EPOD_Clock_Divider PLLMBOOST EPOD Clock Divider 338 * @{ 339 */ 340 #define RCC_PLLMBOOST_DIV1 0x00000000U 341 #define RCC_PLLMBOOST_DIV2 RCC_PLL1CFGR_PLL1MBOOST_0 342 #define RCC_PLLMBOOST_DIV4 RCC_PLL1CFGR_PLL1MBOOST_1 343 #define RCC_PLLMBOOST_DIV6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) 344 #define RCC_PLLMBOOST_DIV8 RCC_PLL1CFGR_PLL1MBOOST_2 345 #define RCC_PLLMBOOST_DIV10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) 346 #define RCC_PLLMBOOST_DIV12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) 347 #define RCC_PLLMBOOST_DIV14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1| RCC_PLL1CFGR_PLL1MBOOST_0) 348 #define RCC_PLLMBOOST_DIV16 RCC_PLL1CFGR_PLL1MBOOST_3 349 /** 350 * @} 351 */ 352 353 /** @defgroup RCC_PLL_VCI_Range RCC PLL1 VCI Range 354 * @{ 355 */ 356 #define RCC_PLLVCIRANGE_0 0x00000000U 357 #define RCC_PLLVCIRANGE_1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) 358 /** 359 * @} 360 */ 361 362 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source 363 * @{ 364 */ 365 #define RCC_PLLSOURCE_NONE 0x00000000U 366 #define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 367 #define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 368 #define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) 369 /** 370 * @} 371 */ 372 373 374 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 375 * @{ 376 */ 377 #define RCC_MSIRANGE_0 0x00000000U /*!< MSI = 48 MHz */ 378 #define RCC_MSIRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSI = 24 MHz */ 379 #define RCC_MSIRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSI = 16 MHz */ 380 #define RCC_MSIRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSI = 12 MHz */ 381 #define RCC_MSIRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSI = 4 MHz */ 382 #define RCC_MSIRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 2 MHz */ 383 #define RCC_MSIRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1.33 MHz */ 384 #define RCC_MSIRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1 MHz */ 385 #define RCC_MSIRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSI = 3.072 MHz */ 386 #define RCC_MSIRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.536 MHz */ 387 #define RCC_MSIRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.024 MHz */ 388 #define RCC_MSIRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 768 KHz */ 389 #define RCC_MSIRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 400 KHz */ 390 #define RCC_MSIRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 200 KHz */ 391 #define RCC_MSIRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 133 KHz */ 392 #define RCC_MSIRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 |\ 393 RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 100 KHz */ 394 /** 395 * @} 396 */ 397 398 /** @defgroup RCC_MSIk_Clock_Range MSIK Clock Range 399 * @{ 400 */ 401 #define RCC_MSIKRANGE_0 0x00000000U /*!< MSIk = 48 MHz */ 402 #define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIk = 24 MHz */ 403 #define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIk = 16 MHz */ 404 #define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIk = 12 MHz */ 405 #define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIk = 4 MHz */ 406 #define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 2 MHz */ 407 #define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1.33 MHz */ 408 #define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1 MHz */ 409 #define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIk = 3.072 MHz */ 410 #define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.536 MHz */ 411 #define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.024 MHz */ 412 #define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 768 KHz */ 413 #define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 400 KHz */ 414 #define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 200 KHz */ 415 #define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 133 KHz */ 416 #define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ 417 RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 100 KHz */ 418 /** 419 * @} 420 */ 421 422 /** @defgroup RCC_System_Clock_Type System Clock Type 423 * @{ 424 */ 425 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 426 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 427 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 428 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 429 #define RCC_CLOCKTYPE_PCLK3 0x00000010U /*!< PCLK3 to configure */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup RCC_System_Clock_Source System Clock Source 435 * @{ 436 */ 437 #define RCC_SYSCLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ 438 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI selection as system clock */ 439 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 440 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ 441 /** 442 * @} 443 */ 444 445 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 446 * @{ 447 */ 448 #define RCC_SYSCLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ 449 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ 450 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 451 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ 452 /** 453 * @} 454 */ 455 456 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 457 * @{ 458 */ 459 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 460 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 461 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ 462 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ 463 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ 464 #define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ 465 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ 466 #define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ 467 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ 468 /** 469 * @} 470 */ 471 472 /** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source 473 * @{ 474 */ 475 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 476 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 477 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ 478 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ 479 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ 480 /** 481 * @} 482 */ 483 484 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 485 * @{ 486 */ 487 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock used as RTC clock */ 488 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 489 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 490 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 491 /** 492 * @} 493 */ 494 495 /** @defgroup RCC_MCO_Index MCO Index 496 * @{ 497 */ 498 #define RCC_MCO1 0x00000000U 499 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 500 /** 501 * @} 502 */ 503 504 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 505 * @{ 506 */ 507 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 508 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 509 #define RCC_MCO1SOURCE_MSI RCC_CFGR1_MCOSEL_1 /*!< MSI selection as MCO1 source */ 510 #define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ 511 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ 512 #define RCC_MCO1SOURCE_PLL1CLK (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_2) /*!< PLL1CLK selection as MCO1 source */ 513 #define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ 514 #define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSE selection as MCO1 source */ 515 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 516 #define RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ 517 /** 518 * @} 519 */ 520 521 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 522 * @{ 523 */ 524 #define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ 525 #define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ 526 #define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ 527 #define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_0 | RCC_CFGR1_MCOPRE_1)/*!< MCO is divided by 8 */ 528 #define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ 529 /** 530 * @} 531 */ 532 533 /** @defgroup RCC_Interrupt Interrupts 534 * @{ 535 */ 536 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 537 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 538 #define RCC_IT_MSIRDY RCC_CIFR_MSISRDYF /*!< MSI Ready Interrupt flag */ 539 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 540 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 541 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 542 #define RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 543 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 544 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ 545 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 546 #define RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF /*!< MSIK Ready Interrupt flag */ 547 #define RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF /*!< SHSI Ready Interrupt flag */ 548 /** 549 * @} 550 */ 551 552 /** @defgroup RCC_Flag Flags 553 * Elements values convention: XXXYYYYYb 554 * - YYYYY : Flag position in the register 555 * - XXX : Register index 556 * - 001: CR register 557 * - 010: BDCR register 558 * - 011: CSR register 559 * - 100: CRRCR register 560 * @{ 561 */ 562 /* Flags in the CR register */ 563 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSISRDY_Pos)) /*!< MSI Ready flag */ 564 #define RCC_FLAG_MSIKRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIKRDY_Pos)) /*!< MSI Ready flag */ 565 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 566 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 567 #define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL Ready flag */ 568 #define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ 569 #define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ 570 #define RCC_FLAG_SHSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_SHSIRDY_Pos)) /*!< SHSI Ready flag */ 571 #define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 572 573 /* Flags in the BDCR register */ 574 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 575 #define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ 576 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 577 #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ 578 579 /* Flags in the CSR register */ 580 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ 581 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ 582 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 583 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ 584 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 585 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 586 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 587 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 588 589 /** 590 * @} 591 */ 592 593 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 594 * @{ 595 */ 596 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 597 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 598 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 599 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 600 /** 601 * @} 602 */ 603 604 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 605 * @{ 606 */ 607 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 608 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ 609 /** 610 * @} 611 */ 612 613 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 614 * @{ 615 */ 616 #define RCC_STOP_KERWAKEUPCLOCK_MSI 0x00000000U /*!< MSI kernel clock selection after wake-up from STOP */ 617 #define RCC_STOP_KERWAKEUPCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI kernel clock selection after wake-up from STOP */ 618 619 /** 620 * @} 621 */ 622 623 /** @defgroup RCC_items RCC items 624 * @brief RCC items to configure attributes on 625 * @{ 626 */ 627 #define RCC_HSI RCC_SECCFGR_HSISEC 628 #define RCC_HSE RCC_SECCFGR_HSESEC 629 #define RCC_MSI RCC_SECCFGR_MSISEC 630 #define RCC_LSI RCC_SECCFGR_LSISEC 631 #define RCC_LSE RCC_SECCFGR_LSESEC 632 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 633 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 634 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 635 #define RCC_PLL2 RCC_SECCFGR_PLL2SEC 636 #define RCC_PLL3 RCC_SECCFGR_PLL3SEC 637 #define RCC_CLK48M RCC_SECCFGR_CLK48MSEC 638 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 639 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 640 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 641 RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ 642 RCC_PLL3|RCC_CLK48M|RCC_RMVF) 643 /** 644 * @} 645 */ 646 647 /** @defgroup RCC_attributes RCC attributes 648 * @brief RCC privilege/non-privilege and secure/non-secure attributes 649 * @{ 650 */ 651 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 652 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 653 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 654 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 655 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 656 #endif /* __ARM_FEATURE_CMSE */ 657 /** 658 * @} 659 */ 660 661 /* Exported macros -----------------------------------------------------------*/ 662 663 /** @defgroup RCC_Exported_Macros RCC Exported Macros 664 * @{ 665 */ 666 667 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 668 * @brief Enable or disable the AHB1 peripheral clock. 669 * @note After reset, the peripheral clock (used for registers read/write access) 670 * is disabled and the application software has to enable this clock before 671 * using it. 672 * @{ 673 */ 674 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 675 __IO uint32_t tmpreg; \ 676 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 677 /* Delay after an RCC peripheral clock enabling */ \ 678 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 679 UNUSED(tmpreg); \ 680 } while(0) 681 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 682 __IO uint32_t tmpreg; \ 683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 684 /* Delay after an RCC peripheral clock enabling */ \ 685 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 686 UNUSED(tmpreg); \ 687 } while(0) 688 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 689 __IO uint32_t tmpreg; \ 690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 691 /* Delay after an RCC peripheral clock enabling */ \ 692 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 693 UNUSED(tmpreg); \ 694 } while(0) 695 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 696 __IO uint32_t tmpreg; \ 697 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 698 /* Delay after an RCC peripheral clock enabling */ \ 699 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 700 UNUSED(tmpreg); \ 701 } while(0) 702 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 703 __IO uint32_t tmpreg; \ 704 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 705 /* Delay after an RCC peripheral clock enabling */ \ 706 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 707 UNUSED(tmpreg); \ 708 } while(0) 709 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 710 __IO uint32_t tmpreg; \ 711 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 712 /* Delay after an RCC peripheral clock enabling */ \ 713 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 714 UNUSED(tmpreg); \ 715 } while(0) 716 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 717 __IO uint32_t tmpreg; \ 718 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 719 /* Delay after an RCC peripheral clock enabling */ \ 720 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 721 UNUSED(tmpreg); \ 722 } while(0) 723 724 #define __HAL_RCC_MDF1_CLK_ENABLE() do { \ 725 __IO uint32_t tmpreg; \ 726 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 727 /* Delay after an RCC peripheral clock enabling */ \ 728 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 729 UNUSED(tmpreg); \ 730 } while(0) 731 732 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 733 __IO uint32_t tmpreg; \ 734 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 735 /* Delay after an RCC peripheral clock enabling */ \ 736 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 737 UNUSED(tmpreg); \ 738 } while(0) 739 740 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 741 __IO uint32_t tmpreg; \ 742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 743 /* Delay after an RCC peripheral clock enabling */ \ 744 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 745 UNUSED(tmpreg); \ 746 } while(0) 747 748 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 749 __IO uint32_t tmpreg; \ 750 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 751 /* Delay after an RCC peripheral clock enabling */ \ 752 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 753 UNUSED(tmpreg); \ 754 } while(0) 755 756 #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ 757 __IO uint32_t tmpreg; \ 758 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 759 /* Delay after an RCC peripheral clock enabling */ \ 760 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 761 UNUSED(tmpreg); \ 762 } while(0) 763 764 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 765 __IO uint32_t tmpreg; \ 766 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 767 /* Delay after an RCC peripheral clock enabling */ \ 768 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 769 UNUSED(tmpreg); \ 770 } while(0) 771 772 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 773 774 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 775 776 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 777 778 #define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) 779 780 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 781 782 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 783 784 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 785 786 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 787 788 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 789 790 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) 791 792 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) 793 794 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) 795 796 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 797 /** 798 * @} 799 */ 800 801 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 802 * @brief Enable or disable the AHB2 peripheral clock. 803 * @note After reset, the peripheral clock (used for registers read/write access) 804 * is disabled and the application software has to enable this clock before 805 * using it. 806 * @{ 807 */ 808 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 809 __IO uint32_t tmpreg; \ 810 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 811 /* Delay after an RCC peripheral clock enabling */ \ 812 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 813 UNUSED(tmpreg); \ 814 } while(0) 815 816 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 817 __IO uint32_t tmpreg; \ 818 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 819 /* Delay after an RCC peripheral clock enabling */ \ 820 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 821 UNUSED(tmpreg); \ 822 } while(0) 823 824 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 825 __IO uint32_t tmpreg; \ 826 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 827 /* Delay after an RCC peripheral clock enabling */ \ 828 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 829 UNUSED(tmpreg); \ 830 } while(0) 831 832 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 833 __IO uint32_t tmpreg; \ 834 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 835 /* Delay after an RCC peripheral clock enabling */ \ 836 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 837 UNUSED(tmpreg); \ 838 } while(0) 839 840 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 841 __IO uint32_t tmpreg; \ 842 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 843 /* Delay after an RCC peripheral clock enabling */ \ 844 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 845 UNUSED(tmpreg); \ 846 } while(0) 847 848 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 849 __IO uint32_t tmpreg; \ 850 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 851 /* Delay after an RCC peripheral clock enabling */ \ 852 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 853 UNUSED(tmpreg); \ 854 } while(0) 855 856 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 857 __IO uint32_t tmpreg; \ 858 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 859 /* Delay after an RCC peripheral clock enabling */ \ 860 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 861 UNUSED(tmpreg); \ 862 } while(0) 863 864 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 865 __IO uint32_t tmpreg; \ 866 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 867 /* Delay after an RCC peripheral clock enabling */ \ 868 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 869 UNUSED(tmpreg); \ 870 } while(0) 871 872 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 873 __IO uint32_t tmpreg; \ 874 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 875 /* Delay after an RCC peripheral clock enabling */ \ 876 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 877 UNUSED(tmpreg); \ 878 } while(0) 879 880 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 881 __IO uint32_t tmpreg; \ 882 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ 883 /* Delay after an RCC peripheral clock enabling */ \ 884 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ 885 UNUSED(tmpreg); \ 886 } while(0) 887 888 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 889 __IO uint32_t tmpreg; \ 890 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 891 /* Delay after an RCC peripheral clock enabling */ \ 892 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 893 UNUSED(tmpreg); \ 894 } while(0) 895 896 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 897 __IO uint32_t tmpreg; \ 898 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 899 /* Delay after an RCC peripheral clock enabling */ \ 900 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 901 UNUSED(tmpreg); \ 902 } while(0) 903 904 #if defined(AES) 905 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 906 __IO uint32_t tmpreg; \ 907 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 908 /* Delay after an RCC peripheral clock enabling */ \ 909 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 910 UNUSED(tmpreg); \ 911 } while(0) 912 #endif /* AES */ 913 914 #if defined(HASH) 915 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 916 __IO uint32_t tmpreg; \ 917 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 918 /* Delay after an RCC peripheral clock enabling */ \ 919 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 920 UNUSED(tmpreg); \ 921 } while(0) 922 #endif /* HASH */ 923 924 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 925 __IO uint32_t tmpreg; \ 926 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 927 /* Delay after an RCC peripheral clock enabling */ \ 928 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 929 UNUSED(tmpreg); \ 930 } while(0) 931 932 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 933 __IO uint32_t tmpreg; \ 934 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 935 /* Delay after an RCC peripheral clock enabling */ \ 936 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 937 UNUSED(tmpreg); \ 938 } while(0) 939 940 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 941 __IO uint32_t tmpreg; \ 942 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 943 /* Delay after an RCC peripheral clock enabling */ \ 944 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 945 UNUSED(tmpreg); \ 946 } while(0) 947 948 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 949 __IO uint32_t tmpreg; \ 950 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 951 /* Delay after an RCC peripheral clock enabling */ \ 952 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 953 UNUSED(tmpreg); \ 954 } while(0) 955 956 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 957 __IO uint32_t tmpreg; \ 958 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 959 /* Delay after an RCC peripheral clock enabling */ \ 960 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 961 UNUSED(tmpreg); \ 962 } while(0) 963 964 #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ 965 __IO uint32_t tmpreg; \ 966 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 967 /* Delay after an RCC peripheral clock enabling */ \ 968 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 969 UNUSED(tmpreg); \ 970 } while(0) 971 972 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 973 __IO uint32_t tmpreg; \ 974 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 975 /* Delay after an RCC peripheral clock enabling */ \ 976 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 977 UNUSED(tmpreg); \ 978 } while(0) 979 980 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 981 __IO uint32_t tmpreg; \ 982 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 983 /* Delay after an RCC peripheral clock enabling */ \ 984 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 985 UNUSED(tmpreg); \ 986 } while(0) 987 988 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 989 __IO uint32_t tmpreg; \ 990 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 991 /* Delay after an RCC peripheral clock enabling */ \ 992 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 993 UNUSED(tmpreg); \ 994 } while(0) 995 996 #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ 997 __IO uint32_t tmpreg; \ 998 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 999 /* Delay after an RCC peripheral clock enabling */ \ 1000 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 1001 UNUSED(tmpreg); \ 1002 } while(0) 1003 1004 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1005 __IO uint32_t tmpreg; \ 1006 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1007 /* Delay after an RCC peripheral clock enabling */ \ 1008 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1009 UNUSED(tmpreg); \ 1010 } while(0) 1011 1012 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1013 __IO uint32_t tmpreg; \ 1014 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1015 /* Delay after an RCC peripheral clock enabling */ \ 1016 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1017 UNUSED(tmpreg); \ 1018 } while(0) 1019 1020 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 1021 __IO uint32_t tmpreg; \ 1022 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1023 /* Delay after an RCC peripheral clock enabling */ \ 1024 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1025 UNUSED(tmpreg); \ 1026 } while(0) 1027 1028 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) 1029 1030 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) 1031 1032 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) 1033 1034 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) 1035 1036 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) 1037 1038 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) 1039 1040 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) 1041 1042 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) 1043 1044 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) 1045 1046 #define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) 1047 1048 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) 1049 1050 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) 1051 1052 #if defined(AES) 1053 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) 1054 #endif /* AES */ 1055 1056 #if defined(HASH) 1057 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) 1058 #endif /* HASH */ 1059 1060 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) 1061 1062 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) 1063 1064 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) 1065 1066 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) 1067 1068 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) 1069 1070 #define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) 1071 1072 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) 1073 1074 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) 1075 1076 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) 1077 1078 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) 1079 1080 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) 1081 1082 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) 1083 1084 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) 1085 /** 1086 * @} 1087 */ 1088 1089 /** @defgroup BUS AHB APB Peripheral Clock Enable Disable 1090 * @{ 1091 */ 1092 #define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); 1093 1094 #define __HAL_RCC_AHB2_1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); 1095 1096 #define __HAL_RCC_AHB2_2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); 1097 1098 #define __HAL_RCC_AHB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); 1099 1100 #define __HAL_RCC_APB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); 1101 1102 #define __HAL_RCC_APB2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); 1103 1104 #define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); 1105 1106 #define __HAL_RCC_AHB1_CLK_ENABLE() do { \ 1107 __IO uint32_t tmpreg; \ 1108 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1109 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1110 UNUSED(tmpreg); \ 1111 } while(0) 1112 1113 #define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ 1114 __IO uint32_t tmpreg; \ 1115 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1116 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1117 UNUSED(tmpreg); \ 1118 } while(0) 1119 1120 #define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ 1121 __IO uint32_t tmpreg; \ 1122 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1123 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1124 UNUSED(tmpreg); \ 1125 } while(0) 1126 1127 1128 #define __HAL_RCC_AHB3_CLK_ENABLE() do { \ 1129 __IO uint32_t tmpreg; \ 1130 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1131 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1132 UNUSED(tmpreg); \ 1133 } while(0) 1134 1135 #define __HAL_RCC_APB1_CLK_ENABLE() do { \ 1136 __IO uint32_t tmpreg; \ 1137 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1138 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1139 UNUSED(tmpreg); \ 1140 } while(0) 1141 1142 #define __HAL_RCC_APB2_CLK_ENABLE() do { \ 1143 __IO uint32_t tmpreg; \ 1144 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1145 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1146 UNUSED(tmpreg); \ 1147 } while(0) 1148 1149 #define __HAL_RCC_APB3_CLK_ENABLE() do { \ 1150 __IO uint32_t tmpreg; \ 1151 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1152 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1153 UNUSED(tmpreg); \ 1154 } while(0) 1155 1156 /** 1157 * @} 1158 */ 1159 1160 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3ENR Peripheral Clock Enable Disable 1161 * @brief Enable or disable the AHB3ENR peripheral clock. 1162 * @note After reset, the peripheral clock (used for registers read/write access) 1163 * is disabled and the application software has to enable this clock before 1164 * using it. 1165 * @{ 1166 */ 1167 #define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ 1168 __IO uint32_t tmpreg; \ 1169 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1170 /* Delay after an RCC peripheral clock enabling */ \ 1171 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1172 UNUSED(tmpreg); \ 1173 } while(0) 1174 1175 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1176 __IO uint32_t tmpreg; \ 1177 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1178 /* Delay after an RCC peripheral clock enabling */ \ 1179 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1180 UNUSED(tmpreg); \ 1181 } while(0) 1182 1183 #define __HAL_RCC_ADC4_CLK_ENABLE() do { \ 1184 __IO uint32_t tmpreg; \ 1185 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1186 /* Delay after an RCC peripheral clock enabling */ \ 1187 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1188 UNUSED(tmpreg); \ 1189 } while(0) 1190 1191 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1192 __IO uint32_t tmpreg; \ 1193 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1194 /* Delay after an RCC peripheral clock enabling */ \ 1195 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1196 UNUSED(tmpreg); \ 1197 } while(0) 1198 1199 #define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ 1200 __IO uint32_t tmpreg; \ 1201 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1202 /* Delay after an RCC peripheral clock enabling */ \ 1203 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1204 UNUSED(tmpreg); \ 1205 } while(0) 1206 1207 #define __HAL_RCC_ADF1_CLK_ENABLE() do { \ 1208 __IO uint32_t tmpreg; \ 1209 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1210 /* Delay after an RCC peripheral clock enabling */ \ 1211 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1212 UNUSED(tmpreg); \ 1213 } while(0) 1214 1215 #define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ 1216 __IO uint32_t tmpreg; \ 1217 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1218 /* Delay after an RCC peripheral clock enabling */ \ 1219 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1220 UNUSED(tmpreg); \ 1221 } while(0) 1222 1223 #define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ 1224 __IO uint32_t tmpreg; \ 1225 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1226 /* Delay after an RCC peripheral clock enabling */ \ 1227 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1228 UNUSED(tmpreg); \ 1229 } while(0) 1230 1231 #define __HAL_RCC_LPGPIO1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) 1232 1233 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) 1234 1235 #define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) 1236 1237 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) 1238 1239 #define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) 1240 1241 #define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) 1242 1243 #define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) 1244 1245 #define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) 1246 /** 1247 * @} 1248 */ 1249 1250 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1251 * @brief Enable or disable the APB1 peripheral clock. 1252 * @note After reset, the peripheral clock (used for registers read/write access) 1253 * is disabled and the application software has to enable this clock before 1254 * using it. 1255 * @{ 1256 */ 1257 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1258 __IO uint32_t tmpreg; \ 1259 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1260 /* Delay after an RCC peripheral clock enabling */ \ 1261 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1262 UNUSED(tmpreg); \ 1263 } while(0) 1264 1265 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1266 __IO uint32_t tmpreg; \ 1267 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1268 /* Delay after an RCC peripheral clock enabling */ \ 1269 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1270 UNUSED(tmpreg); \ 1271 } while(0) 1272 1273 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1274 __IO uint32_t tmpreg; \ 1275 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1276 /* Delay after an RCC peripheral clock enabling */ \ 1277 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1278 UNUSED(tmpreg); \ 1279 } while(0) 1280 1281 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1282 __IO uint32_t tmpreg; \ 1283 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1284 /* Delay after an RCC peripheral clock enabling */ \ 1285 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1286 UNUSED(tmpreg); \ 1287 } while(0) 1288 1289 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1290 __IO uint32_t tmpreg; \ 1291 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1292 /* Delay after an RCC peripheral clock enabling */ \ 1293 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1294 UNUSED(tmpreg); \ 1295 } while(0) 1296 1297 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1298 __IO uint32_t tmpreg; \ 1299 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1300 /* Delay after an RCC peripheral clock enabling */ \ 1301 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1302 UNUSED(tmpreg); \ 1303 } while(0) 1304 1305 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1306 __IO uint32_t tmpreg; \ 1307 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1308 /* Delay after an RCC peripheral clock enabling */ \ 1309 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1310 UNUSED(tmpreg); \ 1311 } while(0) 1312 1313 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1314 __IO uint32_t tmpreg; \ 1315 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1316 /* Delay after an RCC peripheral clock enabling */ \ 1317 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1318 UNUSED(tmpreg); \ 1319 } while(0) 1320 1321 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1322 __IO uint32_t tmpreg; \ 1323 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1324 /* Delay after an RCC peripheral clock enabling */ \ 1325 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1326 UNUSED(tmpreg); \ 1327 } while(0) 1328 1329 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1330 __IO uint32_t tmpreg; \ 1331 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1332 /* Delay after an RCC peripheral clock enabling */ \ 1333 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1334 UNUSED(tmpreg); \ 1335 } while(0) 1336 1337 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1338 __IO uint32_t tmpreg; \ 1339 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1340 /* Delay after an RCC peripheral clock enabling */ \ 1341 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1342 UNUSED(tmpreg); \ 1343 } while(0) 1344 1345 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1346 __IO uint32_t tmpreg; \ 1347 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1348 /* Delay after an RCC peripheral clock enabling */ \ 1349 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1350 UNUSED(tmpreg); \ 1351 } while(0) 1352 1353 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1354 __IO uint32_t tmpreg; \ 1355 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1356 /* Delay after an RCC peripheral clock enabling */ \ 1357 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1358 UNUSED(tmpreg); \ 1359 } while(0) 1360 1361 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1362 __IO uint32_t tmpreg; \ 1363 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1364 /* Delay after an RCC peripheral clock enabling */ \ 1365 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1366 UNUSED(tmpreg); \ 1367 } while(0) 1368 1369 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1370 __IO uint32_t tmpreg; \ 1371 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1372 /* Delay after an RCC peripheral clock enabling */ \ 1373 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1374 UNUSED(tmpreg); \ 1375 } while(0) 1376 1377 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1378 __IO uint32_t tmpreg; \ 1379 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1380 /* Delay after an RCC peripheral clock enabling */ \ 1381 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1382 UNUSED(tmpreg); \ 1383 } while(0) 1384 1385 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 1386 __IO uint32_t tmpreg; \ 1387 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ 1388 /* Delay after an RCC peripheral clock enabling */ \ 1389 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ 1390 UNUSED(tmpreg); \ 1391 } while(0) 1392 1393 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1394 __IO uint32_t tmpreg; \ 1395 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1396 /* Delay after an RCC peripheral clock enabling */ \ 1397 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1398 UNUSED(tmpreg); \ 1399 } while(0) 1400 1401 #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ 1402 __IO uint32_t tmpreg; \ 1403 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1404 /* Delay after an RCC peripheral clock enabling */ \ 1405 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1406 UNUSED(tmpreg); \ 1407 } while(0) 1408 1409 #define __HAL_RCC_UCPD_CLK_ENABLE() do { \ 1410 __IO uint32_t tmpreg; \ 1411 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1412 /* Delay after an RCC peripheral clock enabling */ \ 1413 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1414 UNUSED(tmpreg); \ 1415 } while(0) 1416 1417 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1418 1419 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1420 1421 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1422 1423 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1424 1425 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1426 1427 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1428 1429 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) 1430 1431 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1432 1433 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1434 1435 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1436 1437 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1438 1439 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1440 1441 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1442 1443 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1444 1445 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) 1446 1447 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1448 1449 #define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2 , RCC_APB1ENR2_DTSEN) 1450 1451 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1452 1453 #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) 1454 1455 #define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) 1456 /** 1457 * @} 1458 */ 1459 1460 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1461 * @brief Enable or disable the APB2 peripheral clock. 1462 * @note After reset, the peripheral clock (used for registers read/write access) 1463 * is disabled and the application software has to enable this clock before 1464 * using it. 1465 * @{ 1466 */ 1467 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1468 __IO uint32_t tmpreg; \ 1469 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1470 /* Delay after an RCC peripheral clock enabling */ \ 1471 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1472 UNUSED(tmpreg); \ 1473 } while(0) 1474 1475 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1476 __IO uint32_t tmpreg; \ 1477 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1478 /* Delay after an RCC peripheral clock enabling */ \ 1479 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1480 UNUSED(tmpreg); \ 1481 } while(0) 1482 1483 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1484 __IO uint32_t tmpreg; \ 1485 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1486 /* Delay after an RCC peripheral clock enabling */ \ 1487 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1488 UNUSED(tmpreg); \ 1489 } while(0) 1490 1491 1492 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1493 __IO uint32_t tmpreg; \ 1494 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1495 /* Delay after an RCC peripheral clock enabling */ \ 1496 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1497 UNUSED(tmpreg); \ 1498 } while(0) 1499 1500 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1501 __IO uint32_t tmpreg; \ 1502 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1503 /* Delay after an RCC peripheral clock enabling */ \ 1504 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1505 UNUSED(tmpreg); \ 1506 } while(0) 1507 1508 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1509 __IO uint32_t tmpreg; \ 1510 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1511 /* Delay after an RCC peripheral clock enabling */ \ 1512 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1513 UNUSED(tmpreg); \ 1514 } while(0) 1515 1516 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1517 __IO uint32_t tmpreg; \ 1518 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1519 /* Delay after an RCC peripheral clock enabling */ \ 1520 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1521 UNUSED(tmpreg); \ 1522 } while(0) 1523 1524 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1525 __IO uint32_t tmpreg; \ 1526 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1527 /* Delay after an RCC peripheral clock enabling */ \ 1528 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1529 UNUSED(tmpreg); \ 1530 } while(0) 1531 1532 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1533 __IO uint32_t tmpreg; \ 1534 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1535 /* Delay after an RCC peripheral clock enabling */ \ 1536 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1537 UNUSED(tmpreg); \ 1538 } while(0) 1539 1540 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1541 1542 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1543 1544 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1545 1546 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1547 1548 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1549 1550 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1551 1552 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1553 1554 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1555 1556 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1557 /** 1558 * @} 1559 */ 1560 1561 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1562 * @brief Enable or disable the APB3 peripheral clock. 1563 * @note After reset, the peripheral clock (used for registers read/write access) 1564 * is disabled and the application software has to enable this clock before 1565 * using it. 1566 * @{ 1567 */ 1568 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1569 __IO uint32_t tmpreg; \ 1570 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1571 /* Delay after an RCC peripheral clock enabling */ \ 1572 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1573 UNUSED(tmpreg); \ 1574 } while(0) 1575 1576 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1577 __IO uint32_t tmpreg; \ 1578 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1579 /* Delay after an RCC peripheral clock enabling */ \ 1580 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1581 UNUSED(tmpreg); \ 1582 } while(0) 1583 1584 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1585 __IO uint32_t tmpreg; \ 1586 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1587 /* Delay after an RCC peripheral clock enabling */ \ 1588 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1589 UNUSED(tmpreg); \ 1590 } while(0) 1591 1592 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1593 __IO uint32_t tmpreg; \ 1594 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1595 /* Delay after an RCC peripheral clock enabling */ \ 1596 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1597 UNUSED(tmpreg); \ 1598 } while(0) 1599 1600 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1601 __IO uint32_t tmpreg; \ 1602 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1603 /* Delay after an RCC peripheral clock enabling */ \ 1604 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1605 UNUSED(tmpreg); \ 1606 } while(0) 1607 1608 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1609 __IO uint32_t tmpreg; \ 1610 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1611 /* Delay after an RCC peripheral clock enabling */ \ 1612 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1613 UNUSED(tmpreg); \ 1614 } while(0) 1615 1616 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1617 __IO uint32_t tmpreg; \ 1618 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1619 /* Delay after an RCC peripheral clock enabling */ \ 1620 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1621 UNUSED(tmpreg); \ 1622 } while(0) 1623 1624 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1625 __IO uint32_t tmpreg; \ 1626 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1627 /* Delay after an RCC peripheral clock enabling */ \ 1628 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1629 UNUSED(tmpreg); \ 1630 } while(0) 1631 1632 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1633 __IO uint32_t tmpreg; \ 1634 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1635 /* Delay after an RCC peripheral clock enabling */ \ 1636 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1637 UNUSED(tmpreg); \ 1638 } while(0) 1639 1640 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1641 __IO uint32_t tmpreg; \ 1642 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1643 /* Delay after an RCC peripheral clock enabling */ \ 1644 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1645 UNUSED(tmpreg); \ 1646 } while(0) 1647 1648 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1649 __IO uint32_t tmpreg; \ 1650 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1651 /* Delay after an RCC peripheral clock enabling */ \ 1652 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1653 UNUSED(tmpreg); \ 1654 } while(0) 1655 1656 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) 1657 1658 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) 1659 1660 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) 1661 1662 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) 1663 1664 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) 1665 1666 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) 1667 1668 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) 1669 1670 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) 1671 1672 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) 1673 1674 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) 1675 1676 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) 1677 /** 1678 * @} 1679 */ 1680 1681 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1682 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1683 * @note After reset, the peripheral clock (used for registers read/write access) 1684 * is disabled and the application software has to enable this clock before 1685 * using it. 1686 * @{ 1687 */ 1688 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 1689 1690 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 1691 1692 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 1693 1694 #define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U) 1695 1696 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1697 1698 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1699 1700 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1701 1702 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 1703 1704 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 1705 1706 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) 1707 1708 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) != 0U) 1709 1710 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) 1711 1712 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 1713 1714 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) 1715 1716 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 1717 1718 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 1719 1720 #define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U) 1721 1722 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1723 1724 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1725 1726 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 1727 1728 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) 1729 1730 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 1731 1732 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) 1733 1734 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) == 0U) 1735 1736 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) 1737 1738 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) 1739 /** 1740 * @} 1741 */ 1742 1743 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1744 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1745 * @note After reset, the peripheral clock (used for registers read/write access) 1746 * is disabled and the application software has to enable this clock before 1747 * using it. 1748 * @{ 1749 */ 1750 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) != 0U) 1751 1752 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) != 0U) 1753 1754 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) != 0U) 1755 1756 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) != 0U) 1757 1758 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) 1759 1760 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) 1761 1762 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) 1763 1764 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) 1765 1766 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) 1767 1768 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) != 0U) 1769 1770 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) 1771 1772 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) 1773 1774 #if defined(AES) 1775 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) 1776 #endif /* AES */ 1777 1778 #if defined(HASH) 1779 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) != 0U) 1780 #endif /* HASH */ 1781 1782 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U) 1783 1784 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) 1785 1786 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) 1787 1788 #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) 1789 1790 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) 1791 1792 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) 1793 1794 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) 1795 1796 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) 1797 1798 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) 1799 1800 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) 1801 1802 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) 1803 1804 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) 1805 1806 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) 1807 1808 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) 1809 1810 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) == 0U) 1811 1812 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) == 0U) 1813 1814 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) == 0U) 1815 1816 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) 1817 1818 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) 1819 1820 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) 1821 1822 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) 1823 1824 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) 1825 1826 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) == 0U) 1827 1828 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) 1829 1830 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) 1831 1832 #if defined(AES) 1833 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) 1834 #endif /* AES */ 1835 1836 #if defined(HASH) 1837 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) == 0U) 1838 #endif /* HASH */ 1839 1840 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U) 1841 1842 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) 1843 1844 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) 1845 1846 #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) 1847 1848 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) 1849 1850 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) 1851 1852 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) 1853 1854 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) 1855 1856 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) 1857 1858 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) 1859 1860 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) 1861 1862 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) 1863 1864 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) 1865 /** 1866 * @} 1867 */ 1868 1869 /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1870 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1871 * @note After reset, the peripheral clock (used for registers read/write access) 1872 * is disabled and the application software has to enable this clock before 1873 * using it. 1874 * @{ 1875 */ 1876 #define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) != 0U) 1877 1878 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U) 1879 1880 #define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U) 1881 1882 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U) 1883 1884 #define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) != 0U) 1885 1886 #define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U) 1887 1888 #define __HAL_RCC_GTZC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0U) 1889 1890 #define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0U) 1891 1892 #define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) == 0U) 1893 1894 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U) 1895 1896 #define __HAL_RCC_ADC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U) 1897 1898 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U) 1899 1900 #define __HAL_RCC_LPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) == 0U) 1901 1902 #define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U) 1903 1904 #define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) 1905 1906 #define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) 1907 /** 1908 * @} 1909 */ 1910 1911 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1912 * @brief Check whether the APB1 peripheral clock is enabled or not. 1913 * @note After reset, the peripheral clock (used for registers read/write access) 1914 * is disabled and the application software has to enable this clock before 1915 * using it. 1916 * @{ 1917 */ 1918 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1919 1920 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1921 1922 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1923 1924 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1925 1926 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1927 1928 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1929 1930 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1931 1932 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1933 1934 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1935 1936 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1937 1938 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1939 1940 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1941 1942 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1943 1944 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1945 1946 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1947 1948 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1949 1950 #define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) != 0U) 1951 1952 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1953 1954 #define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) 1955 1956 #define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) 1957 1958 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1959 1960 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1961 1962 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1963 1964 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 1965 1966 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 1967 1968 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 1969 1970 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 1971 1972 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 1973 1974 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 1975 1976 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 1977 1978 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 1979 1980 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 1981 1982 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 1983 1984 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 1985 1986 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 1987 1988 #define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) == 0U) 1989 1990 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 1991 1992 #define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) 1993 1994 #define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) 1995 /** 1996 * @} 1997 */ 1998 1999 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2000 * @brief Check whether the APB2 peripheral clock is enabled or not. 2001 * @note After reset, the peripheral clock (used for registers read/write access) 2002 * is disabled and the application software has to enable this clock before 2003 * using it. 2004 * @{ 2005 */ 2006 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2007 2008 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2009 2010 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2011 2012 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2013 2014 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2015 2016 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2017 2018 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2019 2020 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2021 2022 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2023 2024 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2025 2026 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2027 2028 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2029 2030 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2031 2032 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2033 2034 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2035 2036 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2037 2038 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2039 2040 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2041 /** 2042 * @} 2043 */ 2044 2045 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 2046 * @brief Check whether the APB3 peripheral clock is enabled or not. 2047 * @note After reset, the peripheral clock (used for registers read/write access) 2048 * is disabled and the application software has to enable this clock before 2049 * using it. 2050 * @{ 2051 */ 2052 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) != 0U) 2053 2054 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) != 0U) 2055 2056 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) 2057 2058 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) 2059 2060 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) 2061 2062 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) 2063 2064 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) 2065 2066 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) != 0U) 2067 2068 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) != 0U) 2069 2070 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) 2071 2072 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) 2073 2074 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) == 0U) 2075 2076 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) == 0U) 2077 2078 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) 2079 2080 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) 2081 2082 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) 2083 2084 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) 2085 2086 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) 2087 2088 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) == 0U) 2089 2090 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) == 0U) 2091 2092 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) 2093 2094 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) 2095 /** 2096 * @} 2097 */ 2098 2099 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2100 * @brief Force or release AHB1 peripheral reset. 2101 * @{ 2102 */ 2103 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) 2104 2105 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2106 2107 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2108 2109 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2110 2111 #define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2112 2113 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2114 2115 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2116 2117 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2118 2119 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2120 2121 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2122 2123 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2124 2125 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2126 2127 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2128 2129 #define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2130 2131 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2132 2133 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2134 2135 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2136 2137 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2138 /** 2139 * @} 2140 */ 2141 2142 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2143 * @brief Force or release AHB2 peripheral reset. 2144 * @{ 2145 */ 2146 #define __HAL_RCC_AHB2_FORCE_RESET() do{\ 2147 WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ 2148 WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ 2149 }while(0) 2150 2151 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2152 2153 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2154 2155 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2156 2157 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2158 2159 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2160 2161 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2162 2163 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2164 2165 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2166 2167 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2168 2169 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) 2170 2171 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2172 2173 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2174 2175 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2176 2177 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2178 2179 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2180 2181 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2182 2183 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2184 2185 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2186 2187 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2188 2189 #define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2190 2191 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2192 2193 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2194 2195 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2196 2197 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2198 2199 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2200 2201 #define __HAL_RCC_AHB2_RELEASE_RESET() do{\ 2202 WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ 2203 WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ 2204 }while(0) 2205 2206 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2207 2208 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2209 2210 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2211 2212 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2213 2214 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2215 2216 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2217 2218 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2219 2220 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2221 2222 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2223 2224 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) 2225 2226 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2227 2228 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2229 2230 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2231 2232 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2233 2234 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2235 2236 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2237 2238 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2239 2240 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2241 2242 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2243 2244 #define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2245 2246 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2247 2248 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2249 2250 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2251 2252 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2253 2254 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2255 /** 2256 * @} 2257 */ 2258 2259 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2260 * @brief Force or release AHB3 peripheral reset. 2261 * @{ 2262 */ 2263 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000661U) 2264 2265 #define __HAL_RCC_LPGPIO1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2266 2267 #define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2268 2269 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2270 2271 #define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2272 2273 #define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2274 2275 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 2276 2277 #define __HAL_RCC_LPGPIO1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2278 2279 #define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2280 2281 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2282 2283 #define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2284 2285 #define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2286 /** 2287 * @} 2288 */ 2289 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2290 * @brief Force or release APB1 peripheral reset. 2291 * @{ 2292 */ 2293 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 2294 WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ 2295 WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ 2296 } while(0) 2297 2298 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2299 2300 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2301 2302 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2303 2304 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2305 2306 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2307 2308 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2309 2310 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2311 2312 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2313 2314 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2315 2316 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2317 2318 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2319 2320 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2321 2322 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2323 2324 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2325 2326 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2327 2328 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2329 2330 #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 2331 2332 #define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2333 2334 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 2335 WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ 2336 WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ 2337 } while(0) 2338 2339 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2340 2341 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2342 2343 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2344 2345 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2346 2347 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2348 2349 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2350 2351 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2352 2353 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2354 2355 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2356 2357 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2358 2359 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2360 2361 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2362 2363 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2364 2365 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2366 2367 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2368 2369 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2370 2371 #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 2372 2373 #define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2374 /** 2375 * @} 2376 */ 2377 2378 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 2379 * @brief Force or release APB2 peripheral reset. 2380 * @{ 2381 */ 2382 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00677800U) 2383 2384 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2385 2386 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2387 2388 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2389 2390 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2391 2392 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2393 2394 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2395 2396 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2397 2398 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2399 2400 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2401 2402 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 2403 2404 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2405 2406 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2407 2408 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2409 2410 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2411 2412 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2413 2414 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2415 2416 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2417 2418 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2419 2420 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2421 /** 2422 * @} 2423 */ 2424 2425 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 2426 * @brief Force or release APB3 peripheral reset. 2427 * @{ 2428 */ 2429 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x0010F8E2U) 2430 2431 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 2432 2433 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 2434 2435 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 2436 2437 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 2438 2439 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 2440 2441 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 2442 2443 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 2444 2445 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 2446 2447 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 2448 2449 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 2450 2451 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) 2452 2453 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 2454 2455 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 2456 2457 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 2458 2459 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 2460 2461 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 2462 2463 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 2464 2465 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 2466 2467 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 2468 2469 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 2470 2471 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 2472 /** 2473 * @} 2474 */ 2475 2476 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2477 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. 2478 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2479 * power consumption. 2480 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2481 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2482 * is enabled only when a peripheral requests AHB clock. 2483 * @{ 2484 */ 2485 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 2486 2487 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 2488 2489 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 2490 2491 #define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 2492 2493 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2494 2495 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2496 2497 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2498 2499 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 2500 2501 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2502 2503 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 2504 2505 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 2506 2507 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2508 2509 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 2510 2511 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2512 2513 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 2514 2515 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 2516 2517 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 2518 2519 #define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 2520 2521 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2522 2523 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2524 2525 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2526 2527 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 2528 2529 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2530 2531 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 2532 2533 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 2534 2535 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2536 2537 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 2538 2539 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2540 /** 2541 * @} 2542 */ 2543 2544 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2545 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. 2546 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2547 * power consumption. 2548 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2549 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2550 * is enabled only when a peripheral requests AHB clock. 2551 * @{ 2552 */ 2553 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 2554 2555 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 2556 2557 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 2558 2559 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 2560 2561 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 2562 2563 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 2564 2565 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 2566 2567 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 2568 2569 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 2570 2571 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) 2572 2573 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 2574 2575 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 2576 2577 #if defined(AES) 2578 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); 2579 #endif /* AES */ 2580 2581 #if defined(HASH) 2582 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 2583 #endif /* HASH */ 2584 2585 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 2586 2587 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 2588 2589 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 2590 2591 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 2592 2593 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 2594 2595 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 2596 2597 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 2598 2599 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 2600 2601 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 2602 2603 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 2604 2605 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 2606 2607 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 2608 2609 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 2610 2611 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 2612 2613 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 2614 2615 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 2616 2617 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 2618 2619 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 2620 2621 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 2622 2623 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 2624 2625 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 2626 2627 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 2628 2629 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) 2630 2631 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 2632 2633 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 2634 2635 #if defined(AES) 2636 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); 2637 #endif /* AES */ 2638 2639 #if defined(HASH) 2640 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 2641 #endif /* HASH */ 2642 2643 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 2644 2645 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 2646 2647 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 2648 2649 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 2650 2651 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 2652 2653 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 2654 2655 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 2656 2657 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 2658 2659 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 2660 2661 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 2662 2663 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 2664 2665 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 2666 2667 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 2668 /** 2669 * @} 2670 */ 2671 2672 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3SMENR Peripheral Clock Sleep Enable Disable 2673 * @brief Enable or disable the AHB3SMENR peripheral clock during Low Power (Sleep and STOP ) mode. 2674 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2675 * power consumption. 2676 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2677 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2678 * is enabled only when a peripheral requests AHB clock. 2679 * @{ 2680 */ 2681 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 2682 2683 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 2684 2685 #define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 2686 2687 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 2688 2689 #define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 2690 2691 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 2692 2693 #define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 2694 2695 #define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 2696 2697 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 2698 2699 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 2700 2701 #define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 2702 2703 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 2704 2705 #define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 2706 2707 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 2708 2709 #define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 2710 2711 #define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 2712 /** 2713 * @} 2714 */ 2715 2716 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2717 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. 2718 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2719 * power consumption. 2720 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2721 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2722 * is enabled only when a peripheral requests APB clock. 2723 * @{ 2724 */ 2725 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2726 2727 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2728 2729 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2730 2731 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2732 2733 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2734 2735 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2736 2737 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2738 2739 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2740 2741 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2742 2743 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2744 2745 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2746 2747 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2748 2749 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2750 2751 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2752 2753 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2754 2755 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2756 2757 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2758 2759 #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2760 2761 #define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2762 2763 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2764 2765 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2766 2767 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2768 2769 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2770 2771 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2772 2773 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2774 2775 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2776 2777 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2778 2779 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2780 2781 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2782 2783 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2784 2785 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2786 2787 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2788 2789 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2790 2791 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2792 2793 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2794 2795 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2796 2797 #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2798 2799 #define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2800 /** 2801 * @} 2802 */ 2803 2804 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. 2806 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2807 * power consumption. 2808 * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. 2809 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2810 * is enabled only when a peripheral requests APB clock. 2811 * @{ 2812 */ 2813 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2814 2815 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2816 2817 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2818 2819 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2820 2821 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2822 2823 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2824 2825 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2826 2827 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2828 2829 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2830 2831 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2832 2833 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2834 2835 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2836 2837 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2838 2839 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2840 2841 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2842 2843 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2844 2845 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2846 2847 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2848 2849 /** 2850 * @} 2851 */ 2852 2853 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 2854 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep and Stop) mode. 2855 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 2856 * power consumption. 2857 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 2858 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 2859 * is enabled only when a peripheral requests APB clock. 2860 * @{ 2861 */ 2862 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 2863 2864 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 2865 2866 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 2867 2868 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 2869 2870 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 2871 2872 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 2873 2874 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 2875 2876 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 2877 2878 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 2879 2880 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 2881 2882 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 2883 2884 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 2885 2886 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 2887 2888 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 2889 2890 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 2891 2892 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 2893 2894 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 2895 2896 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 2897 2898 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 2899 2900 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 2901 2902 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 2903 2904 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 2905 /** 2906 * @} 2907 */ 2908 2909 /** @brief Enable or disable peripheral bus clock when SRD domain is in DRUN 2910 * @note After reset, peripheral clock is disabled when CPUs are in CSTOP 2911 * @{ 2912 */ 2913 #define __HAL_RCC_SPI3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 2914 2915 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 2916 2917 #define __HAL_RCC_I2C3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 2918 2919 #define __HAL_RCC_LPTIM1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 2920 2921 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 2922 2923 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 2924 2925 #define __HAL_RCC_OPAMP_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 2926 2927 #define __HAL_RCC_COMP12_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 2928 2929 #define __HAL_RCC_ADC4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 2930 2931 #define __HAL_RCC_VREF_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 2932 2933 #define __HAL_RCC_RTCAPB_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 2934 2935 #define __HAL_RCC_LPGPIO1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 2936 2937 #define __HAL_RCC_DAC1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 2938 2939 #define __HAL_RCC_LPDMA1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 2940 2941 #define __HAL_RCC_ADF1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 2942 2943 #define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 2944 2945 2946 #define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 2947 2948 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 2949 2950 #define __HAL_RCC_I2C3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 2951 2952 #define __HAL_RCC_LPTIM1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 2953 2954 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 2955 2956 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 2957 2958 #define __HAL_RCC_OPAMP_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 2959 2960 #define __HAL_RCC_COMP12_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 2961 2962 #define __HAL_RCC_ADC4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 2963 2964 #define __HAL_RCC_VREF_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 2965 2966 #define __HAL_RCC_RTCAPB_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 2967 2968 #define __HAL_RCC_LPGPIO1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 2969 2970 #define __HAL_RCC_DAC1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 2971 2972 #define __HAL_RCC_LPDMA1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 2973 2974 #define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 2975 2976 #define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 2977 /** 2978 * @} 2979 */ 2980 2981 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2982 * @{ 2983 */ 2984 2985 /** @brief Macros to force or release the Backup domain reset. 2986 * @note This function resets the RTC peripheral (including the backup registers) 2987 * and the RTC clock source selection in RCC_CSR register. 2988 * @note The BKPSRAM is not affected by this reset. 2989 * @retval None 2990 */ 2991 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2992 2993 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2994 2995 /** 2996 * @} 2997 */ 2998 2999 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 3000 * @{ 3001 */ 3002 3003 /** @brief Macros to enable or disable the RTC clock. 3004 * @note As the RTC is in the Backup domain and write access is denied to 3005 * this domain after reset, you have to enable write access using 3006 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 3007 * (to be done once after reset). 3008 * @note These macros must be used after the RTC clock source was selected. 3009 * @retval None 3010 */ 3011 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3012 3013 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3014 3015 /** 3016 * @} 3017 */ 3018 3019 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 3020 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3021 * It is used (enabled by hardware) as system clock source after startup 3022 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3023 * of the HSE used directly or indirectly as system clock (if the Clock 3024 * Security System CSS is enabled). 3025 * @note HSI can not be stopped if it is used as system clock source. In this case, 3026 * you have to select another source of the system clock then stop the HSI. 3027 * @note After enabling the HSI, the application software should wait on HSIRDY 3028 * flag to be set indicating that HSI clock is stable and can be used as 3029 * system clock source. 3030 * This parameter can be: ENABLE or DISABLE. 3031 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3032 * clock cycles. 3033 * @retval None 3034 */ 3035 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3036 3037 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3038 3039 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 3040 * @note The calibration is used to compensate for the variations in voltage 3041 * and temperature that influence the frequency of the internal HSI RC. 3042 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 3043 * (default is RCC_HSICALIBRATION_DEFAULT). 3044 * This parameter must be a number between 0 and 0x20. 3045 * @retval None 3046 */ 3047 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3048 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) 3049 3050 3051 /** 3052 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3053 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3054 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3055 * speed because of the HSI startup time. 3056 * @note The enable of this function has not effect on the HSION bit. 3057 * This parameter can be: ENABLE or DISABLE. 3058 * @retval None 3059 */ 3060 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3061 3062 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3063 3064 /** 3065 * @brief Macros to enable or disable the force of the Internal Multi Speed kernel oscillator (MSIK) 3066 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3067 * @note Keeping the MSIK ON in STOP mode allows to avoid slowing down the communication 3068 * speed because of the MSIK startup time. 3069 * @note The enable of this function has not effect on the MSIKON bit. 3070 * @note The MSIKERON must be configured at 0 before entreing stop 3 mode. 3071 * This parameter can be: ENABLE or DISABLE. 3072 * @retval None 3073 */ 3074 #define __HAL_RCC_MSIKSTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKERON) 3075 3076 #define __HAL_RCC_MSIKSTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON) 3077 3078 /** 3079 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 3080 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3081 * It is used (enabled by hardware) as system clock source after 3082 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 3083 * of failure of the HSE used directly or indirectly as system clock 3084 * (if the Clock Security System CSS is enabled). 3085 * @note MSI can not be stopped if it is used as system clock source. 3086 * In this case, you have to select another source of the system 3087 * clock then stop the MSI. 3088 * @note After enabling the MSI, the application software should wait on 3089 * MSIRDY flag to be set indicating that MSI clock is stable and can 3090 * be used as system clock source. 3091 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3092 * clock cycles. 3093 * @retval None 3094 */ 3095 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSISON) 3096 3097 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSISON) 3098 3099 /** 3100 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 3101 * @note After restart from Reset , the MSI clock is around 4 MHz. 3102 * After stop the startup clock can be MSI (at any of its possible 3103 * frequencies, the one that was used before entering stop mode) or HSI. 3104 * After Standby its frequency can be selected between 4 possible values 3105 * (1, 3.072, 4 or 8 MHz). 3106 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 3107 * (MSIRDY=1). 3108 * @note The MSI clock range after reset can be modified on the fly. 3109 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3110 * This parameter must be one of the following values: 3111 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3112 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3113 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3114 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3115 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3116 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3117 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3118 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3119 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3120 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 3121 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 3122 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 3123 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 3124 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 3125 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 3126 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 3127 * @retval None 3128 */ 3129 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 3130 do { \ 3131 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 3132 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ 3133 } while(0) 3134 /** 3135 * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 3136 * @note After restart from Reset , the MSIK clock is around 4 MHz. 3137 * After stop the startup clock can be MSIK (at any of its possible 3138 * frequencies, the one that was used before entering stop mode) or HSI. 3139 * After Standby its frequency can be selected between 4 possible values 3140 * (1, 3.072, 4 or 8 MHz). 3141 * @note MSIKRANGE can be modified when MSIK is OFF (MSIKON=0) or when MSIK is ready 3142 * (MSIKRDY=1). 3143 * @note The MSI clock range after reset can be modified on the fly. 3144 * @param __MSIKRANGEVALUE__: specifies the MSI clock range. 3145 * @arg @ref RCC_MSIKRANGE_0 MSIK clock is around 48 MHz 3146 * @arg @ref RCC_MSIKRANGE_1 MSIK clock is around 24 KHz 3147 * @arg @ref RCC_MSIKRANGE_2 MSIK clock is around 16 MHz 3148 * @arg @ref RCC_MSIKRANGE_3 MSIK clock is around 12 MHz 3149 * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) 3150 * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz 3151 * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz 3152 * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz 3153 * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz 3154 * @arg @ref RCC_MSIKRANGE_9 MSIK clock is around 1.536 MHz 3155 * @arg @ref RCC_MSIKRANGE_10 MSIK clock is around 1.024 MHz 3156 * @arg @ref RCC_MSIKRANGE_11 MSIK clock is around 768 KHz 3157 * @arg @ref RCC_MSIKRANGE_12 MSIK clock is around 400 KHz 3158 * @arg @ref RCC_MSIKRANGE_13 MSIK clock is around 200 KHz 3159 * @arg @ref RCC_MSIKRANGE_14 MSIK clock is around 133 KHz 3160 * @arg @ref RCC_MSIKRANGE_15 MSIK clock is around 100 KHz 3161 * @retval None 3162 */ 3163 #define __HAL_RCC_MSIK_RANGE_CONFIG(__MSIKRANGEVALUE__) \ 3164 do { \ 3165 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 3166 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, (__MSIKRANGEVALUE__)); \ 3167 } while(0) 3168 3169 /** @brief Macros to enable or disable the MSI bias mode selection. 3170 * @note By default the MSI bias is in continuous mode in order to maintain 3171 * the output clocks accuracy. 3172 * @note Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. 3173 * @retval None 3174 */ 3175 #define __HAL_RCC_MSIBIAS_SELECTION_ENABLE() SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 3176 3177 #define __HAL_RCC_MSIBIAS_SELECTION_DISABLE() CLEAR_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 3178 3179 /** @brief Macros to enable or disable LSE clock glitch filter . 3180 * @note The glitches on LSE can be filtred by setting the LSEGFON. 3181 * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). 3182 * @retval None 3183 */ 3184 3185 #define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 3186 3187 #define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 3188 /** 3189 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 3190 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). 3191 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3192 * This parameter must be one of the following values: 3193 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3194 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3195 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz 3196 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3197 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3198 * @retval None 3199 */ 3200 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);\ 3201 MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ 3202 (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ 3203 RCC_CSR_MSISSRANGE_Pos));\ 3204 } while(0) 3205 /** 3206 * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode 3207 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). 3208 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3209 * This parameter must be one of the following values: 3210 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3211 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3212 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz 3213 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3214 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3215 * @retval None 3216 */ 3217 #define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 3218 MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ 3219 (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ 3220 RCC_CSR_MSISSRANGE_Pos));\ 3221 } while(0) 3222 3223 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 3224 * @retval MSI clock range. 3225 * This parameter must be one of the following values: 3226 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3227 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3228 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3229 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3230 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 3231 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3232 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3233 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3234 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3235 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 3236 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 3237 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 3238 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 3239 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 3240 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 3241 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 3242 */ 3243 #define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 3244 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)) : \ 3245 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE) << \ 3246 (RCC_ICSCR1_MSISRANGE_Pos - RCC_CSR_MSISSRANGE_Pos))) 3247 3248 /** @brief Macro to get the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 3249 * @retval MSIK clock range. 3250 * This parameter must be one of the following values: 3251 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3252 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3253 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3254 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3255 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 3256 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3257 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3258 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3259 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3260 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 3261 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 3262 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 3263 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 3264 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 3265 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 3266 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 3267 */ 3268 #define __HAL_RCC_GET_MSIK_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 3269 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)) : \ 3270 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE) << \ 3271 (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos))) 3272 3273 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 3274 * @note After enabling the LSI, the application software should wait on 3275 * LSIRDY flag to be set indicating that LSI clock is stable and can 3276 * be used to clock the IWDG and/or the RTC. 3277 * @note LSI can not be disabled if the IWDG is running. 3278 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 3279 * clock cycles. 3280 * @retval None 3281 */ 3282 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) 3283 3284 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION|RCC_BDCR_LSIPREDIV) 3285 3286 /** 3287 * @brief Macro to configure the External High Speed oscillator (HSE). 3288 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 3289 * supported by this macro. User should request a transition to HSE Off 3290 * first and then HSE On or HSE Bypass. 3291 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 3292 * software should wait on HSERDY flag to be set indicating that HSE clock 3293 * is stable and can be used to clock the PLL and/or system clock. 3294 * @note HSE state can not be changed if it is used directly or through the 3295 * PLL as system clock. In this case, you have to select another source 3296 * of the system clock then change the HSE state (ex. disable it). 3297 * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. 3298 * @param __STATE__: specifies the new state of the HSE. 3299 * This parameter can be one of the following values: 3300 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 3301 * 6 HSE oscillator clock cycles. 3302 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 3303 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 3304 * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed through I/O Schmitt trigger . 3305 * @retval None 3306 */ 3307 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 3308 do { \ 3309 if((__STATE__) == RCC_HSE_ON) \ 3310 { \ 3311 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3312 } \ 3313 else if((__STATE__) == RCC_HSE_BYPASS) \ 3314 { \ 3315 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3316 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3317 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3318 } \ 3319 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 3320 { \ 3321 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3322 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3323 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3324 } \ 3325 else \ 3326 { \ 3327 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 3328 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3329 } \ 3330 } while(0) 3331 3332 /** @brief Macro to enable or disable the LSE system clock. 3333 * @note This clock can be used by any peripheral when its source clock is the LSE or at system 3334 * in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. 3335 * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by 3336 * the CSS on LSE, by a peripheral or any other source clock using LSE. 3337 * @retval None 3338 */ 3339 #define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 3340 3341 #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 3342 3343 3344 /** @brief Macro to set Low-speed clock (LSI) divider. 3345 * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). 3346 * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 3347 * 3348 * @param __DIVIDER__ : specifies the divider value 3349 * This parameter can be one of the following values 3350 * @arg @ref RCC_LSI_DIV1 3351 * @arg @ref RCC_LSI_DIV128 3352 * @retval None 3353 */ 3354 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \ 3355 do { \ 3356 if((__DIVIDER__) == RCC_LSI_DIV128) \ 3357 { \ 3358 SET_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 3359 } \ 3360 else \ 3361 { \ 3362 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 3363 } \ 3364 } while(0) 3365 3366 /** 3367 * @brief Macro to configure the External Low Speed oscillator (LSE). 3368 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 3369 * supported by this macro. User should request a transition to LSE Off 3370 * first and then LSE On or LSE Bypass. 3371 * @note As the LSE is in the Backup domain and write access is denied to 3372 * this domain after reset, you have to enable write access using 3373 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3374 * (to be done once after reset). 3375 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 3376 * software should wait on LSERDY flag to be set indicating that LSE clock 3377 * is stable and can be used to clock the RTC. 3378 * @param __STATE__: specifies the new state of the LSE. 3379 * This parameter can be one of the following values: 3380 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 3381 * 6 LSE oscillator clock cycles. 3382 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 3383 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 3384 * @retval None 3385 */ 3386 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 3387 do { \ 3388 if((__STATE__) == RCC_LSE_ON) \ 3389 { \ 3390 SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ 3391 } \ 3392 else if((__STATE__) == RCC_LSE_BYPASS) \ 3393 { \ 3394 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3395 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3396 } \ 3397 else \ 3398 { \ 3399 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3400 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3401 } \ 3402 } while(0) 3403 3404 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 3405 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 3406 * @note After enabling the HSI48, the application software should wait on HSI48RDY 3407 * flag to be set indicating that HSI48 clock is stable. 3408 * This parameter can be: ENABLE or DISABLE. 3409 * @retval None 3410 */ 3411 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 3412 3413 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 3414 3415 /** @brief Macros to enable or disable the Internal multi-speed RC oscillator clock (MSIK). 3416 * @note if the peripheral requests its kernel clock in Stop 0 or Stop 1 mode,MSIK is woken up 3417 * @note After enabling the MSIK, the application software should wait on MSIKRDY 3418 * flag to be set indicating that MSIK clock is stable. 3419 * This parameter can be: ENABLE or DISABLE. 3420 * @retval None 3421 */ 3422 #define __HAL_RCC_MSIK_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKON) 3423 3424 #define __HAL_RCC_MSIK_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKON) 3425 3426 /** @brief Macros to enable or disable the secure Internal High Speed oscillator (SHSI). 3427 * @note The SHSI is stopped by hardware when entering STOP and STANDBY modes. 3428 * @note After enabling the SHSI, the application software should wait on SHSI 3429 * flag to be set indicating that SHSI clock is stable. 3430 * This parameter can be: ENABLE or DISABLE. 3431 * @retval None 3432 */ 3433 #define __HAL_RCC_SHSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_SHSION) 3434 3435 #define __HAL_RCC_SHSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_SHSION) 3436 3437 /** @brief Macros to configure the RTC clock (RTCCLK). 3438 * @note As the RTC clock configuration bits are in the Backup domain and write 3439 * access is denied to this domain after reset, you have to enable write 3440 * access using the Power Backup Access macro before to configure 3441 * the RTC clock source (to be done once after reset). 3442 * @note Once the RTC clock is configured it cannot be changed unless the 3443 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 3444 * a Power On Reset (POR). 3445 * 3446 * @param __RTC_CLKSOURCE__: specifies the RTC clock source. 3447 * This parameter can be one of the following values: 3448 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 3449 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3450 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3451 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3452 * 3453 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 3454 * work in STOP and STANDBY modes, and can be used as wakeup source. 3455 * However, when the HSE clock is used as RTC clock source, the RTC 3456 * cannot be used in STOP and STANDBY modes. 3457 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 3458 * RTC clock source). 3459 * @retval None 3460 */ 3461 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 3462 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 3463 3464 /** @brief Macro to get the RTC clock source. 3465 * @retval The returned value can be one of the following: 3466 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 3467 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3468 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3469 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3470 */ 3471 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 3472 3473 /** @brief Macros to enable or disable the main PLL. 3474 * @note After enabling the main PLL, the application software should wait on 3475 * PLLRDY flag to be set indicating that PLL clock is stable and can 3476 * be used as system clock source. 3477 * @note The main PLL can not be disabled if it is used as system clock source 3478 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 3479 */ 3480 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 3481 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 3482 3483 /** 3484 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) 3485 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL, 3486 * This is mainly used to save Power. 3487 * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted 3488 * This parameter can be one of the following values: 3489 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 3490 * high-quality audio performance on SAI interface. 3491 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 3492 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 3493 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 3494 * @retval None 3495 * 3496 */ 3497 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 3498 3499 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 3500 3501 /** 3502 * @brief Macro to get the PLL clock output enable status. 3503 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 3504 * This parameter can be one of the following values: 3505 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 3506 * high-quality audio performance on SAI interface. 3507 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 3508 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 3509 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 3510 * @retval SET / RESET 3511 */ 3512 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 3513 3514 /** 3515 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 3516 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 3517 * @retval None 3518 */ 3519 #define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 3520 3521 #define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 3522 3523 /** 3524 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 3525 * @note This function must be used only when the main PLL is disabled. 3526 * 3527 * @param __PLL1SOURCE__: specifies the PLL entry clock source. 3528 * This parameter can be one of the following values: 3529 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 3530 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 3531 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 3532 * @note This clock source (__PLL1SOURCE__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . 3533 * 3534 * @param __PLL1MBOOST__: specifies the division factor for the EPOD clock 3535 * This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider. 3536 * 3537 * @param __PLL1M__: specifies the division factor for PLL VCO input clock 3538 * This parameter must be a number between 1 and 63. 3539 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3540 * frequency ranges from 1 to 16 MHz. 3541 * 3542 * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock 3543 * This parameter must be a number between 4 and 512. 3544 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3545 * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) 3546 * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. 3547 * 3548 * @param __PLL1P__: specifies the division factor for system clock. 3549 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 3550 * 3551 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks 3552 * This parameter must be a number between 1 and 128 3553 * 3554 * @param __PLL1R__: specifies the division factor for peripheral kernel clocks 3555 * This parameter must be a number between 1 and 128 3556 * 3557 * @retval None 3558 */ 3559 #define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 3560 do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\ 3561 RCC_PLL1CFGR_PLL1MBOOST), ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) |\ 3562 (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos) | (__PLL1MBOOST__));\ 3563 MODIFY_REG(RCC->PLL1DIVR ,(RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P | RCC_PLL1DIVR_PLL1Q |\ 3564 RCC_PLL1DIVR_PLL1R), ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) |\ 3565 ((((__PLL1P__) -1U ) << RCC_PLL1DIVR_PLL1P_Pos) & \ 3566 RCC_PLL1DIVR_PLL1P) | \ 3567 ((((__PLL1Q__) -1U) << RCC_PLL1DIVR_PLL1Q_Pos) & \ 3568 RCC_PLL1DIVR_PLL1Q) |\ 3569 ((((__PLL1R__)- 1U) << RCC_PLL1DIVR_PLL1R_Pos) & \ 3570 RCC_PLL1DIVR_PLL1R))); \ 3571 } while(0) 3572 3573 /** @brief Macro to configure the PLLs clock source. 3574 * @note This function must be used only when all PLLs are disabled. 3575 * @param __PLL1SOURCE__: specifies the PLLs entry clock source. 3576 * This parameter can be one of the following values: 3577 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 3578 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 3579 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 3580 */ 3581 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) 3582 3583 /** 3584 * @brief Macro to configure the main PLL clock Fractional Part Of The Multiplication Factor 3585 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 3586 * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 3587 * It should be a value between 0 and 8191 3588 * @note Warning: The software has to set correctly these bits to insure that the VCO 3589 * output frequency is between its valid frequency range, which is: 3590 * 192 to 836 MHz if PLL1VCOSEL = 0 3591 * 150 to 420 MHz if PLL1VCOSEL = 1. 3592 * @retval None 3593 */ 3594 #define __HAL_RCC_PLLFRACN_CONFIG(__PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN,\ 3595 (uint32_t)(__PLL1FRACN__) << \ 3596 RCC_PLL1FRACR_PLL1FRACN_Pos) 3597 3598 /** @brief Macro to select the PLL1 reference frequency range. 3599 * @param __PLL1VCIRange__: specifies the PLL1 input frequency range 3600 * This parameter can be one of the following values: 3601 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 3602 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 3603 * @retval None 3604 */ 3605 #define __HAL_RCC_PLL_VCIRANGE(__PLL1VCIRange__) \ 3606 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) 3607 3608 /** @brief Macro to get the oscillator used as PLL1 clock source. 3609 * @retval The oscillator used as PLL1 clock source. The returned value can be one 3610 * of the following: 3611 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 3612 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 3613 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 3614 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 3615 */ 3616 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) 3617 3618 /** 3619 * @brief Macro to configure the system clock source. 3620 * @param __SYSCLKSOURCE__: specifies the system clock source. 3621 * This parameter can be one of the following values: 3622 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 3623 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 3624 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 3625 * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1 output is used as system clock source. 3626 * @retval None 3627 */ 3628 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 3629 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 3630 3631 /** @brief Macro to get the clock source used as system clock. 3632 * @retval The clock source used as system clock. The returned value can be one 3633 * of the following: 3634 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 3635 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 3636 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 3637 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. 3638 */ 3639 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) 3640 3641 /** 3642 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3643 * @note As the LSE is in the Backup domain and write access is denied to 3644 * this domain after reset, you have to enable write access using 3645 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3646 * (to be done once after reset). 3647 * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) 3648 * when the LSE is ON. However, once LSEDRV is selected, the drive 3649 * capability can not be increased if LSEON = 1. 3650 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 3651 * This parameter can be one of the following values: 3652 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3653 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3654 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3655 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3656 * @retval None 3657 */ 3658 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 3659 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 3660 3661 /** 3662 * @brief Macro to configure the wake up from stop clock. 3663 * @note The selected clock is also used as emergency clock for the clock security system on HSE. 3664 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 3665 * This parameter can be one of the following values: 3666 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source and CSS backup clock 3667 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source and CSS backup clock 3668 * @retval None 3669 */ 3670 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 3671 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) 3672 3673 /** 3674 * @brief Macro to configure the Kernel wake up from stop clock. 3675 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 3676 * This parameter can be one of the following values: 3677 * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI selected as Kernel clock source 3678 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 3679 * @retval None 3680 */ 3681 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 3682 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 3683 3684 /** @brief Macro to configure the MCO clock. 3685 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 3686 * This parameter can be one of the following values: 3687 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 3688 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 3689 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 3690 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 3691 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 3692 * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source 3693 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 3694 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3695 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 3696 * @param __MCODIV__ specifies the MCO clock prescaler. 3697 * This parameter can be one of the following values: 3698 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3699 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3700 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3701 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3702 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3703 */ 3704 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 3705 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 3706 3707 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3708 * @brief macros to manage the specified RCC Flags and interrupts. 3709 * @{ 3710 */ 3711 3712 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 3713 * the selected interrupts). 3714 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 3715 * This parameter can be any combination of the following values: 3716 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3717 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3718 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3719 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3720 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3721 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3722 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3723 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3724 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3725 * @retval None 3726 */ 3727 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3728 3729 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 3730 * the selected interrupts). 3731 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 3732 * This parameter can be any combination of the following values: 3733 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3734 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3735 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3736 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3737 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3738 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3739 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3740 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3741 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3742 * @retval None 3743 */ 3744 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3745 3746 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 3747 * bits to clear the selected interrupt pending bits. 3748 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 3749 * This parameter can be any combination of the following values: 3750 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3751 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3752 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3753 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3754 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3755 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3756 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3757 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3758 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3759 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3760 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 3761 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 3762 * @retval None 3763 */ 3764 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 3765 3766 /** @brief Check whether the RCC interrupt has occurred or not. 3767 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 3768 * This parameter can be one of the following values: 3769 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3770 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3771 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3772 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3773 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3774 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3775 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 3776 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 3777 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3778 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3779 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 3780 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 3781 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 3782 */ 3783 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 3784 3785 /** @brief Set RMVF bit to clear the reset flags. 3786 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3787 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3788 * @retval None 3789 */ 3790 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 3791 3792 /** @brief Check whether the selected RCC flag is set or not. 3793 * @param __FLAG__: specifies the flag to check. 3794 * This parameter can be one of the following values: 3795 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 3796 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3797 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3798 * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready 3799 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 3800 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready 3801 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 3802 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3803 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3804 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 3805 * @arg @ref RCC_FLAG_BORRST BOR reset 3806 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3807 * @arg @ref RCC_FLAG_PINRST Pin reset 3808 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 3809 * @arg @ref RCC_FLAG_SFTRST Software reset 3810 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3811 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3812 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3813 * @retval The new state of __FLAG__ (TRUE or FALSE). 3814 */ 3815 #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 3816 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 3817 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 3818 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 3819 /** 3820 * @} 3821 */ 3822 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ 3823 ((SOURCE) == RCC_PLLSOURCE_HSI) || \ 3824 ((SOURCE) == RCC_PLLSOURCE_NONE) || \ 3825 ((SOURCE) == RCC_PLLSOURCE_HSE)) 3826 3827 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) 3828 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 3829 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3830 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3831 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 3832 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) ||\ 3833 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 3834 3835 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_MSI) || \ 3836 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 3837 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 3838 ((__RANGE__) == RCC_MSIRANGE_1) || \ 3839 ((__RANGE__) == RCC_MSIRANGE_2) || \ 3840 ((__RANGE__) == RCC_MSIRANGE_3) || \ 3841 ((__RANGE__) == RCC_MSIRANGE_4) || \ 3842 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3843 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3844 ((__RANGE__) == RCC_MSIRANGE_7) || \ 3845 ((__RANGE__) == RCC_MSIRANGE_8) || \ 3846 ((__RANGE__) == RCC_MSIRANGE_9) || \ 3847 ((__RANGE__) == RCC_MSIRANGE_10) || \ 3848 ((__RANGE__) == RCC_MSIRANGE_11) || \ 3849 ((__RANGE__) == RCC_MSIRANGE_12) || \ 3850 ((__RANGE__) == RCC_MSIRANGE_13) || \ 3851 ((__RANGE__) == RCC_MSIRANGE_14) || \ 3852 ((__RANGE__) == RCC_MSIRANGE_15)) 3853 3854 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 3855 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3856 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3857 ((__RANGE__) == RCC_MSIRANGE_7) || \ 3858 ((__RANGE__) == RCC_MSIRANGE_8)) 3859 3860 #define IS_RCC_MSIK_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_0) || \ 3861 ((__RANGE__) == RCC_MSIKRANGE_1) || \ 3862 ((__RANGE__) == RCC_MSIKRANGE_2) || \ 3863 ((__RANGE__) == RCC_MSIKRANGE_3) || \ 3864 ((__RANGE__) == RCC_MSIKRANGE_4) || \ 3865 ((__RANGE__) == RCC_MSIKRANGE_5) || \ 3866 ((__RANGE__) == RCC_MSIKRANGE_6) || \ 3867 ((__RANGE__) == RCC_MSIKRANGE_7) || \ 3868 ((__RANGE__) == RCC_MSIKRANGE_8) || \ 3869 ((__RANGE__) == RCC_MSIKRANGE_9) || \ 3870 ((__RANGE__) == RCC_MSIKRANGE_10) || \ 3871 ((__RANGE__) == RCC_MSIKRANGE_11) || \ 3872 ((__RANGE__) == RCC_MSIKRANGE_12) || \ 3873 ((__RANGE__) == RCC_MSIKRANGE_13) || \ 3874 ((__RANGE__) == RCC_MSIKRANGE_14) || \ 3875 ((__RANGE__) == RCC_MSIKRANGE_15)) 3876 /** 3877 * @} 3878 */ 3879 3880 /* Include RCC HAL Extended module */ 3881 #include "stm32u5xx_hal_rcc_ex.h" 3882 3883 /* Exported functions --------------------------------------------------------*/ 3884 /** @addtogroup RCC_Exported_Functions 3885 * @{ 3886 */ 3887 3888 /** @addtogroup RCC_Exported_Functions_Group1 3889 * @{ 3890 */ 3891 3892 /* Initialization and de-initialization functions ******************************/ 3893 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3894 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); 3895 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); 3896 3897 /** 3898 * @} 3899 */ 3900 3901 /** @addtogroup RCC_Exported_Functions_Group2 3902 * @{ 3903 */ 3904 3905 /* Peripheral Control functions **********************************************/ 3906 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3907 void HAL_RCC_EnableCSS(void); 3908 uint32_t HAL_RCC_GetSysClockFreq(void); 3909 uint32_t HAL_RCC_GetHCLKFreq(void); 3910 uint32_t HAL_RCC_GetPCLK1Freq(void); 3911 uint32_t HAL_RCC_GetPCLK2Freq(void); 3912 uint32_t HAL_RCC_GetPCLK3Freq(void); 3913 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); 3914 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency); 3915 uint32_t HAL_RCC_GetResetSource(void); 3916 /* CSS NMI IRQ handler */ 3917 void HAL_RCC_NMI_IRQHandler(void); 3918 /* User Callbacks in non blocking mode (IT mode) */ 3919 void HAL_RCC_CSSCallback(void); 3920 3921 /** 3922 * @} 3923 */ 3924 3925 /* Attributes management functions ********************************************/ 3926 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 3927 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 3928 3929 /** 3930 * @} 3931 */ 3932 3933 /** 3934 * @} 3935 */ 3936 /** 3937 * @} 3938 */ 3939 3940 #ifdef __cplusplus 3941 } 3942 #endif 3943 3944 #endif /* STM32U5xx_HAL_RCC_H */ 3945
