1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef __STM32H5xx_HAL_H 23 #define __STM32H5xx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif /* __cplusplus */ 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32h5xx_hal_conf.h" 31 32 /** @addtogroup STM32H5xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup HAL_Exported_Types HAL Exported Types 42 * @{ 43 */ 44 45 /** @defgroup HAL_TICK_FREQ Tick Frequency 46 * @{ 47 */ 48 typedef enum 49 { 50 HAL_TICK_FREQ_10HZ = 100U, 51 HAL_TICK_FREQ_100HZ = 10U, 52 HAL_TICK_FREQ_1KHZ = 1U, 53 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 54 } HAL_TickFreqTypeDef; 55 /** 56 * @} 57 */ 58 59 /** 60 * @} 61 */ 62 63 /* Exported variables --------------------------------------------------------*/ 64 /** @defgroup HAL_Exported_Variables HAL Exported Variables 65 * @{ 66 */ 67 extern __IO uint32_t uwTick; 68 extern uint32_t uwTickPrio; 69 extern HAL_TickFreqTypeDef uwTickFreq; 70 /** 71 * @} 72 */ 73 74 /* Exported constants --------------------------------------------------------*/ 75 /** @defgroup SBS_Exported_Constants SBS Exported Constants 76 * @{ 77 */ 78 79 /** @defgroup SBS_FPU_Interrupts FPU Interrupts 80 * @{ 81 */ 82 #define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 83 #define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 84 #define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 85 #define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 86 #define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 87 #define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 88 89 /** 90 * @} 91 */ 92 93 /** @defgroup SBS_BREAK_CONFIG SBS Break Config 94 * @{ 95 */ 96 #define SBS_BREAK_FLASH_ECC SBS_CFGR2_ECCL /*!< Enable and lock the FLASH ECC double error with TIM1/8/15/16/17 97 Break inputs.*/ 98 #define SBS_BREAK_PVD SBS_CFGR2_PVDL /*!< Enable and lock the PVD connection with TIM1/8/15/16/17 99 Break inputs. */ 100 #define SBS_BREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enable and lock the SRAM ECC double error signal with 101 TIM1/8/15/16/17 Break inputs.*/ 102 #define SBS_BREAK_LOCKUP SBS_CFGR2_CLL /*!< Enable and lock the connection of Cortex-M33 LOCKUP (hardfault) 103 output to TIM1/8/15/16/17 Break inputs.*/ 104 105 /** 106 * @} 107 */ 108 109 /** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale 110 * @{ 111 */ 112 #define VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 113 #define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ 114 #define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ 115 #define VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ 116 117 /** 118 * @} 119 */ 120 121 /** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance 122 * @{ 123 */ 124 #define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to 125 Voltage reference buffer output */ 126 #define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 127 128 /** 129 * @} 130 */ 131 132 /** @defgroup SBS_FastModePlus_GPIO Fast-mode Plus on GPIO 133 * @{ 134 */ 135 136 /** @brief Fast-mode Plus driving capability on a specific GPIO 137 */ 138 #define SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 139 #define SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 140 #define SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 141 #if defined(SBS_PMCR_PB9_FMP) 142 #define SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 143 #endif /* SBS_PMCR_PB9_FMP */ 144 145 /** 146 * @} 147 */ 148 149 #if defined(SBS_PMCR_ETH_SEL_PHY) 150 /** @defgroup SBS_Ethernet_Config Ethernet Config 151 * @{ 152 */ 153 #define SBS_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface (MII) or GMII */ 154 #define SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */ 155 156 #define IS_SBS_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SBS_ETH_MII) || \ 157 ((CONFIG) == SBS_ETH_RMII)) 158 159 /** 160 * @} 161 */ 162 #endif /* SBS_PMCR_ETH_SEL_PHY */ 163 164 /** @defgroup SBS_Boostvddsel_Selection Boost VDD Selection 165 * @{ 166 */ 167 #define SBS_BOOSTVDDSEL_VDDA ((uint32_t)0x00000000) /*!< Select VDDA as analog switch supply voltage 168 (when BOOSTEN bit is cleared) */ 169 #define SBS_BOOSTVDDSEL_VDD SBS_PMCR_BOOSTVDDSEL /*!< Select VDD as analog switch supply voltage 170 (regardless of BOOSTEN bit) */ 171 172 #define IS_SBS_BOOSTVDD_SELECTION(BOOSTVDDSEL) (((BOOSTVDDSEL) == SBS_BOOSTVDDSEL_VDDA) || \ 173 ((BOOSTVDDSEL) == SBS_BOOSTVDDSEL_VDD)) 174 175 /** 176 * @} 177 */ 178 179 180 /** @defgroup SBS_Memories_Erase_Flag_Status Memory Erase Flags Status 181 * @{ 182 */ 183 #define SBS_MEMORIES_ERASE_FLAG_IPMEE SBS_MESR_IPMEE /*!< Select the Status of End Of Erase for ICACHE 184 and PKA RAMs */ 185 #define SBS_MEMORIES_ERASE_FLAG_MCLR SBS_MESR_MCLR /*!< Select the Status of Erase after Power-on Reset 186 (SRAM2, BKPRAM, ICACHE, DCACHE, PKA rams) */ 187 188 #define IS_SBS_MEMORIES_ERASE_FLAG(FLAG) (((FLAG) == SBS_MEMORIES_ERASE_FLAG_IPMEE) || \ 189 ((FLAG) == SBS_MEMORIES_ERASE_FLAG_MCLR)) 190 191 /** 192 * @} 193 */ 194 195 /** @defgroup SBS_IOCompenstionCell_Config IOCompenstionCell Config 196 * @{ 197 */ 198 #define SBS_VDD_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 199 #define SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< Code from the SBS compensation cell code register */ 200 201 #define IS_SBS_VDD_CODE_SELECT(SELECT) (((SELECT) == SBS_VDD_CELL_CODE)|| \ 202 ((SELECT) == SBS_VDD_REGISTER_CODE)) 203 204 #define SBS_VDDIO_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 205 #define SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< Code from the SBS compensation cell code register */ 206 207 #define IS_SBS_VDDIO_CODE_SELECT(SELECT) (((SELECT) == SBS_VDDIO_CELL_CODE)|| \ 208 ((SELECT) == SBS_VDDIO_REGISTER_CODE)) 209 210 #define IS_SBS_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) 211 212 /** 213 * @} 214 */ 215 216 #if defined(SBS_EPOCHSELCR_EPOCH_SEL) 217 /** @defgroup SBS_EPOCH_Selection EPOCH Selection 218 * @{ 219 */ 220 #define SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */ 221 #define SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */ 222 #define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */ 223 224 #define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \ 225 ((SELECT) == SBS_EPOCH_SEL_NONSECURE) || \ 226 ((SELECT) == SBS_EPOCH_SEL_PUFCHECK)) 227 /** 228 * @} 229 */ 230 #endif /* SBS_EPOCHSELCR_EPOCH_SEL */ 231 232 #if defined(SBS_NEXTHDPLCR_NEXTHDPL) 233 /** @defgroup SBS_NextHDPL_Selection Next HDPL Selection 234 * @{ 235 */ 236 #define SBS_OBKHDPL_INCR_0 0x00U 237 #define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 238 #define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 239 #define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL 240 /** 241 * @} 242 */ 243 #endif /* SBS_NEXTHDPLCR_NEXTHDPL */ 244 245 /** @defgroup SBS_HDPL_Value HDPL Value 246 * @{ 247 */ 248 #define SBS_HDPL_VALUE_0 0x000000B4U 249 #define SBS_HDPL_VALUE_1 0x00000051U 250 #define SBS_HDPL_VALUE_2 0x0000008AU 251 #define SBS_HDPL_VALUE_3 0x0000006FU 252 /** 253 * @} 254 */ 255 256 257 /** @defgroup SBS_Lock_items SBS Lock items 258 * @brief SBS items to set lock on 259 * @{ 260 */ 261 #define SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or 262 non-secure only) */ 263 #define SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or 264 non-secure only) */ 265 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 266 #define SBS_SAU (SBS_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 267 #define SBS_MPU_SEC (SBS_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) 268 */ 269 #define SBS_VTOR_AIRCR_SEC (SBS_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure 270 code only) */ 271 #define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC|SBS_SAU|SBS_MPU_SEC|SBS_VTOR_AIRCR_SEC) /*!< All */ 272 #else 273 #define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 274 #endif /* __ARM_FEATURE_CMSE */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup SBS_Attributes_items SBS Attributes items 280 * @brief SBS items to configure secure or non-secure attributes on 281 * @{ 282 */ 283 #define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */ 284 #define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */ 285 #define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */ 286 #define SBS_SMPS SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS */ 287 #define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU | SBS_SMPS) /*!< All */ 288 /** 289 * @} 290 */ 291 292 /** @defgroup SBS_attributes SBS attributes 293 * @brief SBS secure or non-secure attributes 294 * @{ 295 */ 296 #define SBS_SEC 0x00000001U /*!< Secure attribute */ 297 #define SBS_NSEC 0x00000000U /*!< Non-secure attribute */ 298 /** 299 * @} 300 */ 301 302 /** 303 * @} 304 */ 305 306 /* Exported macros -----------------------------------------------------------*/ 307 308 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 309 * @{ 310 */ 311 312 /** @brief Freeze/Unfreeze Peripherals in Debug mode 313 */ 314 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 315 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 316 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 317 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 318 319 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 320 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 321 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 322 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 323 324 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 325 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 326 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 327 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 328 329 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 330 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 331 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 332 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 333 334 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 335 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 336 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 337 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 338 339 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 340 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 341 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 342 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 343 344 #if defined(DBGMCU_APB1FZR1_DBG_TIM12_STOP) 345 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) 346 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) 347 #endif /* DBGMCU_APB1FZR1_DBG_TIM12_STOP */ 348 349 #if defined(DBGMCU_APB1FZR1_DBG_TIM13_STOP) 350 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) 351 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) 352 #endif /* DBGMCU_APB1FZR1_DBG_TIM13_STOP */ 353 354 #if defined(DBGMCU_APB1FZR1_DBG_TIM14_STOP) 355 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) 356 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) 357 #endif /* DBGMCU_APB1FZR1_DBG_TIM14_STOP */ 358 359 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 360 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 361 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 362 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 363 364 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 365 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 366 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 367 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 368 369 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 370 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 371 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 372 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 373 374 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 375 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 376 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 377 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 378 379 #if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP) 380 #define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) 381 #define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) 382 #endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */ 383 384 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 385 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 386 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 387 #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ 388 389 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 390 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 391 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 392 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 393 394 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 395 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 396 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 397 #endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ 398 399 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 400 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 401 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 402 #endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ 403 404 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 405 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 406 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 407 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 408 409 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 410 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 411 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 412 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 413 414 #if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) 415 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 416 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 417 #endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ 418 419 #if defined(DBGMCU_APB3FZR_DBG_I2C4_STOP) 420 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) 421 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) 422 #endif /* DBGMCU_APB3FZR_DBG_I2C4_STOP */ 423 424 #if defined(DBGMCU_APB3FZR_DBG_I3C2_STOP) 425 #define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) 426 #define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) 427 #endif /* DBGMCU_APB3FZR_DBG_I3C2_STOP */ 428 429 #if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 430 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 431 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 432 #endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ 433 434 #if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 435 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 436 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 437 #endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ 438 439 #if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 440 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 441 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 442 #endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ 443 444 #if defined(DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 445 #define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 446 #define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 447 #endif /* DBGMCU_APB3FZR_DBG_LPTIM5_STOP */ 448 449 #if defined(DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 450 #define __HAL_DBGMCU_FREEZE_LPTIM6() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 451 #define __HAL_DBGMCU_UNFREEZE_LPTIM6() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 452 #endif /* DBGMCU_APB3FZR_DBG_LPTIM6_STOP */ 453 454 #if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) 455 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 456 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 457 #endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ 458 459 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 460 #define __HAL_DBGMCU_FREEZE_GPDMA1_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 461 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 462 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */ 463 464 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 465 #define __HAL_DBGMCU_FREEZE_GPDMA1_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 466 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 467 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */ 468 469 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 470 #define __HAL_DBGMCU_FREEZE_GPDMA1_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 471 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 472 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */ 473 474 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 475 #define __HAL_DBGMCU_FREEZE_GPDMA1_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 476 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 477 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */ 478 479 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 480 #define __HAL_DBGMCU_FREEZE_GPDMA1_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 481 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 482 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */ 483 484 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 485 #define __HAL_DBGMCU_FREEZE_GPDMA1_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 486 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 487 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */ 488 489 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 490 #define __HAL_DBGMCU_FREEZE_GPDMA1_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 491 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 492 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */ 493 494 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 495 #define __HAL_DBGMCU_FREEZE_GPDMA1_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 496 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 497 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ 498 499 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 500 #define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 501 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 502 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP */ 503 504 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 505 #define __HAL_DBGMCU_FREEZE_GPDMA2_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 506 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 507 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP */ 508 509 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 510 #define __HAL_DBGMCU_FREEZE_GPDMA2_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 511 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 512 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP */ 513 514 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 515 #define __HAL_DBGMCU_FREEZE_GPDMA2_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 516 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 517 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP */ 518 519 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 520 #define __HAL_DBGMCU_FREEZE_GPDMA2_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 521 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 522 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP */ 523 524 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 525 #define __HAL_DBGMCU_FREEZE_GPDMA2_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 526 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 527 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP */ 528 529 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 530 #define __HAL_DBGMCU_FREEZE_GPDMA2_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 531 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 532 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP */ 533 534 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 535 #define __HAL_DBGMCU_FREEZE_GPDMA2_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 536 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 537 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */ 538 539 /** 540 * @} 541 */ 542 543 /** @defgroup SBS_Exported_Macros SBS Exported Macros 544 * @{ 545 */ 546 547 /** @brief Floating Point Unit interrupt enable/disable macros 548 * @param __INTERRUPT__: This parameter can be a value of @ref SBS_FPU_Interrupts 549 */ 550 #define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ 551 SET_BIT(SBS->FPUIMR, (__INTERRUPT__));\ 552 }while(0) 553 554 #define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ 555 CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__));\ 556 }while(0) 557 558 /** @brief SBS Break ECC lock. 559 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 560 * @note The selected configuration is locked and can be unlocked only by system reset. 561 */ 562 #define __HAL_SBS_BREAK_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_ECCL) 563 564 /** @brief SBS Break Cortex-M33 Lockup lock. 565 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 566 * @note The selected configuration is locked and can be unlocked only by system reset. 567 */ 568 #define __HAL_SBS_BREAK_LOCKUP_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_CLL) 569 570 /** @brief SBS Break PVD lock. 571 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] 572 * in the PWR_CR2 register. 573 * @note The selected configuration is locked and can be unlocked only by system reset. 574 */ 575 #define __HAL_SBS_BREAK_PVD_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_PVDL) 576 577 /** @brief SBS Break SRAM double ECC lock. 578 * Enable and lock the connection of SRAM double ECC error to TIM1/8/15/16/17 Break input. 579 * @note The selected configuration is locked and can be unlocked only by system reset. 580 */ 581 #define __HAL_SBS_BREAK_SRAM_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_SEL) 582 583 /** @brief Fast-mode Plus driving capability enable/disable macros 584 * @param __FASTMODEPLUS__: This parameter can be a value of : 585 * @arg @ref SBS_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 586 * @arg @ref SBS_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 587 * @arg @ref SBS_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 588 * @arg @ref SBS_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 589 */ 590 #define __HAL_SBS_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ 591 SET_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ 592 }while(0) 593 594 #define __HAL_SBS_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ 595 CLEAR_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ 596 }while(0) 597 598 /** @brief Check SBS Memories Erase Status Flags. 599 * @param __FLAG__: specifies the flag to check. 600 * This parameter can be one of the following values: 601 * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs 602 * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, 603 * ICACHE, DCACHE, PKA RAMs) 604 * @retval The new state of __FLAG__ (TRUE or FALSE). 605 */ 606 #define __HAL_SBS_GET_MEMORIES_ERASE_STATUS(__FLAG__) ((((SBS->MESR) & (__FLAG__))!= 0) ? 1 : 0) 607 608 /** @brief Clear SBS Memories Erase Status Flags. 609 * @param __FLAG__: specifies the flag to clear. 610 * This parameter can be one of the following values: 611 * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs 612 * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, 613 * ICACHE, DCACHE, PKA RAMs) 614 */ 615 #define __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS(__FLAG__) do {assert_param(IS_SBS_MEMORIES_ERASE_FLAG((__FLAG__)));\ 616 WRITE_REG(SBS->MESR, (__FLAG__));\ 617 }while(0) 618 619 /** 620 * @} 621 */ 622 623 /* Private macros ------------------------------------------------------------*/ 624 625 /** @defgroup SBS_Private_Macros SBS Private Macros 626 * @{ 627 */ 628 629 #define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \ 630 (((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \ 631 (((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \ 632 (((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \ 633 (((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \ 634 (((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC)) 635 636 #define IS_SBS_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SBS_BREAK_FLASH_ECC) || \ 637 ((__CONFIG__) == SBS_BREAK_PVD) || \ 638 ((__CONFIG__) == SBS_BREAK_SRAM_ECC) || \ 639 ((__CONFIG__) == SBS_BREAK_LOCKUP)) 640 641 #define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \ 642 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \ 643 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \ 644 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE3)) 645 646 #define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 647 ((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE)) 648 649 #define IS_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 650 651 #if defined(SBS_FASTMODEPLUS_PB9) 652 #define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ 653 (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ 654 (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8) || \ 655 (((__PIN__) & SBS_FASTMODEPLUS_PB9) == SBS_FASTMODEPLUS_PB9)) 656 #else 657 #define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ 658 (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ 659 (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8)) 660 #endif /* SBS_FASTMODEPLUS_PB9 */ 661 662 #define IS_SBS_OBKHDPL_SELECTION(__SELECT__) (((__SELECT__) == SBS_OBKHDPL_INCR_0) || \ 663 ((__SELECT__) == SBS_OBKHDPL_INCR_1) || \ 664 ((__SELECT__) == SBS_OBKHDPL_INCR_2) || \ 665 ((__SELECT__) == SBS_OBKHDPL_INCR_3)) 666 667 #define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \ 668 (((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \ 669 (((__ITEM__) & SBS_FPU) == SBS_FPU) || \ 670 (((__ITEM__) & SBS_SMPS) == SBS_SMPS) || \ 671 (((__ITEM__) & ~(SBS_ALL)) == 0U)) 672 673 #define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\ 674 ((__ATTRIBUTES__) == SBS_NSEC)) 675 676 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 677 678 #define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ 679 (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ 680 (((__ITEM__) & SBS_SAU) == SBS_SAU) || \ 681 (((__ITEM__) & SBS_MPU_SEC) == SBS_MPU_SEC) || \ 682 (((__ITEM__) & SBS_VTOR_AIRCR_SEC) == SBS_VTOR_AIRCR_SEC) || \ 683 (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) 684 685 #else 686 687 #define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ 688 (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ 689 (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) 690 691 692 #endif /* __ARM_FEATURE_CMSE */ 693 /** 694 * @} 695 */ 696 697 /** @defgroup HAL_Private_Macros HAL Private Macros 698 * @{ 699 */ 700 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 701 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 702 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 703 /** 704 * @} 705 */ 706 /* Exported functions --------------------------------------------------------*/ 707 708 /** @addtogroup HAL_Exported_Functions 709 * @{ 710 */ 711 712 /** @addtogroup HAL_Exported_Functions_Group1 713 * @{ 714 */ 715 716 /* Initialization and de-initialization functions ******************************/ 717 HAL_StatusTypeDef HAL_Init(void); 718 HAL_StatusTypeDef HAL_DeInit(void); 719 void HAL_MspInit(void); 720 void HAL_MspDeInit(void); 721 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 722 723 /** 724 * @} 725 */ 726 727 /** @addtogroup HAL_Exported_Functions_Group2 728 * @{ 729 */ 730 731 /* Peripheral Control functions ************************************************/ 732 void HAL_IncTick(void); 733 void HAL_Delay(uint32_t Delay); 734 uint32_t HAL_GetTick(void); 735 uint32_t HAL_GetTickPrio(void); 736 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 737 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 738 void HAL_SuspendTick(void); 739 void HAL_ResumeTick(void); 740 uint32_t HAL_GetHalVersion(void); 741 uint32_t HAL_GetREVID(void); 742 uint32_t HAL_GetDEVID(void); 743 uint32_t HAL_GetUIDw0(void); 744 uint32_t HAL_GetUIDw1(void); 745 uint32_t HAL_GetUIDw2(void); 746 747 /** 748 * @} 749 */ 750 751 /** @addtogroup HAL_Exported_Functions_Group3 752 * @{ 753 */ 754 755 /* DBGMCU Peripheral Control functions *****************************************/ 756 void HAL_DBGMCU_EnableDBGStopMode(void); 757 void HAL_DBGMCU_DisableDBGStopMode(void); 758 void HAL_DBGMCU_EnableDBGStandbyMode(void); 759 void HAL_DBGMCU_DisableDBGStandbyMode(void); 760 761 /** 762 * @} 763 */ 764 765 /** @addtogroup HAL_Exported_Functions_Group4 766 * @{ 767 */ 768 769 /* SBS Control functions ****************************************************/ 770 771 void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 772 void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); 773 void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 774 HAL_StatusTypeDef HAL_EnableVREFBUF(void); 775 void HAL_DisableVREFBUF(void); 776 777 void HAL_SBS_EnableIOAnalogSwitchBooster(void); 778 void HAL_SBS_DisableIOAnalogSwitchBooster(void); 779 void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface); 780 void HAL_SBS_AnalogSwitchSupplyVoltageSelection(uint32_t SBS_BOOSTVDDSEL); 781 void HAL_SBS_EnableVddIO1CompensationCell(void); 782 void HAL_SBS_DisableVddIO1CompensationCell(void); 783 void HAL_SBS_EnableVddIO2CompensationCell(void); 784 void HAL_SBS_DisableVddIO2CompensationCell(void); 785 void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode); 786 void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode); 787 uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void); 788 uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void); 789 void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); 790 void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); 791 uint32_t HAL_SBS_GetNMOSVddCompensationValue(void); 792 uint32_t HAL_SBS_GetPMOSVddCompensationValue(void); 793 uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void); 794 uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void); 795 void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection); 796 uint32_t HAL_SBS_GetEPOCHSelection(void); 797 void HAL_SBS_IncrementHDPLValue(void); 798 uint32_t HAL_SBS_GetHDPLValue(void); 799 void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value); 800 uint32_t HAL_SBS_GetOBKHDPL(void); 801 void HAL_SBS_FLASH_EnableECCNMI(void); 802 void HAL_SBS_FLASH_DisableECCNMI(void); 803 uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void); 804 805 /** 806 * @} 807 */ 808 809 810 /** @addtogroup HAL_Exported_Functions_Group5 811 * @{ 812 */ 813 814 /* SBS Lock functions ********************************************/ 815 void HAL_SBS_Lock(uint32_t Item); 816 HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem); 817 818 /** 819 * @} 820 */ 821 822 /** @addtogroup HAL_Exported_Functions_Group6 823 * @{ 824 */ 825 826 /* SBS Attributes functions ********************************************/ 827 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 828 void HAL_SBS_ConfigAttributes(uint32_t Item, uint32_t Attributes); 829 HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 830 #endif /* __ARM_FEATURE_CMSE */ 831 832 /** 833 * @} 834 */ 835 836 /** 837 * @} 838 */ 839 840 /** 841 * @} 842 */ 843 844 /** 845 * @} 846 */ 847 848 #ifdef __cplusplus 849 } 850 #endif /* __cplusplus */ 851 852 #endif /* __STM32H5xx_HAL_H */ 853 854
