1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BL_COMMON_H 8 #define BL_COMMON_H 9 10 #include <common/ep_info.h> 11 #include <common/param_header.h> 12 #include <lib/utils_def.h> 13 14 #ifndef __ASSEMBLER__ 15 #include <stddef.h> 16 #include <stdint.h> 17 #include <lib/cassert.h> 18 #endif /* __ASSEMBLER__ */ 19 20 #include <export/common/bl_common_exp.h> 21 22 #define UP U(1) 23 #define DOWN U(0) 24 25 /******************************************************************************* 26 * Constants to identify the location of a memory region in a given memory 27 * layout. 28 ******************************************************************************/ 29 #define TOP U(0x1) 30 #define BOTTOM U(0x0) 31 32 /******************************************************************************* 33 * Constants to indicate type of exception to the common exception handler. 34 ******************************************************************************/ 35 #define SYNC_EXCEPTION_SP_EL0 U(0x0) 36 #define IRQ_SP_EL0 U(0x1) 37 #define FIQ_SP_EL0 U(0x2) 38 #define SERROR_SP_EL0 U(0x3) 39 #define SYNC_EXCEPTION_SP_ELX U(0x4) 40 #define IRQ_SP_ELX U(0x5) 41 #define FIQ_SP_ELX U(0x6) 42 #define SERROR_SP_ELX U(0x7) 43 #define SYNC_EXCEPTION_AARCH64 U(0x8) 44 #define IRQ_AARCH64 U(0x9) 45 #define FIQ_AARCH64 U(0xa) 46 #define SERROR_AARCH64 U(0xb) 47 #define SYNC_EXCEPTION_AARCH32 U(0xc) 48 #define IRQ_AARCH32 U(0xd) 49 #define FIQ_AARCH32 U(0xe) 50 #define SERROR_AARCH32 U(0xf) 51 52 /* 53 * Mapping to connect linker symbols from .ld.S with their counterparts 54 * from .scat for the BL31 image 55 */ 56 #if defined(USE_ARM_LINK) 57 #define __BL31_END__ Load$$LR$$LR_END$$Base 58 #define __BSS_START__ Load$$LR$$LR_BSS$$Base 59 #define __BSS_END__ Load$$LR$$LR_BSS$$Limit 60 #define __BSS_SIZE__ Load$$LR$$LR_BSS$$Length 61 #define __COHERENT_RAM_START__ Load$$LR$$LR_COHERENT_RAM$$Base 62 #define __COHERENT_RAM_END_UNALIGNED__ Load$$__COHERENT_RAM_EPILOGUE_UNALIGNED__$$Base 63 #define __COHERENT_RAM_END__ Load$$LR$$LR_COHERENT_RAM$$Limit 64 #define __COHERENT_RAM_UNALIGNED_SIZE__ Load$$__COHERENT_RAM__$$Length 65 #define __CPU_OPS_START__ Load$$__CPU_OPS__$$Base 66 #define __CPU_OPS_END__ Load$$__CPU_OPS__$$Limit 67 #define __DATA_START__ Load$$__DATA__$$Base 68 #define __DATA_END__ Load$$__DATA__$$Limit 69 #define __GOT_START__ Load$$__GOT__$$Base 70 #define __GOT_END__ Load$$__GOT__$$Limit 71 #define __PERCPU_BAKERY_LOCK_START__ Load$$__BAKERY_LOCKS__$$Base 72 #define __PERCPU_BAKERY_LOCK_END__ Load$$__BAKERY_LOCKS_EPILOGUE__$$Base 73 #define __PMF_SVC_DESCS_START__ Load$$__PMF_SVC_DESCS__$$Base 74 #define __PMF_SVC_DESCS_END__ Load$$__PMF_SVC_DESCS__$$Limit 75 #define __PMF_TIMESTAMP_START__ Load$$__PMF_TIMESTAMP__$$Base 76 #define __PMF_TIMESTAMP_END__ Load$$__PER_CPU_TIMESTAMPS__$$Limit 77 #define __PMF_PERCPU_TIMESTAMP_END__ Load$$__PMF_TIMESTAMP_EPILOGUE__$$Base 78 #define __RELA_END__ Load$$__RELA__$$Limit 79 #define __RELA_START__ Load$$__RELA__$$Base 80 #define __RODATA_START__ Load$$__RODATA__$$Base 81 #define __RODATA_END__ Load$$__RODATA_EPILOGUE__$$Base 82 #define __RT_SVC_DESCS_START__ Load$$__RT_SVC_DESCS__$$Base 83 #define __RT_SVC_DESCS_END__ Load$$__RT_SVC_DESCS__$$Limit 84 #if SPMC_AT_EL3 85 #define __EL3_LP_DESCS_START__ Load$$__EL3_LP_DESCS__$$Base 86 #define __EL3_LP_DESCS_END__ Load$$__EL3_LP_DESCS__$$Limit 87 #endif 88 #if ENABLE_SPMD_LP 89 #define __SPMD_LP_DESCS_START__ Load$$__SPMD_LP_DESCS__$$Base 90 #define __SPMD_LP_DESCS_END__ Load$$__SPMD_LP_DESCS__$$Limit 91 #endif 92 #define __RW_START__ Load$$LR$$LR_RW_DATA$$Base 93 #define __RW_END__ Load$$LR$$LR_END$$Base 94 #define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base 95 #define __SPM_SHIM_EXCEPTIONS_END__ Load$$__SPM_SHIM_EXCEPTIONS_EPILOGUE__$$Base 96 #define __STACKS_START__ Load$$__STACKS__$$Base 97 #define __STACKS_END__ Load$$__STACKS__$$Limit 98 #define __TEXT_START__ Load$$__TEXT__$$Base 99 #define __TEXT_END__ Load$$__TEXT_EPILOGUE__$$Base 100 #endif /* USE_ARM_LINK */ 101 102 #ifndef __ASSEMBLER__ 103 104 /* 105 * Declarations of linker defined symbols to help determine memory layout of 106 * BL images 107 */ 108 #if SEPARATE_CODE_AND_RODATA 109 IMPORT_SYM(uintptr_t, __TEXT_START__, BL_CODE_BASE); 110 IMPORT_SYM(uintptr_t, __TEXT_END__, BL_CODE_END); 111 IMPORT_SYM(uintptr_t, __RODATA_START__, BL_RO_DATA_BASE); 112 IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END); 113 #else 114 IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); 115 IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END); 116 #endif 117 #if SEPARATE_NOBITS_REGION 118 IMPORT_SYM(uintptr_t, __NOBITS_START__, BL_NOBITS_BASE); 119 IMPORT_SYM(uintptr_t, __NOBITS_END__, BL_NOBITS_END); 120 #endif 121 IMPORT_SYM(uintptr_t, __RW_END__, BL_END); 122 123 #if defined(IMAGE_BL1) 124 IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END); 125 126 IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE); 127 IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT); 128 #elif defined(IMAGE_BL2) 129 IMPORT_SYM(uintptr_t, __BL2_END__, BL2_END); 130 #elif defined(IMAGE_BL2U) 131 IMPORT_SYM(uintptr_t, __BL2U_END__, BL2U_END); 132 #elif defined(IMAGE_BL31) 133 IMPORT_SYM(uintptr_t, __BL31_START__, BL31_START); 134 IMPORT_SYM(uintptr_t, __BL31_END__, BL31_END); 135 #elif defined(IMAGE_BL32) 136 IMPORT_SYM(uintptr_t, __BL32_END__, BL32_END); 137 #elif defined(IMAGE_RMM) 138 IMPORT_SYM(uintptr_t, __RMM_END__, RMM_END); 139 #endif /* IMAGE_BLX */ 140 141 /* The following symbols are only exported from the BL2 at EL3 linker script. */ 142 #if BL2_IN_XIP_MEM && defined(IMAGE_BL2) 143 IMPORT_SYM(uintptr_t, __BL2_ROM_END__, BL2_ROM_END); 144 145 IMPORT_SYM(uintptr_t, __BL2_RAM_START__, BL2_RAM_BASE); 146 IMPORT_SYM(uintptr_t, __BL2_RAM_END__, BL2_RAM_END); 147 #endif /* BL2_IN_XIP_MEM */ 148 149 /* 150 * The next 2 constants identify the extents of the coherent memory region. 151 * These addresses are used by the MMU setup code and therefore they must be 152 * page-aligned. It is the responsibility of the linker script to ensure that 153 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 154 * page-aligned addresses. 155 */ 156 #if USE_COHERENT_MEM 157 IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE); 158 IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL_COHERENT_RAM_END); 159 #endif 160 161 /******************************************************************************* 162 * Structure used for telling the next BL how much of a particular type of 163 * memory is available for its use and how much is already used. 164 ******************************************************************************/ 165 typedef struct meminfo { 166 uintptr_t total_base; 167 size_t total_size; 168 } meminfo_t; 169 170 /******************************************************************************* 171 * Function & variable prototypes 172 ******************************************************************************/ 173 int load_auth_image(unsigned int image_id, image_info_t *image_data); 174 175 #if TRUSTED_BOARD_BOOT && defined(DYN_DISABLE_AUTH) 176 /* 177 * API to dynamically disable authentication. Only meant for development 178 * systems. 179 */ 180 void dyn_disable_auth(void); 181 #endif 182 183 extern const char build_message[]; 184 extern const char version_string[]; 185 const char *get_version(void); 186 187 void print_entry_point_info(const entry_point_info_t *ep_info); 188 uintptr_t page_align(uintptr_t value, unsigned dir); 189 190 struct mmap_region; 191 192 void setup_page_tables(const struct mmap_region *bl_regions, 193 const struct mmap_region *plat_regions); 194 195 void bl_handle_pauth(void); 196 197 #endif /*__ASSEMBLER__*/ 198 199 #endif /* BL_COMMON_H */ 200
