1/*
2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15#if BL2_IN_XIP_MEM
16    ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
17    RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
18#else /* BL2_IN_XIP_MEM */
19    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
20#endif /* BL2_IN_XIP_MEM */
21
22#if SEPARATE_BL2_NOLOAD_REGION
23    RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
24#else /* SEPARATE_BL2_NOLOAD_REGION */
25#   define RAM_NOLOAD RAM
26#endif /* SEPARATE_BL2_NOLOAD_REGION */
27}
28
29#if !BL2_IN_XIP_MEM
30#   define ROM RAM
31#endif /* !BL2_IN_XIP_MEM */
32
33SECTIONS {
34    RAM_REGION_START = ORIGIN(RAM);
35    RAM_REGION_LENGTH = LENGTH(RAM);
36#if BL2_IN_XIP_MEM
37    ROM_REGION_START = ORIGIN(ROM);
38    ROM_REGION_LENGTH = LENGTH(ROM);
39
40    . = BL2_RO_BASE;
41
42    ASSERT(. == ALIGN(PAGE_SIZE),
43        "BL2_RO_BASE address is not aligned on a page boundary.")
44#else /* BL2_IN_XIP_MEM */
45    . = BL2_BASE;
46
47    ASSERT(. == ALIGN(PAGE_SIZE),
48        "BL2_BASE address is not aligned on a page boundary.")
49#endif /* BL2_IN_XIP_MEM */
50
51#if SEPARATE_BL2_NOLOAD_REGION
52    RAM_NOLOAD_REGION_START = ORIGIN(RAM_NOLOAD);
53    RAM_NOLOAD_REGION_LENGTH = LENGTH(RAM_NOLOAD);
54#endif
55
56#if SEPARATE_CODE_AND_RODATA
57    .text . : {
58        __TEXT_START__ = .;
59        __TEXT_RESIDENT_START__ = .;
60
61        *bl2_el3_entrypoint.o(.text*)
62        *(.text.asm.*)
63
64        __TEXT_RESIDENT_END__ = .;
65
66        *(SORT_BY_ALIGNMENT(.text*))
67        *(.vectors)
68        __TEXT_END_UNALIGNED__ = .;
69
70        . = ALIGN(PAGE_SIZE);
71
72        __TEXT_END__ = .;
73    } >ROM
74
75    .rodata . : {
76        __RODATA_START__ = .;
77
78        *(SORT_BY_ALIGNMENT(.rodata*))
79
80        RODATA_COMMON
81
82        __RODATA_END_UNALIGNED__ = .;
83        . = ALIGN(PAGE_SIZE);
84
85        __RODATA_END__ = .;
86    } >ROM
87
88    ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
89        "Resident part of BL2 has exceeded its limit.")
90#else /* SEPARATE_CODE_AND_RODATA */
91    .ro . : {
92        __RO_START__ = .;
93        __TEXT_RESIDENT_START__ = .;
94
95        *bl2_el3_entrypoint.o(.text*)
96        *(.text.asm.*)
97
98        __TEXT_RESIDENT_END__ = .;
99
100        *(SORT_BY_ALIGNMENT(.text*))
101        *(SORT_BY_ALIGNMENT(.rodata*))
102
103        RODATA_COMMON
104
105        *(.vectors)
106
107        __RO_END_UNALIGNED__ = .;
108
109        /*
110         * Memory page(s) mapped to this section will be marked as read-only,
111         * executable. No RW data from the next section must creep in. Ensure
112         * that the rest of the current memory page is unused.
113         */
114        . = ALIGN(PAGE_SIZE);
115
116        __RO_END__ = .;
117    } >ROM
118#endif /* SEPARATE_CODE_AND_RODATA */
119
120    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
121        "cpu_ops not defined for this platform.")
122
123#if BL2_IN_XIP_MEM
124    ROM_REGION_END = .;
125    . = BL2_RW_BASE;
126
127    ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
128           "BL2_RW_BASE address is not aligned on a page boundary.")
129#endif /* BL2_IN_XIP_MEM */
130
131    __RW_START__ = .;
132
133    DATA_SECTION >RAM AT>ROM
134
135    __DATA_RAM_START__ = __DATA_START__;
136    __DATA_RAM_END__ = __DATA_END__;
137
138    RELA_SECTION >RAM
139
140#if SEPARATE_BL2_NOLOAD_REGION
141    SAVED_ADDR = .;
142
143    . = BL2_NOLOAD_START;
144
145    __BL2_NOLOAD_START__ = .;
146#endif /* SEPARATE_BL2_NOLOAD_REGION */
147
148    STACK_SECTION >RAM_NOLOAD
149    BSS_SECTION >RAM_NOLOAD
150    XLAT_TABLE_SECTION >RAM_NOLOAD
151
152#if SEPARATE_BL2_NOLOAD_REGION
153    __BL2_NOLOAD_END__ = .;
154    RAM_NOLOAD_REGION_END = .;
155
156    . = SAVED_ADDR;
157#endif /* SEPARATE_BL2_NOLOAD_REGION */
158
159#if USE_COHERENT_MEM
160    /*
161     * The base address of the coherent memory section must be page-aligned to
162     * guarantee that the coherent data are stored on their own pages and are
163     * not mixed with normal data.  This is required to set up the correct
164     * memory attributes for the coherent data page tables.
165     */
166    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
167        __COHERENT_RAM_START__ = .;
168
169        *(.tzfw_coherent_mem)
170
171        __COHERENT_RAM_END_UNALIGNED__ = .;
172
173        /*
174         * Memory page(s) mapped to this section will be marked as device
175         * memory. No other unexpected data must creep in. Ensure the rest of
176         * the current memory page is unused.
177         */
178        . = ALIGN(PAGE_SIZE);
179
180        __COHERENT_RAM_END__ = .;
181    } >RAM
182#endif /* USE_COHERENT_MEM */
183
184    __RW_END__ = .;
185    __BL2_END__ = .;
186
187    /DISCARD/ : {
188        *(.dynsym .dynstr .hash .gnu.hash)
189    }
190
191#if BL2_IN_XIP_MEM
192    __BL2_RAM_START__ = ADDR(.data);
193    __BL2_RAM_END__ = .;
194
195    __DATA_ROM_START__ = LOADADDR(.data);
196    __DATA_SIZE__ = SIZEOF(.data);
197
198    /*
199     * The .data section is the last PROGBITS section so its end marks the end
200     * of BL2's RO content in XIP memory.
201     */
202    __BL2_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
203
204    ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
205           "BL2's RO content has exceeded its limit.")
206#endif /* BL2_IN_XIP_MEM */
207
208    __BSS_SIZE__ = SIZEOF(.bss);
209
210#if USE_COHERENT_MEM
211    __COHERENT_RAM_UNALIGNED_SIZE__ =
212        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
213#endif /* USE_COHERENT_MEM */
214
215    RAM_REGION_END = .;
216#if BL2_IN_XIP_MEM
217    ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
218#else /* BL2_IN_XIP_MEM */
219    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
220#endif /* BL2_IN_XIP_MEM */
221}
222