1 /**************************************************************************//**
2 * @file cmsis_armcc.h
3 * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
4 * @version V5.2.1
5 * @date 26. March 2020
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_ARMCC_H
26 #define __CMSIS_ARMCC_H
27
28
29 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31 #endif
32
33 /* CMSIS compiler control architecture macros */
34 #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36 #define __ARM_ARCH_6M__ 1
37 #endif
38
39 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40 #define __ARM_ARCH_7M__ 1
41 #endif
42
43 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44 #define __ARM_ARCH_7EM__ 1
45 #endif
46
47 /* __ARM_ARCH_8M_BASE__ not applicable */
48 /* __ARM_ARCH_8M_MAIN__ not applicable */
49 /* __ARM_ARCH_8_1M_MAIN__ not applicable */
50
51 /* CMSIS compiler control DSP macros */
52 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
53 #define __ARM_FEATURE_DSP 1
54 #endif
55
56 /* CMSIS compiler specific defines */
57 #ifndef __ASM
58 #define __ASM __asm
59 #endif
60 #ifndef __INLINE
61 #define __INLINE __inline
62 #endif
63 #ifndef __STATIC_INLINE
64 #define __STATIC_INLINE static __inline
65 #endif
66 #ifndef __STATIC_FORCEINLINE
67 #define __STATIC_FORCEINLINE static __forceinline
68 #endif
69 #ifndef __NO_RETURN
70 #define __NO_RETURN __declspec(noreturn)
71 #endif
72 #ifndef __USED
73 #define __USED __attribute__((used))
74 #endif
75 #ifndef __WEAK
76 #define __WEAK __attribute__((weak))
77 #endif
78 #ifndef __PACKED
79 #define __PACKED __attribute__((packed))
80 #endif
81 #ifndef __PACKED_STRUCT
82 #define __PACKED_STRUCT __packed struct
83 #endif
84 #ifndef __PACKED_UNION
85 #define __PACKED_UNION __packed union
86 #endif
87 #ifndef __UNALIGNED_UINT32 /* deprecated */
88 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
89 #endif
90 #ifndef __UNALIGNED_UINT16_WRITE
91 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
92 #endif
93 #ifndef __UNALIGNED_UINT16_READ
94 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
95 #endif
96 #ifndef __UNALIGNED_UINT32_WRITE
97 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
98 #endif
99 #ifndef __UNALIGNED_UINT32_READ
100 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
101 #endif
102 #ifndef __ALIGNED
103 #define __ALIGNED(x) __attribute__((aligned(x)))
104 #endif
105 #ifndef __RESTRICT
106 #define __RESTRICT __restrict
107 #endif
108 #ifndef __COMPILER_BARRIER
109 #define __COMPILER_BARRIER() __memory_changed()
110 #endif
111
112 /* ######################### Startup and Lowlevel Init ######################## */
113
114 #ifndef __PROGRAM_START
115 #define __PROGRAM_START __main
116 #endif
117
118 #ifndef __INITIAL_SP
119 #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
120 #endif
121
122 #ifndef __STACK_LIMIT
123 #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
124 #endif
125
126 #ifndef __VECTOR_TABLE
127 #define __VECTOR_TABLE __Vectors
128 #endif
129
130 #ifndef __VECTOR_TABLE_ATTRIBUTE
131 #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
132 #endif
133
134 /* ########################### Core Function Access ########################### */
135 /** \ingroup CMSIS_Core_FunctionInterface
136 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
137 @{
138 */
139
140 /**
141 \brief Enable IRQ Interrupts
142 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
143 Can only be executed in Privileged modes.
144 */
145 /* intrinsic void __enable_irq(); */
146
147
148 /**
149 \brief Disable IRQ Interrupts
150 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
151 Can only be executed in Privileged modes.
152 */
153 /* intrinsic void __disable_irq(); */
154
155 /**
156 \brief Get Control Register
157 \details Returns the content of the Control Register.
158 \return Control Register value
159 */
__get_CONTROL(void)160 __STATIC_INLINE uint32_t __get_CONTROL(void)
161 {
162 register uint32_t __regControl __ASM("control");
163 return(__regControl);
164 }
165
166
167 /**
168 \brief Set Control Register
169 \details Writes the given value to the Control Register.
170 \param [in] control Control Register value to set
171 */
__set_CONTROL(uint32_t control)172 __STATIC_INLINE void __set_CONTROL(uint32_t control)
173 {
174 register uint32_t __regControl __ASM("control");
175 __regControl = control;
176 }
177
178
179 /**
180 \brief Get IPSR Register
181 \details Returns the content of the IPSR Register.
182 \return IPSR Register value
183 */
__get_IPSR(void)184 __STATIC_INLINE uint32_t __get_IPSR(void)
185 {
186 register uint32_t __regIPSR __ASM("ipsr");
187 return(__regIPSR);
188 }
189
190
191 /**
192 \brief Get APSR Register
193 \details Returns the content of the APSR Register.
194 \return APSR Register value
195 */
__get_APSR(void)196 __STATIC_INLINE uint32_t __get_APSR(void)
197 {
198 register uint32_t __regAPSR __ASM("apsr");
199 return(__regAPSR);
200 }
201
202
203 /**
204 \brief Get xPSR Register
205 \details Returns the content of the xPSR Register.
206 \return xPSR Register value
207 */
__get_xPSR(void)208 __STATIC_INLINE uint32_t __get_xPSR(void)
209 {
210 register uint32_t __regXPSR __ASM("xpsr");
211 return(__regXPSR);
212 }
213
214
215 /**
216 \brief Get Process Stack Pointer
217 \details Returns the current value of the Process Stack Pointer (PSP).
218 \return PSP Register value
219 */
__get_PSP(void)220 __STATIC_INLINE uint32_t __get_PSP(void)
221 {
222 register uint32_t __regProcessStackPointer __ASM("psp");
223 return(__regProcessStackPointer);
224 }
225
226
227 /**
228 \brief Set Process Stack Pointer
229 \details Assigns the given value to the Process Stack Pointer (PSP).
230 \param [in] topOfProcStack Process Stack Pointer value to set
231 */
__set_PSP(uint32_t topOfProcStack)232 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
233 {
234 register uint32_t __regProcessStackPointer __ASM("psp");
235 __regProcessStackPointer = topOfProcStack;
236 }
237
238
239 /**
240 \brief Get Main Stack Pointer
241 \details Returns the current value of the Main Stack Pointer (MSP).
242 \return MSP Register value
243 */
__get_MSP(void)244 __STATIC_INLINE uint32_t __get_MSP(void)
245 {
246 register uint32_t __regMainStackPointer __ASM("msp");
247 return(__regMainStackPointer);
248 }
249
250
251 /**
252 \brief Set Main Stack Pointer
253 \details Assigns the given value to the Main Stack Pointer (MSP).
254 \param [in] topOfMainStack Main Stack Pointer value to set
255 */
__set_MSP(uint32_t topOfMainStack)256 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
257 {
258 register uint32_t __regMainStackPointer __ASM("msp");
259 __regMainStackPointer = topOfMainStack;
260 }
261
262
263 /**
264 \brief Get Priority Mask
265 \details Returns the current state of the priority mask bit from the Priority Mask Register.
266 \return Priority Mask value
267 */
__get_PRIMASK(void)268 __STATIC_INLINE uint32_t __get_PRIMASK(void)
269 {
270 register uint32_t __regPriMask __ASM("primask");
271 return(__regPriMask);
272 }
273
274
275 /**
276 \brief Set Priority Mask
277 \details Assigns the given value to the Priority Mask Register.
278 \param [in] priMask Priority Mask
279 */
__set_PRIMASK(uint32_t priMask)280 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
281 {
282 register uint32_t __regPriMask __ASM("primask");
283 __regPriMask = (priMask);
284 }
285
286
287 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
288 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
289
290 /**
291 \brief Enable FIQ
292 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
293 Can only be executed in Privileged modes.
294 */
295 #define __enable_fault_irq __enable_fiq
296
297
298 /**
299 \brief Disable FIQ
300 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
301 Can only be executed in Privileged modes.
302 */
303 #define __disable_fault_irq __disable_fiq
304
305
306 /**
307 \brief Get Base Priority
308 \details Returns the current value of the Base Priority register.
309 \return Base Priority register value
310 */
__get_BASEPRI(void)311 __STATIC_INLINE uint32_t __get_BASEPRI(void)
312 {
313 register uint32_t __regBasePri __ASM("basepri");
314 return(__regBasePri);
315 }
316
317
318 /**
319 \brief Set Base Priority
320 \details Assigns the given value to the Base Priority register.
321 \param [in] basePri Base Priority value to set
322 */
__set_BASEPRI(uint32_t basePri)323 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
324 {
325 register uint32_t __regBasePri __ASM("basepri");
326 __regBasePri = (basePri & 0xFFU);
327 }
328
329
330 /**
331 \brief Set Base Priority with condition
332 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
333 or the new value increases the BASEPRI priority level.
334 \param [in] basePri Base Priority value to set
335 */
__set_BASEPRI_MAX(uint32_t basePri)336 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
337 {
338 register uint32_t __regBasePriMax __ASM("basepri_max");
339 __regBasePriMax = (basePri & 0xFFU);
340 }
341
342
343 /**
344 \brief Get Fault Mask
345 \details Returns the current value of the Fault Mask register.
346 \return Fault Mask register value
347 */
__get_FAULTMASK(void)348 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
349 {
350 register uint32_t __regFaultMask __ASM("faultmask");
351 return(__regFaultMask);
352 }
353
354
355 /**
356 \brief Set Fault Mask
357 \details Assigns the given value to the Fault Mask register.
358 \param [in] faultMask Fault Mask value to set
359 */
__set_FAULTMASK(uint32_t faultMask)360 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
361 {
362 register uint32_t __regFaultMask __ASM("faultmask");
363 __regFaultMask = (faultMask & (uint32_t)1U);
364 }
365
366 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
367 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
368
369
370 /**
371 \brief Get FPSCR
372 \details Returns the current value of the Floating Point Status/Control register.
373 \return Floating Point Status/Control register value
374 */
__get_FPSCR(void)375 __STATIC_INLINE uint32_t __get_FPSCR(void)
376 {
377 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
378 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
379 register uint32_t __regfpscr __ASM("fpscr");
380 return(__regfpscr);
381 #else
382 return(0U);
383 #endif
384 }
385
386
387 /**
388 \brief Set FPSCR
389 \details Assigns the given value to the Floating Point Status/Control register.
390 \param [in] fpscr Floating Point Status/Control value to set
391 */
__set_FPSCR(uint32_t fpscr)392 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
393 {
394 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
395 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
396 register uint32_t __regfpscr __ASM("fpscr");
397 __regfpscr = (fpscr);
398 #else
399 (void)fpscr;
400 #endif
401 }
402
403
404 /*@} end of CMSIS_Core_RegAccFunctions */
405
406
407 /* ########################## Core Instruction Access ######################### */
408 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
409 Access to dedicated instructions
410 @{
411 */
412
413 /**
414 \brief No Operation
415 \details No Operation does nothing. This instruction can be used for code alignment purposes.
416 */
417 #define __NOP __nop
418
419
420 /**
421 \brief Wait For Interrupt
422 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
423 */
424 #define __WFI __wfi
425
426
427 /**
428 \brief Wait For Event
429 \details Wait For Event is a hint instruction that permits the processor to enter
430 a low-power state until one of a number of events occurs.
431 */
432 #define __WFE __wfe
433
434
435 /**
436 \brief Send Event
437 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
438 */
439 #define __SEV __sev
440
441
442 /**
443 \brief Instruction Synchronization Barrier
444 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
445 so that all instructions following the ISB are fetched from cache or memory,
446 after the instruction has been completed.
447 */
448 #define __ISB() __isb(0xF)
449
450 /**
451 \brief Data Synchronization Barrier
452 \details Acts as a special kind of Data Memory Barrier.
453 It completes when all explicit memory accesses before this instruction complete.
454 */
455 #define __DSB() __dsb(0xF)
456
457 /**
458 \brief Data Memory Barrier
459 \details Ensures the apparent order of the explicit memory operations before
460 and after the instruction, without ensuring their completion.
461 */
462 #define __DMB() __dmb(0xF)
463
464
465 /**
466 \brief Reverse byte order (32 bit)
467 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
468 \param [in] value Value to reverse
469 \return Reversed value
470 */
471 #define __REV __rev
472
473
474 /**
475 \brief Reverse byte order (16 bit)
476 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
477 \param [in] value Value to reverse
478 \return Reversed value
479 */
480 #ifndef __NO_EMBEDDED_ASM
__REV16(uint32_t value)481 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
482 {
483 rev16 r0, r0
484 bx lr
485 }
486 #endif
487
488
489 /**
490 \brief Reverse byte order (16 bit)
491 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
492 \param [in] value Value to reverse
493 \return Reversed value
494 */
495 #ifndef __NO_EMBEDDED_ASM
__REVSH(int16_t value)496 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
497 {
498 revsh r0, r0
499 bx lr
500 }
501 #endif
502
503
504 /**
505 \brief Rotate Right in unsigned value (32 bit)
506 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
507 \param [in] op1 Value to rotate
508 \param [in] op2 Number of Bits to rotate
509 \return Rotated value
510 */
511 #define __ROR __ror
512
513
514 /**
515 \brief Breakpoint
516 \details Causes the processor to enter Debug state.
517 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
518 \param [in] value is ignored by the processor.
519 If required, a debugger can use it to store additional information about the breakpoint.
520 */
521 #define __BKPT(value) __breakpoint(value)
522
523
524 /**
525 \brief Reverse bit order of value
526 \details Reverses the bit order of the given value.
527 \param [in] value Value to reverse
528 \return Reversed value
529 */
530 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
531 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
532 #define __RBIT __rbit
533 #else
__RBIT(uint32_t value)534 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
535 {
536 uint32_t result;
537 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
538
539 result = value; /* r will be reversed bits of v; first get LSB of v */
540 for (value >>= 1U; value != 0U; value >>= 1U)
541 {
542 result <<= 1U;
543 result |= value & 1U;
544 s--;
545 }
546 result <<= s; /* shift when v's highest bits are zero */
547 return result;
548 }
549 #endif
550
551
552 /**
553 \brief Count leading zeros
554 \details Counts the number of leading zeros of a data value.
555 \param [in] value Value to count the leading zeros
556 \return number of leading zeros in value
557 */
558 #define __CLZ __clz
559
560
561 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
562 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
563
564 /**
565 \brief LDR Exclusive (8 bit)
566 \details Executes a exclusive LDR instruction for 8 bit value.
567 \param [in] ptr Pointer to data
568 \return value of type uint8_t at (*ptr)
569 */
570 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
571 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
572 #else
573 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
574 #endif
575
576
577 /**
578 \brief LDR Exclusive (16 bit)
579 \details Executes a exclusive LDR instruction for 16 bit values.
580 \param [in] ptr Pointer to data
581 \return value of type uint16_t at (*ptr)
582 */
583 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
584 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
585 #else
586 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
587 #endif
588
589
590 /**
591 \brief LDR Exclusive (32 bit)
592 \details Executes a exclusive LDR instruction for 32 bit values.
593 \param [in] ptr Pointer to data
594 \return value of type uint32_t at (*ptr)
595 */
596 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
597 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
598 #else
599 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
600 #endif
601
602
603 /**
604 \brief STR Exclusive (8 bit)
605 \details Executes a exclusive STR instruction for 8 bit values.
606 \param [in] value Value to store
607 \param [in] ptr Pointer to location
608 \return 0 Function succeeded
609 \return 1 Function failed
610 */
611 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
612 #define __STREXB(value, ptr) __strex(value, ptr)
613 #else
614 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
615 #endif
616
617
618 /**
619 \brief STR Exclusive (16 bit)
620 \details Executes a exclusive STR instruction for 16 bit values.
621 \param [in] value Value to store
622 \param [in] ptr Pointer to location
623 \return 0 Function succeeded
624 \return 1 Function failed
625 */
626 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
627 #define __STREXH(value, ptr) __strex(value, ptr)
628 #else
629 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
630 #endif
631
632
633 /**
634 \brief STR Exclusive (32 bit)
635 \details Executes a exclusive STR instruction for 32 bit values.
636 \param [in] value Value to store
637 \param [in] ptr Pointer to location
638 \return 0 Function succeeded
639 \return 1 Function failed
640 */
641 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
642 #define __STREXW(value, ptr) __strex(value, ptr)
643 #else
644 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
645 #endif
646
647
648 /**
649 \brief Remove the exclusive lock
650 \details Removes the exclusive lock which is created by LDREX.
651 */
652 #define __CLREX __clrex
653
654
655 /**
656 \brief Signed Saturate
657 \details Saturates a signed value.
658 \param [in] value Value to be saturated
659 \param [in] sat Bit position to saturate to (1..32)
660 \return Saturated value
661 */
662 #define __SSAT __ssat
663
664
665 /**
666 \brief Unsigned Saturate
667 \details Saturates an unsigned value.
668 \param [in] value Value to be saturated
669 \param [in] sat Bit position to saturate to (0..31)
670 \return Saturated value
671 */
672 #define __USAT __usat
673
674
675 /**
676 \brief Rotate Right with Extend (32 bit)
677 \details Moves each bit of a bitstring right by one bit.
678 The carry input is shifted in at the left end of the bitstring.
679 \param [in] value Value to rotate
680 \return Rotated value
681 */
682 #ifndef __NO_EMBEDDED_ASM
__RRX(uint32_t value)683 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
684 {
685 rrx r0, r0
686 bx lr
687 }
688 #endif
689
690
691 /**
692 \brief LDRT Unprivileged (8 bit)
693 \details Executes a Unprivileged LDRT instruction for 8 bit value.
694 \param [in] ptr Pointer to data
695 \return value of type uint8_t at (*ptr)
696 */
697 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
698
699
700 /**
701 \brief LDRT Unprivileged (16 bit)
702 \details Executes a Unprivileged LDRT instruction for 16 bit values.
703 \param [in] ptr Pointer to data
704 \return value of type uint16_t at (*ptr)
705 */
706 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
707
708
709 /**
710 \brief LDRT Unprivileged (32 bit)
711 \details Executes a Unprivileged LDRT instruction for 32 bit values.
712 \param [in] ptr Pointer to data
713 \return value of type uint32_t at (*ptr)
714 */
715 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
716
717
718 /**
719 \brief STRT Unprivileged (8 bit)
720 \details Executes a Unprivileged STRT instruction for 8 bit values.
721 \param [in] value Value to store
722 \param [in] ptr Pointer to location
723 */
724 #define __STRBT(value, ptr) __strt(value, ptr)
725
726
727 /**
728 \brief STRT Unprivileged (16 bit)
729 \details Executes a Unprivileged STRT instruction for 16 bit values.
730 \param [in] value Value to store
731 \param [in] ptr Pointer to location
732 */
733 #define __STRHT(value, ptr) __strt(value, ptr)
734
735
736 /**
737 \brief STRT Unprivileged (32 bit)
738 \details Executes a Unprivileged STRT instruction for 32 bit values.
739 \param [in] value Value to store
740 \param [in] ptr Pointer to location
741 */
742 #define __STRT(value, ptr) __strt(value, ptr)
743
744 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
745 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
746
747 /**
748 \brief Signed Saturate
749 \details Saturates a signed value.
750 \param [in] value Value to be saturated
751 \param [in] sat Bit position to saturate to (1..32)
752 \return Saturated value
753 */
__SSAT(int32_t val,uint32_t sat)754 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
755 {
756 if ((sat >= 1U) && (sat <= 32U))
757 {
758 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
759 const int32_t min = -1 - max ;
760 if (val > max)
761 {
762 return max;
763 }
764 else if (val < min)
765 {
766 return min;
767 }
768 }
769 return val;
770 }
771
772 /**
773 \brief Unsigned Saturate
774 \details Saturates an unsigned value.
775 \param [in] value Value to be saturated
776 \param [in] sat Bit position to saturate to (0..31)
777 \return Saturated value
778 */
__USAT(int32_t val,uint32_t sat)779 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
780 {
781 if (sat <= 31U)
782 {
783 const uint32_t max = ((1U << sat) - 1U);
784 if (val > (int32_t)max)
785 {
786 return max;
787 }
788 else if (val < 0)
789 {
790 return 0U;
791 }
792 }
793 return (uint32_t)val;
794 }
795
796 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
797 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
798
799 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
800
801
802 /* ################### Compiler specific Intrinsics ########################### */
803 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
804 Access to dedicated SIMD instructions
805 @{
806 */
807
808 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
809
810 #define __SADD8 __sadd8
811 #define __QADD8 __qadd8
812 #define __SHADD8 __shadd8
813 #define __UADD8 __uadd8
814 #define __UQADD8 __uqadd8
815 #define __UHADD8 __uhadd8
816 #define __SSUB8 __ssub8
817 #define __QSUB8 __qsub8
818 #define __SHSUB8 __shsub8
819 #define __USUB8 __usub8
820 #define __UQSUB8 __uqsub8
821 #define __UHSUB8 __uhsub8
822 #define __SADD16 __sadd16
823 #define __QADD16 __qadd16
824 #define __SHADD16 __shadd16
825 #define __UADD16 __uadd16
826 #define __UQADD16 __uqadd16
827 #define __UHADD16 __uhadd16
828 #define __SSUB16 __ssub16
829 #define __QSUB16 __qsub16
830 #define __SHSUB16 __shsub16
831 #define __USUB16 __usub16
832 #define __UQSUB16 __uqsub16
833 #define __UHSUB16 __uhsub16
834 #define __SASX __sasx
835 #define __QASX __qasx
836 #define __SHASX __shasx
837 #define __UASX __uasx
838 #define __UQASX __uqasx
839 #define __UHASX __uhasx
840 #define __SSAX __ssax
841 #define __QSAX __qsax
842 #define __SHSAX __shsax
843 #define __USAX __usax
844 #define __UQSAX __uqsax
845 #define __UHSAX __uhsax
846 #define __USAD8 __usad8
847 #define __USADA8 __usada8
848 #define __SSAT16 __ssat16
849 #define __USAT16 __usat16
850 #define __UXTB16 __uxtb16
851 #define __UXTAB16 __uxtab16
852 #define __SXTB16 __sxtb16
853 #define __SXTAB16 __sxtab16
854 #define __SMUAD __smuad
855 #define __SMUADX __smuadx
856 #define __SMLAD __smlad
857 #define __SMLADX __smladx
858 #define __SMLALD __smlald
859 #define __SMLALDX __smlaldx
860 #define __SMUSD __smusd
861 #define __SMUSDX __smusdx
862 #define __SMLSD __smlsd
863 #define __SMLSDX __smlsdx
864 #define __SMLSLD __smlsld
865 #define __SMLSLDX __smlsldx
866 #define __SEL __sel
867 #define __QADD __qadd
868 #define __QSUB __qsub
869
870 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
871 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
872
873 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
874 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
875
876 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
877 ((int64_t)(ARG3) << 32U) ) >> 32U))
878
879 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
880
881 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
882 /*@} end of group CMSIS_SIMD_intrinsics */
883
884
885 #endif /* __CMSIS_ARMCC_H */
886
