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Searched defs:_SMU_PPUPATD0_ADC1_SHIFT (Results 1 – 25 of 64) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h141 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b110f1024iq64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b130f512gm64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b130f512gq64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b130f512im64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b130f512iq64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b110f1024gm64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b110f1024gq64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b110f1024im64.h8363 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b390f1024gl112.h7586 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b390f512gl112.h7586 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b510f1024gl120.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b510f1024gm64.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b510f1024gl112.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b530f512im64.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b530f512iq64.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b530f512iq100.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b510f1024iq100.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
Defm32gg12b510f1024gq64.h8394 #define _SMU_PPUPATD0_ADC1_SHIFT 4 /**< Shift value … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_smu.h146 #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value … macro
Defm32gg11b120f2048im64.h8908 #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value … macro
Defm32gg11b110f2048gm64.h8908 #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value … macro
Defm32gg11b110f2048gq64.h8908 #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value … macro
Defm32gg11b120f2048gm64.h8908 #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value … macro
Defm32gg11b110f2048im64.h8908 #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value … macro

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