1 /***************************************************************************//** 2 * \file gpio_cyw20829a0_40_qfn.h 3 * 4 * \brief 5 * CYW20829 device GPIO header for 40-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_CYW20829A0_40_QFN_H_ 28 #define _GPIO_CYW20829A0_40_QFN_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_SMT, 40 }; 41 42 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN 43 #define CY_GPIO_PIN_COUNT 40u 44 45 /* AMUXBUS Segments */ 46 enum 47 { 48 AMUXBUS_MAIN, 49 AMUXBUS_TEST, 50 AMUXBUS_VDDD, 51 }; 52 53 /* AMUX Splitter Controls */ 54 typedef enum 55 { 56 AMUX_SPLIT_CTL_0 = 0x0000u /* Left = AMUXBUS_TEST; Right = AMUXBUS_VDDD */ 57 } cy_en_amux_split_t; 58 59 /* Port List */ 60 /* PORT 0 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 61 #define P0_4_PORT GPIO_PRT0 62 #define P0_4_PIN 4u 63 #define P0_4_NUM 4u 64 #define P0_5_PORT GPIO_PRT0 65 #define P0_5_PIN 5u 66 #define P0_5_NUM 5u 67 68 /* PORT 1 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 69 #define P1_0_PORT GPIO_PRT1 70 #define P1_0_PIN 0u 71 #define P1_0_NUM 0u 72 #define P1_1_PORT GPIO_PRT1 73 #define P1_1_PIN 1u 74 #define P1_1_NUM 1u 75 #define P1_2_PORT GPIO_PRT1 76 #define P1_2_PIN 2u 77 #define P1_2_NUM 2u 78 #define P1_3_PORT GPIO_PRT1 79 #define P1_3_PIN 3u 80 #define P1_3_NUM 3u 81 82 /* PORT 2 (HSIO, SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 83 #define P2_0_PORT GPIO_PRT2 84 #define P2_0_PIN 0u 85 #define P2_0_NUM 0u 86 #define P2_1_PORT GPIO_PRT2 87 #define P2_1_PIN 1u 88 #define P2_1_NUM 1u 89 #define P2_2_PORT GPIO_PRT2 90 #define P2_2_PIN 2u 91 #define P2_2_NUM 2u 92 #define P2_3_PORT GPIO_PRT2 93 #define P2_3_PIN 3u 94 #define P2_3_NUM 3u 95 #define P2_4_PORT GPIO_PRT2 96 #define P2_4_PIN 4u 97 #define P2_4_NUM 4u 98 #define P2_5_PORT GPIO_PRT2 99 #define P2_5_PIN 5u 100 #define P2_5_NUM 5u 101 102 /* PORT 3 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 103 #define P3_1_PORT GPIO_PRT3 104 #define P3_1_PIN 1u 105 #define P3_1_NUM 1u 106 #define P3_2_PORT GPIO_PRT3 107 #define P3_2_PIN 2u 108 #define P3_2_NUM 2u 109 #define P3_3_PORT GPIO_PRT3 110 #define P3_3_PIN 3u 111 #define P3_3_NUM 3u 112 113 /* PORT 4 (GPIO_OVT, SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 114 #define P4_0_PORT GPIO_PRT4 115 #define P4_0_PIN 0u 116 #define P4_0_NUM 0u 117 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 118 #define P4_1_PORT GPIO_PRT4 119 #define P4_1_PIN 1u 120 #define P4_1_NUM 1u 121 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 122 123 /* PORT 5 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 124 #define P5_0_PORT GPIO_PRT5 125 #define P5_0_PIN 0u 126 #define P5_0_NUM 0u 127 #define P5_1_PORT GPIO_PRT5 128 #define P5_1_PIN 1u 129 #define P5_1_NUM 1u 130 131 /* Analog Connections */ 132 #define ADCMIC_GPIO_ADC_IN1_PORT 3u 133 #define ADCMIC_GPIO_ADC_IN1_PIN 1u 134 #define ADCMIC_GPIO_ADC_IN2_PORT 3u 135 #define ADCMIC_GPIO_ADC_IN2_PIN 2u 136 #define ADCMIC_GPIO_ADC_IN3_PORT 3u 137 #define ADCMIC_GPIO_ADC_IN3_PIN 3u 138 #define IOSS_ADFT0_NET0_PORT 4u 139 #define IOSS_ADFT0_NET0_PIN 0u 140 #define IOSS_ADFT1_NET0_PORT 4u 141 #define IOSS_ADFT1_NET0_PIN 1u 142 #define SRSS_WCO_IN_PORT 5u 143 #define SRSS_WCO_IN_PIN 0u 144 #define SRSS_WCO_OUT_PORT 5u 145 #define SRSS_WCO_OUT_PIN 1u 146 147 /* HSIOM Connections */ 148 typedef enum 149 { 150 /* Generic HSIOM connections */ 151 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 152 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 153 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 154 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 155 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 156 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 157 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 158 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 159 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 160 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 161 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 162 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 163 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 164 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 165 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 166 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 167 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 168 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 169 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 170 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 171 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 172 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 173 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 174 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 175 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 176 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 177 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 178 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 179 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 180 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 181 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 182 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 183 184 /* P0.4 */ 185 P0_4_GPIO = 0, /* GPIO controls 'out' */ 186 P0_4_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 187 P0_4_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ 188 P0_4_BTSS_GPIO5 = 10, /* Digital Active - btss.gpio[5]:0 */ 189 P0_4_BTSS_TXD_PYLD_MOD_TEST1 = 11, /* Digital Active - btss.txd_pyld_mod_test[1] */ 190 P0_4_KEYSCAN_KS_ROW0 = 14, /* Digital Deep Sleep - keyscan.ks_row[0] */ 191 P0_4_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 192 P0_4_CPUSS_TRACE_DATA3 = 17, /* Digital Active - cpuss.trace_data[3]:1 */ 193 P0_4_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 194 P0_4_PERI_TR_IO_INPUT0 = 22, /* Digital Active - peri.tr_io_input[0]:0 */ 195 P0_4_TDM_TDM_TX_MCK0 = 24, /* Digital Active - tdm.tdm_tx_mck[0]:0 */ 196 P0_4_BTSS_DEBUG3 = 26, /* Digital Active - btss.debug[3]:0 */ 197 P0_4_BTSS_SPI_CLK = 27, /* Digital Active - btss.spi_clk:0 */ 198 P0_4_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 199 P0_4_IOSS_DDFT_PIN1 = 31, /* Digital Deep Sleep - ioss.ddft_pin[1]:0 */ 200 201 /* P0.5 */ 202 P0_5_GPIO = 0, /* GPIO controls 'out' */ 203 P0_5_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 204 P0_5_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ 205 P0_5_BTSS_ANTENNA_SWITCH_CTRL0 = 10, /* Digital Active - btss.antenna_switch_ctrl[0] */ 206 P0_5_BTSS_TX_ST_TEST = 11, /* Digital Active - btss.tx_st_test */ 207 P0_5_KEYSCAN_KS_ROW1 = 14, /* Digital Deep Sleep - keyscan.ks_row[1] */ 208 P0_5_CPUSS_TRACE_DATA2 = 17, /* Digital Active - cpuss.trace_data[2]:1 */ 209 P0_5_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 210 P0_5_PERI_TR_IO_INPUT1 = 22, /* Digital Active - peri.tr_io_input[1]:0 */ 211 P0_5_TDM_TDM_TX_SCK0 = 24, /* Digital Active - tdm.tdm_tx_sck[0]:0 */ 212 P0_5_BTSS_GCI_GPIO0 = 25, /* Digital Active - btss.gci_gpio[0] */ 213 P0_5_BTSS_DEBUG4 = 26, /* Digital Active - btss.debug[4] */ 214 P0_5_SMIF_SPIHB_SELECT1 = 27, /* Digital Active - smif.spihb_select1 */ 215 216 /* P1.0 */ 217 P1_0_GPIO = 0, /* GPIO controls 'out' */ 218 P1_0_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 219 P1_0_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 220 P1_0_BTSS_ANTENNA_SWITCH_CTRL1 = 10, /* Digital Active - btss.antenna_switch_ctrl[1] */ 221 P1_0_BTSS_RPU_TDO = 11, /* Digital Active - btss.rpu_tdo */ 222 P1_0_KEYSCAN_KS_ROW5 = 14, /* Digital Deep Sleep - keyscan.ks_row[5] */ 223 P1_0_CPUSS_TRACE_DATA1 = 17, /* Digital Active - cpuss.trace_data[1]:1 */ 224 P1_0_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 225 P1_0_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 226 P1_0_PERI_TR_IO_OUTPUT0 = 23, /* Digital Active - peri.tr_io_output[0]:0 */ 227 P1_0_TDM_TDM_TX_FSYNC0 = 24, /* Digital Active - tdm.tdm_tx_fsync[0]:0 */ 228 P1_0_BTSS_GCI_GPIO1 = 25, /* Digital Active - btss.gci_gpio[1] */ 229 P1_0_BTSS_DEBUG5 = 26, /* Digital Active - btss.debug[5] */ 230 P1_0_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 231 232 /* P1.1 */ 233 P1_1_GPIO = 0, /* GPIO controls 'out' */ 234 P1_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 235 P1_1_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ 236 P1_1_BTSS_ANTENNA_SWITCH_CTRL2 = 10, /* Digital Active - btss.antenna_switch_ctrl[2] */ 237 P1_1_BTSS_RPU_TDI = 11, /* Digital Active - btss.rpu_tdi */ 238 P1_1_KEYSCAN_KS_ROW6 = 14, /* Digital Deep Sleep - keyscan.ks_row[6] */ 239 P1_1_CPUSS_TRACE_DATA0 = 17, /* Digital Active - cpuss.trace_data[0]:1 */ 240 P1_1_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 241 P1_1_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 242 P1_1_PERI_TR_IO_OUTPUT1 = 23, /* Digital Active - peri.tr_io_output[1]:0 */ 243 P1_1_TDM_TDM_TX_SD0 = 24, /* Digital Active - tdm.tdm_tx_sd[0]:0 */ 244 P1_1_BTSS_GCI_GPIO2 = 25, /* Digital Active - btss.gci_gpio[2]:0 */ 245 P1_1_BTSS_DEBUG6 = 26, /* Digital Active - btss.debug[6] */ 246 P1_1_BTSS_UART_TXD = 27, /* Digital Active - btss.uart_txd:2 */ 247 P1_1_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 248 P1_1_IOSS_DDFT_PIN0 = 31, /* Digital Deep Sleep - ioss.ddft_pin[0]:0 */ 249 250 /* P1.2 */ 251 P1_2_GPIO = 0, /* GPIO controls 'out' */ 252 P1_2_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 253 P1_2_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 254 P1_2_BTSS_GPIO0 = 10, /* Digital Active - btss.gpio[0]:0 */ 255 P1_2_BTSS_RPU_SWD = 11, /* Digital Active - btss.rpu_swd */ 256 P1_2_KEYSCAN_KS_COL17 = 15, /* Digital Deep Sleep - keyscan.ks_col[17]:0 */ 257 P1_2_CPUSS_TRACE_CLOCK = 17, /* Digital Active - cpuss.trace_clock:1 */ 258 P1_2_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 259 P1_2_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 260 P1_2_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 261 P1_2_PERI_TR_IO_INPUT2 = 22, /* Digital Active - peri.tr_io_input[2]:0 */ 262 P1_2_BTSS_GCI_GPIO3 = 25, /* Digital Active - btss.gci_gpio[3] */ 263 P1_2_BTSS_DEBUG7 = 26, /* Digital Active - btss.debug[7]:0 */ 264 P1_2_BTSS_SPI_MOSI = 27, /* Digital Active - btss.spi_mosi:1 */ 265 P1_2_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 266 267 /* P1.3 */ 268 P1_3_GPIO = 0, /* GPIO controls 'out' */ 269 P1_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 270 P1_3_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ 271 P1_3_BTSS_GPIO1 = 10, /* Digital Active - btss.gpio[1]:0 */ 272 P1_3_BTSS_RPU_TCK = 11, /* Digital Active - btss.rpu_tck */ 273 P1_3_KEYSCAN_KS_COL16 = 15, /* Digital Deep Sleep - keyscan.ks_col[16]:0 */ 274 P1_3_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 275 P1_3_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 276 P1_3_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 277 P1_3_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 278 P1_3_PERI_TR_IO_INPUT3 = 22, /* Digital Active - peri.tr_io_input[3]:0 */ 279 P1_3_BTSS_GCI_GPIO4 = 25, /* Digital Active - btss.gci_gpio[4] */ 280 P1_3_BTSS_DEBUG8 = 26, /* Digital Active - btss.debug[8]:0 */ 281 P1_3_BTSS_SPI_CLK = 27, /* Digital Active - btss.spi_clk:1 */ 282 P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.clk_swj_swclk_tclk */ 283 284 /* P2.0 */ 285 P2_0_GPIO = 0, /* GPIO controls 'out' */ 286 P2_0_SMIF_SPIHB_SELECT0 = 27, /* Digital Active - smif.spihb_select0 */ 287 288 /* P2.1 */ 289 P2_1_GPIO = 0, /* GPIO controls 'out' */ 290 P2_1_SMIF_SPIHB_DATA3 = 27, /* Digital Active - smif.spihb_data3 */ 291 292 /* P2.2 */ 293 P2_2_GPIO = 0, /* GPIO controls 'out' */ 294 P2_2_SMIF_SPIHB_DATA2 = 27, /* Digital Active - smif.spihb_data2 */ 295 296 /* P2.3 */ 297 P2_3_GPIO = 0, /* GPIO controls 'out' */ 298 P2_3_SMIF_SPIHB_DATA1 = 27, /* Digital Active - smif.spihb_data1 */ 299 300 /* P2.4 */ 301 P2_4_GPIO = 0, /* GPIO controls 'out' */ 302 P2_4_SMIF_SPIHB_DATA0 = 27, /* Digital Active - smif.spihb_data0 */ 303 304 /* P2.5 */ 305 P2_5_GPIO = 0, /* GPIO controls 'out' */ 306 P2_5_SMIF_SPIHB_CLK = 27, /* Digital Active - smif.spihb_clk */ 307 308 /* P3.1 */ 309 P3_1_GPIO = 0, /* GPIO controls 'out' */ 310 P3_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 311 P3_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 312 P3_1_BTSS_RPU_NTRST = 11, /* Digital Active - btss.rpu_ntrst */ 313 P3_1_KEYSCAN_KS_ROW4 = 14, /* Digital Deep Sleep - keyscan.ks_row[4] */ 314 P3_1_CPUSS_TRACE_DATA2 = 17, /* Digital Active - cpuss.trace_data[2]:0 */ 315 P3_1_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 316 P3_1_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 317 P3_1_LIN0_LIN_EN0 = 23, /* Digital Active - lin[0].lin_en[0]:0 */ 318 P3_1_BTSS_UART_RTS = 26, /* Digital Active - btss.uart_rts:0 */ 319 P3_1_BTSS_SYSCLK_RF = 27, /* Digital Active - btss.sysclk_rf */ 320 P3_1_CPUSS_RST_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.rst_swj_trstn */ 321 322 /* P3.2 */ 323 P3_2_GPIO = 0, /* GPIO controls 'out' */ 324 P3_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 325 P3_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ 326 P3_2_BTSS_TXD_SYMB_DATA_TEST0 = 11, /* Digital Active - btss.txd_symb_data_test[0] */ 327 P3_2_KEYSCAN_KS_COL13 = 14, /* Digital Deep Sleep - keyscan.ks_col[13] */ 328 P3_2_CPUSS_TRACE_DATA1 = 17, /* Digital Active - cpuss.trace_data[1]:0 */ 329 P3_2_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 330 P3_2_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 331 P3_2_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 332 P3_2_PDM_PDM_CLK0 = 21, /* Digital Active - pdm.pdm_clk[0]:0 */ 333 P3_2_PERI_TR_IO_INPUT6 = 22, /* Digital Active - peri.tr_io_input[6]:0 */ 334 P3_2_LIN0_LIN_RX0 = 23, /* Digital Active - lin[0].lin_rx[0]:0 */ 335 P3_2_CANFD0_TTCAN_RX0 = 24, /* Digital Active - canfd[0].ttcan_rx[0] */ 336 P3_2_ADCMIC_CLK_PDM = 25, /* Digital Active - adcmic.clk_pdm:0 */ 337 P3_2_BTSS_UART_RXD = 27, /* Digital Active - btss.uart_rxd:0 */ 338 P3_2_IOSS_DDFT_PIN1 = 31, /* Digital Deep Sleep - ioss.ddft_pin[1]:1 */ 339 340 /* P3.3 */ 341 P3_3_GPIO = 0, /* GPIO controls 'out' */ 342 P3_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 343 P3_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 344 P3_3_BTSS_TXD_SYMB_DATA_TEST1 = 11, /* Digital Active - btss.txd_symb_data_test[1] */ 345 P3_3_KEYSCAN_KS_COL14 = 14, /* Digital Deep Sleep - keyscan.ks_col[14] */ 346 P3_3_KEYSCAN_KS_COL17 = 15, /* Digital Deep Sleep - keyscan.ks_col[17]:1 */ 347 P3_3_CPUSS_TRACE_DATA0 = 17, /* Digital Active - cpuss.trace_data[0]:0 */ 348 P3_3_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 349 P3_3_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 350 P3_3_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 351 P3_3_PDM_PDM_DATA0 = 21, /* Digital Active - pdm.pdm_data[0]:0 */ 352 P3_3_PERI_TR_IO_INPUT7 = 22, /* Digital Active - peri.tr_io_input[7]:0 */ 353 P3_3_LIN0_LIN_TX0 = 23, /* Digital Active - lin[0].lin_tx[0]:0 */ 354 P3_3_CANFD0_TTCAN_TX0 = 24, /* Digital Active - canfd[0].ttcan_tx[0] */ 355 P3_3_ADCMIC_PDM_DATA = 25, /* Digital Active - adcmic.pdm_data:0 */ 356 P3_3_BTSS_UART_TXD = 27, /* Digital Active - btss.uart_txd:0 */ 357 P3_3_IOSS_DDFT_PIN0 = 31, /* Digital Deep Sleep - ioss.ddft_pin[0]:1 */ 358 359 /* P4.0 */ 360 P4_0_GPIO = 0, /* GPIO controls 'out' */ 361 P4_0_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 362 P4_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 363 P4_0_BTSS_GPIO2 = 10, /* Digital Active - btss.gpio[2] */ 364 P4_0_BTSS_TXD_SYMB_STRB_TEST = 11, /* Digital Active - btss.txd_symb_strb_test */ 365 P4_0_KEYSCAN_KS_ROW2 = 14, /* Digital Deep Sleep - keyscan.ks_row[2] */ 366 P4_0_SCB0_I2C_SCL = 15, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 367 P4_0_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:2 */ 368 P4_0_BTSS_DEBUG1 = 26, /* Digital Active - btss.debug[1]:0 */ 369 P4_0_BTSS_UART_TXD = 27, /* Digital Active - btss.uart_txd:1 */ 370 P4_0_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 371 372 /* P4.1 */ 373 P4_1_GPIO = 0, /* GPIO controls 'out' */ 374 P4_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 375 P4_1_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ 376 P4_1_BTSS_GPIO4 = 10, /* Digital Active - btss.gpio[4]:1 */ 377 P4_1_BTSS_TXD_PYLD_MOD_TEST0 = 11, /* Digital Active - btss.txd_pyld_mod_test[0] */ 378 P4_1_KEYSCAN_KS_ROW3 = 14, /* Digital Deep Sleep - keyscan.ks_row[3] */ 379 P4_1_SCB0_I2C_SDA = 15, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 380 P4_1_BTSS_DEBUG2 = 26, /* Digital Active - btss.debug[2]:0 */ 381 P4_1_BTSS_SPI_MOSI = 27, /* Digital Active - btss.spi_mosi:0 */ 382 P4_1_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 383 384 /* P5.0 */ 385 P5_0_GPIO = 0, /* GPIO controls 'out' */ 386 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 387 P5_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ 388 P5_0_BTSS_TXD_SYMB_DATA_TEST2 = 11, /* Digital Active - btss.txd_symb_data_test[2] */ 389 P5_0_KEYSCAN_KS_COL0 = 14, /* Digital Deep Sleep - keyscan.ks_col[0] */ 390 P5_0_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:1 */ 391 P5_0_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:2 */ 392 P5_0_PDM_PDM_CLK0 = 21, /* Digital Active - pdm.pdm_clk[0]:1 */ 393 P5_0_ADCMIC_CLK_PDM = 25, /* Digital Active - adcmic.clk_pdm:1 */ 394 P5_0_BTSS_UART_CTS = 26, /* Digital Active - btss.uart_cts:1 */ 395 396 /* P5.1 */ 397 P5_1_GPIO = 0, /* GPIO controls 'out' */ 398 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 399 P5_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 400 P5_1_BTSS_GPIO3 = 10, /* Digital Active - btss.gpio[3] */ 401 P5_1_BTSS_TXD_SYMB_DATA_TEST3 = 11, /* Digital Active - btss.txd_symb_data_test[3] */ 402 P5_1_KEYSCAN_KS_COL1 = 14, /* Digital Deep Sleep - keyscan.ks_col[1] */ 403 P5_1_PDM_PDM_DATA0 = 21, /* Digital Active - pdm.pdm_data[0]:1 */ 404 P5_1_ADCMIC_PDM_DATA = 25, /* Digital Active - adcmic.pdm_data:1 */ 405 P5_1_BTSS_DEBUG0 = 26, /* Digital Active - btss.debug[0] */ 406 P5_1_BTSS_UART_RXD = 27, /* Digital Active - btss.uart_rxd:1 */ 407 P5_1_SCB0_SPI_SELECT0 = 30 /* Digital Deep Sleep - scb[0].spi_select0:0 */ 408 } en_hsiom_sel_t; 409 410 #endif /* _GPIO_CYW20829A0_40_QFN_H_ */ 411 412 413 /* [] END OF FILE */ 414
