1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 DCDC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_DCDC_H 31 #define EFR32BG22_DCDC_H 32 #define DCDC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_DCDC DCDC 40 * @{ 41 * @brief EFR32BG22 DCDC Register Declaration. 42 *****************************************************************************/ 43 44 /** DCDC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IPVERSION */ 47 __IOM uint32_t EN; /**< Enable */ 48 __IOM uint32_t CTRL; /**< Control */ 49 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 50 __IOM uint32_t EM01CTRL0; /**< EM01 Control */ 51 __IOM uint32_t EM23CTRL0; /**< EM23 Control */ 52 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 53 __IOM uint32_t IF; /**< Interrupt Flags */ 54 __IOM uint32_t IEN; /**< Interrupt Enable */ 55 __IM uint32_t STATUS; /**< Status Register */ 56 uint32_t RESERVED2[4U]; /**< Reserved for future use */ 57 __IOM uint32_t LOCK; /**< Lock Register */ 58 __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ 59 uint32_t RESERVED3[2U]; /**< Reserved for future use */ 60 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 61 uint32_t RESERVED5[7U]; /**< Reserved for future use */ 62 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 63 uint32_t RESERVED7[995U]; /**< Reserved for future use */ 64 __IM uint32_t IPVERSION_SET; /**< IPVERSION */ 65 __IOM uint32_t EN_SET; /**< Enable */ 66 __IOM uint32_t CTRL_SET; /**< Control */ 67 uint32_t RESERVED8[1U]; /**< Reserved for future use */ 68 __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ 69 __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ 70 uint32_t RESERVED9[3U]; /**< Reserved for future use */ 71 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 72 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 73 __IM uint32_t STATUS_SET; /**< Status Register */ 74 uint32_t RESERVED10[4U]; /**< Reserved for future use */ 75 __IOM uint32_t LOCK_SET; /**< Lock Register */ 76 __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ 77 uint32_t RESERVED11[2U]; /**< Reserved for future use */ 78 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 79 uint32_t RESERVED13[7U]; /**< Reserved for future use */ 80 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 81 uint32_t RESERVED15[995U]; /**< Reserved for future use */ 82 __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ 83 __IOM uint32_t EN_CLR; /**< Enable */ 84 __IOM uint32_t CTRL_CLR; /**< Control */ 85 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 86 __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ 87 __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ 88 uint32_t RESERVED17[3U]; /**< Reserved for future use */ 89 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 90 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 91 __IM uint32_t STATUS_CLR; /**< Status Register */ 92 uint32_t RESERVED18[4U]; /**< Reserved for future use */ 93 __IOM uint32_t LOCK_CLR; /**< Lock Register */ 94 __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ 95 uint32_t RESERVED19[2U]; /**< Reserved for future use */ 96 uint32_t RESERVED20[1U]; /**< Reserved for future use */ 97 uint32_t RESERVED21[7U]; /**< Reserved for future use */ 98 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 99 uint32_t RESERVED23[995U]; /**< Reserved for future use */ 100 __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ 101 __IOM uint32_t EN_TGL; /**< Enable */ 102 __IOM uint32_t CTRL_TGL; /**< Control */ 103 uint32_t RESERVED24[1U]; /**< Reserved for future use */ 104 __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ 105 __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ 106 uint32_t RESERVED25[3U]; /**< Reserved for future use */ 107 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 108 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 109 __IM uint32_t STATUS_TGL; /**< Status Register */ 110 uint32_t RESERVED26[4U]; /**< Reserved for future use */ 111 __IOM uint32_t LOCK_TGL; /**< Lock Register */ 112 __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ 113 uint32_t RESERVED27[2U]; /**< Reserved for future use */ 114 uint32_t RESERVED28[1U]; /**< Reserved for future use */ 115 uint32_t RESERVED29[7U]; /**< Reserved for future use */ 116 uint32_t RESERVED30[1U]; /**< Reserved for future use */ 117 } DCDC_TypeDef; 118 /** @} End of group EFR32BG22_DCDC */ 119 120 /**************************************************************************//** 121 * @addtogroup EFR32BG22_DCDC 122 * @{ 123 * @defgroup EFR32BG22_DCDC_BitFields DCDC Bit Fields 124 * @{ 125 *****************************************************************************/ 126 127 /* Bit fields for DCDC IPVERSION */ 128 #define _DCDC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for DCDC_IPVERSION */ 129 #define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ 130 #define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ 131 #define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ 132 #define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IPVERSION */ 133 #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ 134 135 /* Bit fields for DCDC EN */ 136 #define _DCDC_EN_RESETVALUE 0x00000000UL /**< Default value for DCDC_EN */ 137 #define _DCDC_EN_MASK 0x00000001UL /**< Mask for DCDC_EN */ 138 #define DCDC_EN_EN (0x1UL << 0) /**< Enable */ 139 #define _DCDC_EN_EN_SHIFT 0 /**< Shift value for DCDC_EN */ 140 #define _DCDC_EN_EN_MASK 0x1UL /**< Bit mask for DCDC_EN */ 141 #define _DCDC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_EN */ 142 #define _DCDC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for DCDC_EN */ 143 #define _DCDC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for DCDC_EN */ 144 #define DCDC_EN_EN_DEFAULT (_DCDC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EN */ 145 #define DCDC_EN_EN_DISABLE (_DCDC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for DCDC_EN */ 146 #define DCDC_EN_EN_ENABLE (_DCDC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for DCDC_EN */ 147 148 /* Bit fields for DCDC CTRL */ 149 #define _DCDC_CTRL_RESETVALUE 0x00000044UL /**< Default value for DCDC_CTRL */ 150 #define _DCDC_CTRL_MASK 0x00000077UL /**< Mask for DCDC_CTRL */ 151 #define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ 152 #define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ 153 #define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ 154 #define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ 155 #define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ 156 #define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ 157 #define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ 158 #define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ 159 #define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ 160 #define DCDC_CTRL_DCMONLYEN (0x1UL << 2) /**< DCDC DCM Only Enable */ 161 #define _DCDC_CTRL_DCMONLYEN_SHIFT 2 /**< Shift value for DCDC_DCMONLYEN */ 162 #define _DCDC_CTRL_DCMONLYEN_MASK 0x4UL /**< Bit mask for DCDC_DCMONLYEN */ 163 #define _DCDC_CTRL_DCMONLYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CTRL */ 164 #define _DCDC_CTRL_DCMONLYEN_DUALMODE 0x00000000UL /**< Mode DUALMODE for DCDC_CTRL */ 165 #define _DCDC_CTRL_DCMONLYEN_DCMONLYEN 0x00000001UL /**< Mode DCMONLYEN for DCDC_CTRL */ 166 #define DCDC_CTRL_DCMONLYEN_DEFAULT (_DCDC_CTRL_DCMONLYEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CTRL */ 167 #define DCDC_CTRL_DCMONLYEN_DUALMODE (_DCDC_CTRL_DCMONLYEN_DUALMODE << 2) /**< Shifted mode DUALMODE for DCDC_CTRL */ 168 #define DCDC_CTRL_DCMONLYEN_DCMONLYEN (_DCDC_CTRL_DCMONLYEN_DCMONLYEN << 2) /**< Shifted mode DCMONLYEN for DCDC_CTRL */ 169 #define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ 170 #define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ 171 #define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_CTRL */ 172 #define _DCDC_CTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_CTRL */ 173 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_CTRL */ 174 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_CTRL */ 175 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_CTRL */ 176 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_CTRL */ 177 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_CTRL */ 178 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_CTRL */ 179 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_CTRL */ 180 #define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ 181 #define DCDC_CTRL_IPKTMAXCTRL_OFF (_DCDC_CTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_CTRL */ 182 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_CTRL */ 183 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_CTRL */ 184 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_CTRL */ 185 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_CTRL */ 186 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_CTRL */ 187 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_CTRL */ 188 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_CTRL */ 189 190 /* Bit fields for DCDC EM01CTRL0 */ 191 #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ 192 #define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ 193 #define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 194 #define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 195 #define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ 196 #define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ 197 #define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ 198 #define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ 199 #define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ 200 #define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ 201 #define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ 202 #define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ 203 #define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ 204 #define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ 205 #define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ 206 #define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ 207 #define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ 208 #define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ 209 #define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ 210 #define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ 211 #define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 212 #define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 213 #define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ 214 #define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ 215 #define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ 216 #define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ 217 #define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ 218 #define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ 219 #define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ 220 #define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ 221 #define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ 222 #define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ 223 224 /* Bit fields for DCDC EM23CTRL0 */ 225 #define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ 226 #define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ 227 #define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 228 #define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 229 #define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ 230 #define _DCDC_EM23CTRL0_IPKVAL_LOAD5MA 0x00000003UL /**< Mode LOAD5MA for DCDC_EM23CTRL0 */ 231 #define _DCDC_EM23CTRL0_IPKVAL_LOAD10MA 0x00000009UL /**< Mode LOAD10MA for DCDC_EM23CTRL0 */ 232 #define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ 233 #define DCDC_EM23CTRL0_IPKVAL_LOAD5MA (_DCDC_EM23CTRL0_IPKVAL_LOAD5MA << 0) /**< Shifted mode LOAD5MA for DCDC_EM23CTRL0 */ 234 #define DCDC_EM23CTRL0_IPKVAL_LOAD10MA (_DCDC_EM23CTRL0_IPKVAL_LOAD10MA << 0) /**< Shifted mode LOAD10MA for DCDC_EM23CTRL0 */ 235 #define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 236 #define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 237 #define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ 238 #define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ 239 #define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ 240 #define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ 241 #define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ 242 #define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ 243 #define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ 244 #define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ 245 #define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ 246 #define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ 247 248 /* Bit fields for DCDC IF */ 249 #define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ 250 #define _DCDC_IF_MASK 0x000000FFUL /**< Mask for DCDC_IF */ 251 #define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ 252 #define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 253 #define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 254 #define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 255 #define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ 256 #define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ 257 #define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 258 #define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 259 #define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 260 #define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ 261 #define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ 262 #define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 263 #define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 264 #define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 265 #define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ 266 #define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold */ 267 #define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ 268 #define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ 269 #define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 270 #define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ 271 #define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold */ 272 #define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ 273 #define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ 274 #define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 275 #define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ 276 #define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ 277 #define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ 278 #define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ 279 #define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 280 #define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ 281 #define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ 282 #define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ 283 #define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ 284 #define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 285 #define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ 286 #define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ 287 #define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ 288 #define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ 289 #define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 290 #define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ 291 292 /* Bit fields for DCDC IEN */ 293 #define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ 294 #define _DCDC_IEN_MASK 0x000000FFUL /**< Mask for DCDC_IEN */ 295 #define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ 296 #define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 297 #define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 298 #define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 299 #define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ 300 #define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ 301 #define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 302 #define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 303 #define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 304 #define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ 305 #define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ 306 #define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 307 #define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 308 #define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 309 #define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ 310 #define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold Interrupt Enable */ 311 #define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ 312 #define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ 313 #define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 314 #define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ 315 #define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold Interrupt Enable */ 316 #define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ 317 #define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ 318 #define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 319 #define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ 320 #define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ 321 #define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ 322 #define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ 323 #define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 324 #define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ 325 #define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ 326 #define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ 327 #define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ 328 #define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 329 #define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ 330 #define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ 331 #define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ 332 #define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ 333 #define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 334 #define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ 335 336 /* Bit fields for DCDC STATUS */ 337 #define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ 338 #define _DCDC_STATUS_MASK 0x0000001FUL /**< Mask for DCDC_STATUS */ 339 #define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ 340 #define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 341 #define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 342 #define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 343 #define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ 344 #define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ 345 #define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 346 #define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 347 #define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 348 #define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ 349 #define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ 350 #define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 351 #define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 352 #define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 353 #define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ 354 #define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ 355 #define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ 356 #define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ 357 #define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 358 #define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ 359 #define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ 360 #define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ 361 #define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ 362 #define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 363 #define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ 364 365 /* Bit fields for DCDC LOCK */ 366 #define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ 367 #define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ 368 #define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ 369 #define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ 370 #define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ 371 #define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ 372 #define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ 373 #define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ 374 375 /* Bit fields for DCDC LOCKSTATUS */ 376 #define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ 377 #define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ 378 #define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ 379 #define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ 380 #define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ 381 #define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ 382 #define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ 383 #define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ 384 #define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ 385 #define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ 386 #define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ 387 388 /** @} End of group EFR32BG22_DCDC_BitFields */ 389 /** @} End of group EFR32BG22_DCDC */ 390 /** @} End of group Parts */ 391 392 #endif /* EFR32BG22_DCDC_H */ 393
