1 /***************************************************************************//**
2 * \file cyhal_triggers_psoc6_01.h
3 *
4 * \brief
5 * PSoC6_01 family HAL triggers header
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _CYHAL_TRIGGERS_PSOC6_01_H_
28 #define _CYHAL_TRIGGERS_PSOC6_01_H_
29 
30 /**
31  * \addtogroup group_hal_impl_triggers_psoc6_01 PSOC6_01
32  * \ingroup group_hal_impl_triggers
33  * \{
34  * Trigger connections for psoc6_01
35  */
36 
37 #if defined(__cplusplus)
38 extern "C" {
39 #endif /* __cplusplus */
40 
41 /** \cond INTERNAL */
42 /** @brief Name of each input trigger. */
43 typedef enum
44 {
45     _CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero
46     _CYHAL_TRIGGER_AUDIOSS_TR_I2S_RX_REQ = 1, //!< audioss.tr_i2s_rx_req
47     _CYHAL_TRIGGER_AUDIOSS_TR_I2S_TX_REQ = 2, //!< audioss.tr_i2s_tx_req
48     _CYHAL_TRIGGER_AUDIOSS_TR_PDM_RX_REQ = 3, //!< audioss.tr_pdm_rx_req
49     _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 4, //!< cpuss.cti_tr_out[0]
50     _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 5, //!< cpuss.cti_tr_out[1]
51     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 6, //!< cpuss.dw0_tr_out[0]
52     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 7, //!< cpuss.dw0_tr_out[1]
53     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 8, //!< cpuss.dw0_tr_out[2]
54     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 9, //!< cpuss.dw0_tr_out[3]
55     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 10, //!< cpuss.dw0_tr_out[4]
56     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 11, //!< cpuss.dw0_tr_out[5]
57     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 12, //!< cpuss.dw0_tr_out[6]
58     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 13, //!< cpuss.dw0_tr_out[7]
59     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 14, //!< cpuss.dw0_tr_out[8]
60     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 15, //!< cpuss.dw0_tr_out[9]
61     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 16, //!< cpuss.dw0_tr_out[10]
62     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 17, //!< cpuss.dw0_tr_out[11]
63     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 18, //!< cpuss.dw0_tr_out[12]
64     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 19, //!< cpuss.dw0_tr_out[13]
65     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 20, //!< cpuss.dw0_tr_out[14]
66     _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 21, //!< cpuss.dw0_tr_out[15]
67     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 22, //!< cpuss.dw1_tr_out[0]
68     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 23, //!< cpuss.dw1_tr_out[1]
69     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 24, //!< cpuss.dw1_tr_out[2]
70     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 25, //!< cpuss.dw1_tr_out[3]
71     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 26, //!< cpuss.dw1_tr_out[4]
72     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 27, //!< cpuss.dw1_tr_out[5]
73     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 28, //!< cpuss.dw1_tr_out[6]
74     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 29, //!< cpuss.dw1_tr_out[7]
75     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 30, //!< cpuss.dw1_tr_out[8]
76     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 31, //!< cpuss.dw1_tr_out[9]
77     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 32, //!< cpuss.dw1_tr_out[10]
78     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 33, //!< cpuss.dw1_tr_out[11]
79     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 34, //!< cpuss.dw1_tr_out[12]
80     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 35, //!< cpuss.dw1_tr_out[13]
81     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 36, //!< cpuss.dw1_tr_out[14]
82     _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 37, //!< cpuss.dw1_tr_out[15]
83     _CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 38, //!< cpuss.tr_fault[0]
84     _CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 39, //!< cpuss.tr_fault[1]
85     _CYHAL_TRIGGER_CSD_DSI_SENSE_OUT = 40, //!< csd.dsi_sense_out
86     _CYHAL_TRIGGER_CSD_TR_ADC_DONE = 41, //!< csd.tr_adc_done
87     _CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 42, //!< lpcomp.dsi_comp0
88     _CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 43, //!< lpcomp.dsi_comp1
89     _CYHAL_TRIGGER_PASS_DSI_CTB_CMP0 = 44, //!< pass.dsi_ctb_cmp0
90     _CYHAL_TRIGGER_PASS_DSI_CTB_CMP1 = 45, //!< pass.dsi_ctb_cmp1
91     _CYHAL_TRIGGER_PASS_TR_CTDAC_EMPTY = 46, //!< pass.tr_ctdac_empty
92     _CYHAL_TRIGGER_PASS_TR_SAR_OUT = 47, //!< pass.tr_sar_out
93     _CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 48, //!< peri.tr_io_input[0]
94     _CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 49, //!< peri.tr_io_input[1]
95     _CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 50, //!< peri.tr_io_input[2]
96     _CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 51, //!< peri.tr_io_input[3]
97     _CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 52, //!< peri.tr_io_input[4]
98     _CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 53, //!< peri.tr_io_input[5]
99     _CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 54, //!< peri.tr_io_input[6]
100     _CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 55, //!< peri.tr_io_input[7]
101     _CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 56, //!< peri.tr_io_input[8]
102     _CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 57, //!< peri.tr_io_input[9]
103     _CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 58, //!< peri.tr_io_input[10]
104     _CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 59, //!< peri.tr_io_input[11]
105     _CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 60, //!< peri.tr_io_input[12]
106     _CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 61, //!< peri.tr_io_input[13]
107     _CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 62, //!< peri.tr_io_input[14]
108     _CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 63, //!< peri.tr_io_input[15]
109     _CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 64, //!< peri.tr_io_input[16]
110     _CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 65, //!< peri.tr_io_input[17]
111     _CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 66, //!< peri.tr_io_input[18]
112     _CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 67, //!< peri.tr_io_input[19]
113     _CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 68, //!< peri.tr_io_input[20]
114     _CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 69, //!< peri.tr_io_input[21]
115     _CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 70, //!< peri.tr_io_input[22]
116     _CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 71, //!< peri.tr_io_input[23]
117     _CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 72, //!< peri.tr_io_input[24]
118     _CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 73, //!< peri.tr_io_input[25]
119     _CYHAL_TRIGGER_PERI_TR_IO_INPUT26 = 74, //!< peri.tr_io_input[26]
120     _CYHAL_TRIGGER_PERI_TR_IO_INPUT27 = 75, //!< peri.tr_io_input[27]
121     _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 76, //!< scb[0].tr_i2c_scl_filtered
122     _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 77, //!< scb[1].tr_i2c_scl_filtered
123     _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 78, //!< scb[2].tr_i2c_scl_filtered
124     _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 79, //!< scb[3].tr_i2c_scl_filtered
125     _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 80, //!< scb[4].tr_i2c_scl_filtered
126     _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 81, //!< scb[5].tr_i2c_scl_filtered
127     _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 82, //!< scb[6].tr_i2c_scl_filtered
128     _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 83, //!< scb[7].tr_i2c_scl_filtered
129     _CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = 84, //!< scb[8].tr_i2c_scl_filtered
130     _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 85, //!< scb[0].tr_rx_req
131     _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 86, //!< scb[1].tr_rx_req
132     _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 87, //!< scb[2].tr_rx_req
133     _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 88, //!< scb[3].tr_rx_req
134     _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 89, //!< scb[4].tr_rx_req
135     _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 90, //!< scb[5].tr_rx_req
136     _CYHAL_TRIGGER_SCB6_TR_RX_REQ = 91, //!< scb[6].tr_rx_req
137     _CYHAL_TRIGGER_SCB7_TR_RX_REQ = 92, //!< scb[7].tr_rx_req
138     _CYHAL_TRIGGER_SCB8_TR_RX_REQ = 93, //!< scb[8].tr_rx_req
139     _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 94, //!< scb[0].tr_tx_req
140     _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 95, //!< scb[1].tr_tx_req
141     _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 96, //!< scb[2].tr_tx_req
142     _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 97, //!< scb[3].tr_tx_req
143     _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 98, //!< scb[4].tr_tx_req
144     _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 99, //!< scb[5].tr_tx_req
145     _CYHAL_TRIGGER_SCB6_TR_TX_REQ = 100, //!< scb[6].tr_tx_req
146     _CYHAL_TRIGGER_SCB7_TR_TX_REQ = 101, //!< scb[7].tr_tx_req
147     _CYHAL_TRIGGER_SCB8_TR_TX_REQ = 102, //!< scb[8].tr_tx_req
148     _CYHAL_TRIGGER_SMIF_TR_RX_REQ = 103, //!< smif.tr_rx_req
149     _CYHAL_TRIGGER_SMIF_TR_TX_REQ = 104, //!< smif.tr_tx_req
150     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = 105, //!< tcpwm[0].tr_compare_match[0]
151     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = 106, //!< tcpwm[0].tr_compare_match[1]
152     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = 107, //!< tcpwm[0].tr_compare_match[2]
153     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = 108, //!< tcpwm[0].tr_compare_match[3]
154     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4 = 109, //!< tcpwm[0].tr_compare_match[4]
155     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5 = 110, //!< tcpwm[0].tr_compare_match[5]
156     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6 = 111, //!< tcpwm[0].tr_compare_match[6]
157     _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7 = 112, //!< tcpwm[0].tr_compare_match[7]
158     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = 113, //!< tcpwm[1].tr_compare_match[0]
159     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = 114, //!< tcpwm[1].tr_compare_match[1]
160     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = 115, //!< tcpwm[1].tr_compare_match[2]
161     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = 116, //!< tcpwm[1].tr_compare_match[3]
162     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = 117, //!< tcpwm[1].tr_compare_match[4]
163     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = 118, //!< tcpwm[1].tr_compare_match[5]
164     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = 119, //!< tcpwm[1].tr_compare_match[6]
165     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = 120, //!< tcpwm[1].tr_compare_match[7]
166     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8 = 121, //!< tcpwm[1].tr_compare_match[8]
167     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9 = 122, //!< tcpwm[1].tr_compare_match[9]
168     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10 = 123, //!< tcpwm[1].tr_compare_match[10]
169     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11 = 124, //!< tcpwm[1].tr_compare_match[11]
170     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12 = 125, //!< tcpwm[1].tr_compare_match[12]
171     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13 = 126, //!< tcpwm[1].tr_compare_match[13]
172     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14 = 127, //!< tcpwm[1].tr_compare_match[14]
173     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15 = 128, //!< tcpwm[1].tr_compare_match[15]
174     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16 = 129, //!< tcpwm[1].tr_compare_match[16]
175     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17 = 130, //!< tcpwm[1].tr_compare_match[17]
176     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18 = 131, //!< tcpwm[1].tr_compare_match[18]
177     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19 = 132, //!< tcpwm[1].tr_compare_match[19]
178     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20 = 133, //!< tcpwm[1].tr_compare_match[20]
179     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21 = 134, //!< tcpwm[1].tr_compare_match[21]
180     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22 = 135, //!< tcpwm[1].tr_compare_match[22]
181     _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23 = 136, //!< tcpwm[1].tr_compare_match[23]
182     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = 137, //!< tcpwm[0].tr_overflow[0]
183     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = 138, //!< tcpwm[0].tr_overflow[1]
184     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = 139, //!< tcpwm[0].tr_overflow[2]
185     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = 140, //!< tcpwm[0].tr_overflow[3]
186     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4 = 141, //!< tcpwm[0].tr_overflow[4]
187     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5 = 142, //!< tcpwm[0].tr_overflow[5]
188     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6 = 143, //!< tcpwm[0].tr_overflow[6]
189     _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7 = 144, //!< tcpwm[0].tr_overflow[7]
190     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = 145, //!< tcpwm[1].tr_overflow[0]
191     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = 146, //!< tcpwm[1].tr_overflow[1]
192     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = 147, //!< tcpwm[1].tr_overflow[2]
193     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = 148, //!< tcpwm[1].tr_overflow[3]
194     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = 149, //!< tcpwm[1].tr_overflow[4]
195     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = 150, //!< tcpwm[1].tr_overflow[5]
196     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = 151, //!< tcpwm[1].tr_overflow[6]
197     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = 152, //!< tcpwm[1].tr_overflow[7]
198     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8 = 153, //!< tcpwm[1].tr_overflow[8]
199     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9 = 154, //!< tcpwm[1].tr_overflow[9]
200     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10 = 155, //!< tcpwm[1].tr_overflow[10]
201     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11 = 156, //!< tcpwm[1].tr_overflow[11]
202     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12 = 157, //!< tcpwm[1].tr_overflow[12]
203     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13 = 158, //!< tcpwm[1].tr_overflow[13]
204     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14 = 159, //!< tcpwm[1].tr_overflow[14]
205     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15 = 160, //!< tcpwm[1].tr_overflow[15]
206     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16 = 161, //!< tcpwm[1].tr_overflow[16]
207     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17 = 162, //!< tcpwm[1].tr_overflow[17]
208     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18 = 163, //!< tcpwm[1].tr_overflow[18]
209     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19 = 164, //!< tcpwm[1].tr_overflow[19]
210     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20 = 165, //!< tcpwm[1].tr_overflow[20]
211     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21 = 166, //!< tcpwm[1].tr_overflow[21]
212     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22 = 167, //!< tcpwm[1].tr_overflow[22]
213     _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23 = 168, //!< tcpwm[1].tr_overflow[23]
214     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = 169, //!< tcpwm[0].tr_underflow[0]
215     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = 170, //!< tcpwm[0].tr_underflow[1]
216     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = 171, //!< tcpwm[0].tr_underflow[2]
217     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = 172, //!< tcpwm[0].tr_underflow[3]
218     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4 = 173, //!< tcpwm[0].tr_underflow[4]
219     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5 = 174, //!< tcpwm[0].tr_underflow[5]
220     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6 = 175, //!< tcpwm[0].tr_underflow[6]
221     _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7 = 176, //!< tcpwm[0].tr_underflow[7]
222     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = 177, //!< tcpwm[1].tr_underflow[0]
223     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = 178, //!< tcpwm[1].tr_underflow[1]
224     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = 179, //!< tcpwm[1].tr_underflow[2]
225     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = 180, //!< tcpwm[1].tr_underflow[3]
226     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = 181, //!< tcpwm[1].tr_underflow[4]
227     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = 182, //!< tcpwm[1].tr_underflow[5]
228     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = 183, //!< tcpwm[1].tr_underflow[6]
229     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = 184, //!< tcpwm[1].tr_underflow[7]
230     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8 = 185, //!< tcpwm[1].tr_underflow[8]
231     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9 = 186, //!< tcpwm[1].tr_underflow[9]
232     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10 = 187, //!< tcpwm[1].tr_underflow[10]
233     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11 = 188, //!< tcpwm[1].tr_underflow[11]
234     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12 = 189, //!< tcpwm[1].tr_underflow[12]
235     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13 = 190, //!< tcpwm[1].tr_underflow[13]
236     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14 = 191, //!< tcpwm[1].tr_underflow[14]
237     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15 = 192, //!< tcpwm[1].tr_underflow[15]
238     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16 = 193, //!< tcpwm[1].tr_underflow[16]
239     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17 = 194, //!< tcpwm[1].tr_underflow[17]
240     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18 = 195, //!< tcpwm[1].tr_underflow[18]
241     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19 = 196, //!< tcpwm[1].tr_underflow[19]
242     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20 = 197, //!< tcpwm[1].tr_underflow[20]
243     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21 = 198, //!< tcpwm[1].tr_underflow[21]
244     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22 = 199, //!< tcpwm[1].tr_underflow[22]
245     _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23 = 200, //!< tcpwm[1].tr_underflow[23]
246     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 = 201, //!< tr_group[10].output[0]
247     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 = 202, //!< tr_group[10].output[1]
248     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 = 203, //!< tr_group[10].output[2]
249     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 = 204, //!< tr_group[10].output[3]
250     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 = 205, //!< tr_group[10].output[4]
251     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT5 = 206, //!< tr_group[10].output[5]
252     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT6 = 207, //!< tr_group[10].output[6]
253     _CYHAL_TRIGGER_TR_GROUP10_OUTPUT7 = 208, //!< tr_group[10].output[7]
254     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT0 = 209, //!< tr_group[11].output[0]
255     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT1 = 210, //!< tr_group[11].output[1]
256     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT2 = 211, //!< tr_group[11].output[2]
257     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT3 = 212, //!< tr_group[11].output[3]
258     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT4 = 213, //!< tr_group[11].output[4]
259     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT5 = 214, //!< tr_group[11].output[5]
260     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT6 = 215, //!< tr_group[11].output[6]
261     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT7 = 216, //!< tr_group[11].output[7]
262     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT8 = 217, //!< tr_group[11].output[8]
263     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT9 = 218, //!< tr_group[11].output[9]
264     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT10 = 219, //!< tr_group[11].output[10]
265     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT11 = 220, //!< tr_group[11].output[11]
266     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT12 = 221, //!< tr_group[11].output[12]
267     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT13 = 222, //!< tr_group[11].output[13]
268     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT14 = 223, //!< tr_group[11].output[14]
269     _CYHAL_TRIGGER_TR_GROUP11_OUTPUT15 = 224, //!< tr_group[11].output[15]
270     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT0 = 225, //!< tr_group[12].output[0]
271     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT1 = 226, //!< tr_group[12].output[1]
272     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT2 = 227, //!< tr_group[12].output[2]
273     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT3 = 228, //!< tr_group[12].output[3]
274     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT4 = 229, //!< tr_group[12].output[4]
275     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT5 = 230, //!< tr_group[12].output[5]
276     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT6 = 231, //!< tr_group[12].output[6]
277     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT7 = 232, //!< tr_group[12].output[7]
278     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT8 = 233, //!< tr_group[12].output[8]
279     _CYHAL_TRIGGER_TR_GROUP12_OUTPUT9 = 234, //!< tr_group[12].output[9]
280     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT0 = 235, //!< tr_group[13].output[0]
281     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT1 = 236, //!< tr_group[13].output[1]
282     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT2 = 237, //!< tr_group[13].output[2]
283     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT3 = 238, //!< tr_group[13].output[3]
284     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT4 = 239, //!< tr_group[13].output[4]
285     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT5 = 240, //!< tr_group[13].output[5]
286     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT6 = 241, //!< tr_group[13].output[6]
287     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT7 = 242, //!< tr_group[13].output[7]
288     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT8 = 243, //!< tr_group[13].output[8]
289     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT9 = 244, //!< tr_group[13].output[9]
290     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT10 = 245, //!< tr_group[13].output[10]
291     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT11 = 246, //!< tr_group[13].output[11]
292     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT12 = 247, //!< tr_group[13].output[12]
293     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT13 = 248, //!< tr_group[13].output[13]
294     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT14 = 249, //!< tr_group[13].output[14]
295     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT15 = 250, //!< tr_group[13].output[15]
296     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT16 = 251, //!< tr_group[13].output[16]
297     _CYHAL_TRIGGER_TR_GROUP13_OUTPUT17 = 252, //!< tr_group[13].output[17]
298     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT0 = 253, //!< tr_group[14].output[0]
299     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT1 = 254, //!< tr_group[14].output[1]
300     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT2 = 255, //!< tr_group[14].output[2]
301     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT3 = 256, //!< tr_group[14].output[3]
302     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT4 = 257, //!< tr_group[14].output[4]
303     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT5 = 258, //!< tr_group[14].output[5]
304     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT6 = 259, //!< tr_group[14].output[6]
305     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT7 = 260, //!< tr_group[14].output[7]
306     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT8 = 261, //!< tr_group[14].output[8]
307     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT9 = 262, //!< tr_group[14].output[9]
308     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT10 = 263, //!< tr_group[14].output[10]
309     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT11 = 264, //!< tr_group[14].output[11]
310     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT12 = 265, //!< tr_group[14].output[12]
311     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT13 = 266, //!< tr_group[14].output[13]
312     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT14 = 267, //!< tr_group[14].output[14]
313     _CYHAL_TRIGGER_TR_GROUP14_OUTPUT15 = 268, //!< tr_group[14].output[15]
314     _CYHAL_TRIGGER_UDB_DSI_OUT_TR0 = 269, //!< udb.dsi_out_tr[0]
315     _CYHAL_TRIGGER_UDB_DSI_OUT_TR1 = 270, //!< udb.dsi_out_tr[1]
316     _CYHAL_TRIGGER_UDB_TR_UDB0 = 271, //!< udb.tr_udb[0]
317     _CYHAL_TRIGGER_UDB_TR_UDB1 = 272, //!< udb.tr_udb[1]
318     _CYHAL_TRIGGER_UDB_TR_UDB2 = 273, //!< udb.tr_udb[2]
319     _CYHAL_TRIGGER_UDB_TR_UDB3 = 274, //!< udb.tr_udb[3]
320     _CYHAL_TRIGGER_UDB_TR_UDB4 = 275, //!< udb.tr_udb[4]
321     _CYHAL_TRIGGER_UDB_TR_UDB5 = 276, //!< udb.tr_udb[5]
322     _CYHAL_TRIGGER_UDB_TR_UDB6 = 277, //!< udb.tr_udb[6]
323     _CYHAL_TRIGGER_UDB_TR_UDB7 = 278, //!< udb.tr_udb[7]
324     _CYHAL_TRIGGER_UDB_TR_UDB8 = 279, //!< udb.tr_udb[8]
325     _CYHAL_TRIGGER_UDB_TR_UDB9 = 280, //!< udb.tr_udb[9]
326     _CYHAL_TRIGGER_UDB_TR_UDB10 = 281, //!< udb.tr_udb[10]
327     _CYHAL_TRIGGER_UDB_TR_UDB11 = 282, //!< udb.tr_udb[11]
328     _CYHAL_TRIGGER_UDB_TR_UDB12 = 283, //!< udb.tr_udb[12]
329     _CYHAL_TRIGGER_UDB_TR_UDB13 = 284, //!< udb.tr_udb[13]
330     _CYHAL_TRIGGER_UDB_TR_UDB14 = 285, //!< udb.tr_udb[14]
331     _CYHAL_TRIGGER_UDB_TR_UDB15 = 286, //!< udb.tr_udb[15]
332     _CYHAL_TRIGGER_USB_DMA_REQ0 = 287, //!< usb.dma_req[0]
333     _CYHAL_TRIGGER_USB_DMA_REQ1 = 288, //!< usb.dma_req[1]
334     _CYHAL_TRIGGER_USB_DMA_REQ2 = 289, //!< usb.dma_req[2]
335     _CYHAL_TRIGGER_USB_DMA_REQ3 = 290, //!< usb.dma_req[3]
336     _CYHAL_TRIGGER_USB_DMA_REQ4 = 291, //!< usb.dma_req[4]
337     _CYHAL_TRIGGER_USB_DMA_REQ5 = 292, //!< usb.dma_req[5]
338     _CYHAL_TRIGGER_USB_DMA_REQ6 = 293, //!< usb.dma_req[6]
339     _CYHAL_TRIGGER_USB_DMA_REQ7 = 294, //!< usb.dma_req[7]
340 } _cyhal_trigger_source_psoc6_01_t;
341 
342 /** Typedef for internal device family specific trigger source to generic trigger source */
343 typedef _cyhal_trigger_source_psoc6_01_t cyhal_internal_source_t;
344 
345 /** @brief Get a public source signal type (cyhal_trigger_source_psoc6_01_t) given an internal source signal and signal type */
346 #define _CYHAL_TRIGGER_CREATE_SOURCE(src, type)    ((src) << 1 | (type))
347 /** @brief Get an internal source signal (_cyhal_trigger_source_psoc6_01_t) given a public source signal. */
348 #define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src)      ((cyhal_internal_source_t)((src) >> 1))
349 /** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */
350 #define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src)        ((cyhal_signal_type_t)((src) & 1))
351 /** \endcond */
352 
353 /** @brief Name of each input trigger. */
354 typedef enum
355 {
356     CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.zero
357     CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.zero
358     CYHAL_TRIGGER_AUDIOSS_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss.tr_i2s_rx_req
359     CYHAL_TRIGGER_AUDIOSS_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss.tr_i2s_tx_req
360     CYHAL_TRIGGER_AUDIOSS_TR_PDM_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS_TR_PDM_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss.tr_pdm_rx_req
361     CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[0]
362     CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[1]
363     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[0]
364     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[1]
365     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[2]
366     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[3]
367     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[4]
368     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[5]
369     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[6]
370     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[7]
371     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[8]
372     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[9]
373     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[10]
374     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[11]
375     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[12]
376     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[13]
377     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[14]
378     CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[15]
379     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[0]
380     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[1]
381     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[2]
382     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[3]
383     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[4]
384     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[5]
385     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[6]
386     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[7]
387     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[8]
388     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[9]
389     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[10]
390     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[11]
391     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[12]
392     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[13]
393     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[14]
394     CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[15]
395     CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[0]
396     CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[1]
397     CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< csd.dsi_sense_out
398     CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_LEVEL), //!< csd.dsi_sense_out
399     CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_EDGE), //!< csd.tr_adc_done
400     CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_LEVEL), //!< csd.tr_adc_done
401     CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP0, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp0
402     CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP1, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp1
403     CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.dsi_ctb_cmp0
404     CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.dsi_ctb_cmp0
405     CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.dsi_ctb_cmp1
406     CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_DSI_CTB_CMP1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.dsi_ctb_cmp1
407     CYHAL_TRIGGER_PASS_TR_CTDAC_EMPTY = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_CTDAC_EMPTY, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_ctdac_empty
408     CYHAL_TRIGGER_PASS_TR_SAR_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_sar_out
409     CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[0]
410     CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[0]
411     CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[1]
412     CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[1]
413     CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[2]
414     CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[2]
415     CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[3]
416     CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[3]
417     CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[4]
418     CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[4]
419     CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[5]
420     CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[5]
421     CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[6]
422     CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[6]
423     CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[7]
424     CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[7]
425     CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[8]
426     CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[8]
427     CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[9]
428     CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[9]
429     CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[10]
430     CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[10]
431     CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[11]
432     CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[11]
433     CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[12]
434     CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[12]
435     CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[13]
436     CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[13]
437     CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[14]
438     CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[14]
439     CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[15]
440     CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[15]
441     CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[16]
442     CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[16]
443     CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[17]
444     CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[17]
445     CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[18]
446     CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[18]
447     CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[19]
448     CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[19]
449     CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[20]
450     CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[20]
451     CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[21]
452     CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[21]
453     CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[22]
454     CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[22]
455     CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[23]
456     CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[23]
457     CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[24]
458     CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[24]
459     CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[25]
460     CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[25]
461     CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[26]
462     CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[26]
463     CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[27]
464     CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[27]
465     CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered
466     CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered
467     CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered
468     CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered
469     CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered
470     CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered
471     CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered
472     CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered
473     CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_i2c_scl_filtered
474     CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req
475     CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req
476     CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req
477     CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req
478     CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req
479     CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req
480     CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req
481     CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req
482     CYHAL_TRIGGER_SCB8_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_rx_req
483     CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req
484     CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req
485     CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req
486     CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req
487     CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req
488     CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req
489     CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req
490     CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req
491     CYHAL_TRIGGER_SCB8_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_tx_req
492     CYHAL_TRIGGER_SMIF_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif.tr_rx_req
493     CYHAL_TRIGGER_SMIF_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif.tr_tx_req
494     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[0]
495     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[1]
496     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[2]
497     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[3]
498     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[4]
499     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[5]
500     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[6]
501     CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[7]
502     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[0]
503     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[1]
504     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[2]
505     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[3]
506     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[4]
507     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[5]
508     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[6]
509     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[7]
510     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[8]
511     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[9]
512     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[10]
513     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[11]
514     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[12]
515     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[13]
516     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[14]
517     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[15]
518     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[16]
519     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[17]
520     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[18]
521     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[19]
522     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[20]
523     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[21]
524     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[22]
525     CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[23]
526     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[0]
527     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[1]
528     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[2]
529     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[3]
530     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[4]
531     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[5]
532     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[6]
533     CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[7]
534     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[0]
535     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[1]
536     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[2]
537     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[3]
538     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[4]
539     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[5]
540     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[6]
541     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[7]
542     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[8]
543     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[9]
544     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[10]
545     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[11]
546     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[12]
547     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[13]
548     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[14]
549     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[15]
550     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[16]
551     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[17]
552     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[18]
553     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[19]
554     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[20]
555     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[21]
556     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[22]
557     CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[23]
558     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[0]
559     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[1]
560     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[2]
561     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[3]
562     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[4]
563     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[5]
564     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[6]
565     CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[7]
566     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[0]
567     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[1]
568     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[2]
569     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[3]
570     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[4]
571     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[5]
572     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[6]
573     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[7]
574     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[8]
575     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[9]
576     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[10]
577     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[11]
578     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[12]
579     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[13]
580     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[14]
581     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[15]
582     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[16]
583     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[17]
584     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[18]
585     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[19]
586     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[20]
587     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[21]
588     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[22]
589     CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[23]
590     CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[0]
591     CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[0]
592     CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[1]
593     CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[1]
594     CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[2]
595     CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[2]
596     CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[3]
597     CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[3]
598     CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[4]
599     CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[4]
600     CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[5]
601     CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[5]
602     CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[6]
603     CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[6]
604     CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[7]
605     CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[7]
606     CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[0]
607     CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[0]
608     CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[1]
609     CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[1]
610     CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[2]
611     CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[2]
612     CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[3]
613     CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[3]
614     CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[4]
615     CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[4]
616     CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[5]
617     CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[5]
618     CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[6]
619     CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[6]
620     CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[7]
621     CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[7]
622     CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[8]
623     CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[8]
624     CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[9]
625     CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[9]
626     CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[10]
627     CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[10]
628     CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[11]
629     CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[11]
630     CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[12]
631     CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[12]
632     CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[13]
633     CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[13]
634     CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[14]
635     CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[14]
636     CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[15]
637     CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[15]
638     CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[0]
639     CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[0]
640     CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[1]
641     CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[1]
642     CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[2]
643     CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[2]
644     CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[3]
645     CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[3]
646     CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[4]
647     CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[4]
648     CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[5]
649     CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[5]
650     CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[6]
651     CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[6]
652     CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[7]
653     CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[7]
654     CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[8]
655     CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[8]
656     CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[9]
657     CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[9]
658     CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[0]
659     CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[0]
660     CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[1]
661     CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[1]
662     CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[2]
663     CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[2]
664     CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[3]
665     CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[3]
666     CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[4]
667     CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[4]
668     CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[5]
669     CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[5]
670     CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[6]
671     CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[6]
672     CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[7]
673     CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[7]
674     CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[8]
675     CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[8]
676     CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[9]
677     CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[9]
678     CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[10]
679     CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[10]
680     CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[11]
681     CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[11]
682     CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[12]
683     CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[12]
684     CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[13]
685     CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[13]
686     CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[14]
687     CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[14]
688     CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[15]
689     CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[15]
690     CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[16]
691     CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[16]
692     CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[13].output[17]
693     CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP13_OUTPUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[13].output[17]
694     CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[0]
695     CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[0]
696     CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[1]
697     CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[1]
698     CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[2]
699     CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[2]
700     CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[3]
701     CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[3]
702     CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[4]
703     CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[4]
704     CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[5]
705     CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[5]
706     CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[6]
707     CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[6]
708     CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[7]
709     CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[7]
710     CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[8]
711     CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[8]
712     CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[9]
713     CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[9]
714     CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[10]
715     CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[10]
716     CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[11]
717     CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[11]
718     CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[12]
719     CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[12]
720     CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[13]
721     CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[13]
722     CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[14]
723     CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[14]
724     CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[14].output[15]
725     CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP14_OUTPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[14].output[15]
726     CYHAL_TRIGGER_UDB_DSI_OUT_TR0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR0, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.dsi_out_tr[0]
727     CYHAL_TRIGGER_UDB_DSI_OUT_TR0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR0, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.dsi_out_tr[0]
728     CYHAL_TRIGGER_UDB_DSI_OUT_TR1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR1, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.dsi_out_tr[1]
729     CYHAL_TRIGGER_UDB_DSI_OUT_TR1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_DSI_OUT_TR1, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.dsi_out_tr[1]
730     CYHAL_TRIGGER_UDB_TR_UDB0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB0, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[0]
731     CYHAL_TRIGGER_UDB_TR_UDB0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB0, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[0]
732     CYHAL_TRIGGER_UDB_TR_UDB1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB1, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[1]
733     CYHAL_TRIGGER_UDB_TR_UDB1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB1, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[1]
734     CYHAL_TRIGGER_UDB_TR_UDB2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB2, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[2]
735     CYHAL_TRIGGER_UDB_TR_UDB2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB2, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[2]
736     CYHAL_TRIGGER_UDB_TR_UDB3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB3, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[3]
737     CYHAL_TRIGGER_UDB_TR_UDB3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB3, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[3]
738     CYHAL_TRIGGER_UDB_TR_UDB4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB4, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[4]
739     CYHAL_TRIGGER_UDB_TR_UDB4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB4, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[4]
740     CYHAL_TRIGGER_UDB_TR_UDB5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB5, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[5]
741     CYHAL_TRIGGER_UDB_TR_UDB5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB5, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[5]
742     CYHAL_TRIGGER_UDB_TR_UDB6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB6, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[6]
743     CYHAL_TRIGGER_UDB_TR_UDB6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB6, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[6]
744     CYHAL_TRIGGER_UDB_TR_UDB7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB7, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[7]
745     CYHAL_TRIGGER_UDB_TR_UDB7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB7, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[7]
746     CYHAL_TRIGGER_UDB_TR_UDB8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB8, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[8]
747     CYHAL_TRIGGER_UDB_TR_UDB8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB8, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[8]
748     CYHAL_TRIGGER_UDB_TR_UDB9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB9, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[9]
749     CYHAL_TRIGGER_UDB_TR_UDB9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB9, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[9]
750     CYHAL_TRIGGER_UDB_TR_UDB10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB10, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[10]
751     CYHAL_TRIGGER_UDB_TR_UDB10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB10, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[10]
752     CYHAL_TRIGGER_UDB_TR_UDB11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB11, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[11]
753     CYHAL_TRIGGER_UDB_TR_UDB11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB11, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[11]
754     CYHAL_TRIGGER_UDB_TR_UDB12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB12, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[12]
755     CYHAL_TRIGGER_UDB_TR_UDB12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB12, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[12]
756     CYHAL_TRIGGER_UDB_TR_UDB13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB13, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[13]
757     CYHAL_TRIGGER_UDB_TR_UDB13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB13, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[13]
758     CYHAL_TRIGGER_UDB_TR_UDB14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB14, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[14]
759     CYHAL_TRIGGER_UDB_TR_UDB14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB14, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[14]
760     CYHAL_TRIGGER_UDB_TR_UDB15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB15, CYHAL_SIGNAL_TYPE_EDGE), //!< udb.tr_udb[15]
761     CYHAL_TRIGGER_UDB_TR_UDB15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_UDB_TR_UDB15, CYHAL_SIGNAL_TYPE_LEVEL), //!< udb.tr_udb[15]
762     CYHAL_TRIGGER_USB_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ0, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[0]
763     CYHAL_TRIGGER_USB_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ1, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[1]
764     CYHAL_TRIGGER_USB_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ2, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[2]
765     CYHAL_TRIGGER_USB_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ3, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[3]
766     CYHAL_TRIGGER_USB_DMA_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ4, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[4]
767     CYHAL_TRIGGER_USB_DMA_REQ5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ5, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[5]
768     CYHAL_TRIGGER_USB_DMA_REQ6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ6, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[6]
769     CYHAL_TRIGGER_USB_DMA_REQ7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ7, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[7]
770 } cyhal_trigger_source_psoc6_01_t;
771 
772 /** Typedef from device family specific trigger source to generic trigger source */
773 typedef cyhal_trigger_source_psoc6_01_t cyhal_source_t;
774 
775 /** Deprecated defines for signals that can be either level or edge. */
776 #define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
777 #define CYHAL_TRIGGER_CSD_DSI_SENSE_OUT (CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
778 #define CYHAL_TRIGGER_CSD_TR_ADC_DONE (CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
779 #define CYHAL_TRIGGER_PASS_DSI_CTB_CMP0 (CYHAL_TRIGGER_PASS_DSI_CTB_CMP0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
780 #define CYHAL_TRIGGER_PASS_DSI_CTB_CMP1 (CYHAL_TRIGGER_PASS_DSI_CTB_CMP1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
781 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT0 (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
782 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT1 (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
783 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT2 (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
784 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT3 (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
785 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT4 (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
786 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT5 (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
787 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT6 (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
788 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT7 (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
789 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT8 (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
790 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT9 (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
791 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT10 (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
792 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT11 (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
793 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT12 (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
794 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT13 (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
795 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT14 (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
796 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT15 (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
797 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT16 (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
798 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT17 (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
799 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT18 (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
800 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT19 (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
801 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT20 (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
802 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT21 (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
803 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT22 (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
804 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT23 (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
805 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT24 (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
806 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT25 (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
807 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT26 (CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
808 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT27 (CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
809 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
810 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
811 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
812 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
813 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
814 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT5 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
815 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT6 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
816 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT7 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
817 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
818 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
819 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
820 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
821 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
822 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT5 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
823 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT6 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
824 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT7 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
825 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT8 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
826 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT9 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
827 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT10 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
828 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT11 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
829 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT12 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
830 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT13 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
831 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT14 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
832 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT15 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
833 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
834 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
835 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
836 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
837 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
838 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT5 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
839 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT6 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
840 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT7 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
841 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT8 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
842 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT9 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
843 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
844 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
845 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
846 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
847 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
848 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT5 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
849 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT6 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
850 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT7 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
851 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT8 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
852 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT9 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
853 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT10 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
854 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT11 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
855 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT12 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
856 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT13 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
857 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT14 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
858 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT15 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
859 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT16 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
860 #define CYHAL_TRIGGER_TR_GROUP13_OUTPUT17 (CYHAL_TRIGGER_TR_GROUP13_OUTPUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
861 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
862 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
863 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
864 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
865 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
866 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT5 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
867 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT6 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
868 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT7 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
869 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT8 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
870 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT9 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
871 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT10 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
872 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT11 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
873 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT12 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
874 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT13 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
875 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT14 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
876 #define CYHAL_TRIGGER_TR_GROUP14_OUTPUT15 (CYHAL_TRIGGER_TR_GROUP14_OUTPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
877 #define CYHAL_TRIGGER_UDB_DSI_OUT_TR0 (CYHAL_TRIGGER_UDB_DSI_OUT_TR0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
878 #define CYHAL_TRIGGER_UDB_DSI_OUT_TR1 (CYHAL_TRIGGER_UDB_DSI_OUT_TR1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
879 #define CYHAL_TRIGGER_UDB_TR_UDB0 (CYHAL_TRIGGER_UDB_TR_UDB0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
880 #define CYHAL_TRIGGER_UDB_TR_UDB1 (CYHAL_TRIGGER_UDB_TR_UDB1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
881 #define CYHAL_TRIGGER_UDB_TR_UDB2 (CYHAL_TRIGGER_UDB_TR_UDB2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
882 #define CYHAL_TRIGGER_UDB_TR_UDB3 (CYHAL_TRIGGER_UDB_TR_UDB3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
883 #define CYHAL_TRIGGER_UDB_TR_UDB4 (CYHAL_TRIGGER_UDB_TR_UDB4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
884 #define CYHAL_TRIGGER_UDB_TR_UDB5 (CYHAL_TRIGGER_UDB_TR_UDB5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
885 #define CYHAL_TRIGGER_UDB_TR_UDB6 (CYHAL_TRIGGER_UDB_TR_UDB6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
886 #define CYHAL_TRIGGER_UDB_TR_UDB7 (CYHAL_TRIGGER_UDB_TR_UDB7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
887 #define CYHAL_TRIGGER_UDB_TR_UDB8 (CYHAL_TRIGGER_UDB_TR_UDB8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
888 #define CYHAL_TRIGGER_UDB_TR_UDB9 (CYHAL_TRIGGER_UDB_TR_UDB9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
889 #define CYHAL_TRIGGER_UDB_TR_UDB10 (CYHAL_TRIGGER_UDB_TR_UDB10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
890 #define CYHAL_TRIGGER_UDB_TR_UDB11 (CYHAL_TRIGGER_UDB_TR_UDB11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
891 #define CYHAL_TRIGGER_UDB_TR_UDB12 (CYHAL_TRIGGER_UDB_TR_UDB12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
892 #define CYHAL_TRIGGER_UDB_TR_UDB13 (CYHAL_TRIGGER_UDB_TR_UDB13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
893 #define CYHAL_TRIGGER_UDB_TR_UDB14 (CYHAL_TRIGGER_UDB_TR_UDB14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
894 #define CYHAL_TRIGGER_UDB_TR_UDB15 (CYHAL_TRIGGER_UDB_TR_UDB15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
895 
896 /** @brief Name of each output trigger. */
897 typedef enum
898 {
899     CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[0]
900     CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[1]
901     CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 2, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[0]
902     CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 3, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[1]
903     CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 4, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[2]
904     CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 5, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[3]
905     CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 6, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[4]
906     CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 7, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[5]
907     CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 8, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[6]
908     CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 9, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[7]
909     CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 10, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[8]
910     CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 11, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[9]
911     CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 12, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[10]
912     CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 13, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[11]
913     CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 14, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[12]
914     CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 15, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[13]
915     CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 16, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[14]
916     CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 17, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[15]
917     CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 18, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[0]
918     CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 19, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[1]
919     CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 20, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[2]
920     CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 21, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[3]
921     CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 22, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[4]
922     CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 23, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[5]
923     CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 24, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[6]
924     CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 25, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[7]
925     CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 26, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[8]
926     CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 27, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[9]
927     CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 28, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[10]
928     CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 29, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[11]
929     CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 30, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[12]
930     CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 31, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[13]
931     CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 32, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[14]
932     CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 33, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[15]
933     CYHAL_TRIGGER_PASS_TR_SAR_IN = 34, //!< PASS trigger multiplexer - pass.tr_sar_in
934     CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 35, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[0]
935     CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 36, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[1]
936     CYHAL_TRIGGER_PROFILE_TR_START = 37, //!< PROFILE trigger multiplexer - profile.tr_start
937     CYHAL_TRIGGER_PROFILE_TR_STOP = 38, //!< PROFILE trigger multiplexer - profile.tr_stop
938     CYHAL_TRIGGER_TCPWM0_TR_IN0 = 39, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[0]
939     CYHAL_TRIGGER_TCPWM0_TR_IN1 = 40, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[1]
940     CYHAL_TRIGGER_TCPWM0_TR_IN2 = 41, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[2]
941     CYHAL_TRIGGER_TCPWM0_TR_IN3 = 42, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[3]
942     CYHAL_TRIGGER_TCPWM0_TR_IN4 = 43, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[4]
943     CYHAL_TRIGGER_TCPWM0_TR_IN5 = 44, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[5]
944     CYHAL_TRIGGER_TCPWM0_TR_IN6 = 45, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[6]
945     CYHAL_TRIGGER_TCPWM0_TR_IN7 = 46, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[7]
946     CYHAL_TRIGGER_TCPWM0_TR_IN8 = 47, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[8]
947     CYHAL_TRIGGER_TCPWM0_TR_IN9 = 48, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[9]
948     CYHAL_TRIGGER_TCPWM0_TR_IN10 = 49, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[10]
949     CYHAL_TRIGGER_TCPWM0_TR_IN11 = 50, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[11]
950     CYHAL_TRIGGER_TCPWM0_TR_IN12 = 51, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[12]
951     CYHAL_TRIGGER_TCPWM0_TR_IN13 = 52, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[13]
952     CYHAL_TRIGGER_TCPWM1_TR_IN0 = 53, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[0]
953     CYHAL_TRIGGER_TCPWM1_TR_IN1 = 54, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[1]
954     CYHAL_TRIGGER_TCPWM1_TR_IN2 = 55, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[2]
955     CYHAL_TRIGGER_TCPWM1_TR_IN3 = 56, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[3]
956     CYHAL_TRIGGER_TCPWM1_TR_IN4 = 57, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[4]
957     CYHAL_TRIGGER_TCPWM1_TR_IN5 = 58, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[5]
958     CYHAL_TRIGGER_TCPWM1_TR_IN6 = 59, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[6]
959     CYHAL_TRIGGER_TCPWM1_TR_IN7 = 60, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[7]
960     CYHAL_TRIGGER_TCPWM1_TR_IN8 = 61, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[8]
961     CYHAL_TRIGGER_TCPWM1_TR_IN9 = 62, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[9]
962     CYHAL_TRIGGER_TCPWM1_TR_IN10 = 63, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[10]
963     CYHAL_TRIGGER_TCPWM1_TR_IN11 = 64, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[11]
964     CYHAL_TRIGGER_TCPWM1_TR_IN12 = 65, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[12]
965     CYHAL_TRIGGER_TCPWM1_TR_IN13 = 66, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[13]
966     CYHAL_TRIGGER_TR_GROUP0_INPUT1 = 67, //!< Datawire output trigger reduction mux - tr_group[0].input[1]
967     CYHAL_TRIGGER_TR_GROUP0_INPUT2 = 68, //!< Datawire output trigger reduction mux - tr_group[0].input[2]
968     CYHAL_TRIGGER_TR_GROUP0_INPUT3 = 69, //!< Datawire output trigger reduction mux - tr_group[0].input[3]
969     CYHAL_TRIGGER_TR_GROUP0_INPUT4 = 70, //!< Datawire output trigger reduction mux - tr_group[0].input[4]
970     CYHAL_TRIGGER_TR_GROUP0_INPUT5 = 71, //!< Datawire output trigger reduction mux - tr_group[0].input[5]
971     CYHAL_TRIGGER_TR_GROUP0_INPUT6 = 72, //!< Datawire output trigger reduction mux - tr_group[0].input[6]
972     CYHAL_TRIGGER_TR_GROUP0_INPUT7 = 73, //!< Datawire output trigger reduction mux - tr_group[0].input[7]
973     CYHAL_TRIGGER_TR_GROUP0_INPUT8 = 74, //!< Datawire output trigger reduction mux - tr_group[0].input[8]
974     CYHAL_TRIGGER_TR_GROUP0_INPUT9 = 75, //!< TCPWM trigger output reduction mux - tr_group[0].input[9]
975     CYHAL_TRIGGER_TR_GROUP0_INPUT10 = 76, //!< TCPWM trigger output reduction mux - tr_group[0].input[10]
976     CYHAL_TRIGGER_TR_GROUP0_INPUT11 = 77, //!< TCPWM trigger output reduction mux - tr_group[0].input[11]
977     CYHAL_TRIGGER_TR_GROUP0_INPUT12 = 78, //!< TCPWM trigger output reduction mux - tr_group[0].input[12]
978     CYHAL_TRIGGER_TR_GROUP0_INPUT13 = 79, //!< TCPWM trigger output reduction mux - tr_group[0].input[13]
979     CYHAL_TRIGGER_TR_GROUP0_INPUT14 = 80, //!< TCPWM trigger output reduction mux - tr_group[0].input[14]
980     CYHAL_TRIGGER_TR_GROUP0_INPUT15 = 81, //!< TCPWM trigger output reduction mux - tr_group[0].input[15]
981     CYHAL_TRIGGER_TR_GROUP0_INPUT16 = 82, //!< TCPWM trigger output reduction mux - tr_group[0].input[16]
982     CYHAL_TRIGGER_TR_GROUP0_INPUT17 = 83, //!< TCPWM trigger output reduction mux - tr_group[0].input[17]
983     CYHAL_TRIGGER_TR_GROUP0_INPUT18 = 84, //!< TCPWM trigger output reduction mux - tr_group[0].input[18]
984     CYHAL_TRIGGER_TR_GROUP0_INPUT19 = 85, //!< TCPWM trigger output reduction mux - tr_group[0].input[19]
985     CYHAL_TRIGGER_TR_GROUP0_INPUT20 = 86, //!< TCPWM trigger output reduction mux - tr_group[0].input[20]
986     CYHAL_TRIGGER_TR_GROUP0_INPUT21 = 87, //!< TCPWM trigger output reduction mux - tr_group[0].input[21]
987     CYHAL_TRIGGER_TR_GROUP0_INPUT22 = 88, //!< TCPWM trigger output reduction mux - tr_group[0].input[22]
988     CYHAL_TRIGGER_TR_GROUP0_INPUT23 = 89, //!< TCPWM trigger output reduction mux - tr_group[0].input[23]
989     CYHAL_TRIGGER_TR_GROUP0_INPUT24 = 90, //!< TCPWM trigger output reduction mux - tr_group[0].input[24]
990     CYHAL_TRIGGER_TR_GROUP0_INPUT25 = 91, //!< HSIOM Pin input reduction mux - tr_group[0].input[25]
991     CYHAL_TRIGGER_TR_GROUP0_INPUT26 = 92, //!< HSIOM Pin input reduction mux - tr_group[0].input[26]
992     CYHAL_TRIGGER_TR_GROUP0_INPUT27 = 93, //!< DMA request reduction mux - tr_group[0].input[27]
993     CYHAL_TRIGGER_TR_GROUP0_INPUT28 = 94, //!< DMA request reduction mux - tr_group[0].input[28]
994     CYHAL_TRIGGER_TR_GROUP0_INPUT29 = 95, //!< DMA request reduction mux - tr_group[0].input[29]
995     CYHAL_TRIGGER_TR_GROUP0_INPUT30 = 96, //!< DMA request reduction mux - tr_group[0].input[30]
996     CYHAL_TRIGGER_TR_GROUP0_INPUT31 = 97, //!< DMA request reduction mux - tr_group[0].input[31]
997     CYHAL_TRIGGER_TR_GROUP0_INPUT32 = 98, //!< DMA request reduction mux - tr_group[0].input[32]
998     CYHAL_TRIGGER_TR_GROUP0_INPUT33 = 99, //!< DMA request reduction mux - tr_group[0].input[33]
999     CYHAL_TRIGGER_TR_GROUP0_INPUT34 = 100, //!< DMA request reduction mux - tr_group[0].input[34]
1000     CYHAL_TRIGGER_TR_GROUP0_INPUT35 = 101, //!< DMA request reduction mux - tr_group[0].input[35]
1001     CYHAL_TRIGGER_TR_GROUP0_INPUT36 = 102, //!< DMA request reduction mux - tr_group[0].input[36]
1002     CYHAL_TRIGGER_TR_GROUP0_INPUT37 = 103, //!< DMA request reduction mux - tr_group[0].input[37]
1003     CYHAL_TRIGGER_TR_GROUP0_INPUT38 = 104, //!< DMA request reduction mux - tr_group[0].input[38]
1004     CYHAL_TRIGGER_TR_GROUP0_INPUT39 = 105, //!< DMA request reduction mux - tr_group[0].input[39]
1005     CYHAL_TRIGGER_TR_GROUP0_INPUT40 = 106, //!< DMA request reduction mux - tr_group[0].input[40]
1006     CYHAL_TRIGGER_TR_GROUP0_INPUT41 = 107, //!< DMA request reduction mux - tr_group[0].input[41]
1007     CYHAL_TRIGGER_TR_GROUP0_INPUT42 = 108, //!< DMA request reduction mux - tr_group[0].input[42]
1008     CYHAL_TRIGGER_TR_GROUP0_INPUT43 = 109, //!< Trigger input reduction mux - tr_group[0].input[43]
1009     CYHAL_TRIGGER_TR_GROUP0_INPUT44 = 110, //!< Trigger input reduction mux - tr_group[0].input[44]
1010     CYHAL_TRIGGER_TR_GROUP0_INPUT45 = 111, //!< Trigger input reduction mux - tr_group[0].input[45]
1011     CYHAL_TRIGGER_TR_GROUP0_INPUT46 = 112, //!< Trigger input reduction mux - tr_group[0].input[46]
1012     CYHAL_TRIGGER_TR_GROUP0_INPUT47 = 113, //!< Trigger input reduction mux - tr_group[0].input[47]
1013     CYHAL_TRIGGER_TR_GROUP0_INPUT48 = 114, //!< Trigger input reduction mux - tr_group[0].input[48]
1014     CYHAL_TRIGGER_TR_GROUP0_INPUT49 = 115, //!< Trigger input reduction mux - tr_group[0].input[49]
1015     CYHAL_TRIGGER_TR_GROUP0_INPUT50 = 116, //!< Trigger input reduction mux - tr_group[0].input[50]
1016     CYHAL_TRIGGER_TR_GROUP1_INPUT1 = 117, //!< Datawire output trigger reduction mux - tr_group[1].input[1]
1017     CYHAL_TRIGGER_TR_GROUP1_INPUT2 = 118, //!< Datawire output trigger reduction mux - tr_group[1].input[2]
1018     CYHAL_TRIGGER_TR_GROUP1_INPUT3 = 119, //!< Datawire output trigger reduction mux - tr_group[1].input[3]
1019     CYHAL_TRIGGER_TR_GROUP1_INPUT4 = 120, //!< Datawire output trigger reduction mux - tr_group[1].input[4]
1020     CYHAL_TRIGGER_TR_GROUP1_INPUT5 = 121, //!< Datawire output trigger reduction mux - tr_group[1].input[5]
1021     CYHAL_TRIGGER_TR_GROUP1_INPUT6 = 122, //!< Datawire output trigger reduction mux - tr_group[1].input[6]
1022     CYHAL_TRIGGER_TR_GROUP1_INPUT7 = 123, //!< Datawire output trigger reduction mux - tr_group[1].input[7]
1023     CYHAL_TRIGGER_TR_GROUP1_INPUT8 = 124, //!< Datawire output trigger reduction mux - tr_group[1].input[8]
1024     CYHAL_TRIGGER_TR_GROUP1_INPUT9 = 125, //!< TCPWM trigger output reduction mux - tr_group[1].input[9]
1025     CYHAL_TRIGGER_TR_GROUP1_INPUT10 = 126, //!< TCPWM trigger output reduction mux - tr_group[1].input[10]
1026     CYHAL_TRIGGER_TR_GROUP1_INPUT11 = 127, //!< TCPWM trigger output reduction mux - tr_group[1].input[11]
1027     CYHAL_TRIGGER_TR_GROUP1_INPUT12 = 128, //!< TCPWM trigger output reduction mux - tr_group[1].input[12]
1028     CYHAL_TRIGGER_TR_GROUP1_INPUT13 = 129, //!< TCPWM trigger output reduction mux - tr_group[1].input[13]
1029     CYHAL_TRIGGER_TR_GROUP1_INPUT14 = 130, //!< TCPWM trigger output reduction mux - tr_group[1].input[14]
1030     CYHAL_TRIGGER_TR_GROUP1_INPUT15 = 131, //!< TCPWM trigger output reduction mux - tr_group[1].input[15]
1031     CYHAL_TRIGGER_TR_GROUP1_INPUT16 = 132, //!< TCPWM trigger output reduction mux - tr_group[1].input[16]
1032     CYHAL_TRIGGER_TR_GROUP1_INPUT17 = 133, //!< TCPWM trigger output reduction mux - tr_group[1].input[17]
1033     CYHAL_TRIGGER_TR_GROUP1_INPUT18 = 134, //!< TCPWM trigger output reduction mux - tr_group[1].input[18]
1034     CYHAL_TRIGGER_TR_GROUP1_INPUT19 = 135, //!< TCPWM trigger output reduction mux - tr_group[1].input[19]
1035     CYHAL_TRIGGER_TR_GROUP1_INPUT20 = 136, //!< TCPWM trigger output reduction mux - tr_group[1].input[20]
1036     CYHAL_TRIGGER_TR_GROUP1_INPUT21 = 137, //!< TCPWM trigger output reduction mux - tr_group[1].input[21]
1037     CYHAL_TRIGGER_TR_GROUP1_INPUT22 = 138, //!< TCPWM trigger output reduction mux - tr_group[1].input[22]
1038     CYHAL_TRIGGER_TR_GROUP1_INPUT23 = 139, //!< TCPWM trigger output reduction mux - tr_group[1].input[23]
1039     CYHAL_TRIGGER_TR_GROUP1_INPUT24 = 140, //!< TCPWM trigger output reduction mux - tr_group[1].input[24]
1040     CYHAL_TRIGGER_TR_GROUP1_INPUT25 = 141, //!< HSIOM Pin input reduction mux - tr_group[1].input[25]
1041     CYHAL_TRIGGER_TR_GROUP1_INPUT26 = 142, //!< HSIOM Pin input reduction mux - tr_group[1].input[26]
1042     CYHAL_TRIGGER_TR_GROUP1_INPUT27 = 143, //!< DMA request reduction mux - tr_group[1].input[27]
1043     CYHAL_TRIGGER_TR_GROUP1_INPUT28 = 144, //!< DMA request reduction mux - tr_group[1].input[28]
1044     CYHAL_TRIGGER_TR_GROUP1_INPUT29 = 145, //!< DMA request reduction mux - tr_group[1].input[29]
1045     CYHAL_TRIGGER_TR_GROUP1_INPUT30 = 146, //!< DMA request reduction mux - tr_group[1].input[30]
1046     CYHAL_TRIGGER_TR_GROUP1_INPUT31 = 147, //!< DMA request reduction mux - tr_group[1].input[31]
1047     CYHAL_TRIGGER_TR_GROUP1_INPUT32 = 148, //!< DMA request reduction mux - tr_group[1].input[32]
1048     CYHAL_TRIGGER_TR_GROUP1_INPUT33 = 149, //!< DMA request reduction mux - tr_group[1].input[33]
1049     CYHAL_TRIGGER_TR_GROUP1_INPUT34 = 150, //!< DMA request reduction mux - tr_group[1].input[34]
1050     CYHAL_TRIGGER_TR_GROUP1_INPUT35 = 151, //!< DMA request reduction mux - tr_group[1].input[35]
1051     CYHAL_TRIGGER_TR_GROUP1_INPUT36 = 152, //!< DMA request reduction mux - tr_group[1].input[36]
1052     CYHAL_TRIGGER_TR_GROUP1_INPUT37 = 153, //!< DMA request reduction mux - tr_group[1].input[37]
1053     CYHAL_TRIGGER_TR_GROUP1_INPUT38 = 154, //!< DMA request reduction mux - tr_group[1].input[38]
1054     CYHAL_TRIGGER_TR_GROUP1_INPUT39 = 155, //!< DMA request reduction mux - tr_group[1].input[39]
1055     CYHAL_TRIGGER_TR_GROUP1_INPUT40 = 156, //!< DMA request reduction mux - tr_group[1].input[40]
1056     CYHAL_TRIGGER_TR_GROUP1_INPUT41 = 157, //!< DMA request reduction mux - tr_group[1].input[41]
1057     CYHAL_TRIGGER_TR_GROUP1_INPUT42 = 158, //!< DMA request reduction mux - tr_group[1].input[42]
1058     CYHAL_TRIGGER_TR_GROUP1_INPUT43 = 159, //!< Trigger input reduction mux - tr_group[1].input[43]
1059     CYHAL_TRIGGER_TR_GROUP1_INPUT44 = 160, //!< Trigger input reduction mux - tr_group[1].input[44]
1060     CYHAL_TRIGGER_TR_GROUP1_INPUT45 = 161, //!< Trigger input reduction mux - tr_group[1].input[45]
1061     CYHAL_TRIGGER_TR_GROUP1_INPUT46 = 162, //!< Trigger input reduction mux - tr_group[1].input[46]
1062     CYHAL_TRIGGER_TR_GROUP1_INPUT47 = 163, //!< Trigger input reduction mux - tr_group[1].input[47]
1063     CYHAL_TRIGGER_TR_GROUP1_INPUT48 = 164, //!< Trigger input reduction mux - tr_group[1].input[48]
1064     CYHAL_TRIGGER_TR_GROUP1_INPUT49 = 165, //!< Trigger input reduction mux - tr_group[1].input[49]
1065     CYHAL_TRIGGER_TR_GROUP1_INPUT50 = 166, //!< Trigger input reduction mux - tr_group[1].input[50]
1066     CYHAL_TRIGGER_TR_GROUP2_INPUT1 = 167, //!< Datawire output trigger reduction mux - tr_group[2].input[1]
1067     CYHAL_TRIGGER_TR_GROUP2_INPUT2 = 168, //!< Datawire output trigger reduction mux - tr_group[2].input[2]
1068     CYHAL_TRIGGER_TR_GROUP2_INPUT3 = 169, //!< Datawire output trigger reduction mux - tr_group[2].input[3]
1069     CYHAL_TRIGGER_TR_GROUP2_INPUT4 = 170, //!< Datawire output trigger reduction mux - tr_group[2].input[4]
1070     CYHAL_TRIGGER_TR_GROUP2_INPUT5 = 171, //!< Datawire output trigger reduction mux - tr_group[2].input[5]
1071     CYHAL_TRIGGER_TR_GROUP2_INPUT6 = 172, //!< Datawire output trigger reduction mux - tr_group[2].input[6]
1072     CYHAL_TRIGGER_TR_GROUP2_INPUT7 = 173, //!< Datawire output trigger reduction mux - tr_group[2].input[7]
1073     CYHAL_TRIGGER_TR_GROUP2_INPUT8 = 174, //!< Datawire output trigger reduction mux - tr_group[2].input[8]
1074     CYHAL_TRIGGER_TR_GROUP2_INPUT9 = 175, //!< TCPWM trigger output reduction mux - tr_group[2].input[9]
1075     CYHAL_TRIGGER_TR_GROUP2_INPUT10 = 176, //!< TCPWM trigger output reduction mux - tr_group[2].input[10]
1076     CYHAL_TRIGGER_TR_GROUP2_INPUT11 = 177, //!< TCPWM trigger output reduction mux - tr_group[2].input[11]
1077     CYHAL_TRIGGER_TR_GROUP2_INPUT12 = 178, //!< TCPWM trigger output reduction mux - tr_group[2].input[12]
1078     CYHAL_TRIGGER_TR_GROUP2_INPUT13 = 179, //!< TCPWM trigger output reduction mux - tr_group[2].input[13]
1079     CYHAL_TRIGGER_TR_GROUP2_INPUT14 = 180, //!< TCPWM trigger output reduction mux - tr_group[2].input[14]
1080     CYHAL_TRIGGER_TR_GROUP2_INPUT15 = 181, //!< TCPWM trigger output reduction mux - tr_group[2].input[15]
1081     CYHAL_TRIGGER_TR_GROUP2_INPUT16 = 182, //!< TCPWM trigger output reduction mux - tr_group[2].input[16]
1082     CYHAL_TRIGGER_TR_GROUP2_INPUT17 = 183, //!< TCPWM trigger output reduction mux - tr_group[2].input[17]
1083     CYHAL_TRIGGER_TR_GROUP2_INPUT18 = 184, //!< TCPWM trigger output reduction mux - tr_group[2].input[18]
1084     CYHAL_TRIGGER_TR_GROUP2_INPUT19 = 185, //!< TCPWM trigger output reduction mux - tr_group[2].input[19]
1085     CYHAL_TRIGGER_TR_GROUP2_INPUT20 = 186, //!< TCPWM trigger output reduction mux - tr_group[2].input[20]
1086     CYHAL_TRIGGER_TR_GROUP2_INPUT21 = 187, //!< TCPWM trigger output reduction mux - tr_group[2].input[21]
1087     CYHAL_TRIGGER_TR_GROUP2_INPUT22 = 188, //!< TCPWM trigger output reduction mux - tr_group[2].input[22]
1088     CYHAL_TRIGGER_TR_GROUP2_INPUT23 = 189, //!< TCPWM trigger output reduction mux - tr_group[2].input[23]
1089     CYHAL_TRIGGER_TR_GROUP2_INPUT24 = 190, //!< TCPWM trigger output reduction mux - tr_group[2].input[24]
1090     CYHAL_TRIGGER_TR_GROUP2_INPUT25 = 191, //!< HSIOM Pin input reduction mux - tr_group[2].input[25]
1091     CYHAL_TRIGGER_TR_GROUP2_INPUT26 = 192, //!< HSIOM Pin input reduction mux - tr_group[2].input[26]
1092     CYHAL_TRIGGER_TR_GROUP2_INPUT27 = 193, //!< HSIOM Pin input reduction mux - tr_group[2].input[27]
1093     CYHAL_TRIGGER_TR_GROUP2_INPUT28 = 194, //!< HSIOM Pin input reduction mux - tr_group[2].input[28]
1094     CYHAL_TRIGGER_TR_GROUP2_INPUT29 = 195, //!< HSIOM Pin input reduction mux - tr_group[2].input[29]
1095     CYHAL_TRIGGER_TR_GROUP2_INPUT30 = 196, //!< HSIOM Pin input reduction mux - tr_group[2].input[30]
1096     CYHAL_TRIGGER_TR_GROUP2_INPUT31 = 197, //!< HSIOM Pin input reduction mux - tr_group[2].input[31]
1097     CYHAL_TRIGGER_TR_GROUP2_INPUT32 = 198, //!< HSIOM Pin input reduction mux - tr_group[2].input[32]
1098     CYHAL_TRIGGER_TR_GROUP2_INPUT33 = 199, //!< DMA request reduction mux - tr_group[2].input[33]
1099     CYHAL_TRIGGER_TR_GROUP2_INPUT34 = 200, //!< DMA request reduction mux - tr_group[2].input[34]
1100     CYHAL_TRIGGER_TR_GROUP2_INPUT35 = 201, //!< Trigger input reduction mux - tr_group[2].input[35]
1101     CYHAL_TRIGGER_TR_GROUP2_INPUT36 = 202, //!< Trigger input reduction mux - tr_group[2].input[36]
1102     CYHAL_TRIGGER_TR_GROUP2_INPUT37 = 203, //!< Trigger input reduction mux - tr_group[2].input[37]
1103     CYHAL_TRIGGER_TR_GROUP2_INPUT38 = 204, //!< Trigger input reduction mux - tr_group[2].input[38]
1104     CYHAL_TRIGGER_TR_GROUP2_INPUT39 = 205, //!< Trigger input reduction mux - tr_group[2].input[39]
1105     CYHAL_TRIGGER_TR_GROUP2_INPUT40 = 206, //!< Trigger input reduction mux - tr_group[2].input[40]
1106     CYHAL_TRIGGER_TR_GROUP2_INPUT41 = 207, //!< Trigger input reduction mux - tr_group[2].input[41]
1107     CYHAL_TRIGGER_TR_GROUP2_INPUT42 = 208, //!< Trigger input reduction mux - tr_group[2].input[42]
1108     CYHAL_TRIGGER_TR_GROUP3_INPUT1 = 209, //!< Datawire output trigger reduction mux - tr_group[3].input[1]
1109     CYHAL_TRIGGER_TR_GROUP3_INPUT2 = 210, //!< Datawire output trigger reduction mux - tr_group[3].input[2]
1110     CYHAL_TRIGGER_TR_GROUP3_INPUT3 = 211, //!< Datawire output trigger reduction mux - tr_group[3].input[3]
1111     CYHAL_TRIGGER_TR_GROUP3_INPUT4 = 212, //!< Datawire output trigger reduction mux - tr_group[3].input[4]
1112     CYHAL_TRIGGER_TR_GROUP3_INPUT5 = 213, //!< Datawire output trigger reduction mux - tr_group[3].input[5]
1113     CYHAL_TRIGGER_TR_GROUP3_INPUT6 = 214, //!< Datawire output trigger reduction mux - tr_group[3].input[6]
1114     CYHAL_TRIGGER_TR_GROUP3_INPUT7 = 215, //!< Datawire output trigger reduction mux - tr_group[3].input[7]
1115     CYHAL_TRIGGER_TR_GROUP3_INPUT8 = 216, //!< Datawire output trigger reduction mux - tr_group[3].input[8]
1116     CYHAL_TRIGGER_TR_GROUP3_INPUT9 = 217, //!< TCPWM trigger output reduction mux - tr_group[3].input[9]
1117     CYHAL_TRIGGER_TR_GROUP3_INPUT10 = 218, //!< TCPWM trigger output reduction mux - tr_group[3].input[10]
1118     CYHAL_TRIGGER_TR_GROUP3_INPUT11 = 219, //!< TCPWM trigger output reduction mux - tr_group[3].input[11]
1119     CYHAL_TRIGGER_TR_GROUP3_INPUT12 = 220, //!< TCPWM trigger output reduction mux - tr_group[3].input[12]
1120     CYHAL_TRIGGER_TR_GROUP3_INPUT13 = 221, //!< TCPWM trigger output reduction mux - tr_group[3].input[13]
1121     CYHAL_TRIGGER_TR_GROUP3_INPUT14 = 222, //!< TCPWM trigger output reduction mux - tr_group[3].input[14]
1122     CYHAL_TRIGGER_TR_GROUP3_INPUT15 = 223, //!< TCPWM trigger output reduction mux - tr_group[3].input[15]
1123     CYHAL_TRIGGER_TR_GROUP3_INPUT16 = 224, //!< TCPWM trigger output reduction mux - tr_group[3].input[16]
1124     CYHAL_TRIGGER_TR_GROUP3_INPUT17 = 225, //!< TCPWM trigger output reduction mux - tr_group[3].input[17]
1125     CYHAL_TRIGGER_TR_GROUP3_INPUT18 = 226, //!< TCPWM trigger output reduction mux - tr_group[3].input[18]
1126     CYHAL_TRIGGER_TR_GROUP3_INPUT19 = 227, //!< TCPWM trigger output reduction mux - tr_group[3].input[19]
1127     CYHAL_TRIGGER_TR_GROUP3_INPUT20 = 228, //!< TCPWM trigger output reduction mux - tr_group[3].input[20]
1128     CYHAL_TRIGGER_TR_GROUP3_INPUT21 = 229, //!< TCPWM trigger output reduction mux - tr_group[3].input[21]
1129     CYHAL_TRIGGER_TR_GROUP3_INPUT22 = 230, //!< TCPWM trigger output reduction mux - tr_group[3].input[22]
1130     CYHAL_TRIGGER_TR_GROUP3_INPUT23 = 231, //!< TCPWM trigger output reduction mux - tr_group[3].input[23]
1131     CYHAL_TRIGGER_TR_GROUP3_INPUT24 = 232, //!< TCPWM trigger output reduction mux - tr_group[3].input[24]
1132     CYHAL_TRIGGER_TR_GROUP3_INPUT25 = 233, //!< HSIOM Pin input reduction mux - tr_group[3].input[25]
1133     CYHAL_TRIGGER_TR_GROUP3_INPUT26 = 234, //!< HSIOM Pin input reduction mux - tr_group[3].input[26]
1134     CYHAL_TRIGGER_TR_GROUP3_INPUT27 = 235, //!< HSIOM Pin input reduction mux - tr_group[3].input[27]
1135     CYHAL_TRIGGER_TR_GROUP3_INPUT28 = 236, //!< HSIOM Pin input reduction mux - tr_group[3].input[28]
1136     CYHAL_TRIGGER_TR_GROUP3_INPUT29 = 237, //!< HSIOM Pin input reduction mux - tr_group[3].input[29]
1137     CYHAL_TRIGGER_TR_GROUP3_INPUT30 = 238, //!< HSIOM Pin input reduction mux - tr_group[3].input[30]
1138     CYHAL_TRIGGER_TR_GROUP3_INPUT31 = 239, //!< HSIOM Pin input reduction mux - tr_group[3].input[31]
1139     CYHAL_TRIGGER_TR_GROUP3_INPUT32 = 240, //!< HSIOM Pin input reduction mux - tr_group[3].input[32]
1140     CYHAL_TRIGGER_TR_GROUP3_INPUT33 = 241, //!< DMA request reduction mux - tr_group[3].input[33]
1141     CYHAL_TRIGGER_TR_GROUP3_INPUT34 = 242, //!< DMA request reduction mux - tr_group[3].input[34]
1142     CYHAL_TRIGGER_TR_GROUP3_INPUT35 = 243, //!< Trigger input reduction mux - tr_group[3].input[35]
1143     CYHAL_TRIGGER_TR_GROUP3_INPUT36 = 244, //!< Trigger input reduction mux - tr_group[3].input[36]
1144     CYHAL_TRIGGER_TR_GROUP3_INPUT37 = 245, //!< Trigger input reduction mux - tr_group[3].input[37]
1145     CYHAL_TRIGGER_TR_GROUP3_INPUT38 = 246, //!< Trigger input reduction mux - tr_group[3].input[38]
1146     CYHAL_TRIGGER_TR_GROUP3_INPUT39 = 247, //!< Trigger input reduction mux - tr_group[3].input[39]
1147     CYHAL_TRIGGER_TR_GROUP3_INPUT40 = 248, //!< Trigger input reduction mux - tr_group[3].input[40]
1148     CYHAL_TRIGGER_TR_GROUP3_INPUT41 = 249, //!< Trigger input reduction mux - tr_group[3].input[41]
1149     CYHAL_TRIGGER_TR_GROUP3_INPUT42 = 250, //!< Trigger input reduction mux - tr_group[3].input[42]
1150     CYHAL_TRIGGER_TR_GROUP4_INPUT1 = 251, //!< Datawire output trigger reduction mux - tr_group[4].input[1]
1151     CYHAL_TRIGGER_TR_GROUP4_INPUT2 = 252, //!< Datawire output trigger reduction mux - tr_group[4].input[2]
1152     CYHAL_TRIGGER_TR_GROUP4_INPUT3 = 253, //!< Datawire output trigger reduction mux - tr_group[4].input[3]
1153     CYHAL_TRIGGER_TR_GROUP4_INPUT4 = 254, //!< Datawire output trigger reduction mux - tr_group[4].input[4]
1154     CYHAL_TRIGGER_TR_GROUP4_INPUT5 = 255, //!< Datawire output trigger reduction mux - tr_group[4].input[5]
1155     CYHAL_TRIGGER_TR_GROUP4_INPUT6 = 256, //!< Datawire output trigger reduction mux - tr_group[4].input[6]
1156     CYHAL_TRIGGER_TR_GROUP4_INPUT7 = 257, //!< Datawire output trigger reduction mux - tr_group[4].input[7]
1157     CYHAL_TRIGGER_TR_GROUP4_INPUT8 = 258, //!< Datawire output trigger reduction mux - tr_group[4].input[8]
1158     CYHAL_TRIGGER_TR_GROUP4_INPUT9 = 259, //!< TCPWM trigger output reduction mux - tr_group[4].input[9]
1159     CYHAL_TRIGGER_TR_GROUP4_INPUT10 = 260, //!< TCPWM trigger output reduction mux - tr_group[4].input[10]
1160     CYHAL_TRIGGER_TR_GROUP4_INPUT11 = 261, //!< TCPWM trigger output reduction mux - tr_group[4].input[11]
1161     CYHAL_TRIGGER_TR_GROUP4_INPUT12 = 262, //!< TCPWM trigger output reduction mux - tr_group[4].input[12]
1162     CYHAL_TRIGGER_TR_GROUP4_INPUT13 = 263, //!< TCPWM trigger output reduction mux - tr_group[4].input[13]
1163     CYHAL_TRIGGER_TR_GROUP4_INPUT14 = 264, //!< TCPWM trigger output reduction mux - tr_group[4].input[14]
1164     CYHAL_TRIGGER_TR_GROUP4_INPUT15 = 265, //!< TCPWM trigger output reduction mux - tr_group[4].input[15]
1165     CYHAL_TRIGGER_TR_GROUP4_INPUT16 = 266, //!< TCPWM trigger output reduction mux - tr_group[4].input[16]
1166     CYHAL_TRIGGER_TR_GROUP4_INPUT17 = 267, //!< TCPWM trigger output reduction mux - tr_group[4].input[17]
1167     CYHAL_TRIGGER_TR_GROUP4_INPUT18 = 268, //!< TCPWM trigger output reduction mux - tr_group[4].input[18]
1168     CYHAL_TRIGGER_TR_GROUP4_INPUT19 = 269, //!< TCPWM trigger output reduction mux - tr_group[4].input[19]
1169     CYHAL_TRIGGER_TR_GROUP4_INPUT20 = 270, //!< TCPWM trigger output reduction mux - tr_group[4].input[20]
1170     CYHAL_TRIGGER_TR_GROUP4_INPUT21 = 271, //!< TCPWM trigger output reduction mux - tr_group[4].input[21]
1171     CYHAL_TRIGGER_TR_GROUP4_INPUT22 = 272, //!< TCPWM trigger output reduction mux - tr_group[4].input[22]
1172     CYHAL_TRIGGER_TR_GROUP4_INPUT23 = 273, //!< TCPWM trigger output reduction mux - tr_group[4].input[23]
1173     CYHAL_TRIGGER_TR_GROUP4_INPUT24 = 274, //!< TCPWM trigger output reduction mux - tr_group[4].input[24]
1174     CYHAL_TRIGGER_TR_GROUP4_INPUT25 = 275, //!< HSIOM Pin input reduction mux - tr_group[4].input[25]
1175     CYHAL_TRIGGER_TR_GROUP4_INPUT26 = 276, //!< HSIOM Pin input reduction mux - tr_group[4].input[26]
1176     CYHAL_TRIGGER_TR_GROUP4_INPUT27 = 277, //!< HSIOM Pin input reduction mux - tr_group[4].input[27]
1177     CYHAL_TRIGGER_TR_GROUP4_INPUT28 = 278, //!< HSIOM Pin input reduction mux - tr_group[4].input[28]
1178     CYHAL_TRIGGER_TR_GROUP4_INPUT29 = 279, //!< HSIOM Pin input reduction mux - tr_group[4].input[29]
1179     CYHAL_TRIGGER_TR_GROUP4_INPUT30 = 280, //!< HSIOM Pin input reduction mux - tr_group[4].input[30]
1180     CYHAL_TRIGGER_TR_GROUP4_INPUT31 = 281, //!< HSIOM Pin input reduction mux - tr_group[4].input[31]
1181     CYHAL_TRIGGER_TR_GROUP4_INPUT32 = 282, //!< HSIOM Pin input reduction mux - tr_group[4].input[32]
1182     CYHAL_TRIGGER_TR_GROUP4_INPUT33 = 283, //!< DMA request reduction mux - tr_group[4].input[33]
1183     CYHAL_TRIGGER_TR_GROUP4_INPUT34 = 284, //!< DMA request reduction mux - tr_group[4].input[34]
1184     CYHAL_TRIGGER_TR_GROUP4_INPUT35 = 285, //!< Trigger input reduction mux - tr_group[4].input[35]
1185     CYHAL_TRIGGER_TR_GROUP4_INPUT36 = 286, //!< Trigger input reduction mux - tr_group[4].input[36]
1186     CYHAL_TRIGGER_TR_GROUP4_INPUT37 = 287, //!< Trigger input reduction mux - tr_group[4].input[37]
1187     CYHAL_TRIGGER_TR_GROUP4_INPUT38 = 288, //!< Trigger input reduction mux - tr_group[4].input[38]
1188     CYHAL_TRIGGER_TR_GROUP4_INPUT39 = 289, //!< Trigger input reduction mux - tr_group[4].input[39]
1189     CYHAL_TRIGGER_TR_GROUP4_INPUT40 = 290, //!< Trigger input reduction mux - tr_group[4].input[40]
1190     CYHAL_TRIGGER_TR_GROUP4_INPUT41 = 291, //!< Trigger input reduction mux - tr_group[4].input[41]
1191     CYHAL_TRIGGER_TR_GROUP4_INPUT42 = 292, //!< Trigger input reduction mux - tr_group[4].input[42]
1192     CYHAL_TRIGGER_TR_GROUP5_INPUT1 = 293, //!< Datawire output trigger reduction mux - tr_group[5].input[1]
1193     CYHAL_TRIGGER_TR_GROUP5_INPUT2 = 294, //!< Datawire output trigger reduction mux - tr_group[5].input[2]
1194     CYHAL_TRIGGER_TR_GROUP5_INPUT3 = 295, //!< Datawire output trigger reduction mux - tr_group[5].input[3]
1195     CYHAL_TRIGGER_TR_GROUP5_INPUT4 = 296, //!< Datawire output trigger reduction mux - tr_group[5].input[4]
1196     CYHAL_TRIGGER_TR_GROUP5_INPUT5 = 297, //!< Datawire output trigger reduction mux - tr_group[5].input[5]
1197     CYHAL_TRIGGER_TR_GROUP5_INPUT6 = 298, //!< Datawire output trigger reduction mux - tr_group[5].input[6]
1198     CYHAL_TRIGGER_TR_GROUP5_INPUT7 = 299, //!< Datawire output trigger reduction mux - tr_group[5].input[7]
1199     CYHAL_TRIGGER_TR_GROUP5_INPUT8 = 300, //!< Datawire output trigger reduction mux - tr_group[5].input[8]
1200     CYHAL_TRIGGER_TR_GROUP5_INPUT9 = 301, //!< TCPWM trigger output reduction mux - tr_group[5].input[9]
1201     CYHAL_TRIGGER_TR_GROUP5_INPUT10 = 302, //!< TCPWM trigger output reduction mux - tr_group[5].input[10]
1202     CYHAL_TRIGGER_TR_GROUP5_INPUT11 = 303, //!< TCPWM trigger output reduction mux - tr_group[5].input[11]
1203     CYHAL_TRIGGER_TR_GROUP5_INPUT12 = 304, //!< TCPWM trigger output reduction mux - tr_group[5].input[12]
1204     CYHAL_TRIGGER_TR_GROUP5_INPUT13 = 305, //!< TCPWM trigger output reduction mux - tr_group[5].input[13]
1205     CYHAL_TRIGGER_TR_GROUP5_INPUT14 = 306, //!< TCPWM trigger output reduction mux - tr_group[5].input[14]
1206     CYHAL_TRIGGER_TR_GROUP5_INPUT15 = 307, //!< TCPWM trigger output reduction mux - tr_group[5].input[15]
1207     CYHAL_TRIGGER_TR_GROUP5_INPUT16 = 308, //!< TCPWM trigger output reduction mux - tr_group[5].input[16]
1208     CYHAL_TRIGGER_TR_GROUP5_INPUT17 = 309, //!< TCPWM trigger output reduction mux - tr_group[5].input[17]
1209     CYHAL_TRIGGER_TR_GROUP5_INPUT18 = 310, //!< TCPWM trigger output reduction mux - tr_group[5].input[18]
1210     CYHAL_TRIGGER_TR_GROUP5_INPUT19 = 311, //!< TCPWM trigger output reduction mux - tr_group[5].input[19]
1211     CYHAL_TRIGGER_TR_GROUP5_INPUT20 = 312, //!< TCPWM trigger output reduction mux - tr_group[5].input[20]
1212     CYHAL_TRIGGER_TR_GROUP5_INPUT21 = 313, //!< TCPWM trigger output reduction mux - tr_group[5].input[21]
1213     CYHAL_TRIGGER_TR_GROUP5_INPUT22 = 314, //!< TCPWM trigger output reduction mux - tr_group[5].input[22]
1214     CYHAL_TRIGGER_TR_GROUP5_INPUT23 = 315, //!< TCPWM trigger output reduction mux - tr_group[5].input[23]
1215     CYHAL_TRIGGER_TR_GROUP5_INPUT24 = 316, //!< TCPWM trigger output reduction mux - tr_group[5].input[24]
1216     CYHAL_TRIGGER_TR_GROUP5_INPUT25 = 317, //!< HSIOM Pin input reduction mux - tr_group[5].input[25]
1217     CYHAL_TRIGGER_TR_GROUP5_INPUT26 = 318, //!< HSIOM Pin input reduction mux - tr_group[5].input[26]
1218     CYHAL_TRIGGER_TR_GROUP5_INPUT27 = 319, //!< HSIOM Pin input reduction mux - tr_group[5].input[27]
1219     CYHAL_TRIGGER_TR_GROUP5_INPUT28 = 320, //!< HSIOM Pin input reduction mux - tr_group[5].input[28]
1220     CYHAL_TRIGGER_TR_GROUP5_INPUT29 = 321, //!< HSIOM Pin input reduction mux - tr_group[5].input[29]
1221     CYHAL_TRIGGER_TR_GROUP5_INPUT30 = 322, //!< HSIOM Pin input reduction mux - tr_group[5].input[30]
1222     CYHAL_TRIGGER_TR_GROUP5_INPUT31 = 323, //!< HSIOM Pin input reduction mux - tr_group[5].input[31]
1223     CYHAL_TRIGGER_TR_GROUP5_INPUT32 = 324, //!< HSIOM Pin input reduction mux - tr_group[5].input[32]
1224     CYHAL_TRIGGER_TR_GROUP5_INPUT33 = 325, //!< DMA request reduction mux - tr_group[5].input[33]
1225     CYHAL_TRIGGER_TR_GROUP5_INPUT34 = 326, //!< DMA request reduction mux - tr_group[5].input[34]
1226     CYHAL_TRIGGER_TR_GROUP5_INPUT35 = 327, //!< Trigger input reduction mux - tr_group[5].input[35]
1227     CYHAL_TRIGGER_TR_GROUP5_INPUT36 = 328, //!< Trigger input reduction mux - tr_group[5].input[36]
1228     CYHAL_TRIGGER_TR_GROUP5_INPUT37 = 329, //!< Trigger input reduction mux - tr_group[5].input[37]
1229     CYHAL_TRIGGER_TR_GROUP5_INPUT38 = 330, //!< Trigger input reduction mux - tr_group[5].input[38]
1230     CYHAL_TRIGGER_TR_GROUP5_INPUT39 = 331, //!< Trigger input reduction mux - tr_group[5].input[39]
1231     CYHAL_TRIGGER_TR_GROUP5_INPUT40 = 332, //!< Trigger input reduction mux - tr_group[5].input[40]
1232     CYHAL_TRIGGER_TR_GROUP5_INPUT41 = 333, //!< Trigger input reduction mux - tr_group[5].input[41]
1233     CYHAL_TRIGGER_TR_GROUP5_INPUT42 = 334, //!< Trigger input reduction mux - tr_group[5].input[42]
1234     CYHAL_TRIGGER_TR_GROUP6_INPUT1 = 335, //!< Datawire output trigger reduction mux - tr_group[6].input[1]
1235     CYHAL_TRIGGER_TR_GROUP6_INPUT2 = 336, //!< Datawire output trigger reduction mux - tr_group[6].input[2]
1236     CYHAL_TRIGGER_TR_GROUP6_INPUT3 = 337, //!< Datawire output trigger reduction mux - tr_group[6].input[3]
1237     CYHAL_TRIGGER_TR_GROUP6_INPUT4 = 338, //!< Datawire output trigger reduction mux - tr_group[6].input[4]
1238     CYHAL_TRIGGER_TR_GROUP6_INPUT5 = 339, //!< Datawire output trigger reduction mux - tr_group[6].input[5]
1239     CYHAL_TRIGGER_TR_GROUP6_INPUT6 = 340, //!< Datawire output trigger reduction mux - tr_group[6].input[6]
1240     CYHAL_TRIGGER_TR_GROUP6_INPUT7 = 341, //!< Datawire output trigger reduction mux - tr_group[6].input[7]
1241     CYHAL_TRIGGER_TR_GROUP6_INPUT8 = 342, //!< Datawire output trigger reduction mux - tr_group[6].input[8]
1242     CYHAL_TRIGGER_TR_GROUP6_INPUT9 = 343, //!< TCPWM trigger output reduction mux - tr_group[6].input[9]
1243     CYHAL_TRIGGER_TR_GROUP6_INPUT10 = 344, //!< TCPWM trigger output reduction mux - tr_group[6].input[10]
1244     CYHAL_TRIGGER_TR_GROUP6_INPUT11 = 345, //!< TCPWM trigger output reduction mux - tr_group[6].input[11]
1245     CYHAL_TRIGGER_TR_GROUP6_INPUT12 = 346, //!< TCPWM trigger output reduction mux - tr_group[6].input[12]
1246     CYHAL_TRIGGER_TR_GROUP6_INPUT13 = 347, //!< TCPWM trigger output reduction mux - tr_group[6].input[13]
1247     CYHAL_TRIGGER_TR_GROUP6_INPUT14 = 348, //!< TCPWM trigger output reduction mux - tr_group[6].input[14]
1248     CYHAL_TRIGGER_TR_GROUP6_INPUT15 = 349, //!< TCPWM trigger output reduction mux - tr_group[6].input[15]
1249     CYHAL_TRIGGER_TR_GROUP6_INPUT16 = 350, //!< TCPWM trigger output reduction mux - tr_group[6].input[16]
1250     CYHAL_TRIGGER_TR_GROUP6_INPUT17 = 351, //!< TCPWM trigger output reduction mux - tr_group[6].input[17]
1251     CYHAL_TRIGGER_TR_GROUP6_INPUT18 = 352, //!< TCPWM trigger output reduction mux - tr_group[6].input[18]
1252     CYHAL_TRIGGER_TR_GROUP6_INPUT19 = 353, //!< TCPWM trigger output reduction mux - tr_group[6].input[19]
1253     CYHAL_TRIGGER_TR_GROUP6_INPUT20 = 354, //!< TCPWM trigger output reduction mux - tr_group[6].input[20]
1254     CYHAL_TRIGGER_TR_GROUP6_INPUT21 = 355, //!< TCPWM trigger output reduction mux - tr_group[6].input[21]
1255     CYHAL_TRIGGER_TR_GROUP6_INPUT22 = 356, //!< TCPWM trigger output reduction mux - tr_group[6].input[22]
1256     CYHAL_TRIGGER_TR_GROUP6_INPUT23 = 357, //!< TCPWM trigger output reduction mux - tr_group[6].input[23]
1257     CYHAL_TRIGGER_TR_GROUP6_INPUT24 = 358, //!< TCPWM trigger output reduction mux - tr_group[6].input[24]
1258     CYHAL_TRIGGER_TR_GROUP6_INPUT25 = 359, //!< HSIOM Pin input reduction mux - tr_group[6].input[25]
1259     CYHAL_TRIGGER_TR_GROUP6_INPUT26 = 360, //!< HSIOM Pin input reduction mux - tr_group[6].input[26]
1260     CYHAL_TRIGGER_TR_GROUP6_INPUT27 = 361, //!< HSIOM Pin input reduction mux - tr_group[6].input[27]
1261     CYHAL_TRIGGER_TR_GROUP6_INPUT28 = 362, //!< HSIOM Pin input reduction mux - tr_group[6].input[28]
1262     CYHAL_TRIGGER_TR_GROUP6_INPUT29 = 363, //!< HSIOM Pin input reduction mux - tr_group[6].input[29]
1263     CYHAL_TRIGGER_TR_GROUP6_INPUT30 = 364, //!< HSIOM Pin input reduction mux - tr_group[6].input[30]
1264     CYHAL_TRIGGER_TR_GROUP6_INPUT31 = 365, //!< HSIOM Pin input reduction mux - tr_group[6].input[31]
1265     CYHAL_TRIGGER_TR_GROUP6_INPUT32 = 366, //!< HSIOM Pin input reduction mux - tr_group[6].input[32]
1266     CYHAL_TRIGGER_TR_GROUP6_INPUT33 = 367, //!< DMA request reduction mux - tr_group[6].input[33]
1267     CYHAL_TRIGGER_TR_GROUP6_INPUT34 = 368, //!< DMA request reduction mux - tr_group[6].input[34]
1268     CYHAL_TRIGGER_TR_GROUP6_INPUT35 = 369, //!< Trigger input reduction mux - tr_group[6].input[35]
1269     CYHAL_TRIGGER_TR_GROUP6_INPUT36 = 370, //!< Trigger input reduction mux - tr_group[6].input[36]
1270     CYHAL_TRIGGER_TR_GROUP6_INPUT37 = 371, //!< Trigger input reduction mux - tr_group[6].input[37]
1271     CYHAL_TRIGGER_TR_GROUP6_INPUT38 = 372, //!< Trigger input reduction mux - tr_group[6].input[38]
1272     CYHAL_TRIGGER_TR_GROUP6_INPUT39 = 373, //!< Trigger input reduction mux - tr_group[6].input[39]
1273     CYHAL_TRIGGER_TR_GROUP6_INPUT40 = 374, //!< Trigger input reduction mux - tr_group[6].input[40]
1274     CYHAL_TRIGGER_TR_GROUP6_INPUT41 = 375, //!< Trigger input reduction mux - tr_group[6].input[41]
1275     CYHAL_TRIGGER_TR_GROUP6_INPUT42 = 376, //!< Trigger input reduction mux - tr_group[6].input[42]
1276     CYHAL_TRIGGER_TR_GROUP7_INPUT1 = 377, //!< Datawire output trigger reduction mux - tr_group[7].input[1]
1277     CYHAL_TRIGGER_TR_GROUP7_INPUT2 = 378, //!< Datawire output trigger reduction mux - tr_group[7].input[2]
1278     CYHAL_TRIGGER_TR_GROUP7_INPUT3 = 379, //!< Datawire output trigger reduction mux - tr_group[7].input[3]
1279     CYHAL_TRIGGER_TR_GROUP7_INPUT4 = 380, //!< Datawire output trigger reduction mux - tr_group[7].input[4]
1280     CYHAL_TRIGGER_TR_GROUP7_INPUT5 = 381, //!< Datawire output trigger reduction mux - tr_group[7].input[5]
1281     CYHAL_TRIGGER_TR_GROUP7_INPUT6 = 382, //!< Datawire output trigger reduction mux - tr_group[7].input[6]
1282     CYHAL_TRIGGER_TR_GROUP7_INPUT7 = 383, //!< Datawire output trigger reduction mux - tr_group[7].input[7]
1283     CYHAL_TRIGGER_TR_GROUP7_INPUT8 = 384, //!< Datawire output trigger reduction mux - tr_group[7].input[8]
1284     CYHAL_TRIGGER_TR_GROUP7_INPUT9 = 385, //!< TCPWM trigger output reduction mux - tr_group[7].input[9]
1285     CYHAL_TRIGGER_TR_GROUP7_INPUT10 = 386, //!< TCPWM trigger output reduction mux - tr_group[7].input[10]
1286     CYHAL_TRIGGER_TR_GROUP7_INPUT11 = 387, //!< TCPWM trigger output reduction mux - tr_group[7].input[11]
1287     CYHAL_TRIGGER_TR_GROUP7_INPUT12 = 388, //!< TCPWM trigger output reduction mux - tr_group[7].input[12]
1288     CYHAL_TRIGGER_TR_GROUP7_INPUT13 = 389, //!< TCPWM trigger output reduction mux - tr_group[7].input[13]
1289     CYHAL_TRIGGER_TR_GROUP7_INPUT14 = 390, //!< TCPWM trigger output reduction mux - tr_group[7].input[14]
1290     CYHAL_TRIGGER_TR_GROUP7_INPUT15 = 391, //!< TCPWM trigger output reduction mux - tr_group[7].input[15]
1291     CYHAL_TRIGGER_TR_GROUP7_INPUT16 = 392, //!< TCPWM trigger output reduction mux - tr_group[7].input[16]
1292     CYHAL_TRIGGER_TR_GROUP7_INPUT17 = 393, //!< TCPWM trigger output reduction mux - tr_group[7].input[17]
1293     CYHAL_TRIGGER_TR_GROUP7_INPUT18 = 394, //!< TCPWM trigger output reduction mux - tr_group[7].input[18]
1294     CYHAL_TRIGGER_TR_GROUP7_INPUT19 = 395, //!< TCPWM trigger output reduction mux - tr_group[7].input[19]
1295     CYHAL_TRIGGER_TR_GROUP7_INPUT20 = 396, //!< TCPWM trigger output reduction mux - tr_group[7].input[20]
1296     CYHAL_TRIGGER_TR_GROUP7_INPUT21 = 397, //!< TCPWM trigger output reduction mux - tr_group[7].input[21]
1297     CYHAL_TRIGGER_TR_GROUP7_INPUT22 = 398, //!< TCPWM trigger output reduction mux - tr_group[7].input[22]
1298     CYHAL_TRIGGER_TR_GROUP7_INPUT23 = 399, //!< TCPWM trigger output reduction mux - tr_group[7].input[23]
1299     CYHAL_TRIGGER_TR_GROUP7_INPUT24 = 400, //!< TCPWM trigger output reduction mux - tr_group[7].input[24]
1300     CYHAL_TRIGGER_TR_GROUP7_INPUT25 = 401, //!< HSIOM Pin input reduction mux - tr_group[7].input[25]
1301     CYHAL_TRIGGER_TR_GROUP7_INPUT26 = 402, //!< HSIOM Pin input reduction mux - tr_group[7].input[26]
1302     CYHAL_TRIGGER_TR_GROUP7_INPUT27 = 403, //!< HSIOM Pin input reduction mux - tr_group[7].input[27]
1303     CYHAL_TRIGGER_TR_GROUP7_INPUT28 = 404, //!< HSIOM Pin input reduction mux - tr_group[7].input[28]
1304     CYHAL_TRIGGER_TR_GROUP7_INPUT29 = 405, //!< HSIOM Pin input reduction mux - tr_group[7].input[29]
1305     CYHAL_TRIGGER_TR_GROUP7_INPUT30 = 406, //!< HSIOM Pin input reduction mux - tr_group[7].input[30]
1306     CYHAL_TRIGGER_TR_GROUP7_INPUT31 = 407, //!< HSIOM Pin input reduction mux - tr_group[7].input[31]
1307     CYHAL_TRIGGER_TR_GROUP7_INPUT32 = 408, //!< HSIOM Pin input reduction mux - tr_group[7].input[32]
1308     CYHAL_TRIGGER_TR_GROUP7_INPUT33 = 409, //!< DMA request reduction mux - tr_group[7].input[33]
1309     CYHAL_TRIGGER_TR_GROUP7_INPUT34 = 410, //!< DMA request reduction mux - tr_group[7].input[34]
1310     CYHAL_TRIGGER_TR_GROUP7_INPUT35 = 411, //!< Trigger input reduction mux - tr_group[7].input[35]
1311     CYHAL_TRIGGER_TR_GROUP7_INPUT36 = 412, //!< Trigger input reduction mux - tr_group[7].input[36]
1312     CYHAL_TRIGGER_TR_GROUP7_INPUT37 = 413, //!< Trigger input reduction mux - tr_group[7].input[37]
1313     CYHAL_TRIGGER_TR_GROUP7_INPUT38 = 414, //!< Trigger input reduction mux - tr_group[7].input[38]
1314     CYHAL_TRIGGER_TR_GROUP7_INPUT39 = 415, //!< Trigger input reduction mux - tr_group[7].input[39]
1315     CYHAL_TRIGGER_TR_GROUP7_INPUT40 = 416, //!< Trigger input reduction mux - tr_group[7].input[40]
1316     CYHAL_TRIGGER_TR_GROUP7_INPUT41 = 417, //!< Trigger input reduction mux - tr_group[7].input[41]
1317     CYHAL_TRIGGER_TR_GROUP7_INPUT42 = 418, //!< Trigger input reduction mux - tr_group[7].input[42]
1318     CYHAL_TRIGGER_TR_GROUP8_INPUT1 = 419, //!< Datawire output trigger reduction mux - tr_group[8].input[1]
1319     CYHAL_TRIGGER_TR_GROUP8_INPUT2 = 420, //!< Datawire output trigger reduction mux - tr_group[8].input[2]
1320     CYHAL_TRIGGER_TR_GROUP8_INPUT3 = 421, //!< Datawire output trigger reduction mux - tr_group[8].input[3]
1321     CYHAL_TRIGGER_TR_GROUP8_INPUT4 = 422, //!< Datawire output trigger reduction mux - tr_group[8].input[4]
1322     CYHAL_TRIGGER_TR_GROUP8_INPUT5 = 423, //!< Datawire output trigger reduction mux - tr_group[8].input[5]
1323     CYHAL_TRIGGER_TR_GROUP8_INPUT6 = 424, //!< Datawire output trigger reduction mux - tr_group[8].input[6]
1324     CYHAL_TRIGGER_TR_GROUP8_INPUT7 = 425, //!< Datawire output trigger reduction mux - tr_group[8].input[7]
1325     CYHAL_TRIGGER_TR_GROUP8_INPUT8 = 426, //!< Datawire output trigger reduction mux - tr_group[8].input[8]
1326     CYHAL_TRIGGER_TR_GROUP8_INPUT9 = 427, //!< TCPWM trigger output reduction mux - tr_group[8].input[9]
1327     CYHAL_TRIGGER_TR_GROUP8_INPUT10 = 428, //!< TCPWM trigger output reduction mux - tr_group[8].input[10]
1328     CYHAL_TRIGGER_TR_GROUP8_INPUT11 = 429, //!< TCPWM trigger output reduction mux - tr_group[8].input[11]
1329     CYHAL_TRIGGER_TR_GROUP8_INPUT12 = 430, //!< TCPWM trigger output reduction mux - tr_group[8].input[12]
1330     CYHAL_TRIGGER_TR_GROUP8_INPUT13 = 431, //!< TCPWM trigger output reduction mux - tr_group[8].input[13]
1331     CYHAL_TRIGGER_TR_GROUP8_INPUT14 = 432, //!< TCPWM trigger output reduction mux - tr_group[8].input[14]
1332     CYHAL_TRIGGER_TR_GROUP8_INPUT15 = 433, //!< TCPWM trigger output reduction mux - tr_group[8].input[15]
1333     CYHAL_TRIGGER_TR_GROUP8_INPUT16 = 434, //!< TCPWM trigger output reduction mux - tr_group[8].input[16]
1334     CYHAL_TRIGGER_TR_GROUP8_INPUT17 = 435, //!< TCPWM trigger output reduction mux - tr_group[8].input[17]
1335     CYHAL_TRIGGER_TR_GROUP8_INPUT18 = 436, //!< TCPWM trigger output reduction mux - tr_group[8].input[18]
1336     CYHAL_TRIGGER_TR_GROUP8_INPUT19 = 437, //!< TCPWM trigger output reduction mux - tr_group[8].input[19]
1337     CYHAL_TRIGGER_TR_GROUP8_INPUT20 = 438, //!< TCPWM trigger output reduction mux - tr_group[8].input[20]
1338     CYHAL_TRIGGER_TR_GROUP8_INPUT21 = 439, //!< TCPWM trigger output reduction mux - tr_group[8].input[21]
1339     CYHAL_TRIGGER_TR_GROUP8_INPUT22 = 440, //!< TCPWM trigger output reduction mux - tr_group[8].input[22]
1340     CYHAL_TRIGGER_TR_GROUP8_INPUT23 = 441, //!< TCPWM trigger output reduction mux - tr_group[8].input[23]
1341     CYHAL_TRIGGER_TR_GROUP8_INPUT24 = 442, //!< TCPWM trigger output reduction mux - tr_group[8].input[24]
1342     CYHAL_TRIGGER_TR_GROUP8_INPUT25 = 443, //!< HSIOM Pin input reduction mux - tr_group[8].input[25]
1343     CYHAL_TRIGGER_TR_GROUP8_INPUT26 = 444, //!< HSIOM Pin input reduction mux - tr_group[8].input[26]
1344     CYHAL_TRIGGER_TR_GROUP8_INPUT27 = 445, //!< HSIOM Pin input reduction mux - tr_group[8].input[27]
1345     CYHAL_TRIGGER_TR_GROUP8_INPUT28 = 446, //!< HSIOM Pin input reduction mux - tr_group[8].input[28]
1346     CYHAL_TRIGGER_TR_GROUP8_INPUT29 = 447, //!< HSIOM Pin input reduction mux - tr_group[8].input[29]
1347     CYHAL_TRIGGER_TR_GROUP8_INPUT30 = 448, //!< HSIOM Pin input reduction mux - tr_group[8].input[30]
1348     CYHAL_TRIGGER_TR_GROUP8_INPUT31 = 449, //!< HSIOM Pin input reduction mux - tr_group[8].input[31]
1349     CYHAL_TRIGGER_TR_GROUP8_INPUT32 = 450, //!< HSIOM Pin input reduction mux - tr_group[8].input[32]
1350     CYHAL_TRIGGER_TR_GROUP8_INPUT33 = 451, //!< DMA request reduction mux - tr_group[8].input[33]
1351     CYHAL_TRIGGER_TR_GROUP8_INPUT34 = 452, //!< DMA request reduction mux - tr_group[8].input[34]
1352     CYHAL_TRIGGER_TR_GROUP8_INPUT35 = 453, //!< Trigger input reduction mux - tr_group[8].input[35]
1353     CYHAL_TRIGGER_TR_GROUP8_INPUT36 = 454, //!< Trigger input reduction mux - tr_group[8].input[36]
1354     CYHAL_TRIGGER_TR_GROUP8_INPUT37 = 455, //!< Trigger input reduction mux - tr_group[8].input[37]
1355     CYHAL_TRIGGER_TR_GROUP8_INPUT38 = 456, //!< Trigger input reduction mux - tr_group[8].input[38]
1356     CYHAL_TRIGGER_TR_GROUP8_INPUT39 = 457, //!< Trigger input reduction mux - tr_group[8].input[39]
1357     CYHAL_TRIGGER_TR_GROUP8_INPUT40 = 458, //!< Trigger input reduction mux - tr_group[8].input[40]
1358     CYHAL_TRIGGER_TR_GROUP8_INPUT41 = 459, //!< Trigger input reduction mux - tr_group[8].input[41]
1359     CYHAL_TRIGGER_TR_GROUP8_INPUT42 = 460, //!< Trigger input reduction mux - tr_group[8].input[42]
1360     CYHAL_TRIGGER_UDB_TR_DW_ACK0 = 461, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[0]
1361     CYHAL_TRIGGER_UDB_TR_DW_ACK1 = 462, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[1]
1362     CYHAL_TRIGGER_UDB_TR_DW_ACK2 = 463, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[2]
1363     CYHAL_TRIGGER_UDB_TR_DW_ACK3 = 464, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[3]
1364     CYHAL_TRIGGER_UDB_TR_DW_ACK4 = 465, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[4]
1365     CYHAL_TRIGGER_UDB_TR_DW_ACK5 = 466, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[5]
1366     CYHAL_TRIGGER_UDB_TR_DW_ACK6 = 467, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[6]
1367     CYHAL_TRIGGER_UDB_TR_DW_ACK7 = 468, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[7]
1368     CYHAL_TRIGGER_UDB_TR_IN0 = 469, //!< UDB trigger multiplexer - udb.tr_in[0]
1369     CYHAL_TRIGGER_UDB_TR_IN1 = 470, //!< UDB trigger multiplexer - udb.tr_in[1]
1370     CYHAL_TRIGGER_USB_DMA_BURSTEND0 = 471, //!< USB DMA burstend multiplexer - usb.dma_burstend[0]
1371     CYHAL_TRIGGER_USB_DMA_BURSTEND1 = 472, //!< USB DMA burstend multiplexer - usb.dma_burstend[1]
1372     CYHAL_TRIGGER_USB_DMA_BURSTEND2 = 473, //!< USB DMA burstend multiplexer - usb.dma_burstend[2]
1373     CYHAL_TRIGGER_USB_DMA_BURSTEND3 = 474, //!< USB DMA burstend multiplexer - usb.dma_burstend[3]
1374     CYHAL_TRIGGER_USB_DMA_BURSTEND4 = 475, //!< USB DMA burstend multiplexer - usb.dma_burstend[4]
1375     CYHAL_TRIGGER_USB_DMA_BURSTEND5 = 476, //!< USB DMA burstend multiplexer - usb.dma_burstend[5]
1376     CYHAL_TRIGGER_USB_DMA_BURSTEND6 = 477, //!< USB DMA burstend multiplexer - usb.dma_burstend[6]
1377     CYHAL_TRIGGER_USB_DMA_BURSTEND7 = 478, //!< USB DMA burstend multiplexer - usb.dma_burstend[7]
1378 } cyhal_trigger_dest_psoc6_01_t;
1379 
1380 /** Typedef from device family specific trigger dest to generic trigger dest */
1381 typedef cyhal_trigger_dest_psoc6_01_t cyhal_dest_t;
1382 
1383 /** \cond INTERNAL */
1384 /** Table of number of inputs to each mux. */
1385 extern const uint16_t cyhal_sources_per_mux[15];
1386 
1387 /** Table indicating whether mux is 1to1. */
1388 extern const bool cyhal_is_mux_1to1[15];
1389 
1390 /** Table pointing to each mux source table. The index of each source in the table is its mux input index. */
1391 extern const _cyhal_trigger_source_psoc6_01_t* cyhal_mux_to_sources [15];
1392 
1393 /** Maps each cyhal_destination_t to a mux index.
1394  * If bit 8 of the mux index is set, this denotes that the trigger is a
1395  * one to one trigger.
1396  */
1397 extern const uint8_t cyhal_dest_to_mux[479];
1398 
1399 /* Maps each cyhal_destination_t to a specific output in its mux */
1400 extern const uint8_t cyhal_mux_dest_index[479];
1401 /** \endcond */
1402 
1403 #if defined(__cplusplus)
1404 }
1405 #endif /* __cplusplus */
1406 /** \} group_hal_impl_triggers_psoc6_01 */
1407 #endif /* _CYHAL_TRIGGERS_PSOC6_01_H_ */
1408 
1409 
1410 /* [] END OF FILE */
1411