1 /***************************************************************************//** 2 * \file cyhal_triggers_psoc6_02.h 3 * 4 * \brief 5 * PSoC6_02 family HAL triggers header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TRIGGERS_PSOC6_02_H_ 28 #define _CYHAL_TRIGGERS_PSOC6_02_H_ 29 30 /** 31 * \addtogroup group_hal_impl_triggers_psoc6_02 PSOC6_02 32 * \ingroup group_hal_impl_triggers 33 * \{ 34 * Trigger connections for psoc6_02 35 */ 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** \cond INTERNAL */ 42 /** @brief Name of each input trigger. */ 43 typedef enum 44 { 45 _CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero 46 _CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ = 1, //!< audioss[0].tr_i2s_rx_req 47 _CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ = 2, //!< audioss[1].tr_i2s_rx_req 48 _CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ = 3, //!< audioss[0].tr_i2s_tx_req 49 _CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ = 4, //!< audioss[1].tr_i2s_tx_req 50 _CYHAL_TRIGGER_AUDIOSS0_TR_PDM_RX_REQ = 5, //!< audioss[0].tr_pdm_rx_req 51 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 6, //!< cpuss.cti_tr_out[0] 52 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 7, //!< cpuss.cti_tr_out[1] 53 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 8, //!< cpuss.dmac_tr_out[0] 54 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 9, //!< cpuss.dmac_tr_out[1] 55 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = 10, //!< cpuss.dmac_tr_out[2] 56 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = 11, //!< cpuss.dmac_tr_out[3] 57 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 12, //!< cpuss.dw0_tr_out[0] 58 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 13, //!< cpuss.dw0_tr_out[1] 59 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 14, //!< cpuss.dw0_tr_out[2] 60 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 15, //!< cpuss.dw0_tr_out[3] 61 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 16, //!< cpuss.dw0_tr_out[4] 62 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 17, //!< cpuss.dw0_tr_out[5] 63 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 18, //!< cpuss.dw0_tr_out[6] 64 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 19, //!< cpuss.dw0_tr_out[7] 65 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 20, //!< cpuss.dw0_tr_out[8] 66 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 21, //!< cpuss.dw0_tr_out[9] 67 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 22, //!< cpuss.dw0_tr_out[10] 68 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 23, //!< cpuss.dw0_tr_out[11] 69 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 24, //!< cpuss.dw0_tr_out[12] 70 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 25, //!< cpuss.dw0_tr_out[13] 71 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 26, //!< cpuss.dw0_tr_out[14] 72 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 27, //!< cpuss.dw0_tr_out[15] 73 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 28, //!< cpuss.dw0_tr_out[16] 74 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 29, //!< cpuss.dw0_tr_out[17] 75 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 30, //!< cpuss.dw0_tr_out[18] 76 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 31, //!< cpuss.dw0_tr_out[19] 77 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 32, //!< cpuss.dw0_tr_out[20] 78 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 33, //!< cpuss.dw0_tr_out[21] 79 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 34, //!< cpuss.dw0_tr_out[22] 80 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 35, //!< cpuss.dw0_tr_out[23] 81 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 36, //!< cpuss.dw0_tr_out[24] 82 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 37, //!< cpuss.dw0_tr_out[25] 83 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 38, //!< cpuss.dw0_tr_out[26] 84 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 39, //!< cpuss.dw0_tr_out[27] 85 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 40, //!< cpuss.dw0_tr_out[28] 86 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 41, //!< cpuss.dw1_tr_out[0] 87 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 42, //!< cpuss.dw1_tr_out[1] 88 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 43, //!< cpuss.dw1_tr_out[2] 89 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 44, //!< cpuss.dw1_tr_out[3] 90 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 45, //!< cpuss.dw1_tr_out[4] 91 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 46, //!< cpuss.dw1_tr_out[5] 92 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 47, //!< cpuss.dw1_tr_out[6] 93 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 48, //!< cpuss.dw1_tr_out[7] 94 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 49, //!< cpuss.dw1_tr_out[8] 95 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 50, //!< cpuss.dw1_tr_out[9] 96 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 51, //!< cpuss.dw1_tr_out[10] 97 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 52, //!< cpuss.dw1_tr_out[11] 98 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 53, //!< cpuss.dw1_tr_out[12] 99 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 54, //!< cpuss.dw1_tr_out[13] 100 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 55, //!< cpuss.dw1_tr_out[14] 101 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 56, //!< cpuss.dw1_tr_out[15] 102 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 57, //!< cpuss.dw1_tr_out[16] 103 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 58, //!< cpuss.dw1_tr_out[17] 104 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 59, //!< cpuss.dw1_tr_out[18] 105 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 60, //!< cpuss.dw1_tr_out[19] 106 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 61, //!< cpuss.dw1_tr_out[20] 107 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 62, //!< cpuss.dw1_tr_out[21] 108 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 63, //!< cpuss.dw1_tr_out[22] 109 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 64, //!< cpuss.dw1_tr_out[23] 110 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 65, //!< cpuss.dw1_tr_out[24] 111 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 66, //!< cpuss.dw1_tr_out[25] 112 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 67, //!< cpuss.dw1_tr_out[26] 113 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 68, //!< cpuss.dw1_tr_out[27] 114 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 69, //!< cpuss.dw1_tr_out[28] 115 _CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 70, //!< cpuss.tr_fault[0] 116 _CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 71, //!< cpuss.tr_fault[1] 117 _CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT = 72, //!< csd.dsi_sample_out 118 _CYHAL_TRIGGER_CSD_DSI_SENSE_OUT = 73, //!< csd.dsi_sense_out 119 _CYHAL_TRIGGER_CSD_TR_ADC_DONE = 74, //!< csd.tr_adc_done 120 _CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 75, //!< lpcomp.dsi_comp0 121 _CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 76, //!< lpcomp.dsi_comp1 122 _CYHAL_TRIGGER_PASS_TR_SAR_OUT = 77, //!< pass.tr_sar_out 123 _CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 78, //!< peri.tr_io_input[0] 124 _CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 79, //!< peri.tr_io_input[1] 125 _CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 80, //!< peri.tr_io_input[2] 126 _CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 81, //!< peri.tr_io_input[3] 127 _CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 82, //!< peri.tr_io_input[4] 128 _CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 83, //!< peri.tr_io_input[5] 129 _CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 84, //!< peri.tr_io_input[6] 130 _CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 85, //!< peri.tr_io_input[7] 131 _CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 86, //!< peri.tr_io_input[8] 132 _CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 87, //!< peri.tr_io_input[9] 133 _CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 88, //!< peri.tr_io_input[10] 134 _CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 89, //!< peri.tr_io_input[11] 135 _CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 90, //!< peri.tr_io_input[12] 136 _CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 91, //!< peri.tr_io_input[13] 137 _CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 92, //!< peri.tr_io_input[14] 138 _CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 93, //!< peri.tr_io_input[15] 139 _CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 94, //!< peri.tr_io_input[16] 140 _CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 95, //!< peri.tr_io_input[17] 141 _CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 96, //!< peri.tr_io_input[18] 142 _CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 97, //!< peri.tr_io_input[19] 143 _CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 98, //!< peri.tr_io_input[20] 144 _CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 99, //!< peri.tr_io_input[21] 145 _CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 100, //!< peri.tr_io_input[22] 146 _CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 101, //!< peri.tr_io_input[23] 147 _CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 102, //!< peri.tr_io_input[24] 148 _CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 103, //!< peri.tr_io_input[25] 149 _CYHAL_TRIGGER_PERI_TR_IO_INPUT26 = 104, //!< peri.tr_io_input[26] 150 _CYHAL_TRIGGER_PERI_TR_IO_INPUT27 = 105, //!< peri.tr_io_input[27] 151 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 106, //!< scb[0].tr_i2c_scl_filtered 152 _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 107, //!< scb[1].tr_i2c_scl_filtered 153 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 108, //!< scb[2].tr_i2c_scl_filtered 154 _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 109, //!< scb[3].tr_i2c_scl_filtered 155 _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 110, //!< scb[4].tr_i2c_scl_filtered 156 _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 111, //!< scb[5].tr_i2c_scl_filtered 157 _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 112, //!< scb[6].tr_i2c_scl_filtered 158 _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 113, //!< scb[7].tr_i2c_scl_filtered 159 _CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = 114, //!< scb[8].tr_i2c_scl_filtered 160 _CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = 115, //!< scb[9].tr_i2c_scl_filtered 161 _CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = 116, //!< scb[10].tr_i2c_scl_filtered 162 _CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED = 117, //!< scb[11].tr_i2c_scl_filtered 163 _CYHAL_TRIGGER_SCB12_TR_I2C_SCL_FILTERED = 118, //!< scb[12].tr_i2c_scl_filtered 164 _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 119, //!< scb[0].tr_rx_req 165 _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 120, //!< scb[1].tr_rx_req 166 _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 121, //!< scb[2].tr_rx_req 167 _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 122, //!< scb[3].tr_rx_req 168 _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 123, //!< scb[4].tr_rx_req 169 _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 124, //!< scb[5].tr_rx_req 170 _CYHAL_TRIGGER_SCB6_TR_RX_REQ = 125, //!< scb[6].tr_rx_req 171 _CYHAL_TRIGGER_SCB7_TR_RX_REQ = 126, //!< scb[7].tr_rx_req 172 _CYHAL_TRIGGER_SCB8_TR_RX_REQ = 127, //!< scb[8].tr_rx_req 173 _CYHAL_TRIGGER_SCB9_TR_RX_REQ = 128, //!< scb[9].tr_rx_req 174 _CYHAL_TRIGGER_SCB10_TR_RX_REQ = 129, //!< scb[10].tr_rx_req 175 _CYHAL_TRIGGER_SCB11_TR_RX_REQ = 130, //!< scb[11].tr_rx_req 176 _CYHAL_TRIGGER_SCB12_TR_RX_REQ = 131, //!< scb[12].tr_rx_req 177 _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 132, //!< scb[0].tr_tx_req 178 _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 133, //!< scb[1].tr_tx_req 179 _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 134, //!< scb[2].tr_tx_req 180 _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 135, //!< scb[3].tr_tx_req 181 _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 136, //!< scb[4].tr_tx_req 182 _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 137, //!< scb[5].tr_tx_req 183 _CYHAL_TRIGGER_SCB6_TR_TX_REQ = 138, //!< scb[6].tr_tx_req 184 _CYHAL_TRIGGER_SCB7_TR_TX_REQ = 139, //!< scb[7].tr_tx_req 185 _CYHAL_TRIGGER_SCB8_TR_TX_REQ = 140, //!< scb[8].tr_tx_req 186 _CYHAL_TRIGGER_SCB9_TR_TX_REQ = 141, //!< scb[9].tr_tx_req 187 _CYHAL_TRIGGER_SCB10_TR_TX_REQ = 142, //!< scb[10].tr_tx_req 188 _CYHAL_TRIGGER_SCB11_TR_TX_REQ = 143, //!< scb[11].tr_tx_req 189 _CYHAL_TRIGGER_SCB12_TR_TX_REQ = 144, //!< scb[12].tr_tx_req 190 _CYHAL_TRIGGER_SMIF_TR_RX_REQ = 145, //!< smif.tr_rx_req 191 _CYHAL_TRIGGER_SMIF_TR_TX_REQ = 146, //!< smif.tr_tx_req 192 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = 147, //!< tcpwm[0].tr_compare_match[0] 193 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = 148, //!< tcpwm[0].tr_compare_match[1] 194 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = 149, //!< tcpwm[0].tr_compare_match[2] 195 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = 150, //!< tcpwm[0].tr_compare_match[3] 196 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4 = 151, //!< tcpwm[0].tr_compare_match[4] 197 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5 = 152, //!< tcpwm[0].tr_compare_match[5] 198 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6 = 153, //!< tcpwm[0].tr_compare_match[6] 199 _CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7 = 154, //!< tcpwm[0].tr_compare_match[7] 200 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = 155, //!< tcpwm[1].tr_compare_match[0] 201 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = 156, //!< tcpwm[1].tr_compare_match[1] 202 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = 157, //!< tcpwm[1].tr_compare_match[2] 203 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = 158, //!< tcpwm[1].tr_compare_match[3] 204 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = 159, //!< tcpwm[1].tr_compare_match[4] 205 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = 160, //!< tcpwm[1].tr_compare_match[5] 206 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = 161, //!< tcpwm[1].tr_compare_match[6] 207 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = 162, //!< tcpwm[1].tr_compare_match[7] 208 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8 = 163, //!< tcpwm[1].tr_compare_match[8] 209 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9 = 164, //!< tcpwm[1].tr_compare_match[9] 210 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10 = 165, //!< tcpwm[1].tr_compare_match[10] 211 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11 = 166, //!< tcpwm[1].tr_compare_match[11] 212 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12 = 167, //!< tcpwm[1].tr_compare_match[12] 213 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13 = 168, //!< tcpwm[1].tr_compare_match[13] 214 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14 = 169, //!< tcpwm[1].tr_compare_match[14] 215 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15 = 170, //!< tcpwm[1].tr_compare_match[15] 216 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16 = 171, //!< tcpwm[1].tr_compare_match[16] 217 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17 = 172, //!< tcpwm[1].tr_compare_match[17] 218 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18 = 173, //!< tcpwm[1].tr_compare_match[18] 219 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19 = 174, //!< tcpwm[1].tr_compare_match[19] 220 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20 = 175, //!< tcpwm[1].tr_compare_match[20] 221 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21 = 176, //!< tcpwm[1].tr_compare_match[21] 222 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22 = 177, //!< tcpwm[1].tr_compare_match[22] 223 _CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23 = 178, //!< tcpwm[1].tr_compare_match[23] 224 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = 179, //!< tcpwm[0].tr_overflow[0] 225 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = 180, //!< tcpwm[0].tr_overflow[1] 226 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = 181, //!< tcpwm[0].tr_overflow[2] 227 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = 182, //!< tcpwm[0].tr_overflow[3] 228 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4 = 183, //!< tcpwm[0].tr_overflow[4] 229 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5 = 184, //!< tcpwm[0].tr_overflow[5] 230 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6 = 185, //!< tcpwm[0].tr_overflow[6] 231 _CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7 = 186, //!< tcpwm[0].tr_overflow[7] 232 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = 187, //!< tcpwm[1].tr_overflow[0] 233 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = 188, //!< tcpwm[1].tr_overflow[1] 234 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = 189, //!< tcpwm[1].tr_overflow[2] 235 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = 190, //!< tcpwm[1].tr_overflow[3] 236 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = 191, //!< tcpwm[1].tr_overflow[4] 237 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = 192, //!< tcpwm[1].tr_overflow[5] 238 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = 193, //!< tcpwm[1].tr_overflow[6] 239 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = 194, //!< tcpwm[1].tr_overflow[7] 240 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8 = 195, //!< tcpwm[1].tr_overflow[8] 241 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9 = 196, //!< tcpwm[1].tr_overflow[9] 242 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10 = 197, //!< tcpwm[1].tr_overflow[10] 243 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11 = 198, //!< tcpwm[1].tr_overflow[11] 244 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12 = 199, //!< tcpwm[1].tr_overflow[12] 245 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13 = 200, //!< tcpwm[1].tr_overflow[13] 246 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14 = 201, //!< tcpwm[1].tr_overflow[14] 247 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15 = 202, //!< tcpwm[1].tr_overflow[15] 248 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16 = 203, //!< tcpwm[1].tr_overflow[16] 249 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17 = 204, //!< tcpwm[1].tr_overflow[17] 250 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18 = 205, //!< tcpwm[1].tr_overflow[18] 251 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19 = 206, //!< tcpwm[1].tr_overflow[19] 252 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20 = 207, //!< tcpwm[1].tr_overflow[20] 253 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21 = 208, //!< tcpwm[1].tr_overflow[21] 254 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22 = 209, //!< tcpwm[1].tr_overflow[22] 255 _CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23 = 210, //!< tcpwm[1].tr_overflow[23] 256 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = 211, //!< tcpwm[0].tr_underflow[0] 257 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = 212, //!< tcpwm[0].tr_underflow[1] 258 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = 213, //!< tcpwm[0].tr_underflow[2] 259 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = 214, //!< tcpwm[0].tr_underflow[3] 260 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4 = 215, //!< tcpwm[0].tr_underflow[4] 261 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5 = 216, //!< tcpwm[0].tr_underflow[5] 262 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6 = 217, //!< tcpwm[0].tr_underflow[6] 263 _CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7 = 218, //!< tcpwm[0].tr_underflow[7] 264 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = 219, //!< tcpwm[1].tr_underflow[0] 265 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = 220, //!< tcpwm[1].tr_underflow[1] 266 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = 221, //!< tcpwm[1].tr_underflow[2] 267 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = 222, //!< tcpwm[1].tr_underflow[3] 268 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = 223, //!< tcpwm[1].tr_underflow[4] 269 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = 224, //!< tcpwm[1].tr_underflow[5] 270 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = 225, //!< tcpwm[1].tr_underflow[6] 271 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = 226, //!< tcpwm[1].tr_underflow[7] 272 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8 = 227, //!< tcpwm[1].tr_underflow[8] 273 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9 = 228, //!< tcpwm[1].tr_underflow[9] 274 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10 = 229, //!< tcpwm[1].tr_underflow[10] 275 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11 = 230, //!< tcpwm[1].tr_underflow[11] 276 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12 = 231, //!< tcpwm[1].tr_underflow[12] 277 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13 = 232, //!< tcpwm[1].tr_underflow[13] 278 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14 = 233, //!< tcpwm[1].tr_underflow[14] 279 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15 = 234, //!< tcpwm[1].tr_underflow[15] 280 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16 = 235, //!< tcpwm[1].tr_underflow[16] 281 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17 = 236, //!< tcpwm[1].tr_underflow[17] 282 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18 = 237, //!< tcpwm[1].tr_underflow[18] 283 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19 = 238, //!< tcpwm[1].tr_underflow[19] 284 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20 = 239, //!< tcpwm[1].tr_underflow[20] 285 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21 = 240, //!< tcpwm[1].tr_underflow[21] 286 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22 = 241, //!< tcpwm[1].tr_underflow[22] 287 _CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23 = 242, //!< tcpwm[1].tr_underflow[23] 288 _CYHAL_TRIGGER_USB_DMA_REQ0 = 243, //!< usb.dma_req[0] 289 _CYHAL_TRIGGER_USB_DMA_REQ1 = 244, //!< usb.dma_req[1] 290 _CYHAL_TRIGGER_USB_DMA_REQ2 = 245, //!< usb.dma_req[2] 291 _CYHAL_TRIGGER_USB_DMA_REQ3 = 246, //!< usb.dma_req[3] 292 _CYHAL_TRIGGER_USB_DMA_REQ4 = 247, //!< usb.dma_req[4] 293 _CYHAL_TRIGGER_USB_DMA_REQ5 = 248, //!< usb.dma_req[5] 294 _CYHAL_TRIGGER_USB_DMA_REQ6 = 249, //!< usb.dma_req[6] 295 _CYHAL_TRIGGER_USB_DMA_REQ7 = 250, //!< usb.dma_req[7] 296 } _cyhal_trigger_source_psoc6_02_t; 297 298 /** Typedef for internal device family specific trigger source to generic trigger source */ 299 typedef _cyhal_trigger_source_psoc6_02_t cyhal_internal_source_t; 300 301 /** @brief Get a public source signal type (cyhal_trigger_source_psoc6_02_t) given an internal source signal and signal type */ 302 #define _CYHAL_TRIGGER_CREATE_SOURCE(src, type) ((src) << 1 | (type)) 303 /** @brief Get an internal source signal (_cyhal_trigger_source_psoc6_02_t) given a public source signal. */ 304 #define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src) ((cyhal_internal_source_t)((src) >> 1)) 305 /** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */ 306 #define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src) ((cyhal_signal_type_t)((src) & 1)) 307 /** \endcond */ 308 309 /** @brief Name of each input trigger. */ 310 typedef enum 311 { 312 CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.zero 313 CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.zero 314 CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[0].tr_i2s_rx_req 315 CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[1].tr_i2s_rx_req 316 CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[0].tr_i2s_tx_req 317 CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[1].tr_i2s_tx_req 318 CYHAL_TRIGGER_AUDIOSS0_TR_PDM_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS0_TR_PDM_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[0].tr_pdm_rx_req 319 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[0] 320 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[1] 321 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[0] 322 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[1] 323 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[2] 324 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[3] 325 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[0] 326 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[1] 327 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[2] 328 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[3] 329 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[4] 330 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[5] 331 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[6] 332 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[7] 333 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[8] 334 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[9] 335 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[10] 336 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[11] 337 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[12] 338 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[13] 339 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[14] 340 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[15] 341 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[16] 342 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[17] 343 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[18] 344 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[19] 345 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[20] 346 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[21] 347 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[22] 348 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[23] 349 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[24] 350 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[25] 351 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[26] 352 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[27] 353 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[28] 354 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[0] 355 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[1] 356 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[2] 357 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[3] 358 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[4] 359 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[5] 360 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[6] 361 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[7] 362 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[8] 363 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[9] 364 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[10] 365 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[11] 366 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[12] 367 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[13] 368 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[14] 369 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[15] 370 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[16] 371 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[17] 372 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[18] 373 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[19] 374 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[20] 375 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[21] 376 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[22] 377 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[23] 378 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[24] 379 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[25] 380 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[26] 381 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[27] 382 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[28] 383 CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[0] 384 CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[1] 385 CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< csd.dsi_sample_out 386 CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< csd.dsi_sense_out 387 CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_DSI_SENSE_OUT, CYHAL_SIGNAL_TYPE_LEVEL), //!< csd.dsi_sense_out 388 CYHAL_TRIGGER_CSD_TR_ADC_DONE_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_EDGE), //!< csd.tr_adc_done 389 CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CSD_TR_ADC_DONE, CYHAL_SIGNAL_TYPE_LEVEL), //!< csd.tr_adc_done 390 CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP0, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp0 391 CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP1, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp1 392 CYHAL_TRIGGER_PASS_TR_SAR_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_SAR_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_sar_out 393 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[0] 394 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[0] 395 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[1] 396 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[1] 397 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[2] 398 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[2] 399 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[3] 400 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[3] 401 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[4] 402 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[4] 403 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[5] 404 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[5] 405 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[6] 406 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[6] 407 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[7] 408 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[7] 409 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[8] 410 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[8] 411 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[9] 412 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[9] 413 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[10] 414 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[10] 415 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[11] 416 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[11] 417 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[12] 418 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[12] 419 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[13] 420 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[13] 421 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[14] 422 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[14] 423 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[15] 424 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[15] 425 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[16] 426 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[16] 427 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[17] 428 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[17] 429 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[18] 430 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[18] 431 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[19] 432 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[19] 433 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[20] 434 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[20] 435 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[21] 436 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[21] 437 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[22] 438 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[22] 439 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[23] 440 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[23] 441 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[24] 442 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[24] 443 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[25] 444 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[25] 445 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[26] 446 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[26] 447 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[27] 448 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[27] 449 CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered 450 CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered 451 CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered 452 CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered 453 CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered 454 CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered 455 CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered 456 CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered 457 CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_i2c_scl_filtered 458 CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_i2c_scl_filtered 459 CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_i2c_scl_filtered 460 CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_i2c_scl_filtered 461 CYHAL_TRIGGER_SCB12_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB12_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[12].tr_i2c_scl_filtered 462 CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req 463 CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req 464 CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req 465 CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req 466 CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req 467 CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req 468 CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req 469 CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req 470 CYHAL_TRIGGER_SCB8_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_rx_req 471 CYHAL_TRIGGER_SCB9_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_rx_req 472 CYHAL_TRIGGER_SCB10_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_rx_req 473 CYHAL_TRIGGER_SCB11_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_rx_req 474 CYHAL_TRIGGER_SCB12_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB12_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[12].tr_rx_req 475 CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req 476 CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req 477 CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req 478 CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req 479 CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req 480 CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req 481 CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req 482 CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req 483 CYHAL_TRIGGER_SCB8_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_tx_req 484 CYHAL_TRIGGER_SCB9_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_tx_req 485 CYHAL_TRIGGER_SCB10_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_tx_req 486 CYHAL_TRIGGER_SCB11_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_tx_req 487 CYHAL_TRIGGER_SCB12_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB12_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[12].tr_tx_req 488 CYHAL_TRIGGER_SMIF_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif.tr_rx_req 489 CYHAL_TRIGGER_SMIF_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif.tr_tx_req 490 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[0] 491 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[1] 492 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[2] 493 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[3] 494 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[4] 495 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[5] 496 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[6] 497 CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_compare_match[7] 498 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[0] 499 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[1] 500 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[2] 501 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[3] 502 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[4] 503 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[5] 504 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[6] 505 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[7] 506 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[8] 507 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[9] 508 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[10] 509 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[11] 510 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[12] 511 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[13] 512 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[14] 513 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[15] 514 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[16] 515 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[17] 516 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[18] 517 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[19] 518 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[20] 519 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[21] 520 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[22] 521 CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_compare_match[23] 522 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[0] 523 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[1] 524 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[2] 525 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[3] 526 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[4] 527 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[5] 528 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[6] 529 CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_overflow[7] 530 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[0] 531 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[1] 532 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[2] 533 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[3] 534 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[4] 535 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[5] 536 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[6] 537 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[7] 538 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[8] 539 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[9] 540 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[10] 541 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[11] 542 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[12] 543 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[13] 544 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[14] 545 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[15] 546 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[16] 547 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[17] 548 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[18] 549 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[19] 550 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[20] 551 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[21] 552 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[22] 553 CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_overflow[23] 554 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[0] 555 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[1] 556 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[2] 557 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[3] 558 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[4] 559 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[5] 560 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[6] 561 CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_underflow[7] 562 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[0] 563 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[1] 564 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[2] 565 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[3] 566 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[4] 567 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[5] 568 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[6] 569 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[7] 570 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[8] 571 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[9] 572 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[10] 573 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[11] 574 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[12] 575 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[13] 576 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[14] 577 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[15] 578 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[16] 579 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[17] 580 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[18] 581 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[19] 582 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[20] 583 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[21] 584 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[22] 585 CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_underflow[23] 586 CYHAL_TRIGGER_USB_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ0, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[0] 587 CYHAL_TRIGGER_USB_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ1, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[1] 588 CYHAL_TRIGGER_USB_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ2, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[2] 589 CYHAL_TRIGGER_USB_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ3, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[3] 590 CYHAL_TRIGGER_USB_DMA_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ4, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[4] 591 CYHAL_TRIGGER_USB_DMA_REQ5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ5, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[5] 592 CYHAL_TRIGGER_USB_DMA_REQ6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ6, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[6] 593 CYHAL_TRIGGER_USB_DMA_REQ7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_USB_DMA_REQ7, CYHAL_SIGNAL_TYPE_EDGE), //!< usb.dma_req[7] 594 } cyhal_trigger_source_psoc6_02_t; 595 596 /** Typedef from device family specific trigger source to generic trigger source */ 597 typedef cyhal_trigger_source_psoc6_02_t cyhal_source_t; 598 599 /** Deprecated defines for signals that can be either level or edge. */ 600 #define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 601 #define CYHAL_TRIGGER_CSD_DSI_SENSE_OUT (CYHAL_TRIGGER_CSD_DSI_SENSE_OUT_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 602 #define CYHAL_TRIGGER_CSD_TR_ADC_DONE (CYHAL_TRIGGER_CSD_TR_ADC_DONE_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 603 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT0 (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 604 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT1 (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 605 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT2 (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 606 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT3 (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 607 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT4 (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 608 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT5 (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 609 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT6 (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 610 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT7 (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 611 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT8 (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 612 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT9 (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 613 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT10 (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 614 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT11 (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 615 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT12 (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 616 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT13 (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 617 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT14 (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 618 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT15 (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 619 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT16 (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 620 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT17 (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 621 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT18 (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 622 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT19 (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 623 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT20 (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 624 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT21 (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 625 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT22 (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 626 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT23 (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 627 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT24 (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 628 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT25 (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 629 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT26 (CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 630 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT27 (CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 631 632 /** @brief Name of each output trigger. */ 633 typedef enum 634 { 635 CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[0] 636 CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[1] 637 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 2, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0] 638 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 3, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1] 639 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[2] 640 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[3] 641 CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0] 642 CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1] 643 CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2] 644 CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3] 645 CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4] 646 CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5] 647 CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6] 648 CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7] 649 CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8] 650 CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9] 651 CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10] 652 CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11] 653 CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12] 654 CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13] 655 CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14] 656 CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15] 657 CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[16] 658 CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[17] 659 CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[18] 660 CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[19] 661 CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[20] 662 CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[21] 663 CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[22] 664 CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[23] 665 CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[24] 666 CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[25] 667 CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[26] 668 CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[27] 669 CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA0 direct connect - cpuss.dw0_tr_in[28] 670 CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0] 671 CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1] 672 CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2] 673 CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3] 674 CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4] 675 CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5] 676 CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6] 677 CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7] 678 CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8] 679 CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9] 680 CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10] 681 CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11] 682 CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12] 683 CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13] 684 CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14] 685 CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15] 686 CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16] 687 CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17] 688 CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18] 689 CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19] 690 CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20] 691 CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21] 692 CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22] 693 CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23] 694 CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[24] 695 CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[25] 696 CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[26] 697 CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[27] 698 CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[28] 699 CYHAL_TRIGGER_CSD_DSI_START = 64, //!< Capsense trigger multiplexer - csd.dsi_start 700 CYHAL_TRIGGER_PASS_TR_SAR_IN = 65, //!< ADC trigger multiplexer - pass.tr_sar_in 701 CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 66, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze 702 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 67, //!< HSIOM trigger multiplexer - peri.tr_io_output[0] 703 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 68, //!< HSIOM trigger multiplexer - peri.tr_io_output[1] 704 CYHAL_TRIGGER_PROFILE_TR_START = 69, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_start 705 CYHAL_TRIGGER_PROFILE_TR_STOP = 70, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_stop 706 CYHAL_TRIGGER_TCPWM0_TR_IN0 = 71, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0] 707 CYHAL_TRIGGER_TCPWM0_TR_IN1 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1] 708 CYHAL_TRIGGER_TCPWM0_TR_IN2 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2] 709 CYHAL_TRIGGER_TCPWM0_TR_IN3 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3] 710 CYHAL_TRIGGER_TCPWM0_TR_IN4 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4] 711 CYHAL_TRIGGER_TCPWM0_TR_IN5 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5] 712 CYHAL_TRIGGER_TCPWM0_TR_IN6 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6] 713 CYHAL_TRIGGER_TCPWM0_TR_IN7 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7] 714 CYHAL_TRIGGER_TCPWM0_TR_IN8 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8] 715 CYHAL_TRIGGER_TCPWM0_TR_IN9 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9] 716 CYHAL_TRIGGER_TCPWM0_TR_IN10 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10] 717 CYHAL_TRIGGER_TCPWM0_TR_IN11 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11] 718 CYHAL_TRIGGER_TCPWM0_TR_IN12 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12] 719 CYHAL_TRIGGER_TCPWM0_TR_IN13 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13] 720 CYHAL_TRIGGER_TCPWM1_TR_IN0 = 85, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0] 721 CYHAL_TRIGGER_TCPWM1_TR_IN1 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1] 722 CYHAL_TRIGGER_TCPWM1_TR_IN2 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2] 723 CYHAL_TRIGGER_TCPWM1_TR_IN3 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3] 724 CYHAL_TRIGGER_TCPWM1_TR_IN4 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4] 725 CYHAL_TRIGGER_TCPWM1_TR_IN5 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5] 726 CYHAL_TRIGGER_TCPWM1_TR_IN6 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6] 727 CYHAL_TRIGGER_TCPWM1_TR_IN7 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7] 728 CYHAL_TRIGGER_TCPWM1_TR_IN8 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8] 729 CYHAL_TRIGGER_TCPWM1_TR_IN9 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9] 730 CYHAL_TRIGGER_TCPWM1_TR_IN10 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10] 731 CYHAL_TRIGGER_TCPWM1_TR_IN11 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11] 732 CYHAL_TRIGGER_TCPWM1_TR_IN12 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12] 733 CYHAL_TRIGGER_TCPWM1_TR_IN13 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13] 734 CYHAL_TRIGGER_USB_DMA_BURSTEND0 = 99, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0] 735 CYHAL_TRIGGER_USB_DMA_BURSTEND1 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1] 736 CYHAL_TRIGGER_USB_DMA_BURSTEND2 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2] 737 CYHAL_TRIGGER_USB_DMA_BURSTEND3 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3] 738 CYHAL_TRIGGER_USB_DMA_BURSTEND4 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4] 739 CYHAL_TRIGGER_USB_DMA_BURSTEND5 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5] 740 CYHAL_TRIGGER_USB_DMA_BURSTEND6 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6] 741 CYHAL_TRIGGER_USB_DMA_BURSTEND7 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7] 742 } cyhal_trigger_dest_psoc6_02_t; 743 744 /** Typedef from device family specific trigger dest to generic trigger dest */ 745 typedef cyhal_trigger_dest_psoc6_02_t cyhal_dest_t; 746 747 /** \cond INTERNAL */ 748 /** Table of number of inputs to each mux. */ 749 extern const uint16_t cyhal_sources_per_mux[17]; 750 751 /** Table indicating whether mux is 1to1. */ 752 extern const bool cyhal_is_mux_1to1[17]; 753 754 /** Table pointing to each mux source table. The index of each source in the table is its mux input index. */ 755 extern const _cyhal_trigger_source_psoc6_02_t* cyhal_mux_to_sources [17]; 756 757 /** Maps each cyhal_destination_t to a mux index. 758 * If bit 8 of the mux index is set, this denotes that the trigger is a 759 * one to one trigger. 760 */ 761 extern const uint8_t cyhal_dest_to_mux[107]; 762 763 /* Maps each cyhal_destination_t to a specific output in its mux */ 764 extern const uint8_t cyhal_mux_dest_index[107]; 765 /** \endcond */ 766 767 #if defined(__cplusplus) 768 } 769 #endif /* __cplusplus */ 770 /** \} group_hal_impl_triggers_psoc6_02 */ 771 #endif /* _CYHAL_TRIGGERS_PSOC6_02_H_ */ 772 773 774 /* [] END OF FILE */ 775
