1 /***************************************************************************//** 2 * \file cyhal_triggers_xmc7200.h 3 * 4 * \brief 5 * XMC7200 family HAL triggers header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TRIGGERS_XMC7200_H_ 28 #define _CYHAL_TRIGGERS_XMC7200_H_ 29 30 /** 31 * \addtogroup group_hal_impl_triggers_xmc7200 XMC7200 32 * \ingroup group_hal_impl_triggers 33 * \{ 34 * Trigger connections for xmc7200 35 */ 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** \cond INTERNAL */ 42 /** @brief Name of each input trigger. */ 43 typedef enum 44 { 45 _CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero 46 _CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ = 1, //!< audioss[0].tr_i2s_rx_req 47 _CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ = 2, //!< audioss[1].tr_i2s_rx_req 48 _CYHAL_TRIGGER_AUDIOSS2_TR_I2S_RX_REQ = 3, //!< audioss[2].tr_i2s_rx_req 49 _CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ = 4, //!< audioss[0].tr_i2s_tx_req 50 _CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ = 5, //!< audioss[1].tr_i2s_tx_req 51 _CYHAL_TRIGGER_AUDIOSS2_TR_I2S_TX_REQ = 6, //!< audioss[2].tr_i2s_tx_req 52 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = 7, //!< canfd[0].tr_dbg_dma_req[0] 53 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = 8, //!< canfd[0].tr_dbg_dma_req[1] 54 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = 9, //!< canfd[0].tr_dbg_dma_req[2] 55 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3 = 10, //!< canfd[0].tr_dbg_dma_req[3] 56 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ4 = 11, //!< canfd[0].tr_dbg_dma_req[4] 57 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = 12, //!< canfd[1].tr_dbg_dma_req[0] 58 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = 13, //!< canfd[1].tr_dbg_dma_req[1] 59 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = 14, //!< canfd[1].tr_dbg_dma_req[2] 60 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3 = 15, //!< canfd[1].tr_dbg_dma_req[3] 61 _CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ4 = 16, //!< canfd[1].tr_dbg_dma_req[4] 62 _CYHAL_TRIGGER_CANFD0_TR_FIFO00 = 17, //!< canfd[0].tr_fifo0[0] 63 _CYHAL_TRIGGER_CANFD0_TR_FIFO01 = 18, //!< canfd[0].tr_fifo0[1] 64 _CYHAL_TRIGGER_CANFD0_TR_FIFO02 = 19, //!< canfd[0].tr_fifo0[2] 65 _CYHAL_TRIGGER_CANFD0_TR_FIFO03 = 20, //!< canfd[0].tr_fifo0[3] 66 _CYHAL_TRIGGER_CANFD0_TR_FIFO04 = 21, //!< canfd[0].tr_fifo0[4] 67 _CYHAL_TRIGGER_CANFD1_TR_FIFO00 = 22, //!< canfd[1].tr_fifo0[0] 68 _CYHAL_TRIGGER_CANFD1_TR_FIFO01 = 23, //!< canfd[1].tr_fifo0[1] 69 _CYHAL_TRIGGER_CANFD1_TR_FIFO02 = 24, //!< canfd[1].tr_fifo0[2] 70 _CYHAL_TRIGGER_CANFD1_TR_FIFO03 = 25, //!< canfd[1].tr_fifo0[3] 71 _CYHAL_TRIGGER_CANFD1_TR_FIFO04 = 26, //!< canfd[1].tr_fifo0[4] 72 _CYHAL_TRIGGER_CANFD0_TR_FIFO10 = 27, //!< canfd[0].tr_fifo1[0] 73 _CYHAL_TRIGGER_CANFD0_TR_FIFO11 = 28, //!< canfd[0].tr_fifo1[1] 74 _CYHAL_TRIGGER_CANFD0_TR_FIFO12 = 29, //!< canfd[0].tr_fifo1[2] 75 _CYHAL_TRIGGER_CANFD0_TR_FIFO13 = 30, //!< canfd[0].tr_fifo1[3] 76 _CYHAL_TRIGGER_CANFD0_TR_FIFO14 = 31, //!< canfd[0].tr_fifo1[4] 77 _CYHAL_TRIGGER_CANFD1_TR_FIFO10 = 32, //!< canfd[1].tr_fifo1[0] 78 _CYHAL_TRIGGER_CANFD1_TR_FIFO11 = 33, //!< canfd[1].tr_fifo1[1] 79 _CYHAL_TRIGGER_CANFD1_TR_FIFO12 = 34, //!< canfd[1].tr_fifo1[2] 80 _CYHAL_TRIGGER_CANFD1_TR_FIFO13 = 35, //!< canfd[1].tr_fifo1[3] 81 _CYHAL_TRIGGER_CANFD1_TR_FIFO14 = 36, //!< canfd[1].tr_fifo1[4] 82 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = 37, //!< canfd[0].tr_tmp_rtp_out[0] 83 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = 38, //!< canfd[0].tr_tmp_rtp_out[1] 84 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = 39, //!< canfd[0].tr_tmp_rtp_out[2] 85 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3 = 40, //!< canfd[0].tr_tmp_rtp_out[3] 86 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT4 = 41, //!< canfd[0].tr_tmp_rtp_out[4] 87 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = 42, //!< canfd[1].tr_tmp_rtp_out[0] 88 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = 43, //!< canfd[1].tr_tmp_rtp_out[1] 89 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = 44, //!< canfd[1].tr_tmp_rtp_out[2] 90 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3 = 45, //!< canfd[1].tr_tmp_rtp_out[3] 91 _CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT4 = 46, //!< canfd[1].tr_tmp_rtp_out[4] 92 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 47, //!< cpuss.cti_tr_out[0] 93 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 48, //!< cpuss.cti_tr_out[1] 94 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 49, //!< cpuss.dmac_tr_out[0] 95 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 50, //!< cpuss.dmac_tr_out[1] 96 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = 51, //!< cpuss.dmac_tr_out[2] 97 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = 52, //!< cpuss.dmac_tr_out[3] 98 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4 = 53, //!< cpuss.dmac_tr_out[4] 99 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5 = 54, //!< cpuss.dmac_tr_out[5] 100 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6 = 55, //!< cpuss.dmac_tr_out[6] 101 _CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7 = 56, //!< cpuss.dmac_tr_out[7] 102 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 57, //!< cpuss.dw0_tr_out[0] 103 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 58, //!< cpuss.dw0_tr_out[1] 104 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 59, //!< cpuss.dw0_tr_out[2] 105 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 60, //!< cpuss.dw0_tr_out[3] 106 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 61, //!< cpuss.dw0_tr_out[4] 107 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 62, //!< cpuss.dw0_tr_out[5] 108 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 63, //!< cpuss.dw0_tr_out[6] 109 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 64, //!< cpuss.dw0_tr_out[7] 110 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 65, //!< cpuss.dw0_tr_out[8] 111 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 66, //!< cpuss.dw0_tr_out[9] 112 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 67, //!< cpuss.dw0_tr_out[10] 113 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 68, //!< cpuss.dw0_tr_out[11] 114 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 69, //!< cpuss.dw0_tr_out[12] 115 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 70, //!< cpuss.dw0_tr_out[13] 116 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 71, //!< cpuss.dw0_tr_out[14] 117 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 72, //!< cpuss.dw0_tr_out[15] 118 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 73, //!< cpuss.dw0_tr_out[16] 119 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 74, //!< cpuss.dw0_tr_out[17] 120 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 75, //!< cpuss.dw0_tr_out[18] 121 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 76, //!< cpuss.dw0_tr_out[19] 122 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 77, //!< cpuss.dw0_tr_out[20] 123 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 78, //!< cpuss.dw0_tr_out[21] 124 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 79, //!< cpuss.dw0_tr_out[22] 125 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 80, //!< cpuss.dw0_tr_out[23] 126 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 81, //!< cpuss.dw0_tr_out[24] 127 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 82, //!< cpuss.dw0_tr_out[25] 128 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 83, //!< cpuss.dw0_tr_out[26] 129 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 84, //!< cpuss.dw0_tr_out[27] 130 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 85, //!< cpuss.dw0_tr_out[28] 131 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = 86, //!< cpuss.dw0_tr_out[29] 132 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = 87, //!< cpuss.dw0_tr_out[30] 133 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = 88, //!< cpuss.dw0_tr_out[31] 134 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = 89, //!< cpuss.dw0_tr_out[32] 135 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = 90, //!< cpuss.dw0_tr_out[33] 136 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = 91, //!< cpuss.dw0_tr_out[34] 137 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = 92, //!< cpuss.dw0_tr_out[35] 138 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = 93, //!< cpuss.dw0_tr_out[36] 139 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = 94, //!< cpuss.dw0_tr_out[37] 140 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = 95, //!< cpuss.dw0_tr_out[38] 141 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = 96, //!< cpuss.dw0_tr_out[39] 142 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = 97, //!< cpuss.dw0_tr_out[40] 143 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = 98, //!< cpuss.dw0_tr_out[41] 144 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = 99, //!< cpuss.dw0_tr_out[42] 145 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = 100, //!< cpuss.dw0_tr_out[43] 146 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = 101, //!< cpuss.dw0_tr_out[44] 147 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = 102, //!< cpuss.dw0_tr_out[45] 148 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = 103, //!< cpuss.dw0_tr_out[46] 149 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = 104, //!< cpuss.dw0_tr_out[47] 150 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = 105, //!< cpuss.dw0_tr_out[48] 151 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = 106, //!< cpuss.dw0_tr_out[49] 152 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = 107, //!< cpuss.dw0_tr_out[50] 153 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = 108, //!< cpuss.dw0_tr_out[51] 154 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = 109, //!< cpuss.dw0_tr_out[52] 155 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = 110, //!< cpuss.dw0_tr_out[53] 156 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = 111, //!< cpuss.dw0_tr_out[54] 157 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = 112, //!< cpuss.dw0_tr_out[55] 158 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = 113, //!< cpuss.dw0_tr_out[56] 159 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = 114, //!< cpuss.dw0_tr_out[57] 160 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = 115, //!< cpuss.dw0_tr_out[58] 161 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = 116, //!< cpuss.dw0_tr_out[59] 162 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = 117, //!< cpuss.dw0_tr_out[60] 163 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = 118, //!< cpuss.dw0_tr_out[61] 164 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = 119, //!< cpuss.dw0_tr_out[62] 165 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = 120, //!< cpuss.dw0_tr_out[63] 166 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = 121, //!< cpuss.dw0_tr_out[64] 167 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = 122, //!< cpuss.dw0_tr_out[65] 168 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = 123, //!< cpuss.dw0_tr_out[66] 169 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = 124, //!< cpuss.dw0_tr_out[67] 170 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = 125, //!< cpuss.dw0_tr_out[68] 171 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = 126, //!< cpuss.dw0_tr_out[69] 172 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = 127, //!< cpuss.dw0_tr_out[70] 173 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = 128, //!< cpuss.dw0_tr_out[71] 174 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = 129, //!< cpuss.dw0_tr_out[72] 175 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = 130, //!< cpuss.dw0_tr_out[73] 176 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = 131, //!< cpuss.dw0_tr_out[74] 177 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = 132, //!< cpuss.dw0_tr_out[75] 178 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = 133, //!< cpuss.dw0_tr_out[76] 179 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = 134, //!< cpuss.dw0_tr_out[77] 180 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = 135, //!< cpuss.dw0_tr_out[78] 181 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = 136, //!< cpuss.dw0_tr_out[79] 182 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = 137, //!< cpuss.dw0_tr_out[80] 183 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = 138, //!< cpuss.dw0_tr_out[81] 184 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = 139, //!< cpuss.dw0_tr_out[82] 185 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = 140, //!< cpuss.dw0_tr_out[83] 186 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = 141, //!< cpuss.dw0_tr_out[84] 187 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = 142, //!< cpuss.dw0_tr_out[85] 188 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = 143, //!< cpuss.dw0_tr_out[86] 189 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = 144, //!< cpuss.dw0_tr_out[87] 190 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = 145, //!< cpuss.dw0_tr_out[88] 191 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89 = 146, //!< cpuss.dw0_tr_out[89] 192 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90 = 147, //!< cpuss.dw0_tr_out[90] 193 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91 = 148, //!< cpuss.dw0_tr_out[91] 194 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT92 = 149, //!< cpuss.dw0_tr_out[92] 195 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT93 = 150, //!< cpuss.dw0_tr_out[93] 196 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT94 = 151, //!< cpuss.dw0_tr_out[94] 197 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT95 = 152, //!< cpuss.dw0_tr_out[95] 198 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT96 = 153, //!< cpuss.dw0_tr_out[96] 199 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT97 = 154, //!< cpuss.dw0_tr_out[97] 200 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT98 = 155, //!< cpuss.dw0_tr_out[98] 201 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT99 = 156, //!< cpuss.dw0_tr_out[99] 202 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT100 = 157, //!< cpuss.dw0_tr_out[100] 203 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT101 = 158, //!< cpuss.dw0_tr_out[101] 204 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT102 = 159, //!< cpuss.dw0_tr_out[102] 205 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT103 = 160, //!< cpuss.dw0_tr_out[103] 206 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT104 = 161, //!< cpuss.dw0_tr_out[104] 207 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT105 = 162, //!< cpuss.dw0_tr_out[105] 208 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT106 = 163, //!< cpuss.dw0_tr_out[106] 209 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT107 = 164, //!< cpuss.dw0_tr_out[107] 210 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT108 = 165, //!< cpuss.dw0_tr_out[108] 211 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT109 = 166, //!< cpuss.dw0_tr_out[109] 212 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT110 = 167, //!< cpuss.dw0_tr_out[110] 213 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT111 = 168, //!< cpuss.dw0_tr_out[111] 214 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT112 = 169, //!< cpuss.dw0_tr_out[112] 215 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT113 = 170, //!< cpuss.dw0_tr_out[113] 216 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT114 = 171, //!< cpuss.dw0_tr_out[114] 217 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT115 = 172, //!< cpuss.dw0_tr_out[115] 218 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT116 = 173, //!< cpuss.dw0_tr_out[116] 219 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT117 = 174, //!< cpuss.dw0_tr_out[117] 220 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT118 = 175, //!< cpuss.dw0_tr_out[118] 221 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT119 = 176, //!< cpuss.dw0_tr_out[119] 222 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT120 = 177, //!< cpuss.dw0_tr_out[120] 223 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT121 = 178, //!< cpuss.dw0_tr_out[121] 224 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT122 = 179, //!< cpuss.dw0_tr_out[122] 225 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT123 = 180, //!< cpuss.dw0_tr_out[123] 226 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT124 = 181, //!< cpuss.dw0_tr_out[124] 227 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT125 = 182, //!< cpuss.dw0_tr_out[125] 228 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT126 = 183, //!< cpuss.dw0_tr_out[126] 229 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT127 = 184, //!< cpuss.dw0_tr_out[127] 230 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT128 = 185, //!< cpuss.dw0_tr_out[128] 231 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT129 = 186, //!< cpuss.dw0_tr_out[129] 232 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT130 = 187, //!< cpuss.dw0_tr_out[130] 233 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT131 = 188, //!< cpuss.dw0_tr_out[131] 234 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT132 = 189, //!< cpuss.dw0_tr_out[132] 235 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT133 = 190, //!< cpuss.dw0_tr_out[133] 236 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT134 = 191, //!< cpuss.dw0_tr_out[134] 237 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT135 = 192, //!< cpuss.dw0_tr_out[135] 238 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT136 = 193, //!< cpuss.dw0_tr_out[136] 239 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT137 = 194, //!< cpuss.dw0_tr_out[137] 240 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT138 = 195, //!< cpuss.dw0_tr_out[138] 241 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT139 = 196, //!< cpuss.dw0_tr_out[139] 242 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT140 = 197, //!< cpuss.dw0_tr_out[140] 243 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT141 = 198, //!< cpuss.dw0_tr_out[141] 244 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT142 = 199, //!< cpuss.dw0_tr_out[142] 245 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 200, //!< cpuss.dw1_tr_out[0] 246 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 201, //!< cpuss.dw1_tr_out[1] 247 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 202, //!< cpuss.dw1_tr_out[2] 248 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 203, //!< cpuss.dw1_tr_out[3] 249 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 204, //!< cpuss.dw1_tr_out[4] 250 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 205, //!< cpuss.dw1_tr_out[5] 251 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 206, //!< cpuss.dw1_tr_out[6] 252 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 207, //!< cpuss.dw1_tr_out[7] 253 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 208, //!< cpuss.dw1_tr_out[8] 254 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 209, //!< cpuss.dw1_tr_out[9] 255 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 210, //!< cpuss.dw1_tr_out[10] 256 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 211, //!< cpuss.dw1_tr_out[11] 257 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 212, //!< cpuss.dw1_tr_out[12] 258 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 213, //!< cpuss.dw1_tr_out[13] 259 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 214, //!< cpuss.dw1_tr_out[14] 260 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 215, //!< cpuss.dw1_tr_out[15] 261 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 216, //!< cpuss.dw1_tr_out[16] 262 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 217, //!< cpuss.dw1_tr_out[17] 263 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 218, //!< cpuss.dw1_tr_out[18] 264 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 219, //!< cpuss.dw1_tr_out[19] 265 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 220, //!< cpuss.dw1_tr_out[20] 266 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 221, //!< cpuss.dw1_tr_out[21] 267 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 222, //!< cpuss.dw1_tr_out[22] 268 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 223, //!< cpuss.dw1_tr_out[23] 269 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 224, //!< cpuss.dw1_tr_out[24] 270 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 225, //!< cpuss.dw1_tr_out[25] 271 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 226, //!< cpuss.dw1_tr_out[26] 272 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 227, //!< cpuss.dw1_tr_out[27] 273 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 228, //!< cpuss.dw1_tr_out[28] 274 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = 229, //!< cpuss.dw1_tr_out[29] 275 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = 230, //!< cpuss.dw1_tr_out[30] 276 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = 231, //!< cpuss.dw1_tr_out[31] 277 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = 232, //!< cpuss.dw1_tr_out[32] 278 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33 = 233, //!< cpuss.dw1_tr_out[33] 279 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34 = 234, //!< cpuss.dw1_tr_out[34] 280 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35 = 235, //!< cpuss.dw1_tr_out[35] 281 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36 = 236, //!< cpuss.dw1_tr_out[36] 282 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37 = 237, //!< cpuss.dw1_tr_out[37] 283 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38 = 238, //!< cpuss.dw1_tr_out[38] 284 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39 = 239, //!< cpuss.dw1_tr_out[39] 285 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40 = 240, //!< cpuss.dw1_tr_out[40] 286 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41 = 241, //!< cpuss.dw1_tr_out[41] 287 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42 = 242, //!< cpuss.dw1_tr_out[42] 288 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43 = 243, //!< cpuss.dw1_tr_out[43] 289 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT44 = 244, //!< cpuss.dw1_tr_out[44] 290 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT45 = 245, //!< cpuss.dw1_tr_out[45] 291 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT46 = 246, //!< cpuss.dw1_tr_out[46] 292 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT47 = 247, //!< cpuss.dw1_tr_out[47] 293 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT48 = 248, //!< cpuss.dw1_tr_out[48] 294 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT49 = 249, //!< cpuss.dw1_tr_out[49] 295 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT50 = 250, //!< cpuss.dw1_tr_out[50] 296 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT51 = 251, //!< cpuss.dw1_tr_out[51] 297 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT52 = 252, //!< cpuss.dw1_tr_out[52] 298 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT53 = 253, //!< cpuss.dw1_tr_out[53] 299 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT54 = 254, //!< cpuss.dw1_tr_out[54] 300 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT55 = 255, //!< cpuss.dw1_tr_out[55] 301 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT56 = 256, //!< cpuss.dw1_tr_out[56] 302 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT57 = 257, //!< cpuss.dw1_tr_out[57] 303 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT58 = 258, //!< cpuss.dw1_tr_out[58] 304 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT59 = 259, //!< cpuss.dw1_tr_out[59] 305 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT60 = 260, //!< cpuss.dw1_tr_out[60] 306 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT61 = 261, //!< cpuss.dw1_tr_out[61] 307 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT62 = 262, //!< cpuss.dw1_tr_out[62] 308 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT63 = 263, //!< cpuss.dw1_tr_out[63] 309 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT64 = 264, //!< cpuss.dw1_tr_out[64] 310 _CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 265, //!< cpuss.tr_fault[0] 311 _CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 266, //!< cpuss.tr_fault[1] 312 _CYHAL_TRIGGER_CPUSS_TR_FAULT2 = 267, //!< cpuss.tr_fault[2] 313 _CYHAL_TRIGGER_CPUSS_TR_FAULT3 = 268, //!< cpuss.tr_fault[3] 314 _CYHAL_TRIGGER_EVTGEN0_TR_OUT0 = 269, //!< evtgen[0].tr_out[0] 315 _CYHAL_TRIGGER_EVTGEN0_TR_OUT1 = 270, //!< evtgen[0].tr_out[1] 316 _CYHAL_TRIGGER_EVTGEN0_TR_OUT2 = 271, //!< evtgen[0].tr_out[2] 317 _CYHAL_TRIGGER_EVTGEN0_TR_OUT3 = 272, //!< evtgen[0].tr_out[3] 318 _CYHAL_TRIGGER_EVTGEN0_TR_OUT4 = 273, //!< evtgen[0].tr_out[4] 319 _CYHAL_TRIGGER_EVTGEN0_TR_OUT5 = 274, //!< evtgen[0].tr_out[5] 320 _CYHAL_TRIGGER_EVTGEN0_TR_OUT6 = 275, //!< evtgen[0].tr_out[6] 321 _CYHAL_TRIGGER_EVTGEN0_TR_OUT7 = 276, //!< evtgen[0].tr_out[7] 322 _CYHAL_TRIGGER_EVTGEN0_TR_OUT8 = 277, //!< evtgen[0].tr_out[8] 323 _CYHAL_TRIGGER_EVTGEN0_TR_OUT9 = 278, //!< evtgen[0].tr_out[9] 324 _CYHAL_TRIGGER_EVTGEN0_TR_OUT10 = 279, //!< evtgen[0].tr_out[10] 325 _CYHAL_TRIGGER_EVTGEN0_TR_OUT11 = 280, //!< evtgen[0].tr_out[11] 326 _CYHAL_TRIGGER_EVTGEN0_TR_OUT12 = 281, //!< evtgen[0].tr_out[12] 327 _CYHAL_TRIGGER_EVTGEN0_TR_OUT13 = 282, //!< evtgen[0].tr_out[13] 328 _CYHAL_TRIGGER_EVTGEN0_TR_OUT14 = 283, //!< evtgen[0].tr_out[14] 329 _CYHAL_TRIGGER_EVTGEN0_TR_OUT15 = 284, //!< evtgen[0].tr_out[15] 330 _CYHAL_TRIGGER_FLEXRAY0_TR_IBF_OUT = 285, //!< flexray[0].tr_ibf_out 331 _CYHAL_TRIGGER_FLEXRAY0_TR_OBF_OUT = 286, //!< flexray[0].tr_obf_out 332 _CYHAL_TRIGGER_FLEXRAY0_TR_TINT0_OUT = 287, //!< flexray[0].tr_tint0_out 333 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 = 288, //!< pass[0].tr_sar_ch_done[0] 334 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 = 289, //!< pass[0].tr_sar_ch_done[1] 335 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 = 290, //!< pass[0].tr_sar_ch_done[2] 336 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 = 291, //!< pass[0].tr_sar_ch_done[3] 337 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 = 292, //!< pass[0].tr_sar_ch_done[4] 338 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 = 293, //!< pass[0].tr_sar_ch_done[5] 339 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 = 294, //!< pass[0].tr_sar_ch_done[6] 340 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 = 295, //!< pass[0].tr_sar_ch_done[7] 341 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 = 296, //!< pass[0].tr_sar_ch_done[8] 342 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 = 297, //!< pass[0].tr_sar_ch_done[9] 343 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 = 298, //!< pass[0].tr_sar_ch_done[10] 344 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 = 299, //!< pass[0].tr_sar_ch_done[11] 345 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 = 300, //!< pass[0].tr_sar_ch_done[12] 346 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 = 301, //!< pass[0].tr_sar_ch_done[13] 347 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 = 302, //!< pass[0].tr_sar_ch_done[14] 348 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 = 303, //!< pass[0].tr_sar_ch_done[15] 349 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 = 304, //!< pass[0].tr_sar_ch_done[16] 350 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 = 305, //!< pass[0].tr_sar_ch_done[17] 351 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 = 306, //!< pass[0].tr_sar_ch_done[18] 352 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 = 307, //!< pass[0].tr_sar_ch_done[19] 353 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 = 308, //!< pass[0].tr_sar_ch_done[20] 354 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 = 309, //!< pass[0].tr_sar_ch_done[21] 355 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 = 310, //!< pass[0].tr_sar_ch_done[22] 356 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 = 311, //!< pass[0].tr_sar_ch_done[23] 357 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24 = 312, //!< pass[0].tr_sar_ch_done[24] 358 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25 = 313, //!< pass[0].tr_sar_ch_done[25] 359 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26 = 314, //!< pass[0].tr_sar_ch_done[26] 360 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27 = 315, //!< pass[0].tr_sar_ch_done[27] 361 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28 = 316, //!< pass[0].tr_sar_ch_done[28] 362 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29 = 317, //!< pass[0].tr_sar_ch_done[29] 363 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30 = 318, //!< pass[0].tr_sar_ch_done[30] 364 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31 = 319, //!< pass[0].tr_sar_ch_done[31] 365 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 = 320, //!< pass[0].tr_sar_ch_done[32] 366 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 = 321, //!< pass[0].tr_sar_ch_done[33] 367 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 = 322, //!< pass[0].tr_sar_ch_done[34] 368 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 = 323, //!< pass[0].tr_sar_ch_done[35] 369 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 = 324, //!< pass[0].tr_sar_ch_done[36] 370 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 = 325, //!< pass[0].tr_sar_ch_done[37] 371 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 = 326, //!< pass[0].tr_sar_ch_done[38] 372 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 = 327, //!< pass[0].tr_sar_ch_done[39] 373 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 = 328, //!< pass[0].tr_sar_ch_done[40] 374 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 = 329, //!< pass[0].tr_sar_ch_done[41] 375 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 = 330, //!< pass[0].tr_sar_ch_done[42] 376 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 = 331, //!< pass[0].tr_sar_ch_done[43] 377 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 = 332, //!< pass[0].tr_sar_ch_done[44] 378 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 = 333, //!< pass[0].tr_sar_ch_done[45] 379 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 = 334, //!< pass[0].tr_sar_ch_done[46] 380 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 = 335, //!< pass[0].tr_sar_ch_done[47] 381 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 = 336, //!< pass[0].tr_sar_ch_done[48] 382 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 = 337, //!< pass[0].tr_sar_ch_done[49] 383 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 = 338, //!< pass[0].tr_sar_ch_done[50] 384 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 = 339, //!< pass[0].tr_sar_ch_done[51] 385 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 = 340, //!< pass[0].tr_sar_ch_done[52] 386 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 = 341, //!< pass[0].tr_sar_ch_done[53] 387 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 = 342, //!< pass[0].tr_sar_ch_done[54] 388 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 = 343, //!< pass[0].tr_sar_ch_done[55] 389 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 = 344, //!< pass[0].tr_sar_ch_done[56] 390 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 = 345, //!< pass[0].tr_sar_ch_done[57] 391 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 = 346, //!< pass[0].tr_sar_ch_done[58] 392 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 = 347, //!< pass[0].tr_sar_ch_done[59] 393 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 = 348, //!< pass[0].tr_sar_ch_done[60] 394 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 = 349, //!< pass[0].tr_sar_ch_done[61] 395 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 = 350, //!< pass[0].tr_sar_ch_done[62] 396 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 = 351, //!< pass[0].tr_sar_ch_done[63] 397 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 = 352, //!< pass[0].tr_sar_ch_done[64] 398 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 = 353, //!< pass[0].tr_sar_ch_done[65] 399 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 = 354, //!< pass[0].tr_sar_ch_done[66] 400 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 = 355, //!< pass[0].tr_sar_ch_done[67] 401 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 = 356, //!< pass[0].tr_sar_ch_done[68] 402 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 = 357, //!< pass[0].tr_sar_ch_done[69] 403 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 = 358, //!< pass[0].tr_sar_ch_done[70] 404 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 = 359, //!< pass[0].tr_sar_ch_done[71] 405 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE72 = 360, //!< pass[0].tr_sar_ch_done[72] 406 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE73 = 361, //!< pass[0].tr_sar_ch_done[73] 407 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE74 = 362, //!< pass[0].tr_sar_ch_done[74] 408 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE75 = 363, //!< pass[0].tr_sar_ch_done[75] 409 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE76 = 364, //!< pass[0].tr_sar_ch_done[76] 410 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE77 = 365, //!< pass[0].tr_sar_ch_done[77] 411 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE78 = 366, //!< pass[0].tr_sar_ch_done[78] 412 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE79 = 367, //!< pass[0].tr_sar_ch_done[79] 413 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE80 = 368, //!< pass[0].tr_sar_ch_done[80] 414 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE81 = 369, //!< pass[0].tr_sar_ch_done[81] 415 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE82 = 370, //!< pass[0].tr_sar_ch_done[82] 416 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE83 = 371, //!< pass[0].tr_sar_ch_done[83] 417 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE84 = 372, //!< pass[0].tr_sar_ch_done[84] 418 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE85 = 373, //!< pass[0].tr_sar_ch_done[85] 419 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE86 = 374, //!< pass[0].tr_sar_ch_done[86] 420 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE87 = 375, //!< pass[0].tr_sar_ch_done[87] 421 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE88 = 376, //!< pass[0].tr_sar_ch_done[88] 422 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE89 = 377, //!< pass[0].tr_sar_ch_done[89] 423 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE90 = 378, //!< pass[0].tr_sar_ch_done[90] 424 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE91 = 379, //!< pass[0].tr_sar_ch_done[91] 425 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE92 = 380, //!< pass[0].tr_sar_ch_done[92] 426 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE93 = 381, //!< pass[0].tr_sar_ch_done[93] 427 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE94 = 382, //!< pass[0].tr_sar_ch_done[94] 428 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE95 = 383, //!< pass[0].tr_sar_ch_done[95] 429 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = 384, //!< pass[0].tr_sar_ch_rangevio[0] 430 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = 385, //!< pass[0].tr_sar_ch_rangevio[1] 431 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = 386, //!< pass[0].tr_sar_ch_rangevio[2] 432 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = 387, //!< pass[0].tr_sar_ch_rangevio[3] 433 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = 388, //!< pass[0].tr_sar_ch_rangevio[4] 434 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = 389, //!< pass[0].tr_sar_ch_rangevio[5] 435 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = 390, //!< pass[0].tr_sar_ch_rangevio[6] 436 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = 391, //!< pass[0].tr_sar_ch_rangevio[7] 437 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = 392, //!< pass[0].tr_sar_ch_rangevio[8] 438 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = 393, //!< pass[0].tr_sar_ch_rangevio[9] 439 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = 394, //!< pass[0].tr_sar_ch_rangevio[10] 440 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = 395, //!< pass[0].tr_sar_ch_rangevio[11] 441 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = 396, //!< pass[0].tr_sar_ch_rangevio[12] 442 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = 397, //!< pass[0].tr_sar_ch_rangevio[13] 443 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = 398, //!< pass[0].tr_sar_ch_rangevio[14] 444 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = 399, //!< pass[0].tr_sar_ch_rangevio[15] 445 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = 400, //!< pass[0].tr_sar_ch_rangevio[16] 446 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = 401, //!< pass[0].tr_sar_ch_rangevio[17] 447 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = 402, //!< pass[0].tr_sar_ch_rangevio[18] 448 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = 403, //!< pass[0].tr_sar_ch_rangevio[19] 449 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = 404, //!< pass[0].tr_sar_ch_rangevio[20] 450 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = 405, //!< pass[0].tr_sar_ch_rangevio[21] 451 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = 406, //!< pass[0].tr_sar_ch_rangevio[22] 452 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = 407, //!< pass[0].tr_sar_ch_rangevio[23] 453 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO24 = 408, //!< pass[0].tr_sar_ch_rangevio[24] 454 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO25 = 409, //!< pass[0].tr_sar_ch_rangevio[25] 455 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO26 = 410, //!< pass[0].tr_sar_ch_rangevio[26] 456 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO27 = 411, //!< pass[0].tr_sar_ch_rangevio[27] 457 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO28 = 412, //!< pass[0].tr_sar_ch_rangevio[28] 458 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO29 = 413, //!< pass[0].tr_sar_ch_rangevio[29] 459 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO30 = 414, //!< pass[0].tr_sar_ch_rangevio[30] 460 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO31 = 415, //!< pass[0].tr_sar_ch_rangevio[31] 461 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = 416, //!< pass[0].tr_sar_ch_rangevio[32] 462 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = 417, //!< pass[0].tr_sar_ch_rangevio[33] 463 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = 418, //!< pass[0].tr_sar_ch_rangevio[34] 464 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = 419, //!< pass[0].tr_sar_ch_rangevio[35] 465 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = 420, //!< pass[0].tr_sar_ch_rangevio[36] 466 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = 421, //!< pass[0].tr_sar_ch_rangevio[37] 467 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = 422, //!< pass[0].tr_sar_ch_rangevio[38] 468 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = 423, //!< pass[0].tr_sar_ch_rangevio[39] 469 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = 424, //!< pass[0].tr_sar_ch_rangevio[40] 470 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = 425, //!< pass[0].tr_sar_ch_rangevio[41] 471 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = 426, //!< pass[0].tr_sar_ch_rangevio[42] 472 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = 427, //!< pass[0].tr_sar_ch_rangevio[43] 473 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = 428, //!< pass[0].tr_sar_ch_rangevio[44] 474 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = 429, //!< pass[0].tr_sar_ch_rangevio[45] 475 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = 430, //!< pass[0].tr_sar_ch_rangevio[46] 476 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = 431, //!< pass[0].tr_sar_ch_rangevio[47] 477 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = 432, //!< pass[0].tr_sar_ch_rangevio[48] 478 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = 433, //!< pass[0].tr_sar_ch_rangevio[49] 479 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = 434, //!< pass[0].tr_sar_ch_rangevio[50] 480 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = 435, //!< pass[0].tr_sar_ch_rangevio[51] 481 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = 436, //!< pass[0].tr_sar_ch_rangevio[52] 482 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = 437, //!< pass[0].tr_sar_ch_rangevio[53] 483 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = 438, //!< pass[0].tr_sar_ch_rangevio[54] 484 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = 439, //!< pass[0].tr_sar_ch_rangevio[55] 485 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = 440, //!< pass[0].tr_sar_ch_rangevio[56] 486 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = 441, //!< pass[0].tr_sar_ch_rangevio[57] 487 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = 442, //!< pass[0].tr_sar_ch_rangevio[58] 488 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = 443, //!< pass[0].tr_sar_ch_rangevio[59] 489 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = 444, //!< pass[0].tr_sar_ch_rangevio[60] 490 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = 445, //!< pass[0].tr_sar_ch_rangevio[61] 491 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = 446, //!< pass[0].tr_sar_ch_rangevio[62] 492 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = 447, //!< pass[0].tr_sar_ch_rangevio[63] 493 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = 448, //!< pass[0].tr_sar_ch_rangevio[64] 494 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = 449, //!< pass[0].tr_sar_ch_rangevio[65] 495 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = 450, //!< pass[0].tr_sar_ch_rangevio[66] 496 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = 451, //!< pass[0].tr_sar_ch_rangevio[67] 497 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = 452, //!< pass[0].tr_sar_ch_rangevio[68] 498 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = 453, //!< pass[0].tr_sar_ch_rangevio[69] 499 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = 454, //!< pass[0].tr_sar_ch_rangevio[70] 500 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = 455, //!< pass[0].tr_sar_ch_rangevio[71] 501 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO72 = 456, //!< pass[0].tr_sar_ch_rangevio[72] 502 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO73 = 457, //!< pass[0].tr_sar_ch_rangevio[73] 503 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO74 = 458, //!< pass[0].tr_sar_ch_rangevio[74] 504 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO75 = 459, //!< pass[0].tr_sar_ch_rangevio[75] 505 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO76 = 460, //!< pass[0].tr_sar_ch_rangevio[76] 506 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO77 = 461, //!< pass[0].tr_sar_ch_rangevio[77] 507 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO78 = 462, //!< pass[0].tr_sar_ch_rangevio[78] 508 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO79 = 463, //!< pass[0].tr_sar_ch_rangevio[79] 509 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO80 = 464, //!< pass[0].tr_sar_ch_rangevio[80] 510 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO81 = 465, //!< pass[0].tr_sar_ch_rangevio[81] 511 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO82 = 466, //!< pass[0].tr_sar_ch_rangevio[82] 512 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO83 = 467, //!< pass[0].tr_sar_ch_rangevio[83] 513 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO84 = 468, //!< pass[0].tr_sar_ch_rangevio[84] 514 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO85 = 469, //!< pass[0].tr_sar_ch_rangevio[85] 515 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO86 = 470, //!< pass[0].tr_sar_ch_rangevio[86] 516 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO87 = 471, //!< pass[0].tr_sar_ch_rangevio[87] 517 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO88 = 472, //!< pass[0].tr_sar_ch_rangevio[88] 518 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO89 = 473, //!< pass[0].tr_sar_ch_rangevio[89] 519 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO90 = 474, //!< pass[0].tr_sar_ch_rangevio[90] 520 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO91 = 475, //!< pass[0].tr_sar_ch_rangevio[91] 521 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO92 = 476, //!< pass[0].tr_sar_ch_rangevio[92] 522 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO93 = 477, //!< pass[0].tr_sar_ch_rangevio[93] 523 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO94 = 478, //!< pass[0].tr_sar_ch_rangevio[94] 524 _CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO95 = 479, //!< pass[0].tr_sar_ch_rangevio[95] 525 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 = 480, //!< pass[0].tr_sar_gen_out[0] 526 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 = 481, //!< pass[0].tr_sar_gen_out[1] 527 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 = 482, //!< pass[0].tr_sar_gen_out[2] 528 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 = 483, //!< pass[0].tr_sar_gen_out[3] 529 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 = 484, //!< pass[0].tr_sar_gen_out[4] 530 _CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 = 485, //!< pass[0].tr_sar_gen_out[5] 531 _CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 486, //!< peri.tr_io_input[0] 532 _CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 487, //!< peri.tr_io_input[1] 533 _CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 488, //!< peri.tr_io_input[2] 534 _CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 489, //!< peri.tr_io_input[3] 535 _CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 490, //!< peri.tr_io_input[4] 536 _CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 491, //!< peri.tr_io_input[5] 537 _CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 492, //!< peri.tr_io_input[6] 538 _CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 493, //!< peri.tr_io_input[7] 539 _CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 494, //!< peri.tr_io_input[8] 540 _CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 495, //!< peri.tr_io_input[9] 541 _CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 496, //!< peri.tr_io_input[10] 542 _CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 497, //!< peri.tr_io_input[11] 543 _CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 498, //!< peri.tr_io_input[12] 544 _CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 499, //!< peri.tr_io_input[13] 545 _CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 500, //!< peri.tr_io_input[14] 546 _CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 501, //!< peri.tr_io_input[15] 547 _CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 502, //!< peri.tr_io_input[16] 548 _CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 503, //!< peri.tr_io_input[17] 549 _CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 504, //!< peri.tr_io_input[18] 550 _CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 505, //!< peri.tr_io_input[19] 551 _CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 506, //!< peri.tr_io_input[20] 552 _CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 507, //!< peri.tr_io_input[21] 553 _CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 508, //!< peri.tr_io_input[22] 554 _CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 509, //!< peri.tr_io_input[23] 555 _CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 510, //!< peri.tr_io_input[24] 556 _CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 511, //!< peri.tr_io_input[25] 557 _CYHAL_TRIGGER_PERI_TR_IO_INPUT26 = 512, //!< peri.tr_io_input[26] 558 _CYHAL_TRIGGER_PERI_TR_IO_INPUT27 = 513, //!< peri.tr_io_input[27] 559 _CYHAL_TRIGGER_PERI_TR_IO_INPUT28 = 514, //!< peri.tr_io_input[28] 560 _CYHAL_TRIGGER_PERI_TR_IO_INPUT29 = 515, //!< peri.tr_io_input[29] 561 _CYHAL_TRIGGER_PERI_TR_IO_INPUT30 = 516, //!< peri.tr_io_input[30] 562 _CYHAL_TRIGGER_PERI_TR_IO_INPUT31 = 517, //!< peri.tr_io_input[31] 563 _CYHAL_TRIGGER_PERI_TR_IO_INPUT32 = 518, //!< peri.tr_io_input[32] 564 _CYHAL_TRIGGER_PERI_TR_IO_INPUT33 = 519, //!< peri.tr_io_input[33] 565 _CYHAL_TRIGGER_PERI_TR_IO_INPUT34 = 520, //!< peri.tr_io_input[34] 566 _CYHAL_TRIGGER_PERI_TR_IO_INPUT35 = 521, //!< peri.tr_io_input[35] 567 _CYHAL_TRIGGER_PERI_TR_IO_INPUT36 = 522, //!< peri.tr_io_input[36] 568 _CYHAL_TRIGGER_PERI_TR_IO_INPUT37 = 523, //!< peri.tr_io_input[37] 569 _CYHAL_TRIGGER_PERI_TR_IO_INPUT38 = 524, //!< peri.tr_io_input[38] 570 _CYHAL_TRIGGER_PERI_TR_IO_INPUT39 = 525, //!< peri.tr_io_input[39] 571 _CYHAL_TRIGGER_PERI_TR_IO_INPUT40 = 526, //!< peri.tr_io_input[40] 572 _CYHAL_TRIGGER_PERI_TR_IO_INPUT41 = 527, //!< peri.tr_io_input[41] 573 _CYHAL_TRIGGER_PERI_TR_IO_INPUT42 = 528, //!< peri.tr_io_input[42] 574 _CYHAL_TRIGGER_PERI_TR_IO_INPUT43 = 529, //!< peri.tr_io_input[43] 575 _CYHAL_TRIGGER_PERI_TR_IO_INPUT44 = 530, //!< peri.tr_io_input[44] 576 _CYHAL_TRIGGER_PERI_TR_IO_INPUT45 = 531, //!< peri.tr_io_input[45] 577 _CYHAL_TRIGGER_PERI_TR_IO_INPUT46 = 532, //!< peri.tr_io_input[46] 578 _CYHAL_TRIGGER_PERI_TR_IO_INPUT47 = 533, //!< peri.tr_io_input[47] 579 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 534, //!< scb[0].tr_i2c_scl_filtered 580 _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 535, //!< scb[1].tr_i2c_scl_filtered 581 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 536, //!< scb[2].tr_i2c_scl_filtered 582 _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 537, //!< scb[3].tr_i2c_scl_filtered 583 _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 538, //!< scb[4].tr_i2c_scl_filtered 584 _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 539, //!< scb[5].tr_i2c_scl_filtered 585 _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 540, //!< scb[6].tr_i2c_scl_filtered 586 _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 541, //!< scb[7].tr_i2c_scl_filtered 587 _CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = 542, //!< scb[8].tr_i2c_scl_filtered 588 _CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = 543, //!< scb[9].tr_i2c_scl_filtered 589 _CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = 544, //!< scb[10].tr_i2c_scl_filtered 590 _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 545, //!< scb[0].tr_rx_req 591 _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 546, //!< scb[1].tr_rx_req 592 _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 547, //!< scb[2].tr_rx_req 593 _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 548, //!< scb[3].tr_rx_req 594 _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 549, //!< scb[4].tr_rx_req 595 _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 550, //!< scb[5].tr_rx_req 596 _CYHAL_TRIGGER_SCB6_TR_RX_REQ = 551, //!< scb[6].tr_rx_req 597 _CYHAL_TRIGGER_SCB7_TR_RX_REQ = 552, //!< scb[7].tr_rx_req 598 _CYHAL_TRIGGER_SCB8_TR_RX_REQ = 553, //!< scb[8].tr_rx_req 599 _CYHAL_TRIGGER_SCB9_TR_RX_REQ = 554, //!< scb[9].tr_rx_req 600 _CYHAL_TRIGGER_SCB10_TR_RX_REQ = 555, //!< scb[10].tr_rx_req 601 _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 556, //!< scb[0].tr_tx_req 602 _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 557, //!< scb[1].tr_tx_req 603 _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 558, //!< scb[2].tr_tx_req 604 _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 559, //!< scb[3].tr_tx_req 605 _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 560, //!< scb[4].tr_tx_req 606 _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 561, //!< scb[5].tr_tx_req 607 _CYHAL_TRIGGER_SCB6_TR_TX_REQ = 562, //!< scb[6].tr_tx_req 608 _CYHAL_TRIGGER_SCB7_TR_TX_REQ = 563, //!< scb[7].tr_tx_req 609 _CYHAL_TRIGGER_SCB8_TR_TX_REQ = 564, //!< scb[8].tr_tx_req 610 _CYHAL_TRIGGER_SCB9_TR_TX_REQ = 565, //!< scb[9].tr_tx_req 611 _CYHAL_TRIGGER_SCB10_TR_TX_REQ = 566, //!< scb[10].tr_tx_req 612 _CYHAL_TRIGGER_SMIF0_TR_RX_REQ = 567, //!< smif[0].tr_rx_req 613 _CYHAL_TRIGGER_SMIF0_TR_TX_REQ = 568, //!< smif[0].tr_tx_req 614 _CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 569, //!< tcpwm[0].tr_out0[0] 615 _CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 570, //!< tcpwm[0].tr_out0[1] 616 _CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 571, //!< tcpwm[0].tr_out0[2] 617 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 572, //!< tcpwm[0].tr_out0[256] 618 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 573, //!< tcpwm[0].tr_out0[257] 619 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 574, //!< tcpwm[0].tr_out0[258] 620 _CYHAL_TRIGGER_TCPWM0_TR_OUT0512 = 575, //!< tcpwm[0].tr_out0[512] 621 _CYHAL_TRIGGER_TCPWM0_TR_OUT0513 = 576, //!< tcpwm[0].tr_out0[513] 622 _CYHAL_TRIGGER_TCPWM0_TR_OUT0514 = 577, //!< tcpwm[0].tr_out0[514] 623 _CYHAL_TRIGGER_TCPWM1_TR_OUT00 = 578, //!< tcpwm[1].tr_out0[0] 624 _CYHAL_TRIGGER_TCPWM1_TR_OUT01 = 579, //!< tcpwm[1].tr_out0[1] 625 _CYHAL_TRIGGER_TCPWM1_TR_OUT02 = 580, //!< tcpwm[1].tr_out0[2] 626 _CYHAL_TRIGGER_TCPWM1_TR_OUT03 = 581, //!< tcpwm[1].tr_out0[3] 627 _CYHAL_TRIGGER_TCPWM1_TR_OUT04 = 582, //!< tcpwm[1].tr_out0[4] 628 _CYHAL_TRIGGER_TCPWM1_TR_OUT05 = 583, //!< tcpwm[1].tr_out0[5] 629 _CYHAL_TRIGGER_TCPWM1_TR_OUT06 = 584, //!< tcpwm[1].tr_out0[6] 630 _CYHAL_TRIGGER_TCPWM1_TR_OUT07 = 585, //!< tcpwm[1].tr_out0[7] 631 _CYHAL_TRIGGER_TCPWM1_TR_OUT08 = 586, //!< tcpwm[1].tr_out0[8] 632 _CYHAL_TRIGGER_TCPWM1_TR_OUT09 = 587, //!< tcpwm[1].tr_out0[9] 633 _CYHAL_TRIGGER_TCPWM1_TR_OUT010 = 588, //!< tcpwm[1].tr_out0[10] 634 _CYHAL_TRIGGER_TCPWM1_TR_OUT011 = 589, //!< tcpwm[1].tr_out0[11] 635 _CYHAL_TRIGGER_TCPWM1_TR_OUT012 = 590, //!< tcpwm[1].tr_out0[12] 636 _CYHAL_TRIGGER_TCPWM1_TR_OUT013 = 591, //!< tcpwm[1].tr_out0[13] 637 _CYHAL_TRIGGER_TCPWM1_TR_OUT014 = 592, //!< tcpwm[1].tr_out0[14] 638 _CYHAL_TRIGGER_TCPWM1_TR_OUT015 = 593, //!< tcpwm[1].tr_out0[15] 639 _CYHAL_TRIGGER_TCPWM1_TR_OUT016 = 594, //!< tcpwm[1].tr_out0[16] 640 _CYHAL_TRIGGER_TCPWM1_TR_OUT017 = 595, //!< tcpwm[1].tr_out0[17] 641 _CYHAL_TRIGGER_TCPWM1_TR_OUT018 = 596, //!< tcpwm[1].tr_out0[18] 642 _CYHAL_TRIGGER_TCPWM1_TR_OUT019 = 597, //!< tcpwm[1].tr_out0[19] 643 _CYHAL_TRIGGER_TCPWM1_TR_OUT020 = 598, //!< tcpwm[1].tr_out0[20] 644 _CYHAL_TRIGGER_TCPWM1_TR_OUT021 = 599, //!< tcpwm[1].tr_out0[21] 645 _CYHAL_TRIGGER_TCPWM1_TR_OUT022 = 600, //!< tcpwm[1].tr_out0[22] 646 _CYHAL_TRIGGER_TCPWM1_TR_OUT023 = 601, //!< tcpwm[1].tr_out0[23] 647 _CYHAL_TRIGGER_TCPWM1_TR_OUT024 = 602, //!< tcpwm[1].tr_out0[24] 648 _CYHAL_TRIGGER_TCPWM1_TR_OUT025 = 603, //!< tcpwm[1].tr_out0[25] 649 _CYHAL_TRIGGER_TCPWM1_TR_OUT026 = 604, //!< tcpwm[1].tr_out0[26] 650 _CYHAL_TRIGGER_TCPWM1_TR_OUT027 = 605, //!< tcpwm[1].tr_out0[27] 651 _CYHAL_TRIGGER_TCPWM1_TR_OUT028 = 606, //!< tcpwm[1].tr_out0[28] 652 _CYHAL_TRIGGER_TCPWM1_TR_OUT029 = 607, //!< tcpwm[1].tr_out0[29] 653 _CYHAL_TRIGGER_TCPWM1_TR_OUT030 = 608, //!< tcpwm[1].tr_out0[30] 654 _CYHAL_TRIGGER_TCPWM1_TR_OUT031 = 609, //!< tcpwm[1].tr_out0[31] 655 _CYHAL_TRIGGER_TCPWM1_TR_OUT032 = 610, //!< tcpwm[1].tr_out0[32] 656 _CYHAL_TRIGGER_TCPWM1_TR_OUT033 = 611, //!< tcpwm[1].tr_out0[33] 657 _CYHAL_TRIGGER_TCPWM1_TR_OUT034 = 612, //!< tcpwm[1].tr_out0[34] 658 _CYHAL_TRIGGER_TCPWM1_TR_OUT035 = 613, //!< tcpwm[1].tr_out0[35] 659 _CYHAL_TRIGGER_TCPWM1_TR_OUT036 = 614, //!< tcpwm[1].tr_out0[36] 660 _CYHAL_TRIGGER_TCPWM1_TR_OUT037 = 615, //!< tcpwm[1].tr_out0[37] 661 _CYHAL_TRIGGER_TCPWM1_TR_OUT038 = 616, //!< tcpwm[1].tr_out0[38] 662 _CYHAL_TRIGGER_TCPWM1_TR_OUT039 = 617, //!< tcpwm[1].tr_out0[39] 663 _CYHAL_TRIGGER_TCPWM1_TR_OUT040 = 618, //!< tcpwm[1].tr_out0[40] 664 _CYHAL_TRIGGER_TCPWM1_TR_OUT041 = 619, //!< tcpwm[1].tr_out0[41] 665 _CYHAL_TRIGGER_TCPWM1_TR_OUT042 = 620, //!< tcpwm[1].tr_out0[42] 666 _CYHAL_TRIGGER_TCPWM1_TR_OUT043 = 621, //!< tcpwm[1].tr_out0[43] 667 _CYHAL_TRIGGER_TCPWM1_TR_OUT044 = 622, //!< tcpwm[1].tr_out0[44] 668 _CYHAL_TRIGGER_TCPWM1_TR_OUT045 = 623, //!< tcpwm[1].tr_out0[45] 669 _CYHAL_TRIGGER_TCPWM1_TR_OUT046 = 624, //!< tcpwm[1].tr_out0[46] 670 _CYHAL_TRIGGER_TCPWM1_TR_OUT047 = 625, //!< tcpwm[1].tr_out0[47] 671 _CYHAL_TRIGGER_TCPWM1_TR_OUT048 = 626, //!< tcpwm[1].tr_out0[48] 672 _CYHAL_TRIGGER_TCPWM1_TR_OUT049 = 627, //!< tcpwm[1].tr_out0[49] 673 _CYHAL_TRIGGER_TCPWM1_TR_OUT050 = 628, //!< tcpwm[1].tr_out0[50] 674 _CYHAL_TRIGGER_TCPWM1_TR_OUT051 = 629, //!< tcpwm[1].tr_out0[51] 675 _CYHAL_TRIGGER_TCPWM1_TR_OUT052 = 630, //!< tcpwm[1].tr_out0[52] 676 _CYHAL_TRIGGER_TCPWM1_TR_OUT053 = 631, //!< tcpwm[1].tr_out0[53] 677 _CYHAL_TRIGGER_TCPWM1_TR_OUT054 = 632, //!< tcpwm[1].tr_out0[54] 678 _CYHAL_TRIGGER_TCPWM1_TR_OUT055 = 633, //!< tcpwm[1].tr_out0[55] 679 _CYHAL_TRIGGER_TCPWM1_TR_OUT056 = 634, //!< tcpwm[1].tr_out0[56] 680 _CYHAL_TRIGGER_TCPWM1_TR_OUT057 = 635, //!< tcpwm[1].tr_out0[57] 681 _CYHAL_TRIGGER_TCPWM1_TR_OUT058 = 636, //!< tcpwm[1].tr_out0[58] 682 _CYHAL_TRIGGER_TCPWM1_TR_OUT059 = 637, //!< tcpwm[1].tr_out0[59] 683 _CYHAL_TRIGGER_TCPWM1_TR_OUT060 = 638, //!< tcpwm[1].tr_out0[60] 684 _CYHAL_TRIGGER_TCPWM1_TR_OUT061 = 639, //!< tcpwm[1].tr_out0[61] 685 _CYHAL_TRIGGER_TCPWM1_TR_OUT062 = 640, //!< tcpwm[1].tr_out0[62] 686 _CYHAL_TRIGGER_TCPWM1_TR_OUT063 = 641, //!< tcpwm[1].tr_out0[63] 687 _CYHAL_TRIGGER_TCPWM1_TR_OUT064 = 642, //!< tcpwm[1].tr_out0[64] 688 _CYHAL_TRIGGER_TCPWM1_TR_OUT065 = 643, //!< tcpwm[1].tr_out0[65] 689 _CYHAL_TRIGGER_TCPWM1_TR_OUT066 = 644, //!< tcpwm[1].tr_out0[66] 690 _CYHAL_TRIGGER_TCPWM1_TR_OUT067 = 645, //!< tcpwm[1].tr_out0[67] 691 _CYHAL_TRIGGER_TCPWM1_TR_OUT068 = 646, //!< tcpwm[1].tr_out0[68] 692 _CYHAL_TRIGGER_TCPWM1_TR_OUT069 = 647, //!< tcpwm[1].tr_out0[69] 693 _CYHAL_TRIGGER_TCPWM1_TR_OUT070 = 648, //!< tcpwm[1].tr_out0[70] 694 _CYHAL_TRIGGER_TCPWM1_TR_OUT071 = 649, //!< tcpwm[1].tr_out0[71] 695 _CYHAL_TRIGGER_TCPWM1_TR_OUT072 = 650, //!< tcpwm[1].tr_out0[72] 696 _CYHAL_TRIGGER_TCPWM1_TR_OUT073 = 651, //!< tcpwm[1].tr_out0[73] 697 _CYHAL_TRIGGER_TCPWM1_TR_OUT074 = 652, //!< tcpwm[1].tr_out0[74] 698 _CYHAL_TRIGGER_TCPWM1_TR_OUT075 = 653, //!< tcpwm[1].tr_out0[75] 699 _CYHAL_TRIGGER_TCPWM1_TR_OUT076 = 654, //!< tcpwm[1].tr_out0[76] 700 _CYHAL_TRIGGER_TCPWM1_TR_OUT077 = 655, //!< tcpwm[1].tr_out0[77] 701 _CYHAL_TRIGGER_TCPWM1_TR_OUT078 = 656, //!< tcpwm[1].tr_out0[78] 702 _CYHAL_TRIGGER_TCPWM1_TR_OUT079 = 657, //!< tcpwm[1].tr_out0[79] 703 _CYHAL_TRIGGER_TCPWM1_TR_OUT080 = 658, //!< tcpwm[1].tr_out0[80] 704 _CYHAL_TRIGGER_TCPWM1_TR_OUT081 = 659, //!< tcpwm[1].tr_out0[81] 705 _CYHAL_TRIGGER_TCPWM1_TR_OUT082 = 660, //!< tcpwm[1].tr_out0[82] 706 _CYHAL_TRIGGER_TCPWM1_TR_OUT083 = 661, //!< tcpwm[1].tr_out0[83] 707 _CYHAL_TRIGGER_TCPWM1_TR_OUT0256 = 662, //!< tcpwm[1].tr_out0[256] 708 _CYHAL_TRIGGER_TCPWM1_TR_OUT0257 = 663, //!< tcpwm[1].tr_out0[257] 709 _CYHAL_TRIGGER_TCPWM1_TR_OUT0258 = 664, //!< tcpwm[1].tr_out0[258] 710 _CYHAL_TRIGGER_TCPWM1_TR_OUT0259 = 665, //!< tcpwm[1].tr_out0[259] 711 _CYHAL_TRIGGER_TCPWM1_TR_OUT0260 = 666, //!< tcpwm[1].tr_out0[260] 712 _CYHAL_TRIGGER_TCPWM1_TR_OUT0261 = 667, //!< tcpwm[1].tr_out0[261] 713 _CYHAL_TRIGGER_TCPWM1_TR_OUT0262 = 668, //!< tcpwm[1].tr_out0[262] 714 _CYHAL_TRIGGER_TCPWM1_TR_OUT0263 = 669, //!< tcpwm[1].tr_out0[263] 715 _CYHAL_TRIGGER_TCPWM1_TR_OUT0264 = 670, //!< tcpwm[1].tr_out0[264] 716 _CYHAL_TRIGGER_TCPWM1_TR_OUT0265 = 671, //!< tcpwm[1].tr_out0[265] 717 _CYHAL_TRIGGER_TCPWM1_TR_OUT0266 = 672, //!< tcpwm[1].tr_out0[266] 718 _CYHAL_TRIGGER_TCPWM1_TR_OUT0267 = 673, //!< tcpwm[1].tr_out0[267] 719 _CYHAL_TRIGGER_TCPWM1_TR_OUT0512 = 674, //!< tcpwm[1].tr_out0[512] 720 _CYHAL_TRIGGER_TCPWM1_TR_OUT0513 = 675, //!< tcpwm[1].tr_out0[513] 721 _CYHAL_TRIGGER_TCPWM1_TR_OUT0514 = 676, //!< tcpwm[1].tr_out0[514] 722 _CYHAL_TRIGGER_TCPWM1_TR_OUT0515 = 677, //!< tcpwm[1].tr_out0[515] 723 _CYHAL_TRIGGER_TCPWM1_TR_OUT0516 = 678, //!< tcpwm[1].tr_out0[516] 724 _CYHAL_TRIGGER_TCPWM1_TR_OUT0517 = 679, //!< tcpwm[1].tr_out0[517] 725 _CYHAL_TRIGGER_TCPWM1_TR_OUT0518 = 680, //!< tcpwm[1].tr_out0[518] 726 _CYHAL_TRIGGER_TCPWM1_TR_OUT0519 = 681, //!< tcpwm[1].tr_out0[519] 727 _CYHAL_TRIGGER_TCPWM1_TR_OUT0520 = 682, //!< tcpwm[1].tr_out0[520] 728 _CYHAL_TRIGGER_TCPWM1_TR_OUT0521 = 683, //!< tcpwm[1].tr_out0[521] 729 _CYHAL_TRIGGER_TCPWM1_TR_OUT0522 = 684, //!< tcpwm[1].tr_out0[522] 730 _CYHAL_TRIGGER_TCPWM1_TR_OUT0523 = 685, //!< tcpwm[1].tr_out0[523] 731 _CYHAL_TRIGGER_TCPWM1_TR_OUT0524 = 686, //!< tcpwm[1].tr_out0[524] 732 _CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 687, //!< tcpwm[0].tr_out1[0] 733 _CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 688, //!< tcpwm[0].tr_out1[1] 734 _CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 689, //!< tcpwm[0].tr_out1[2] 735 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 690, //!< tcpwm[0].tr_out1[256] 736 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 691, //!< tcpwm[0].tr_out1[257] 737 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 692, //!< tcpwm[0].tr_out1[258] 738 _CYHAL_TRIGGER_TCPWM0_TR_OUT1512 = 693, //!< tcpwm[0].tr_out1[512] 739 _CYHAL_TRIGGER_TCPWM0_TR_OUT1513 = 694, //!< tcpwm[0].tr_out1[513] 740 _CYHAL_TRIGGER_TCPWM0_TR_OUT1514 = 695, //!< tcpwm[0].tr_out1[514] 741 _CYHAL_TRIGGER_TCPWM1_TR_OUT10 = 696, //!< tcpwm[1].tr_out1[0] 742 _CYHAL_TRIGGER_TCPWM1_TR_OUT11 = 697, //!< tcpwm[1].tr_out1[1] 743 _CYHAL_TRIGGER_TCPWM1_TR_OUT12 = 698, //!< tcpwm[1].tr_out1[2] 744 _CYHAL_TRIGGER_TCPWM1_TR_OUT13 = 699, //!< tcpwm[1].tr_out1[3] 745 _CYHAL_TRIGGER_TCPWM1_TR_OUT14 = 700, //!< tcpwm[1].tr_out1[4] 746 _CYHAL_TRIGGER_TCPWM1_TR_OUT15 = 701, //!< tcpwm[1].tr_out1[5] 747 _CYHAL_TRIGGER_TCPWM1_TR_OUT16 = 702, //!< tcpwm[1].tr_out1[6] 748 _CYHAL_TRIGGER_TCPWM1_TR_OUT17 = 703, //!< tcpwm[1].tr_out1[7] 749 _CYHAL_TRIGGER_TCPWM1_TR_OUT18 = 704, //!< tcpwm[1].tr_out1[8] 750 _CYHAL_TRIGGER_TCPWM1_TR_OUT19 = 705, //!< tcpwm[1].tr_out1[9] 751 _CYHAL_TRIGGER_TCPWM1_TR_OUT110 = 706, //!< tcpwm[1].tr_out1[10] 752 _CYHAL_TRIGGER_TCPWM1_TR_OUT111 = 707, //!< tcpwm[1].tr_out1[11] 753 _CYHAL_TRIGGER_TCPWM1_TR_OUT112 = 708, //!< tcpwm[1].tr_out1[12] 754 _CYHAL_TRIGGER_TCPWM1_TR_OUT113 = 709, //!< tcpwm[1].tr_out1[13] 755 _CYHAL_TRIGGER_TCPWM1_TR_OUT114 = 710, //!< tcpwm[1].tr_out1[14] 756 _CYHAL_TRIGGER_TCPWM1_TR_OUT115 = 711, //!< tcpwm[1].tr_out1[15] 757 _CYHAL_TRIGGER_TCPWM1_TR_OUT116 = 712, //!< tcpwm[1].tr_out1[16] 758 _CYHAL_TRIGGER_TCPWM1_TR_OUT117 = 713, //!< tcpwm[1].tr_out1[17] 759 _CYHAL_TRIGGER_TCPWM1_TR_OUT118 = 714, //!< tcpwm[1].tr_out1[18] 760 _CYHAL_TRIGGER_TCPWM1_TR_OUT119 = 715, //!< tcpwm[1].tr_out1[19] 761 _CYHAL_TRIGGER_TCPWM1_TR_OUT120 = 716, //!< tcpwm[1].tr_out1[20] 762 _CYHAL_TRIGGER_TCPWM1_TR_OUT121 = 717, //!< tcpwm[1].tr_out1[21] 763 _CYHAL_TRIGGER_TCPWM1_TR_OUT122 = 718, //!< tcpwm[1].tr_out1[22] 764 _CYHAL_TRIGGER_TCPWM1_TR_OUT123 = 719, //!< tcpwm[1].tr_out1[23] 765 _CYHAL_TRIGGER_TCPWM1_TR_OUT124 = 720, //!< tcpwm[1].tr_out1[24] 766 _CYHAL_TRIGGER_TCPWM1_TR_OUT125 = 721, //!< tcpwm[1].tr_out1[25] 767 _CYHAL_TRIGGER_TCPWM1_TR_OUT126 = 722, //!< tcpwm[1].tr_out1[26] 768 _CYHAL_TRIGGER_TCPWM1_TR_OUT127 = 723, //!< tcpwm[1].tr_out1[27] 769 _CYHAL_TRIGGER_TCPWM1_TR_OUT128 = 724, //!< tcpwm[1].tr_out1[28] 770 _CYHAL_TRIGGER_TCPWM1_TR_OUT129 = 725, //!< tcpwm[1].tr_out1[29] 771 _CYHAL_TRIGGER_TCPWM1_TR_OUT130 = 726, //!< tcpwm[1].tr_out1[30] 772 _CYHAL_TRIGGER_TCPWM1_TR_OUT131 = 727, //!< tcpwm[1].tr_out1[31] 773 _CYHAL_TRIGGER_TCPWM1_TR_OUT132 = 728, //!< tcpwm[1].tr_out1[32] 774 _CYHAL_TRIGGER_TCPWM1_TR_OUT133 = 729, //!< tcpwm[1].tr_out1[33] 775 _CYHAL_TRIGGER_TCPWM1_TR_OUT134 = 730, //!< tcpwm[1].tr_out1[34] 776 _CYHAL_TRIGGER_TCPWM1_TR_OUT135 = 731, //!< tcpwm[1].tr_out1[35] 777 _CYHAL_TRIGGER_TCPWM1_TR_OUT136 = 732, //!< tcpwm[1].tr_out1[36] 778 _CYHAL_TRIGGER_TCPWM1_TR_OUT137 = 733, //!< tcpwm[1].tr_out1[37] 779 _CYHAL_TRIGGER_TCPWM1_TR_OUT138 = 734, //!< tcpwm[1].tr_out1[38] 780 _CYHAL_TRIGGER_TCPWM1_TR_OUT139 = 735, //!< tcpwm[1].tr_out1[39] 781 _CYHAL_TRIGGER_TCPWM1_TR_OUT140 = 736, //!< tcpwm[1].tr_out1[40] 782 _CYHAL_TRIGGER_TCPWM1_TR_OUT141 = 737, //!< tcpwm[1].tr_out1[41] 783 _CYHAL_TRIGGER_TCPWM1_TR_OUT142 = 738, //!< tcpwm[1].tr_out1[42] 784 _CYHAL_TRIGGER_TCPWM1_TR_OUT143 = 739, //!< tcpwm[1].tr_out1[43] 785 _CYHAL_TRIGGER_TCPWM1_TR_OUT144 = 740, //!< tcpwm[1].tr_out1[44] 786 _CYHAL_TRIGGER_TCPWM1_TR_OUT145 = 741, //!< tcpwm[1].tr_out1[45] 787 _CYHAL_TRIGGER_TCPWM1_TR_OUT146 = 742, //!< tcpwm[1].tr_out1[46] 788 _CYHAL_TRIGGER_TCPWM1_TR_OUT147 = 743, //!< tcpwm[1].tr_out1[47] 789 _CYHAL_TRIGGER_TCPWM1_TR_OUT148 = 744, //!< tcpwm[1].tr_out1[48] 790 _CYHAL_TRIGGER_TCPWM1_TR_OUT149 = 745, //!< tcpwm[1].tr_out1[49] 791 _CYHAL_TRIGGER_TCPWM1_TR_OUT150 = 746, //!< tcpwm[1].tr_out1[50] 792 _CYHAL_TRIGGER_TCPWM1_TR_OUT151 = 747, //!< tcpwm[1].tr_out1[51] 793 _CYHAL_TRIGGER_TCPWM1_TR_OUT152 = 748, //!< tcpwm[1].tr_out1[52] 794 _CYHAL_TRIGGER_TCPWM1_TR_OUT153 = 749, //!< tcpwm[1].tr_out1[53] 795 _CYHAL_TRIGGER_TCPWM1_TR_OUT154 = 750, //!< tcpwm[1].tr_out1[54] 796 _CYHAL_TRIGGER_TCPWM1_TR_OUT155 = 751, //!< tcpwm[1].tr_out1[55] 797 _CYHAL_TRIGGER_TCPWM1_TR_OUT156 = 752, //!< tcpwm[1].tr_out1[56] 798 _CYHAL_TRIGGER_TCPWM1_TR_OUT157 = 753, //!< tcpwm[1].tr_out1[57] 799 _CYHAL_TRIGGER_TCPWM1_TR_OUT158 = 754, //!< tcpwm[1].tr_out1[58] 800 _CYHAL_TRIGGER_TCPWM1_TR_OUT159 = 755, //!< tcpwm[1].tr_out1[59] 801 _CYHAL_TRIGGER_TCPWM1_TR_OUT160 = 756, //!< tcpwm[1].tr_out1[60] 802 _CYHAL_TRIGGER_TCPWM1_TR_OUT161 = 757, //!< tcpwm[1].tr_out1[61] 803 _CYHAL_TRIGGER_TCPWM1_TR_OUT162 = 758, //!< tcpwm[1].tr_out1[62] 804 _CYHAL_TRIGGER_TCPWM1_TR_OUT163 = 759, //!< tcpwm[1].tr_out1[63] 805 _CYHAL_TRIGGER_TCPWM1_TR_OUT164 = 760, //!< tcpwm[1].tr_out1[64] 806 _CYHAL_TRIGGER_TCPWM1_TR_OUT165 = 761, //!< tcpwm[1].tr_out1[65] 807 _CYHAL_TRIGGER_TCPWM1_TR_OUT166 = 762, //!< tcpwm[1].tr_out1[66] 808 _CYHAL_TRIGGER_TCPWM1_TR_OUT167 = 763, //!< tcpwm[1].tr_out1[67] 809 _CYHAL_TRIGGER_TCPWM1_TR_OUT168 = 764, //!< tcpwm[1].tr_out1[68] 810 _CYHAL_TRIGGER_TCPWM1_TR_OUT169 = 765, //!< tcpwm[1].tr_out1[69] 811 _CYHAL_TRIGGER_TCPWM1_TR_OUT170 = 766, //!< tcpwm[1].tr_out1[70] 812 _CYHAL_TRIGGER_TCPWM1_TR_OUT171 = 767, //!< tcpwm[1].tr_out1[71] 813 _CYHAL_TRIGGER_TCPWM1_TR_OUT172 = 768, //!< tcpwm[1].tr_out1[72] 814 _CYHAL_TRIGGER_TCPWM1_TR_OUT173 = 769, //!< tcpwm[1].tr_out1[73] 815 _CYHAL_TRIGGER_TCPWM1_TR_OUT174 = 770, //!< tcpwm[1].tr_out1[74] 816 _CYHAL_TRIGGER_TCPWM1_TR_OUT175 = 771, //!< tcpwm[1].tr_out1[75] 817 _CYHAL_TRIGGER_TCPWM1_TR_OUT176 = 772, //!< tcpwm[1].tr_out1[76] 818 _CYHAL_TRIGGER_TCPWM1_TR_OUT177 = 773, //!< tcpwm[1].tr_out1[77] 819 _CYHAL_TRIGGER_TCPWM1_TR_OUT178 = 774, //!< tcpwm[1].tr_out1[78] 820 _CYHAL_TRIGGER_TCPWM1_TR_OUT179 = 775, //!< tcpwm[1].tr_out1[79] 821 _CYHAL_TRIGGER_TCPWM1_TR_OUT180 = 776, //!< tcpwm[1].tr_out1[80] 822 _CYHAL_TRIGGER_TCPWM1_TR_OUT181 = 777, //!< tcpwm[1].tr_out1[81] 823 _CYHAL_TRIGGER_TCPWM1_TR_OUT182 = 778, //!< tcpwm[1].tr_out1[82] 824 _CYHAL_TRIGGER_TCPWM1_TR_OUT183 = 779, //!< tcpwm[1].tr_out1[83] 825 _CYHAL_TRIGGER_TCPWM1_TR_OUT1256 = 780, //!< tcpwm[1].tr_out1[256] 826 _CYHAL_TRIGGER_TCPWM1_TR_OUT1257 = 781, //!< tcpwm[1].tr_out1[257] 827 _CYHAL_TRIGGER_TCPWM1_TR_OUT1258 = 782, //!< tcpwm[1].tr_out1[258] 828 _CYHAL_TRIGGER_TCPWM1_TR_OUT1259 = 783, //!< tcpwm[1].tr_out1[259] 829 _CYHAL_TRIGGER_TCPWM1_TR_OUT1260 = 784, //!< tcpwm[1].tr_out1[260] 830 _CYHAL_TRIGGER_TCPWM1_TR_OUT1261 = 785, //!< tcpwm[1].tr_out1[261] 831 _CYHAL_TRIGGER_TCPWM1_TR_OUT1262 = 786, //!< tcpwm[1].tr_out1[262] 832 _CYHAL_TRIGGER_TCPWM1_TR_OUT1263 = 787, //!< tcpwm[1].tr_out1[263] 833 _CYHAL_TRIGGER_TCPWM1_TR_OUT1264 = 788, //!< tcpwm[1].tr_out1[264] 834 _CYHAL_TRIGGER_TCPWM1_TR_OUT1265 = 789, //!< tcpwm[1].tr_out1[265] 835 _CYHAL_TRIGGER_TCPWM1_TR_OUT1266 = 790, //!< tcpwm[1].tr_out1[266] 836 _CYHAL_TRIGGER_TCPWM1_TR_OUT1267 = 791, //!< tcpwm[1].tr_out1[267] 837 _CYHAL_TRIGGER_TCPWM1_TR_OUT1512 = 792, //!< tcpwm[1].tr_out1[512] 838 _CYHAL_TRIGGER_TCPWM1_TR_OUT1513 = 793, //!< tcpwm[1].tr_out1[513] 839 _CYHAL_TRIGGER_TCPWM1_TR_OUT1514 = 794, //!< tcpwm[1].tr_out1[514] 840 _CYHAL_TRIGGER_TCPWM1_TR_OUT1515 = 795, //!< tcpwm[1].tr_out1[515] 841 _CYHAL_TRIGGER_TCPWM1_TR_OUT1516 = 796, //!< tcpwm[1].tr_out1[516] 842 _CYHAL_TRIGGER_TCPWM1_TR_OUT1517 = 797, //!< tcpwm[1].tr_out1[517] 843 _CYHAL_TRIGGER_TCPWM1_TR_OUT1518 = 798, //!< tcpwm[1].tr_out1[518] 844 _CYHAL_TRIGGER_TCPWM1_TR_OUT1519 = 799, //!< tcpwm[1].tr_out1[519] 845 _CYHAL_TRIGGER_TCPWM1_TR_OUT1520 = 800, //!< tcpwm[1].tr_out1[520] 846 _CYHAL_TRIGGER_TCPWM1_TR_OUT1521 = 801, //!< tcpwm[1].tr_out1[521] 847 _CYHAL_TRIGGER_TCPWM1_TR_OUT1522 = 802, //!< tcpwm[1].tr_out1[522] 848 _CYHAL_TRIGGER_TCPWM1_TR_OUT1523 = 803, //!< tcpwm[1].tr_out1[523] 849 _CYHAL_TRIGGER_TCPWM1_TR_OUT1524 = 804, //!< tcpwm[1].tr_out1[524] 850 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 = 805, //!< tr_group[10].output[0] 851 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 = 806, //!< tr_group[10].output[1] 852 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 = 807, //!< tr_group[10].output[2] 853 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 = 808, //!< tr_group[10].output[3] 854 _CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 = 809, //!< tr_group[10].output[4] 855 _CYHAL_TRIGGER_TR_GROUP11_OUTPUT0 = 810, //!< tr_group[11].output[0] 856 _CYHAL_TRIGGER_TR_GROUP11_OUTPUT1 = 811, //!< tr_group[11].output[1] 857 _CYHAL_TRIGGER_TR_GROUP11_OUTPUT2 = 812, //!< tr_group[11].output[2] 858 _CYHAL_TRIGGER_TR_GROUP11_OUTPUT3 = 813, //!< tr_group[11].output[3] 859 _CYHAL_TRIGGER_TR_GROUP11_OUTPUT4 = 814, //!< tr_group[11].output[4] 860 _CYHAL_TRIGGER_TR_GROUP12_OUTPUT0 = 815, //!< tr_group[12].output[0] 861 _CYHAL_TRIGGER_TR_GROUP12_OUTPUT1 = 816, //!< tr_group[12].output[1] 862 _CYHAL_TRIGGER_TR_GROUP12_OUTPUT2 = 817, //!< tr_group[12].output[2] 863 _CYHAL_TRIGGER_TR_GROUP12_OUTPUT3 = 818, //!< tr_group[12].output[3] 864 _CYHAL_TRIGGER_TR_GROUP12_OUTPUT4 = 819, //!< tr_group[12].output[4] 865 } _cyhal_trigger_source_xmc7200_t; 866 867 /** Typedef for internal device family specific trigger source to generic trigger source */ 868 typedef _cyhal_trigger_source_xmc7200_t cyhal_internal_source_t; 869 870 /** @brief Get a public source signal type (cyhal_trigger_source_xmc7200_t) given an internal source signal and signal type */ 871 #define _CYHAL_TRIGGER_CREATE_SOURCE(src, type) ((src) << 1 | (type)) 872 /** @brief Get an internal source signal (_cyhal_trigger_source_xmc7200_t) given a public source signal. */ 873 #define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src) ((cyhal_internal_source_t)((src) >> 1)) 874 /** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */ 875 #define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src) ((cyhal_signal_type_t)((src) & 1)) 876 /** \endcond */ 877 878 /** @brief Name of each input trigger. */ 879 typedef enum 880 { 881 CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.zero 882 CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.zero 883 CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[0].tr_i2s_rx_req 884 CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[1].tr_i2s_rx_req 885 CYHAL_TRIGGER_AUDIOSS2_TR_I2S_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS2_TR_I2S_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[2].tr_i2s_rx_req 886 CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[0].tr_i2s_tx_req 887 CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[1].tr_i2s_tx_req 888 CYHAL_TRIGGER_AUDIOSS2_TR_I2S_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_AUDIOSS2_TR_I2S_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< audioss[2].tr_i2s_tx_req 889 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[0] 890 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[1] 891 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[2] 892 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[3] 893 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ4, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[4] 894 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[0] 895 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[1] 896 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[2] 897 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[3] 898 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_REQ4, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_dbg_dma_req[4] 899 CYHAL_TRIGGER_CANFD0_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[0] 900 CYHAL_TRIGGER_CANFD0_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[1] 901 CYHAL_TRIGGER_CANFD0_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[2] 902 CYHAL_TRIGGER_CANFD0_TR_FIFO03 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO03, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[3] 903 CYHAL_TRIGGER_CANFD0_TR_FIFO04 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO04, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[4] 904 CYHAL_TRIGGER_CANFD1_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[0] 905 CYHAL_TRIGGER_CANFD1_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[1] 906 CYHAL_TRIGGER_CANFD1_TR_FIFO02 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO02, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[2] 907 CYHAL_TRIGGER_CANFD1_TR_FIFO03 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO03, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[3] 908 CYHAL_TRIGGER_CANFD1_TR_FIFO04 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO04, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo0[4] 909 CYHAL_TRIGGER_CANFD0_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[0] 910 CYHAL_TRIGGER_CANFD0_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[1] 911 CYHAL_TRIGGER_CANFD0_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[2] 912 CYHAL_TRIGGER_CANFD0_TR_FIFO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO13, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[3] 913 CYHAL_TRIGGER_CANFD0_TR_FIFO14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO14, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[4] 914 CYHAL_TRIGGER_CANFD1_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[0] 915 CYHAL_TRIGGER_CANFD1_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[1] 916 CYHAL_TRIGGER_CANFD1_TR_FIFO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO12, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[2] 917 CYHAL_TRIGGER_CANFD1_TR_FIFO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO13, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[3] 918 CYHAL_TRIGGER_CANFD1_TR_FIFO14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_FIFO14, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[1].tr_fifo1[4] 919 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[0] 920 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[1] 921 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[2] 922 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[3] 923 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[4] 924 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[0] 925 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[1] 926 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[2] 927 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[3] 928 CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD1_TR_TMP_RTP_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[1].tr_tmp_rtp_out[4] 929 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[0] 930 CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.cti_tr_out[1] 931 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[0] 932 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[1] 933 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[2] 934 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[3] 935 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[4] 936 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[5] 937 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[6] 938 CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dmac_tr_out[7] 939 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[0] 940 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[1] 941 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[2] 942 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[3] 943 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[4] 944 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[5] 945 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[6] 946 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[7] 947 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[8] 948 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[9] 949 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[10] 950 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[11] 951 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[12] 952 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[13] 953 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[14] 954 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[15] 955 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[16] 956 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[17] 957 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[18] 958 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[19] 959 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[20] 960 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[21] 961 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[22] 962 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[23] 963 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[24] 964 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[25] 965 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[26] 966 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[27] 967 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[28] 968 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[29] 969 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[30] 970 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[31] 971 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[32] 972 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[33] 973 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[34] 974 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[35] 975 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[36] 976 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[37] 977 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[38] 978 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[39] 979 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[40] 980 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[41] 981 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[42] 982 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[43] 983 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT44, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[44] 984 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT45, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[45] 985 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT46, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[46] 986 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT47, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[47] 987 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT48, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[48] 988 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT49, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[49] 989 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT50, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[50] 990 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT51, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[51] 991 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT52, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[52] 992 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT53, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[53] 993 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT54, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[54] 994 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT55, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[55] 995 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT56, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[56] 996 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT57, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[57] 997 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT58, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[58] 998 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT59, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[59] 999 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT60, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[60] 1000 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT61, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[61] 1001 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT62, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[62] 1002 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT63, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[63] 1003 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT64, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[64] 1004 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT65, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[65] 1005 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT66, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[66] 1006 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT67, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[67] 1007 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT68, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[68] 1008 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT69, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[69] 1009 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT70, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[70] 1010 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT71, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[71] 1011 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT72, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[72] 1012 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT73, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[73] 1013 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT74, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[74] 1014 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT75, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[75] 1015 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT76, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[76] 1016 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT77, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[77] 1017 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT78, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[78] 1018 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT79, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[79] 1019 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT80, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[80] 1020 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT81, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[81] 1021 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT82, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[82] 1022 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT83, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[83] 1023 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT84, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[84] 1024 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT85, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[85] 1025 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT86, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[86] 1026 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT87, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[87] 1027 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT88, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[88] 1028 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT89, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[89] 1029 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT90, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[90] 1030 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT91, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[91] 1031 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT92 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT92, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[92] 1032 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT93 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT93, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[93] 1033 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT94 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT94, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[94] 1034 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT95 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT95, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[95] 1035 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT96 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT96, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[96] 1036 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT97 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT97, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[97] 1037 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT98 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT98, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[98] 1038 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT99 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT99, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[99] 1039 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT100 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT100, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[100] 1040 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT101 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT101, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[101] 1041 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT102 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT102, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[102] 1042 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT103 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT103, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[103] 1043 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT104 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT104, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[104] 1044 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT105 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT105, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[105] 1045 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT106 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT106, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[106] 1046 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT107 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT107, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[107] 1047 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT108 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT108, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[108] 1048 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT109 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT109, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[109] 1049 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT110 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT110, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[110] 1050 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT111 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT111, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[111] 1051 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT112 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT112, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[112] 1052 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT113 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT113, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[113] 1053 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT114 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT114, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[114] 1054 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT115 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT115, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[115] 1055 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT116 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT116, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[116] 1056 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT117 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT117, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[117] 1057 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT118 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT118, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[118] 1058 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT119 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT119, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[119] 1059 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT120 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT120, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[120] 1060 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT121 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT121, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[121] 1061 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT122 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT122, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[122] 1062 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT123 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT123, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[123] 1063 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT124 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT124, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[124] 1064 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT125 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT125, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[125] 1065 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT126 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT126, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[126] 1066 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT127 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT127, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[127] 1067 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT128 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT128, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[128] 1068 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT129 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT129, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[129] 1069 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT130 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT130, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[130] 1070 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT131 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT131, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[131] 1071 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT132 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT132, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[132] 1072 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT133 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT133, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[133] 1073 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT134 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT134, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[134] 1074 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT135 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT135, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[135] 1075 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT136 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT136, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[136] 1076 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT137 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT137, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[137] 1077 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT138 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT138, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[138] 1078 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT139 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT139, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[139] 1079 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT140 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT140, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[140] 1080 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT141 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT141, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[141] 1081 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT142 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT142, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[142] 1082 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[0] 1083 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[1] 1084 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[2] 1085 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[3] 1086 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[4] 1087 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[5] 1088 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[6] 1089 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[7] 1090 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[8] 1091 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[9] 1092 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[10] 1093 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[11] 1094 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[12] 1095 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[13] 1096 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[14] 1097 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[15] 1098 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[16] 1099 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[17] 1100 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[18] 1101 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[19] 1102 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[20] 1103 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[21] 1104 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[22] 1105 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[23] 1106 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[24] 1107 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[25] 1108 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[26] 1109 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[27] 1110 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[28] 1111 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[29] 1112 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[30] 1113 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[31] 1114 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[32] 1115 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[33] 1116 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[34] 1117 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[35] 1118 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[36] 1119 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[37] 1120 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[38] 1121 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[39] 1122 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[40] 1123 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[41] 1124 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[42] 1125 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[43] 1126 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT44, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[44] 1127 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT45, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[45] 1128 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT46, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[46] 1129 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT47, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[47] 1130 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT48, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[48] 1131 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT49, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[49] 1132 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT50, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[50] 1133 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT51, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[51] 1134 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT52, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[52] 1135 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT53, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[53] 1136 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT54, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[54] 1137 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT55, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[55] 1138 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT56, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[56] 1139 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT57, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[57] 1140 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT58, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[58] 1141 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT59, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[59] 1142 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT60, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[60] 1143 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT61, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[61] 1144 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT62, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[62] 1145 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT63, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[63] 1146 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT64, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[64] 1147 CYHAL_TRIGGER_CPUSS_TR_FAULT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[0] 1148 CYHAL_TRIGGER_CPUSS_TR_FAULT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[1] 1149 CYHAL_TRIGGER_CPUSS_TR_FAULT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[2] 1150 CYHAL_TRIGGER_CPUSS_TR_FAULT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[3] 1151 CYHAL_TRIGGER_EVTGEN0_TR_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[0] 1152 CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[0] 1153 CYHAL_TRIGGER_EVTGEN0_TR_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[1] 1154 CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[1] 1155 CYHAL_TRIGGER_EVTGEN0_TR_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[2] 1156 CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[2] 1157 CYHAL_TRIGGER_EVTGEN0_TR_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[3] 1158 CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[3] 1159 CYHAL_TRIGGER_EVTGEN0_TR_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[4] 1160 CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[4] 1161 CYHAL_TRIGGER_EVTGEN0_TR_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[5] 1162 CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[5] 1163 CYHAL_TRIGGER_EVTGEN0_TR_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[6] 1164 CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[6] 1165 CYHAL_TRIGGER_EVTGEN0_TR_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[7] 1166 CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[7] 1167 CYHAL_TRIGGER_EVTGEN0_TR_OUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[8] 1168 CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[8] 1169 CYHAL_TRIGGER_EVTGEN0_TR_OUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[9] 1170 CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[9] 1171 CYHAL_TRIGGER_EVTGEN0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[10] 1172 CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[10] 1173 CYHAL_TRIGGER_EVTGEN0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[11] 1174 CYHAL_TRIGGER_EVTGEN0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[11] 1175 CYHAL_TRIGGER_EVTGEN0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[12] 1176 CYHAL_TRIGGER_EVTGEN0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[12] 1177 CYHAL_TRIGGER_EVTGEN0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[13] 1178 CYHAL_TRIGGER_EVTGEN0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[13] 1179 CYHAL_TRIGGER_EVTGEN0_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[14] 1180 CYHAL_TRIGGER_EVTGEN0_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[14] 1181 CYHAL_TRIGGER_EVTGEN0_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< evtgen[0].tr_out[15] 1182 CYHAL_TRIGGER_EVTGEN0_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_EVTGEN0_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< evtgen[0].tr_out[15] 1183 CYHAL_TRIGGER_FLEXRAY0_TR_IBF_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_FLEXRAY0_TR_IBF_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< flexray[0].tr_ibf_out 1184 CYHAL_TRIGGER_FLEXRAY0_TR_OBF_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_FLEXRAY0_TR_OBF_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< flexray[0].tr_obf_out 1185 CYHAL_TRIGGER_FLEXRAY0_TR_TINT0_OUT = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_FLEXRAY0_TR_TINT0_OUT, CYHAL_SIGNAL_TYPE_EDGE), //!< flexray[0].tr_tint0_out 1186 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[0] 1187 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[0] 1188 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[1] 1189 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[1] 1190 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[2] 1191 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[2] 1192 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[3] 1193 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[3] 1194 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[4] 1195 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[4] 1196 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[5] 1197 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[5] 1198 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[6] 1199 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[6] 1200 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[7] 1201 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[7] 1202 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[8] 1203 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[8] 1204 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[9] 1205 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[9] 1206 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[10] 1207 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[10] 1208 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[11] 1209 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[11] 1210 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[12] 1211 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[12] 1212 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[13] 1213 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[13] 1214 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[14] 1215 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[14] 1216 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[15] 1217 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[15] 1218 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[16] 1219 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[16] 1220 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[17] 1221 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[17] 1222 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[18] 1223 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[18] 1224 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[19] 1225 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[19] 1226 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[20] 1227 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[20] 1228 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[21] 1229 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[21] 1230 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[22] 1231 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[22] 1232 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[23] 1233 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[23] 1234 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[24] 1235 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[24] 1236 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[25] 1237 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[25] 1238 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[26] 1239 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[26] 1240 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[27] 1241 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[27] 1242 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[28] 1243 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[28] 1244 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[29] 1245 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[29] 1246 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[30] 1247 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[30] 1248 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[31] 1249 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[31] 1250 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[32] 1251 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[32] 1252 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[33] 1253 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[33] 1254 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[34] 1255 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[34] 1256 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[35] 1257 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[35] 1258 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[36] 1259 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[36] 1260 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[37] 1261 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[37] 1262 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[38] 1263 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[38] 1264 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[39] 1265 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[39] 1266 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[40] 1267 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[40] 1268 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[41] 1269 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[41] 1270 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[42] 1271 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[42] 1272 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[43] 1273 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[43] 1274 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[44] 1275 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[44] 1276 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[45] 1277 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[45] 1278 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[46] 1279 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[46] 1280 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[47] 1281 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[47] 1282 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[48] 1283 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[48] 1284 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[49] 1285 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[49] 1286 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[50] 1287 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[50] 1288 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[51] 1289 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[51] 1290 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[52] 1291 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[52] 1292 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[53] 1293 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[53] 1294 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[54] 1295 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[54] 1296 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[55] 1297 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[55] 1298 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[56] 1299 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[56] 1300 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[57] 1301 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[57] 1302 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[58] 1303 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[58] 1304 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[59] 1305 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[59] 1306 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[60] 1307 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[60] 1308 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[61] 1309 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[61] 1310 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[62] 1311 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[62] 1312 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[63] 1313 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[63] 1314 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[64] 1315 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[64] 1316 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[65] 1317 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[65] 1318 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[66] 1319 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[66] 1320 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[67] 1321 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[67] 1322 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[68] 1323 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[68] 1324 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[69] 1325 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[69] 1326 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[70] 1327 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[70] 1328 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[71] 1329 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[71] 1330 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE72_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE72, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[72] 1331 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE72_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE72, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[72] 1332 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE73_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE73, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[73] 1333 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE73_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE73, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[73] 1334 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE74_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE74, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[74] 1335 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE74_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE74, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[74] 1336 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE75_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE75, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[75] 1337 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE75_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE75, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[75] 1338 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE76_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE76, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[76] 1339 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE76_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE76, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[76] 1340 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE77_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE77, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[77] 1341 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE77_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE77, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[77] 1342 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE78_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE78, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[78] 1343 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE78_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE78, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[78] 1344 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE79_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE79, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[79] 1345 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE79_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE79, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[79] 1346 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE80_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE80, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[80] 1347 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE80_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE80, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[80] 1348 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE81_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE81, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[81] 1349 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE81_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE81, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[81] 1350 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE82_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE82, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[82] 1351 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE82_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE82, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[82] 1352 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE83_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE83, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[83] 1353 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE83_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE83, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[83] 1354 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE84_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE84, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[84] 1355 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE84_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE84, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[84] 1356 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE85_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE85, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[85] 1357 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE85_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE85, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[85] 1358 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE86_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE86, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[86] 1359 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE86_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE86, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[86] 1360 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE87_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE87, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[87] 1361 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE87_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE87, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[87] 1362 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE88_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE88, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[88] 1363 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE88_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE88, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[88] 1364 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE89_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE89, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[89] 1365 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE89_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE89, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[89] 1366 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE90_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE90, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[90] 1367 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE90_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE90, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[90] 1368 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE91_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE91, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[91] 1369 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE91_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE91, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[91] 1370 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE92_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE92, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[92] 1371 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE92_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE92, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[92] 1372 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE93_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE93, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[93] 1373 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE93_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE93, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[93] 1374 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE94_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE94, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[94] 1375 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE94_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE94, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[94] 1376 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE95_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE95, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_done[95] 1377 CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE95_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE95, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_ch_done[95] 1378 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[0] 1379 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[1] 1380 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[2] 1381 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[3] 1382 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[4] 1383 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[5] 1384 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[6] 1385 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[7] 1386 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO8, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[8] 1387 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO9, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[9] 1388 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO10, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[10] 1389 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO11, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[11] 1390 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO12, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[12] 1391 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO13, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[13] 1392 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO14, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[14] 1393 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO15, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[15] 1394 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO16, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[16] 1395 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO17, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[17] 1396 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO18, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[18] 1397 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO19, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[19] 1398 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO20, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[20] 1399 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO21, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[21] 1400 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO22, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[22] 1401 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO23, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[23] 1402 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO24 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO24, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[24] 1403 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO25 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO25, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[25] 1404 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO26 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO26, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[26] 1405 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO27 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO27, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[27] 1406 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO28 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO28, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[28] 1407 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO29 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO29, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[29] 1408 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO30 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO30, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[30] 1409 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO31 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO31, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[31] 1410 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO32, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[32] 1411 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO33, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[33] 1412 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO34, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[34] 1413 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO35, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[35] 1414 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO36, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[36] 1415 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO37, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[37] 1416 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO38, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[38] 1417 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO39, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[39] 1418 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO40, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[40] 1419 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO41, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[41] 1420 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO42, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[42] 1421 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO43, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[43] 1422 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO44, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[44] 1423 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO45, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[45] 1424 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO46, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[46] 1425 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO47, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[47] 1426 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO48, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[48] 1427 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO49, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[49] 1428 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO50, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[50] 1429 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO51, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[51] 1430 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO52, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[52] 1431 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO53, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[53] 1432 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO54, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[54] 1433 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO55, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[55] 1434 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO56, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[56] 1435 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO57, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[57] 1436 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO58, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[58] 1437 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO59, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[59] 1438 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO60, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[60] 1439 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO61, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[61] 1440 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO62, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[62] 1441 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO63, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[63] 1442 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO64, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[64] 1443 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO65, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[65] 1444 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO66, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[66] 1445 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO67, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[67] 1446 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO68, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[68] 1447 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO69, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[69] 1448 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO70, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[70] 1449 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO71, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[71] 1450 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO72 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO72, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[72] 1451 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO73 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO73, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[73] 1452 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO74 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO74, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[74] 1453 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO75 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO75, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[75] 1454 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO76 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO76, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[76] 1455 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO77 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO77, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[77] 1456 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO78 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO78, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[78] 1457 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO79 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO79, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[79] 1458 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO80 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO80, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[80] 1459 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO81 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO81, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[81] 1460 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO82 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO82, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[82] 1461 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO83 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO83, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[83] 1462 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO84 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO84, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[84] 1463 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO85 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO85, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[85] 1464 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO86 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO86, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[86] 1465 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO87 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO87, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[87] 1466 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO88 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO88, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[88] 1467 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO89 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO89, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[89] 1468 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO90 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO90, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[90] 1469 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO91 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO91, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[91] 1470 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO92 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO92, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[92] 1471 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO93 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO93, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[93] 1472 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO94 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO94, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[94] 1473 CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO95 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_CH_RANGEVIO95, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_ch_rangevio[95] 1474 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[0] 1475 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[0] 1476 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[1] 1477 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[1] 1478 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[2] 1479 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[2] 1480 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[3] 1481 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[3] 1482 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[4] 1483 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[4] 1484 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass[0].tr_sar_gen_out[5] 1485 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass[0].tr_sar_gen_out[5] 1486 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[0] 1487 CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[0] 1488 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[1] 1489 CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[1] 1490 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[2] 1491 CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[2] 1492 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[3] 1493 CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[3] 1494 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[4] 1495 CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[4] 1496 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[5] 1497 CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[5] 1498 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[6] 1499 CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[6] 1500 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[7] 1501 CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[7] 1502 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[8] 1503 CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT8, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[8] 1504 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[9] 1505 CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT9, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[9] 1506 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[10] 1507 CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[10] 1508 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[11] 1509 CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[11] 1510 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[12] 1511 CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[12] 1512 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[13] 1513 CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[13] 1514 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[14] 1515 CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[14] 1516 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[15] 1517 CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[15] 1518 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[16] 1519 CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[16] 1520 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[17] 1521 CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[17] 1522 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[18] 1523 CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[18] 1524 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[19] 1525 CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[19] 1526 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[20] 1527 CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT20, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[20] 1528 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[21] 1529 CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT21, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[21] 1530 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[22] 1531 CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT22, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[22] 1532 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[23] 1533 CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT23, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[23] 1534 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[24] 1535 CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT24, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[24] 1536 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[25] 1537 CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT25, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[25] 1538 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[26] 1539 CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT26, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[26] 1540 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[27] 1541 CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT27, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[27] 1542 CYHAL_TRIGGER_PERI_TR_IO_INPUT28_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[28] 1543 CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT28, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[28] 1544 CYHAL_TRIGGER_PERI_TR_IO_INPUT29_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[29] 1545 CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT29, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[29] 1546 CYHAL_TRIGGER_PERI_TR_IO_INPUT30_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[30] 1547 CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT30, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[30] 1548 CYHAL_TRIGGER_PERI_TR_IO_INPUT31_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[31] 1549 CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT31, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[31] 1550 CYHAL_TRIGGER_PERI_TR_IO_INPUT32_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT32, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[32] 1551 CYHAL_TRIGGER_PERI_TR_IO_INPUT32_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT32, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[32] 1552 CYHAL_TRIGGER_PERI_TR_IO_INPUT33_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT33, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[33] 1553 CYHAL_TRIGGER_PERI_TR_IO_INPUT33_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT33, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[33] 1554 CYHAL_TRIGGER_PERI_TR_IO_INPUT34_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT34, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[34] 1555 CYHAL_TRIGGER_PERI_TR_IO_INPUT34_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT34, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[34] 1556 CYHAL_TRIGGER_PERI_TR_IO_INPUT35_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT35, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[35] 1557 CYHAL_TRIGGER_PERI_TR_IO_INPUT35_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT35, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[35] 1558 CYHAL_TRIGGER_PERI_TR_IO_INPUT36_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT36, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[36] 1559 CYHAL_TRIGGER_PERI_TR_IO_INPUT36_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT36, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[36] 1560 CYHAL_TRIGGER_PERI_TR_IO_INPUT37_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT37, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[37] 1561 CYHAL_TRIGGER_PERI_TR_IO_INPUT37_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT37, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[37] 1562 CYHAL_TRIGGER_PERI_TR_IO_INPUT38_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT38, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[38] 1563 CYHAL_TRIGGER_PERI_TR_IO_INPUT38_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT38, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[38] 1564 CYHAL_TRIGGER_PERI_TR_IO_INPUT39_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT39, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[39] 1565 CYHAL_TRIGGER_PERI_TR_IO_INPUT39_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT39, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[39] 1566 CYHAL_TRIGGER_PERI_TR_IO_INPUT40_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT40, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[40] 1567 CYHAL_TRIGGER_PERI_TR_IO_INPUT40_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT40, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[40] 1568 CYHAL_TRIGGER_PERI_TR_IO_INPUT41_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT41, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[41] 1569 CYHAL_TRIGGER_PERI_TR_IO_INPUT41_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT41, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[41] 1570 CYHAL_TRIGGER_PERI_TR_IO_INPUT42_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT42, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[42] 1571 CYHAL_TRIGGER_PERI_TR_IO_INPUT42_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT42, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[42] 1572 CYHAL_TRIGGER_PERI_TR_IO_INPUT43_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT43, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[43] 1573 CYHAL_TRIGGER_PERI_TR_IO_INPUT43_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT43, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[43] 1574 CYHAL_TRIGGER_PERI_TR_IO_INPUT44_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT44, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[44] 1575 CYHAL_TRIGGER_PERI_TR_IO_INPUT44_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT44, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[44] 1576 CYHAL_TRIGGER_PERI_TR_IO_INPUT45_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT45, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[45] 1577 CYHAL_TRIGGER_PERI_TR_IO_INPUT45_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT45, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[45] 1578 CYHAL_TRIGGER_PERI_TR_IO_INPUT46_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT46, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[46] 1579 CYHAL_TRIGGER_PERI_TR_IO_INPUT46_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT46, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[46] 1580 CYHAL_TRIGGER_PERI_TR_IO_INPUT47_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT47, CYHAL_SIGNAL_TYPE_EDGE), //!< peri.tr_io_input[47] 1581 CYHAL_TRIGGER_PERI_TR_IO_INPUT47_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PERI_TR_IO_INPUT47, CYHAL_SIGNAL_TYPE_LEVEL), //!< peri.tr_io_input[47] 1582 CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered 1583 CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered 1584 CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered 1585 CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered 1586 CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered 1587 CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered 1588 CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered 1589 CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered 1590 CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_i2c_scl_filtered 1591 CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_i2c_scl_filtered 1592 CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_i2c_scl_filtered 1593 CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req 1594 CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req 1595 CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req 1596 CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req 1597 CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req 1598 CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req 1599 CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req 1600 CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req 1601 CYHAL_TRIGGER_SCB8_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_rx_req 1602 CYHAL_TRIGGER_SCB9_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_rx_req 1603 CYHAL_TRIGGER_SCB10_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_rx_req 1604 CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req 1605 CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req 1606 CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req 1607 CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req 1608 CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req 1609 CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req 1610 CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req 1611 CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req 1612 CYHAL_TRIGGER_SCB8_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_tx_req 1613 CYHAL_TRIGGER_SCB9_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_tx_req 1614 CYHAL_TRIGGER_SCB10_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_tx_req 1615 CYHAL_TRIGGER_SMIF0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif[0].tr_rx_req 1616 CYHAL_TRIGGER_SMIF0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SMIF0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< smif[0].tr_tx_req 1617 CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[0] 1618 CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[0] 1619 CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[1] 1620 CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[1] 1621 CYHAL_TRIGGER_TCPWM0_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[2] 1622 CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[2] 1623 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[256] 1624 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[256] 1625 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[257] 1626 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[257] 1627 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[258] 1628 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[258] 1629 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[512] 1630 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[512] 1631 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[513] 1632 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[513] 1633 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[514] 1634 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[514] 1635 CYHAL_TRIGGER_TCPWM1_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[0] 1636 CYHAL_TRIGGER_TCPWM1_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[0] 1637 CYHAL_TRIGGER_TCPWM1_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[1] 1638 CYHAL_TRIGGER_TCPWM1_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[1] 1639 CYHAL_TRIGGER_TCPWM1_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[2] 1640 CYHAL_TRIGGER_TCPWM1_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[2] 1641 CYHAL_TRIGGER_TCPWM1_TR_OUT03_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT03, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[3] 1642 CYHAL_TRIGGER_TCPWM1_TR_OUT03_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT03, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[3] 1643 CYHAL_TRIGGER_TCPWM1_TR_OUT04_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT04, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[4] 1644 CYHAL_TRIGGER_TCPWM1_TR_OUT04_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT04, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[4] 1645 CYHAL_TRIGGER_TCPWM1_TR_OUT05_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT05, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[5] 1646 CYHAL_TRIGGER_TCPWM1_TR_OUT05_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT05, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[5] 1647 CYHAL_TRIGGER_TCPWM1_TR_OUT06_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT06, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[6] 1648 CYHAL_TRIGGER_TCPWM1_TR_OUT06_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT06, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[6] 1649 CYHAL_TRIGGER_TCPWM1_TR_OUT07_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT07, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[7] 1650 CYHAL_TRIGGER_TCPWM1_TR_OUT07_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT07, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[7] 1651 CYHAL_TRIGGER_TCPWM1_TR_OUT08_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT08, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[8] 1652 CYHAL_TRIGGER_TCPWM1_TR_OUT08_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT08, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[8] 1653 CYHAL_TRIGGER_TCPWM1_TR_OUT09_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT09, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[9] 1654 CYHAL_TRIGGER_TCPWM1_TR_OUT09_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT09, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[9] 1655 CYHAL_TRIGGER_TCPWM1_TR_OUT010_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT010, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[10] 1656 CYHAL_TRIGGER_TCPWM1_TR_OUT010_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT010, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[10] 1657 CYHAL_TRIGGER_TCPWM1_TR_OUT011_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT011, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[11] 1658 CYHAL_TRIGGER_TCPWM1_TR_OUT011_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT011, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[11] 1659 CYHAL_TRIGGER_TCPWM1_TR_OUT012_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT012, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[12] 1660 CYHAL_TRIGGER_TCPWM1_TR_OUT012_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT012, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[12] 1661 CYHAL_TRIGGER_TCPWM1_TR_OUT013_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT013, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[13] 1662 CYHAL_TRIGGER_TCPWM1_TR_OUT013_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT013, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[13] 1663 CYHAL_TRIGGER_TCPWM1_TR_OUT014_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT014, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[14] 1664 CYHAL_TRIGGER_TCPWM1_TR_OUT014_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT014, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[14] 1665 CYHAL_TRIGGER_TCPWM1_TR_OUT015_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT015, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[15] 1666 CYHAL_TRIGGER_TCPWM1_TR_OUT015_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT015, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[15] 1667 CYHAL_TRIGGER_TCPWM1_TR_OUT016_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT016, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[16] 1668 CYHAL_TRIGGER_TCPWM1_TR_OUT016_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT016, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[16] 1669 CYHAL_TRIGGER_TCPWM1_TR_OUT017_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT017, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[17] 1670 CYHAL_TRIGGER_TCPWM1_TR_OUT017_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT017, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[17] 1671 CYHAL_TRIGGER_TCPWM1_TR_OUT018_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT018, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[18] 1672 CYHAL_TRIGGER_TCPWM1_TR_OUT018_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT018, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[18] 1673 CYHAL_TRIGGER_TCPWM1_TR_OUT019_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT019, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[19] 1674 CYHAL_TRIGGER_TCPWM1_TR_OUT019_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT019, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[19] 1675 CYHAL_TRIGGER_TCPWM1_TR_OUT020_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT020, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[20] 1676 CYHAL_TRIGGER_TCPWM1_TR_OUT020_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT020, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[20] 1677 CYHAL_TRIGGER_TCPWM1_TR_OUT021_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT021, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[21] 1678 CYHAL_TRIGGER_TCPWM1_TR_OUT021_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT021, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[21] 1679 CYHAL_TRIGGER_TCPWM1_TR_OUT022_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT022, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[22] 1680 CYHAL_TRIGGER_TCPWM1_TR_OUT022_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT022, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[22] 1681 CYHAL_TRIGGER_TCPWM1_TR_OUT023_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT023, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[23] 1682 CYHAL_TRIGGER_TCPWM1_TR_OUT023_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT023, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[23] 1683 CYHAL_TRIGGER_TCPWM1_TR_OUT024_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT024, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[24] 1684 CYHAL_TRIGGER_TCPWM1_TR_OUT024_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT024, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[24] 1685 CYHAL_TRIGGER_TCPWM1_TR_OUT025_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT025, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[25] 1686 CYHAL_TRIGGER_TCPWM1_TR_OUT025_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT025, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[25] 1687 CYHAL_TRIGGER_TCPWM1_TR_OUT026_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT026, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[26] 1688 CYHAL_TRIGGER_TCPWM1_TR_OUT026_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT026, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[26] 1689 CYHAL_TRIGGER_TCPWM1_TR_OUT027_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT027, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[27] 1690 CYHAL_TRIGGER_TCPWM1_TR_OUT027_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT027, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[27] 1691 CYHAL_TRIGGER_TCPWM1_TR_OUT028_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT028, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[28] 1692 CYHAL_TRIGGER_TCPWM1_TR_OUT028_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT028, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[28] 1693 CYHAL_TRIGGER_TCPWM1_TR_OUT029_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT029, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[29] 1694 CYHAL_TRIGGER_TCPWM1_TR_OUT029_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT029, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[29] 1695 CYHAL_TRIGGER_TCPWM1_TR_OUT030_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT030, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[30] 1696 CYHAL_TRIGGER_TCPWM1_TR_OUT030_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT030, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[30] 1697 CYHAL_TRIGGER_TCPWM1_TR_OUT031_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT031, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[31] 1698 CYHAL_TRIGGER_TCPWM1_TR_OUT031_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT031, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[31] 1699 CYHAL_TRIGGER_TCPWM1_TR_OUT032_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT032, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[32] 1700 CYHAL_TRIGGER_TCPWM1_TR_OUT032_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT032, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[32] 1701 CYHAL_TRIGGER_TCPWM1_TR_OUT033_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT033, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[33] 1702 CYHAL_TRIGGER_TCPWM1_TR_OUT033_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT033, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[33] 1703 CYHAL_TRIGGER_TCPWM1_TR_OUT034_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT034, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[34] 1704 CYHAL_TRIGGER_TCPWM1_TR_OUT034_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT034, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[34] 1705 CYHAL_TRIGGER_TCPWM1_TR_OUT035_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT035, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[35] 1706 CYHAL_TRIGGER_TCPWM1_TR_OUT035_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT035, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[35] 1707 CYHAL_TRIGGER_TCPWM1_TR_OUT036_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT036, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[36] 1708 CYHAL_TRIGGER_TCPWM1_TR_OUT036_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT036, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[36] 1709 CYHAL_TRIGGER_TCPWM1_TR_OUT037_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT037, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[37] 1710 CYHAL_TRIGGER_TCPWM1_TR_OUT037_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT037, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[37] 1711 CYHAL_TRIGGER_TCPWM1_TR_OUT038_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT038, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[38] 1712 CYHAL_TRIGGER_TCPWM1_TR_OUT038_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT038, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[38] 1713 CYHAL_TRIGGER_TCPWM1_TR_OUT039_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT039, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[39] 1714 CYHAL_TRIGGER_TCPWM1_TR_OUT039_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT039, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[39] 1715 CYHAL_TRIGGER_TCPWM1_TR_OUT040_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT040, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[40] 1716 CYHAL_TRIGGER_TCPWM1_TR_OUT040_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT040, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[40] 1717 CYHAL_TRIGGER_TCPWM1_TR_OUT041_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT041, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[41] 1718 CYHAL_TRIGGER_TCPWM1_TR_OUT041_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT041, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[41] 1719 CYHAL_TRIGGER_TCPWM1_TR_OUT042_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT042, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[42] 1720 CYHAL_TRIGGER_TCPWM1_TR_OUT042_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT042, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[42] 1721 CYHAL_TRIGGER_TCPWM1_TR_OUT043_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT043, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[43] 1722 CYHAL_TRIGGER_TCPWM1_TR_OUT043_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT043, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[43] 1723 CYHAL_TRIGGER_TCPWM1_TR_OUT044_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT044, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[44] 1724 CYHAL_TRIGGER_TCPWM1_TR_OUT044_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT044, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[44] 1725 CYHAL_TRIGGER_TCPWM1_TR_OUT045_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT045, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[45] 1726 CYHAL_TRIGGER_TCPWM1_TR_OUT045_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT045, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[45] 1727 CYHAL_TRIGGER_TCPWM1_TR_OUT046_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT046, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[46] 1728 CYHAL_TRIGGER_TCPWM1_TR_OUT046_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT046, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[46] 1729 CYHAL_TRIGGER_TCPWM1_TR_OUT047_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT047, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[47] 1730 CYHAL_TRIGGER_TCPWM1_TR_OUT047_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT047, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[47] 1731 CYHAL_TRIGGER_TCPWM1_TR_OUT048_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT048, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[48] 1732 CYHAL_TRIGGER_TCPWM1_TR_OUT048_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT048, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[48] 1733 CYHAL_TRIGGER_TCPWM1_TR_OUT049_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT049, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[49] 1734 CYHAL_TRIGGER_TCPWM1_TR_OUT049_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT049, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[49] 1735 CYHAL_TRIGGER_TCPWM1_TR_OUT050_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT050, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[50] 1736 CYHAL_TRIGGER_TCPWM1_TR_OUT050_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT050, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[50] 1737 CYHAL_TRIGGER_TCPWM1_TR_OUT051_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT051, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[51] 1738 CYHAL_TRIGGER_TCPWM1_TR_OUT051_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT051, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[51] 1739 CYHAL_TRIGGER_TCPWM1_TR_OUT052_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT052, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[52] 1740 CYHAL_TRIGGER_TCPWM1_TR_OUT052_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT052, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[52] 1741 CYHAL_TRIGGER_TCPWM1_TR_OUT053_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT053, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[53] 1742 CYHAL_TRIGGER_TCPWM1_TR_OUT053_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT053, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[53] 1743 CYHAL_TRIGGER_TCPWM1_TR_OUT054_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT054, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[54] 1744 CYHAL_TRIGGER_TCPWM1_TR_OUT054_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT054, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[54] 1745 CYHAL_TRIGGER_TCPWM1_TR_OUT055_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT055, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[55] 1746 CYHAL_TRIGGER_TCPWM1_TR_OUT055_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT055, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[55] 1747 CYHAL_TRIGGER_TCPWM1_TR_OUT056_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT056, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[56] 1748 CYHAL_TRIGGER_TCPWM1_TR_OUT056_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT056, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[56] 1749 CYHAL_TRIGGER_TCPWM1_TR_OUT057_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT057, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[57] 1750 CYHAL_TRIGGER_TCPWM1_TR_OUT057_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT057, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[57] 1751 CYHAL_TRIGGER_TCPWM1_TR_OUT058_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT058, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[58] 1752 CYHAL_TRIGGER_TCPWM1_TR_OUT058_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT058, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[58] 1753 CYHAL_TRIGGER_TCPWM1_TR_OUT059_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT059, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[59] 1754 CYHAL_TRIGGER_TCPWM1_TR_OUT059_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT059, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[59] 1755 CYHAL_TRIGGER_TCPWM1_TR_OUT060_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT060, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[60] 1756 CYHAL_TRIGGER_TCPWM1_TR_OUT060_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT060, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[60] 1757 CYHAL_TRIGGER_TCPWM1_TR_OUT061_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT061, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[61] 1758 CYHAL_TRIGGER_TCPWM1_TR_OUT061_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT061, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[61] 1759 CYHAL_TRIGGER_TCPWM1_TR_OUT062_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT062, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[62] 1760 CYHAL_TRIGGER_TCPWM1_TR_OUT062_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT062, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[62] 1761 CYHAL_TRIGGER_TCPWM1_TR_OUT063_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT063, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[63] 1762 CYHAL_TRIGGER_TCPWM1_TR_OUT063_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT063, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[63] 1763 CYHAL_TRIGGER_TCPWM1_TR_OUT064_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT064, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[64] 1764 CYHAL_TRIGGER_TCPWM1_TR_OUT064_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT064, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[64] 1765 CYHAL_TRIGGER_TCPWM1_TR_OUT065_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT065, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[65] 1766 CYHAL_TRIGGER_TCPWM1_TR_OUT065_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT065, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[65] 1767 CYHAL_TRIGGER_TCPWM1_TR_OUT066_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT066, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[66] 1768 CYHAL_TRIGGER_TCPWM1_TR_OUT066_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT066, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[66] 1769 CYHAL_TRIGGER_TCPWM1_TR_OUT067_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT067, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[67] 1770 CYHAL_TRIGGER_TCPWM1_TR_OUT067_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT067, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[67] 1771 CYHAL_TRIGGER_TCPWM1_TR_OUT068_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT068, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[68] 1772 CYHAL_TRIGGER_TCPWM1_TR_OUT068_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT068, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[68] 1773 CYHAL_TRIGGER_TCPWM1_TR_OUT069_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT069, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[69] 1774 CYHAL_TRIGGER_TCPWM1_TR_OUT069_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT069, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[69] 1775 CYHAL_TRIGGER_TCPWM1_TR_OUT070_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT070, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[70] 1776 CYHAL_TRIGGER_TCPWM1_TR_OUT070_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT070, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[70] 1777 CYHAL_TRIGGER_TCPWM1_TR_OUT071_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT071, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[71] 1778 CYHAL_TRIGGER_TCPWM1_TR_OUT071_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT071, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[71] 1779 CYHAL_TRIGGER_TCPWM1_TR_OUT072_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT072, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[72] 1780 CYHAL_TRIGGER_TCPWM1_TR_OUT072_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT072, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[72] 1781 CYHAL_TRIGGER_TCPWM1_TR_OUT073_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT073, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[73] 1782 CYHAL_TRIGGER_TCPWM1_TR_OUT073_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT073, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[73] 1783 CYHAL_TRIGGER_TCPWM1_TR_OUT074_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT074, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[74] 1784 CYHAL_TRIGGER_TCPWM1_TR_OUT074_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT074, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[74] 1785 CYHAL_TRIGGER_TCPWM1_TR_OUT075_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT075, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[75] 1786 CYHAL_TRIGGER_TCPWM1_TR_OUT075_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT075, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[75] 1787 CYHAL_TRIGGER_TCPWM1_TR_OUT076_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT076, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[76] 1788 CYHAL_TRIGGER_TCPWM1_TR_OUT076_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT076, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[76] 1789 CYHAL_TRIGGER_TCPWM1_TR_OUT077_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT077, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[77] 1790 CYHAL_TRIGGER_TCPWM1_TR_OUT077_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT077, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[77] 1791 CYHAL_TRIGGER_TCPWM1_TR_OUT078_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT078, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[78] 1792 CYHAL_TRIGGER_TCPWM1_TR_OUT078_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT078, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[78] 1793 CYHAL_TRIGGER_TCPWM1_TR_OUT079_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT079, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[79] 1794 CYHAL_TRIGGER_TCPWM1_TR_OUT079_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT079, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[79] 1795 CYHAL_TRIGGER_TCPWM1_TR_OUT080_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT080, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[80] 1796 CYHAL_TRIGGER_TCPWM1_TR_OUT080_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT080, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[80] 1797 CYHAL_TRIGGER_TCPWM1_TR_OUT081_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT081, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[81] 1798 CYHAL_TRIGGER_TCPWM1_TR_OUT081_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT081, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[81] 1799 CYHAL_TRIGGER_TCPWM1_TR_OUT082_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT082, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[82] 1800 CYHAL_TRIGGER_TCPWM1_TR_OUT082_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT082, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[82] 1801 CYHAL_TRIGGER_TCPWM1_TR_OUT083_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT083, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[83] 1802 CYHAL_TRIGGER_TCPWM1_TR_OUT083_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT083, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[83] 1803 CYHAL_TRIGGER_TCPWM1_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[256] 1804 CYHAL_TRIGGER_TCPWM1_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[256] 1805 CYHAL_TRIGGER_TCPWM1_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[257] 1806 CYHAL_TRIGGER_TCPWM1_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[257] 1807 CYHAL_TRIGGER_TCPWM1_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[258] 1808 CYHAL_TRIGGER_TCPWM1_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[258] 1809 CYHAL_TRIGGER_TCPWM1_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[259] 1810 CYHAL_TRIGGER_TCPWM1_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[259] 1811 CYHAL_TRIGGER_TCPWM1_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[260] 1812 CYHAL_TRIGGER_TCPWM1_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[260] 1813 CYHAL_TRIGGER_TCPWM1_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[261] 1814 CYHAL_TRIGGER_TCPWM1_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[261] 1815 CYHAL_TRIGGER_TCPWM1_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[262] 1816 CYHAL_TRIGGER_TCPWM1_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[262] 1817 CYHAL_TRIGGER_TCPWM1_TR_OUT0263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[263] 1818 CYHAL_TRIGGER_TCPWM1_TR_OUT0263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[263] 1819 CYHAL_TRIGGER_TCPWM1_TR_OUT0264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[264] 1820 CYHAL_TRIGGER_TCPWM1_TR_OUT0264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[264] 1821 CYHAL_TRIGGER_TCPWM1_TR_OUT0265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[265] 1822 CYHAL_TRIGGER_TCPWM1_TR_OUT0265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[265] 1823 CYHAL_TRIGGER_TCPWM1_TR_OUT0266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[266] 1824 CYHAL_TRIGGER_TCPWM1_TR_OUT0266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[266] 1825 CYHAL_TRIGGER_TCPWM1_TR_OUT0267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[267] 1826 CYHAL_TRIGGER_TCPWM1_TR_OUT0267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[267] 1827 CYHAL_TRIGGER_TCPWM1_TR_OUT0512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[512] 1828 CYHAL_TRIGGER_TCPWM1_TR_OUT0512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[512] 1829 CYHAL_TRIGGER_TCPWM1_TR_OUT0513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[513] 1830 CYHAL_TRIGGER_TCPWM1_TR_OUT0513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[513] 1831 CYHAL_TRIGGER_TCPWM1_TR_OUT0514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[514] 1832 CYHAL_TRIGGER_TCPWM1_TR_OUT0514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[514] 1833 CYHAL_TRIGGER_TCPWM1_TR_OUT0515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[515] 1834 CYHAL_TRIGGER_TCPWM1_TR_OUT0515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[515] 1835 CYHAL_TRIGGER_TCPWM1_TR_OUT0516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[516] 1836 CYHAL_TRIGGER_TCPWM1_TR_OUT0516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[516] 1837 CYHAL_TRIGGER_TCPWM1_TR_OUT0517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[517] 1838 CYHAL_TRIGGER_TCPWM1_TR_OUT0517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[517] 1839 CYHAL_TRIGGER_TCPWM1_TR_OUT0518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[518] 1840 CYHAL_TRIGGER_TCPWM1_TR_OUT0518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[518] 1841 CYHAL_TRIGGER_TCPWM1_TR_OUT0519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[519] 1842 CYHAL_TRIGGER_TCPWM1_TR_OUT0519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[519] 1843 CYHAL_TRIGGER_TCPWM1_TR_OUT0520_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0520, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[520] 1844 CYHAL_TRIGGER_TCPWM1_TR_OUT0520_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0520, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[520] 1845 CYHAL_TRIGGER_TCPWM1_TR_OUT0521_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0521, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[521] 1846 CYHAL_TRIGGER_TCPWM1_TR_OUT0521_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0521, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[521] 1847 CYHAL_TRIGGER_TCPWM1_TR_OUT0522_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0522, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[522] 1848 CYHAL_TRIGGER_TCPWM1_TR_OUT0522_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0522, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[522] 1849 CYHAL_TRIGGER_TCPWM1_TR_OUT0523_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0523, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[523] 1850 CYHAL_TRIGGER_TCPWM1_TR_OUT0523_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0523, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[523] 1851 CYHAL_TRIGGER_TCPWM1_TR_OUT0524_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0524, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out0[524] 1852 CYHAL_TRIGGER_TCPWM1_TR_OUT0524_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT0524, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out0[524] 1853 CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[0] 1854 CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[0] 1855 CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[1] 1856 CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[1] 1857 CYHAL_TRIGGER_TCPWM0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[2] 1858 CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[2] 1859 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[256] 1860 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[256] 1861 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[257] 1862 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[257] 1863 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[258] 1864 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[258] 1865 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[512] 1866 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[512] 1867 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[513] 1868 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[513] 1869 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[514] 1870 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[514] 1871 CYHAL_TRIGGER_TCPWM1_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[0] 1872 CYHAL_TRIGGER_TCPWM1_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[0] 1873 CYHAL_TRIGGER_TCPWM1_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[1] 1874 CYHAL_TRIGGER_TCPWM1_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[1] 1875 CYHAL_TRIGGER_TCPWM1_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[2] 1876 CYHAL_TRIGGER_TCPWM1_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[2] 1877 CYHAL_TRIGGER_TCPWM1_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[3] 1878 CYHAL_TRIGGER_TCPWM1_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[3] 1879 CYHAL_TRIGGER_TCPWM1_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[4] 1880 CYHAL_TRIGGER_TCPWM1_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[4] 1881 CYHAL_TRIGGER_TCPWM1_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[5] 1882 CYHAL_TRIGGER_TCPWM1_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[5] 1883 CYHAL_TRIGGER_TCPWM1_TR_OUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[6] 1884 CYHAL_TRIGGER_TCPWM1_TR_OUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[6] 1885 CYHAL_TRIGGER_TCPWM1_TR_OUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[7] 1886 CYHAL_TRIGGER_TCPWM1_TR_OUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[7] 1887 CYHAL_TRIGGER_TCPWM1_TR_OUT18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT18, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[8] 1888 CYHAL_TRIGGER_TCPWM1_TR_OUT18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT18, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[8] 1889 CYHAL_TRIGGER_TCPWM1_TR_OUT19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT19, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[9] 1890 CYHAL_TRIGGER_TCPWM1_TR_OUT19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT19, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[9] 1891 CYHAL_TRIGGER_TCPWM1_TR_OUT110_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT110, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[10] 1892 CYHAL_TRIGGER_TCPWM1_TR_OUT110_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT110, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[10] 1893 CYHAL_TRIGGER_TCPWM1_TR_OUT111_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT111, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[11] 1894 CYHAL_TRIGGER_TCPWM1_TR_OUT111_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT111, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[11] 1895 CYHAL_TRIGGER_TCPWM1_TR_OUT112_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT112, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[12] 1896 CYHAL_TRIGGER_TCPWM1_TR_OUT112_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT112, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[12] 1897 CYHAL_TRIGGER_TCPWM1_TR_OUT113_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT113, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[13] 1898 CYHAL_TRIGGER_TCPWM1_TR_OUT113_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT113, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[13] 1899 CYHAL_TRIGGER_TCPWM1_TR_OUT114_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT114, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[14] 1900 CYHAL_TRIGGER_TCPWM1_TR_OUT114_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT114, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[14] 1901 CYHAL_TRIGGER_TCPWM1_TR_OUT115_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT115, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[15] 1902 CYHAL_TRIGGER_TCPWM1_TR_OUT115_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT115, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[15] 1903 CYHAL_TRIGGER_TCPWM1_TR_OUT116_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT116, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[16] 1904 CYHAL_TRIGGER_TCPWM1_TR_OUT116_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT116, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[16] 1905 CYHAL_TRIGGER_TCPWM1_TR_OUT117_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT117, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[17] 1906 CYHAL_TRIGGER_TCPWM1_TR_OUT117_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT117, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[17] 1907 CYHAL_TRIGGER_TCPWM1_TR_OUT118_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT118, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[18] 1908 CYHAL_TRIGGER_TCPWM1_TR_OUT118_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT118, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[18] 1909 CYHAL_TRIGGER_TCPWM1_TR_OUT119_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT119, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[19] 1910 CYHAL_TRIGGER_TCPWM1_TR_OUT119_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT119, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[19] 1911 CYHAL_TRIGGER_TCPWM1_TR_OUT120_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT120, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[20] 1912 CYHAL_TRIGGER_TCPWM1_TR_OUT120_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT120, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[20] 1913 CYHAL_TRIGGER_TCPWM1_TR_OUT121_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT121, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[21] 1914 CYHAL_TRIGGER_TCPWM1_TR_OUT121_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT121, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[21] 1915 CYHAL_TRIGGER_TCPWM1_TR_OUT122_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT122, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[22] 1916 CYHAL_TRIGGER_TCPWM1_TR_OUT122_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT122, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[22] 1917 CYHAL_TRIGGER_TCPWM1_TR_OUT123_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT123, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[23] 1918 CYHAL_TRIGGER_TCPWM1_TR_OUT123_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT123, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[23] 1919 CYHAL_TRIGGER_TCPWM1_TR_OUT124_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT124, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[24] 1920 CYHAL_TRIGGER_TCPWM1_TR_OUT124_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT124, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[24] 1921 CYHAL_TRIGGER_TCPWM1_TR_OUT125_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT125, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[25] 1922 CYHAL_TRIGGER_TCPWM1_TR_OUT125_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT125, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[25] 1923 CYHAL_TRIGGER_TCPWM1_TR_OUT126_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT126, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[26] 1924 CYHAL_TRIGGER_TCPWM1_TR_OUT126_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT126, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[26] 1925 CYHAL_TRIGGER_TCPWM1_TR_OUT127_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT127, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[27] 1926 CYHAL_TRIGGER_TCPWM1_TR_OUT127_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT127, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[27] 1927 CYHAL_TRIGGER_TCPWM1_TR_OUT128_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT128, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[28] 1928 CYHAL_TRIGGER_TCPWM1_TR_OUT128_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT128, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[28] 1929 CYHAL_TRIGGER_TCPWM1_TR_OUT129_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT129, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[29] 1930 CYHAL_TRIGGER_TCPWM1_TR_OUT129_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT129, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[29] 1931 CYHAL_TRIGGER_TCPWM1_TR_OUT130_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT130, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[30] 1932 CYHAL_TRIGGER_TCPWM1_TR_OUT130_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT130, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[30] 1933 CYHAL_TRIGGER_TCPWM1_TR_OUT131_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT131, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[31] 1934 CYHAL_TRIGGER_TCPWM1_TR_OUT131_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT131, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[31] 1935 CYHAL_TRIGGER_TCPWM1_TR_OUT132_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT132, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[32] 1936 CYHAL_TRIGGER_TCPWM1_TR_OUT132_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT132, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[32] 1937 CYHAL_TRIGGER_TCPWM1_TR_OUT133_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT133, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[33] 1938 CYHAL_TRIGGER_TCPWM1_TR_OUT133_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT133, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[33] 1939 CYHAL_TRIGGER_TCPWM1_TR_OUT134_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT134, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[34] 1940 CYHAL_TRIGGER_TCPWM1_TR_OUT134_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT134, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[34] 1941 CYHAL_TRIGGER_TCPWM1_TR_OUT135_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT135, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[35] 1942 CYHAL_TRIGGER_TCPWM1_TR_OUT135_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT135, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[35] 1943 CYHAL_TRIGGER_TCPWM1_TR_OUT136_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT136, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[36] 1944 CYHAL_TRIGGER_TCPWM1_TR_OUT136_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT136, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[36] 1945 CYHAL_TRIGGER_TCPWM1_TR_OUT137_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT137, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[37] 1946 CYHAL_TRIGGER_TCPWM1_TR_OUT137_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT137, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[37] 1947 CYHAL_TRIGGER_TCPWM1_TR_OUT138_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT138, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[38] 1948 CYHAL_TRIGGER_TCPWM1_TR_OUT138_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT138, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[38] 1949 CYHAL_TRIGGER_TCPWM1_TR_OUT139_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT139, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[39] 1950 CYHAL_TRIGGER_TCPWM1_TR_OUT139_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT139, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[39] 1951 CYHAL_TRIGGER_TCPWM1_TR_OUT140_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT140, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[40] 1952 CYHAL_TRIGGER_TCPWM1_TR_OUT140_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT140, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[40] 1953 CYHAL_TRIGGER_TCPWM1_TR_OUT141_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT141, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[41] 1954 CYHAL_TRIGGER_TCPWM1_TR_OUT141_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT141, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[41] 1955 CYHAL_TRIGGER_TCPWM1_TR_OUT142_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT142, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[42] 1956 CYHAL_TRIGGER_TCPWM1_TR_OUT142_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT142, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[42] 1957 CYHAL_TRIGGER_TCPWM1_TR_OUT143_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT143, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[43] 1958 CYHAL_TRIGGER_TCPWM1_TR_OUT143_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT143, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[43] 1959 CYHAL_TRIGGER_TCPWM1_TR_OUT144_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT144, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[44] 1960 CYHAL_TRIGGER_TCPWM1_TR_OUT144_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT144, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[44] 1961 CYHAL_TRIGGER_TCPWM1_TR_OUT145_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT145, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[45] 1962 CYHAL_TRIGGER_TCPWM1_TR_OUT145_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT145, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[45] 1963 CYHAL_TRIGGER_TCPWM1_TR_OUT146_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT146, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[46] 1964 CYHAL_TRIGGER_TCPWM1_TR_OUT146_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT146, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[46] 1965 CYHAL_TRIGGER_TCPWM1_TR_OUT147_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT147, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[47] 1966 CYHAL_TRIGGER_TCPWM1_TR_OUT147_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT147, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[47] 1967 CYHAL_TRIGGER_TCPWM1_TR_OUT148_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT148, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[48] 1968 CYHAL_TRIGGER_TCPWM1_TR_OUT148_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT148, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[48] 1969 CYHAL_TRIGGER_TCPWM1_TR_OUT149_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT149, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[49] 1970 CYHAL_TRIGGER_TCPWM1_TR_OUT149_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT149, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[49] 1971 CYHAL_TRIGGER_TCPWM1_TR_OUT150_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT150, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[50] 1972 CYHAL_TRIGGER_TCPWM1_TR_OUT150_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT150, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[50] 1973 CYHAL_TRIGGER_TCPWM1_TR_OUT151_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT151, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[51] 1974 CYHAL_TRIGGER_TCPWM1_TR_OUT151_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT151, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[51] 1975 CYHAL_TRIGGER_TCPWM1_TR_OUT152_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT152, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[52] 1976 CYHAL_TRIGGER_TCPWM1_TR_OUT152_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT152, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[52] 1977 CYHAL_TRIGGER_TCPWM1_TR_OUT153_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT153, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[53] 1978 CYHAL_TRIGGER_TCPWM1_TR_OUT153_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT153, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[53] 1979 CYHAL_TRIGGER_TCPWM1_TR_OUT154_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT154, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[54] 1980 CYHAL_TRIGGER_TCPWM1_TR_OUT154_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT154, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[54] 1981 CYHAL_TRIGGER_TCPWM1_TR_OUT155_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT155, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[55] 1982 CYHAL_TRIGGER_TCPWM1_TR_OUT155_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT155, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[55] 1983 CYHAL_TRIGGER_TCPWM1_TR_OUT156_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT156, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[56] 1984 CYHAL_TRIGGER_TCPWM1_TR_OUT156_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT156, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[56] 1985 CYHAL_TRIGGER_TCPWM1_TR_OUT157_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT157, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[57] 1986 CYHAL_TRIGGER_TCPWM1_TR_OUT157_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT157, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[57] 1987 CYHAL_TRIGGER_TCPWM1_TR_OUT158_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT158, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[58] 1988 CYHAL_TRIGGER_TCPWM1_TR_OUT158_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT158, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[58] 1989 CYHAL_TRIGGER_TCPWM1_TR_OUT159_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT159, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[59] 1990 CYHAL_TRIGGER_TCPWM1_TR_OUT159_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT159, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[59] 1991 CYHAL_TRIGGER_TCPWM1_TR_OUT160_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT160, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[60] 1992 CYHAL_TRIGGER_TCPWM1_TR_OUT160_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT160, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[60] 1993 CYHAL_TRIGGER_TCPWM1_TR_OUT161_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT161, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[61] 1994 CYHAL_TRIGGER_TCPWM1_TR_OUT161_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT161, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[61] 1995 CYHAL_TRIGGER_TCPWM1_TR_OUT162_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT162, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[62] 1996 CYHAL_TRIGGER_TCPWM1_TR_OUT162_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT162, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[62] 1997 CYHAL_TRIGGER_TCPWM1_TR_OUT163_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT163, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[63] 1998 CYHAL_TRIGGER_TCPWM1_TR_OUT163_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT163, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[63] 1999 CYHAL_TRIGGER_TCPWM1_TR_OUT164_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT164, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[64] 2000 CYHAL_TRIGGER_TCPWM1_TR_OUT164_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT164, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[64] 2001 CYHAL_TRIGGER_TCPWM1_TR_OUT165_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT165, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[65] 2002 CYHAL_TRIGGER_TCPWM1_TR_OUT165_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT165, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[65] 2003 CYHAL_TRIGGER_TCPWM1_TR_OUT166_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT166, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[66] 2004 CYHAL_TRIGGER_TCPWM1_TR_OUT166_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT166, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[66] 2005 CYHAL_TRIGGER_TCPWM1_TR_OUT167_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT167, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[67] 2006 CYHAL_TRIGGER_TCPWM1_TR_OUT167_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT167, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[67] 2007 CYHAL_TRIGGER_TCPWM1_TR_OUT168_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT168, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[68] 2008 CYHAL_TRIGGER_TCPWM1_TR_OUT168_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT168, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[68] 2009 CYHAL_TRIGGER_TCPWM1_TR_OUT169_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT169, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[69] 2010 CYHAL_TRIGGER_TCPWM1_TR_OUT169_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT169, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[69] 2011 CYHAL_TRIGGER_TCPWM1_TR_OUT170_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT170, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[70] 2012 CYHAL_TRIGGER_TCPWM1_TR_OUT170_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT170, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[70] 2013 CYHAL_TRIGGER_TCPWM1_TR_OUT171_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT171, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[71] 2014 CYHAL_TRIGGER_TCPWM1_TR_OUT171_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT171, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[71] 2015 CYHAL_TRIGGER_TCPWM1_TR_OUT172_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT172, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[72] 2016 CYHAL_TRIGGER_TCPWM1_TR_OUT172_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT172, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[72] 2017 CYHAL_TRIGGER_TCPWM1_TR_OUT173_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT173, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[73] 2018 CYHAL_TRIGGER_TCPWM1_TR_OUT173_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT173, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[73] 2019 CYHAL_TRIGGER_TCPWM1_TR_OUT174_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT174, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[74] 2020 CYHAL_TRIGGER_TCPWM1_TR_OUT174_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT174, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[74] 2021 CYHAL_TRIGGER_TCPWM1_TR_OUT175_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT175, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[75] 2022 CYHAL_TRIGGER_TCPWM1_TR_OUT175_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT175, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[75] 2023 CYHAL_TRIGGER_TCPWM1_TR_OUT176_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT176, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[76] 2024 CYHAL_TRIGGER_TCPWM1_TR_OUT176_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT176, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[76] 2025 CYHAL_TRIGGER_TCPWM1_TR_OUT177_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT177, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[77] 2026 CYHAL_TRIGGER_TCPWM1_TR_OUT177_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT177, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[77] 2027 CYHAL_TRIGGER_TCPWM1_TR_OUT178_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT178, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[78] 2028 CYHAL_TRIGGER_TCPWM1_TR_OUT178_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT178, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[78] 2029 CYHAL_TRIGGER_TCPWM1_TR_OUT179_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT179, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[79] 2030 CYHAL_TRIGGER_TCPWM1_TR_OUT179_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT179, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[79] 2031 CYHAL_TRIGGER_TCPWM1_TR_OUT180_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT180, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[80] 2032 CYHAL_TRIGGER_TCPWM1_TR_OUT180_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT180, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[80] 2033 CYHAL_TRIGGER_TCPWM1_TR_OUT181_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT181, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[81] 2034 CYHAL_TRIGGER_TCPWM1_TR_OUT181_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT181, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[81] 2035 CYHAL_TRIGGER_TCPWM1_TR_OUT182_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT182, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[82] 2036 CYHAL_TRIGGER_TCPWM1_TR_OUT182_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT182, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[82] 2037 CYHAL_TRIGGER_TCPWM1_TR_OUT183_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT183, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[83] 2038 CYHAL_TRIGGER_TCPWM1_TR_OUT183_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT183, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[83] 2039 CYHAL_TRIGGER_TCPWM1_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[256] 2040 CYHAL_TRIGGER_TCPWM1_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[256] 2041 CYHAL_TRIGGER_TCPWM1_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[257] 2042 CYHAL_TRIGGER_TCPWM1_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[257] 2043 CYHAL_TRIGGER_TCPWM1_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[258] 2044 CYHAL_TRIGGER_TCPWM1_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[258] 2045 CYHAL_TRIGGER_TCPWM1_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[259] 2046 CYHAL_TRIGGER_TCPWM1_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[259] 2047 CYHAL_TRIGGER_TCPWM1_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[260] 2048 CYHAL_TRIGGER_TCPWM1_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[260] 2049 CYHAL_TRIGGER_TCPWM1_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[261] 2050 CYHAL_TRIGGER_TCPWM1_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[261] 2051 CYHAL_TRIGGER_TCPWM1_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[262] 2052 CYHAL_TRIGGER_TCPWM1_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[262] 2053 CYHAL_TRIGGER_TCPWM1_TR_OUT1263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[263] 2054 CYHAL_TRIGGER_TCPWM1_TR_OUT1263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[263] 2055 CYHAL_TRIGGER_TCPWM1_TR_OUT1264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[264] 2056 CYHAL_TRIGGER_TCPWM1_TR_OUT1264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[264] 2057 CYHAL_TRIGGER_TCPWM1_TR_OUT1265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[265] 2058 CYHAL_TRIGGER_TCPWM1_TR_OUT1265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[265] 2059 CYHAL_TRIGGER_TCPWM1_TR_OUT1266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[266] 2060 CYHAL_TRIGGER_TCPWM1_TR_OUT1266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[266] 2061 CYHAL_TRIGGER_TCPWM1_TR_OUT1267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[267] 2062 CYHAL_TRIGGER_TCPWM1_TR_OUT1267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[267] 2063 CYHAL_TRIGGER_TCPWM1_TR_OUT1512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[512] 2064 CYHAL_TRIGGER_TCPWM1_TR_OUT1512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[512] 2065 CYHAL_TRIGGER_TCPWM1_TR_OUT1513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[513] 2066 CYHAL_TRIGGER_TCPWM1_TR_OUT1513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[513] 2067 CYHAL_TRIGGER_TCPWM1_TR_OUT1514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[514] 2068 CYHAL_TRIGGER_TCPWM1_TR_OUT1514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[514] 2069 CYHAL_TRIGGER_TCPWM1_TR_OUT1515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[515] 2070 CYHAL_TRIGGER_TCPWM1_TR_OUT1515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[515] 2071 CYHAL_TRIGGER_TCPWM1_TR_OUT1516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[516] 2072 CYHAL_TRIGGER_TCPWM1_TR_OUT1516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[516] 2073 CYHAL_TRIGGER_TCPWM1_TR_OUT1517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[517] 2074 CYHAL_TRIGGER_TCPWM1_TR_OUT1517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[517] 2075 CYHAL_TRIGGER_TCPWM1_TR_OUT1518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[518] 2076 CYHAL_TRIGGER_TCPWM1_TR_OUT1518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[518] 2077 CYHAL_TRIGGER_TCPWM1_TR_OUT1519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[519] 2078 CYHAL_TRIGGER_TCPWM1_TR_OUT1519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[519] 2079 CYHAL_TRIGGER_TCPWM1_TR_OUT1520_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1520, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[520] 2080 CYHAL_TRIGGER_TCPWM1_TR_OUT1520_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1520, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[520] 2081 CYHAL_TRIGGER_TCPWM1_TR_OUT1521_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1521, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[521] 2082 CYHAL_TRIGGER_TCPWM1_TR_OUT1521_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1521, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[521] 2083 CYHAL_TRIGGER_TCPWM1_TR_OUT1522_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1522, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[522] 2084 CYHAL_TRIGGER_TCPWM1_TR_OUT1522_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1522, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[522] 2085 CYHAL_TRIGGER_TCPWM1_TR_OUT1523_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1523, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[523] 2086 CYHAL_TRIGGER_TCPWM1_TR_OUT1523_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1523, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[523] 2087 CYHAL_TRIGGER_TCPWM1_TR_OUT1524_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1524, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[1].tr_out1[524] 2088 CYHAL_TRIGGER_TCPWM1_TR_OUT1524_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM1_TR_OUT1524, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[1].tr_out1[524] 2089 CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[0] 2090 CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[0] 2091 CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[1] 2092 CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[1] 2093 CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[2] 2094 CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[2] 2095 CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[3] 2096 CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[3] 2097 CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[10].output[4] 2098 CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP10_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[10].output[4] 2099 CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[0] 2100 CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[0] 2101 CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[1] 2102 CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[1] 2103 CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[2] 2104 CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[2] 2105 CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[3] 2106 CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[3] 2107 CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[11].output[4] 2108 CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP11_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[11].output[4] 2109 CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[0] 2110 CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[0] 2111 CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[1] 2112 CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[1] 2113 CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[2] 2114 CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[2] 2115 CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[3] 2116 CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[3] 2117 CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< tr_group[12].output[4] 2118 CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TR_GROUP12_OUTPUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< tr_group[12].output[4] 2119 } cyhal_trigger_source_xmc7200_t; 2120 2121 /** Typedef from device family specific trigger source to generic trigger source */ 2122 typedef cyhal_trigger_source_xmc7200_t cyhal_source_t; 2123 2124 /** Deprecated defines for signals that can be either level or edge. */ 2125 #define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2126 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT0 (CYHAL_TRIGGER_EVTGEN0_TR_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2127 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT1 (CYHAL_TRIGGER_EVTGEN0_TR_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2128 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT2 (CYHAL_TRIGGER_EVTGEN0_TR_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2129 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT3 (CYHAL_TRIGGER_EVTGEN0_TR_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2130 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT4 (CYHAL_TRIGGER_EVTGEN0_TR_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2131 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT5 (CYHAL_TRIGGER_EVTGEN0_TR_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2132 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT6 (CYHAL_TRIGGER_EVTGEN0_TR_OUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2133 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT7 (CYHAL_TRIGGER_EVTGEN0_TR_OUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2134 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT8 (CYHAL_TRIGGER_EVTGEN0_TR_OUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2135 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT9 (CYHAL_TRIGGER_EVTGEN0_TR_OUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2136 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT10 (CYHAL_TRIGGER_EVTGEN0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2137 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT11 (CYHAL_TRIGGER_EVTGEN0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2138 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT12 (CYHAL_TRIGGER_EVTGEN0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2139 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT13 (CYHAL_TRIGGER_EVTGEN0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2140 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT14 (CYHAL_TRIGGER_EVTGEN0_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2141 #define CYHAL_TRIGGER_EVTGEN0_TR_OUT15 (CYHAL_TRIGGER_EVTGEN0_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2142 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2143 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2144 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2145 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2146 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2147 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2148 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2149 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2150 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2151 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2152 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2153 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2154 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2155 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2156 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2157 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2158 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2159 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2160 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2161 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2162 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2163 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2164 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2165 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2166 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2167 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2168 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2169 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2170 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE28_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2171 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE29_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2172 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE30_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2173 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE31_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2174 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE32_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2175 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE33_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2176 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE34_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2177 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE35_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2178 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE36_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2179 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE37_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2180 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE38_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2181 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE39_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2182 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE40_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2183 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE41_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2184 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE42_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2185 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE43_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2186 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE44_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2187 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE45_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2188 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE46_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2189 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE47_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2190 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE48_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2191 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE49_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2192 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE50_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2193 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE51_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2194 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE52_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2195 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE53_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2196 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE54_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2197 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE55_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2198 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE56_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2199 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE57_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2200 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE58_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2201 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE59_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2202 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE60_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2203 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE61_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2204 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE62_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2205 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE63_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2206 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE64_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2207 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE65_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2208 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE66_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2209 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE67_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2210 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE68_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2211 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE69_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2212 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE70_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2213 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE71_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2214 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE72 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE72_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2215 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE73 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE73_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2216 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE74 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE74_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2217 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE75 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE75_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2218 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE76 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE76_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2219 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE77 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE77_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2220 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE78 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE78_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2221 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE79 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE79_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2222 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE80 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE80_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2223 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE81 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE81_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2224 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE82 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE82_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2225 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE83 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE83_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2226 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE84 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE84_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2227 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE85 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE85_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2228 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE86 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE86_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2229 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE87 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE87_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2230 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE88 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE88_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2231 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE89 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE89_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2232 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE90 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE90_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2233 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE91 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE91_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2234 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE92 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE92_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2235 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE93 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE93_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2236 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE94 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE94_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2237 #define CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE95 (CYHAL_TRIGGER_PASS0_TR_SAR_CH_DONE95_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2238 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2239 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2240 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2241 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2242 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2243 #define CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5 (CYHAL_TRIGGER_PASS0_TR_SAR_GEN_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2244 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT0 (CYHAL_TRIGGER_PERI_TR_IO_INPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2245 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT1 (CYHAL_TRIGGER_PERI_TR_IO_INPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2246 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT2 (CYHAL_TRIGGER_PERI_TR_IO_INPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2247 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT3 (CYHAL_TRIGGER_PERI_TR_IO_INPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2248 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT4 (CYHAL_TRIGGER_PERI_TR_IO_INPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2249 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT5 (CYHAL_TRIGGER_PERI_TR_IO_INPUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2250 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT6 (CYHAL_TRIGGER_PERI_TR_IO_INPUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2251 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT7 (CYHAL_TRIGGER_PERI_TR_IO_INPUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2252 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT8 (CYHAL_TRIGGER_PERI_TR_IO_INPUT8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2253 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT9 (CYHAL_TRIGGER_PERI_TR_IO_INPUT9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2254 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT10 (CYHAL_TRIGGER_PERI_TR_IO_INPUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2255 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT11 (CYHAL_TRIGGER_PERI_TR_IO_INPUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2256 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT12 (CYHAL_TRIGGER_PERI_TR_IO_INPUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2257 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT13 (CYHAL_TRIGGER_PERI_TR_IO_INPUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2258 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT14 (CYHAL_TRIGGER_PERI_TR_IO_INPUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2259 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT15 (CYHAL_TRIGGER_PERI_TR_IO_INPUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2260 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT16 (CYHAL_TRIGGER_PERI_TR_IO_INPUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2261 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT17 (CYHAL_TRIGGER_PERI_TR_IO_INPUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2262 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT18 (CYHAL_TRIGGER_PERI_TR_IO_INPUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2263 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT19 (CYHAL_TRIGGER_PERI_TR_IO_INPUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2264 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT20 (CYHAL_TRIGGER_PERI_TR_IO_INPUT20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2265 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT21 (CYHAL_TRIGGER_PERI_TR_IO_INPUT21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2266 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT22 (CYHAL_TRIGGER_PERI_TR_IO_INPUT22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2267 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT23 (CYHAL_TRIGGER_PERI_TR_IO_INPUT23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2268 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT24 (CYHAL_TRIGGER_PERI_TR_IO_INPUT24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2269 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT25 (CYHAL_TRIGGER_PERI_TR_IO_INPUT25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2270 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT26 (CYHAL_TRIGGER_PERI_TR_IO_INPUT26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2271 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT27 (CYHAL_TRIGGER_PERI_TR_IO_INPUT27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2272 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT28 (CYHAL_TRIGGER_PERI_TR_IO_INPUT28_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2273 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT29 (CYHAL_TRIGGER_PERI_TR_IO_INPUT29_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2274 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT30 (CYHAL_TRIGGER_PERI_TR_IO_INPUT30_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2275 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT31 (CYHAL_TRIGGER_PERI_TR_IO_INPUT31_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2276 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT32 (CYHAL_TRIGGER_PERI_TR_IO_INPUT32_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2277 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT33 (CYHAL_TRIGGER_PERI_TR_IO_INPUT33_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2278 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT34 (CYHAL_TRIGGER_PERI_TR_IO_INPUT34_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2279 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT35 (CYHAL_TRIGGER_PERI_TR_IO_INPUT35_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2280 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT36 (CYHAL_TRIGGER_PERI_TR_IO_INPUT36_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2281 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT37 (CYHAL_TRIGGER_PERI_TR_IO_INPUT37_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2282 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT38 (CYHAL_TRIGGER_PERI_TR_IO_INPUT38_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2283 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT39 (CYHAL_TRIGGER_PERI_TR_IO_INPUT39_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2284 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT40 (CYHAL_TRIGGER_PERI_TR_IO_INPUT40_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2285 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT41 (CYHAL_TRIGGER_PERI_TR_IO_INPUT41_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2286 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT42 (CYHAL_TRIGGER_PERI_TR_IO_INPUT42_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2287 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT43 (CYHAL_TRIGGER_PERI_TR_IO_INPUT43_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2288 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT44 (CYHAL_TRIGGER_PERI_TR_IO_INPUT44_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2289 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT45 (CYHAL_TRIGGER_PERI_TR_IO_INPUT45_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2290 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT46 (CYHAL_TRIGGER_PERI_TR_IO_INPUT46_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2291 #define CYHAL_TRIGGER_PERI_TR_IO_INPUT47 (CYHAL_TRIGGER_PERI_TR_IO_INPUT47_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2292 #define CYHAL_TRIGGER_TCPWM0_TR_OUT00 (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2293 #define CYHAL_TRIGGER_TCPWM0_TR_OUT01 (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2294 #define CYHAL_TRIGGER_TCPWM0_TR_OUT02 (CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2295 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0256 (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2296 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0257 (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2297 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0258 (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2298 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0512 (CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2299 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0513 (CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2300 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0514 (CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2301 #define CYHAL_TRIGGER_TCPWM1_TR_OUT00 (CYHAL_TRIGGER_TCPWM1_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2302 #define CYHAL_TRIGGER_TCPWM1_TR_OUT01 (CYHAL_TRIGGER_TCPWM1_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2303 #define CYHAL_TRIGGER_TCPWM1_TR_OUT02 (CYHAL_TRIGGER_TCPWM1_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2304 #define CYHAL_TRIGGER_TCPWM1_TR_OUT03 (CYHAL_TRIGGER_TCPWM1_TR_OUT03_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2305 #define CYHAL_TRIGGER_TCPWM1_TR_OUT04 (CYHAL_TRIGGER_TCPWM1_TR_OUT04_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2306 #define CYHAL_TRIGGER_TCPWM1_TR_OUT05 (CYHAL_TRIGGER_TCPWM1_TR_OUT05_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2307 #define CYHAL_TRIGGER_TCPWM1_TR_OUT06 (CYHAL_TRIGGER_TCPWM1_TR_OUT06_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2308 #define CYHAL_TRIGGER_TCPWM1_TR_OUT07 (CYHAL_TRIGGER_TCPWM1_TR_OUT07_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2309 #define CYHAL_TRIGGER_TCPWM1_TR_OUT08 (CYHAL_TRIGGER_TCPWM1_TR_OUT08_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2310 #define CYHAL_TRIGGER_TCPWM1_TR_OUT09 (CYHAL_TRIGGER_TCPWM1_TR_OUT09_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2311 #define CYHAL_TRIGGER_TCPWM1_TR_OUT010 (CYHAL_TRIGGER_TCPWM1_TR_OUT010_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2312 #define CYHAL_TRIGGER_TCPWM1_TR_OUT011 (CYHAL_TRIGGER_TCPWM1_TR_OUT011_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2313 #define CYHAL_TRIGGER_TCPWM1_TR_OUT012 (CYHAL_TRIGGER_TCPWM1_TR_OUT012_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2314 #define CYHAL_TRIGGER_TCPWM1_TR_OUT013 (CYHAL_TRIGGER_TCPWM1_TR_OUT013_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2315 #define CYHAL_TRIGGER_TCPWM1_TR_OUT014 (CYHAL_TRIGGER_TCPWM1_TR_OUT014_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2316 #define CYHAL_TRIGGER_TCPWM1_TR_OUT015 (CYHAL_TRIGGER_TCPWM1_TR_OUT015_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2317 #define CYHAL_TRIGGER_TCPWM1_TR_OUT016 (CYHAL_TRIGGER_TCPWM1_TR_OUT016_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2318 #define CYHAL_TRIGGER_TCPWM1_TR_OUT017 (CYHAL_TRIGGER_TCPWM1_TR_OUT017_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2319 #define CYHAL_TRIGGER_TCPWM1_TR_OUT018 (CYHAL_TRIGGER_TCPWM1_TR_OUT018_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2320 #define CYHAL_TRIGGER_TCPWM1_TR_OUT019 (CYHAL_TRIGGER_TCPWM1_TR_OUT019_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2321 #define CYHAL_TRIGGER_TCPWM1_TR_OUT020 (CYHAL_TRIGGER_TCPWM1_TR_OUT020_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2322 #define CYHAL_TRIGGER_TCPWM1_TR_OUT021 (CYHAL_TRIGGER_TCPWM1_TR_OUT021_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2323 #define CYHAL_TRIGGER_TCPWM1_TR_OUT022 (CYHAL_TRIGGER_TCPWM1_TR_OUT022_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2324 #define CYHAL_TRIGGER_TCPWM1_TR_OUT023 (CYHAL_TRIGGER_TCPWM1_TR_OUT023_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2325 #define CYHAL_TRIGGER_TCPWM1_TR_OUT024 (CYHAL_TRIGGER_TCPWM1_TR_OUT024_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2326 #define CYHAL_TRIGGER_TCPWM1_TR_OUT025 (CYHAL_TRIGGER_TCPWM1_TR_OUT025_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2327 #define CYHAL_TRIGGER_TCPWM1_TR_OUT026 (CYHAL_TRIGGER_TCPWM1_TR_OUT026_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2328 #define CYHAL_TRIGGER_TCPWM1_TR_OUT027 (CYHAL_TRIGGER_TCPWM1_TR_OUT027_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2329 #define CYHAL_TRIGGER_TCPWM1_TR_OUT028 (CYHAL_TRIGGER_TCPWM1_TR_OUT028_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2330 #define CYHAL_TRIGGER_TCPWM1_TR_OUT029 (CYHAL_TRIGGER_TCPWM1_TR_OUT029_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2331 #define CYHAL_TRIGGER_TCPWM1_TR_OUT030 (CYHAL_TRIGGER_TCPWM1_TR_OUT030_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2332 #define CYHAL_TRIGGER_TCPWM1_TR_OUT031 (CYHAL_TRIGGER_TCPWM1_TR_OUT031_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2333 #define CYHAL_TRIGGER_TCPWM1_TR_OUT032 (CYHAL_TRIGGER_TCPWM1_TR_OUT032_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2334 #define CYHAL_TRIGGER_TCPWM1_TR_OUT033 (CYHAL_TRIGGER_TCPWM1_TR_OUT033_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2335 #define CYHAL_TRIGGER_TCPWM1_TR_OUT034 (CYHAL_TRIGGER_TCPWM1_TR_OUT034_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2336 #define CYHAL_TRIGGER_TCPWM1_TR_OUT035 (CYHAL_TRIGGER_TCPWM1_TR_OUT035_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2337 #define CYHAL_TRIGGER_TCPWM1_TR_OUT036 (CYHAL_TRIGGER_TCPWM1_TR_OUT036_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2338 #define CYHAL_TRIGGER_TCPWM1_TR_OUT037 (CYHAL_TRIGGER_TCPWM1_TR_OUT037_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2339 #define CYHAL_TRIGGER_TCPWM1_TR_OUT038 (CYHAL_TRIGGER_TCPWM1_TR_OUT038_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2340 #define CYHAL_TRIGGER_TCPWM1_TR_OUT039 (CYHAL_TRIGGER_TCPWM1_TR_OUT039_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2341 #define CYHAL_TRIGGER_TCPWM1_TR_OUT040 (CYHAL_TRIGGER_TCPWM1_TR_OUT040_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2342 #define CYHAL_TRIGGER_TCPWM1_TR_OUT041 (CYHAL_TRIGGER_TCPWM1_TR_OUT041_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2343 #define CYHAL_TRIGGER_TCPWM1_TR_OUT042 (CYHAL_TRIGGER_TCPWM1_TR_OUT042_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2344 #define CYHAL_TRIGGER_TCPWM1_TR_OUT043 (CYHAL_TRIGGER_TCPWM1_TR_OUT043_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2345 #define CYHAL_TRIGGER_TCPWM1_TR_OUT044 (CYHAL_TRIGGER_TCPWM1_TR_OUT044_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2346 #define CYHAL_TRIGGER_TCPWM1_TR_OUT045 (CYHAL_TRIGGER_TCPWM1_TR_OUT045_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2347 #define CYHAL_TRIGGER_TCPWM1_TR_OUT046 (CYHAL_TRIGGER_TCPWM1_TR_OUT046_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2348 #define CYHAL_TRIGGER_TCPWM1_TR_OUT047 (CYHAL_TRIGGER_TCPWM1_TR_OUT047_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2349 #define CYHAL_TRIGGER_TCPWM1_TR_OUT048 (CYHAL_TRIGGER_TCPWM1_TR_OUT048_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2350 #define CYHAL_TRIGGER_TCPWM1_TR_OUT049 (CYHAL_TRIGGER_TCPWM1_TR_OUT049_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2351 #define CYHAL_TRIGGER_TCPWM1_TR_OUT050 (CYHAL_TRIGGER_TCPWM1_TR_OUT050_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2352 #define CYHAL_TRIGGER_TCPWM1_TR_OUT051 (CYHAL_TRIGGER_TCPWM1_TR_OUT051_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2353 #define CYHAL_TRIGGER_TCPWM1_TR_OUT052 (CYHAL_TRIGGER_TCPWM1_TR_OUT052_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2354 #define CYHAL_TRIGGER_TCPWM1_TR_OUT053 (CYHAL_TRIGGER_TCPWM1_TR_OUT053_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2355 #define CYHAL_TRIGGER_TCPWM1_TR_OUT054 (CYHAL_TRIGGER_TCPWM1_TR_OUT054_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2356 #define CYHAL_TRIGGER_TCPWM1_TR_OUT055 (CYHAL_TRIGGER_TCPWM1_TR_OUT055_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2357 #define CYHAL_TRIGGER_TCPWM1_TR_OUT056 (CYHAL_TRIGGER_TCPWM1_TR_OUT056_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2358 #define CYHAL_TRIGGER_TCPWM1_TR_OUT057 (CYHAL_TRIGGER_TCPWM1_TR_OUT057_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2359 #define CYHAL_TRIGGER_TCPWM1_TR_OUT058 (CYHAL_TRIGGER_TCPWM1_TR_OUT058_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2360 #define CYHAL_TRIGGER_TCPWM1_TR_OUT059 (CYHAL_TRIGGER_TCPWM1_TR_OUT059_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2361 #define CYHAL_TRIGGER_TCPWM1_TR_OUT060 (CYHAL_TRIGGER_TCPWM1_TR_OUT060_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2362 #define CYHAL_TRIGGER_TCPWM1_TR_OUT061 (CYHAL_TRIGGER_TCPWM1_TR_OUT061_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2363 #define CYHAL_TRIGGER_TCPWM1_TR_OUT062 (CYHAL_TRIGGER_TCPWM1_TR_OUT062_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2364 #define CYHAL_TRIGGER_TCPWM1_TR_OUT063 (CYHAL_TRIGGER_TCPWM1_TR_OUT063_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2365 #define CYHAL_TRIGGER_TCPWM1_TR_OUT064 (CYHAL_TRIGGER_TCPWM1_TR_OUT064_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2366 #define CYHAL_TRIGGER_TCPWM1_TR_OUT065 (CYHAL_TRIGGER_TCPWM1_TR_OUT065_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2367 #define CYHAL_TRIGGER_TCPWM1_TR_OUT066 (CYHAL_TRIGGER_TCPWM1_TR_OUT066_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2368 #define CYHAL_TRIGGER_TCPWM1_TR_OUT067 (CYHAL_TRIGGER_TCPWM1_TR_OUT067_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2369 #define CYHAL_TRIGGER_TCPWM1_TR_OUT068 (CYHAL_TRIGGER_TCPWM1_TR_OUT068_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2370 #define CYHAL_TRIGGER_TCPWM1_TR_OUT069 (CYHAL_TRIGGER_TCPWM1_TR_OUT069_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2371 #define CYHAL_TRIGGER_TCPWM1_TR_OUT070 (CYHAL_TRIGGER_TCPWM1_TR_OUT070_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2372 #define CYHAL_TRIGGER_TCPWM1_TR_OUT071 (CYHAL_TRIGGER_TCPWM1_TR_OUT071_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2373 #define CYHAL_TRIGGER_TCPWM1_TR_OUT072 (CYHAL_TRIGGER_TCPWM1_TR_OUT072_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2374 #define CYHAL_TRIGGER_TCPWM1_TR_OUT073 (CYHAL_TRIGGER_TCPWM1_TR_OUT073_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2375 #define CYHAL_TRIGGER_TCPWM1_TR_OUT074 (CYHAL_TRIGGER_TCPWM1_TR_OUT074_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2376 #define CYHAL_TRIGGER_TCPWM1_TR_OUT075 (CYHAL_TRIGGER_TCPWM1_TR_OUT075_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2377 #define CYHAL_TRIGGER_TCPWM1_TR_OUT076 (CYHAL_TRIGGER_TCPWM1_TR_OUT076_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2378 #define CYHAL_TRIGGER_TCPWM1_TR_OUT077 (CYHAL_TRIGGER_TCPWM1_TR_OUT077_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2379 #define CYHAL_TRIGGER_TCPWM1_TR_OUT078 (CYHAL_TRIGGER_TCPWM1_TR_OUT078_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2380 #define CYHAL_TRIGGER_TCPWM1_TR_OUT079 (CYHAL_TRIGGER_TCPWM1_TR_OUT079_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2381 #define CYHAL_TRIGGER_TCPWM1_TR_OUT080 (CYHAL_TRIGGER_TCPWM1_TR_OUT080_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2382 #define CYHAL_TRIGGER_TCPWM1_TR_OUT081 (CYHAL_TRIGGER_TCPWM1_TR_OUT081_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2383 #define CYHAL_TRIGGER_TCPWM1_TR_OUT082 (CYHAL_TRIGGER_TCPWM1_TR_OUT082_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2384 #define CYHAL_TRIGGER_TCPWM1_TR_OUT083 (CYHAL_TRIGGER_TCPWM1_TR_OUT083_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2385 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0256 (CYHAL_TRIGGER_TCPWM1_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2386 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0257 (CYHAL_TRIGGER_TCPWM1_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2387 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0258 (CYHAL_TRIGGER_TCPWM1_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2388 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0259 (CYHAL_TRIGGER_TCPWM1_TR_OUT0259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2389 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0260 (CYHAL_TRIGGER_TCPWM1_TR_OUT0260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2390 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0261 (CYHAL_TRIGGER_TCPWM1_TR_OUT0261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2391 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0262 (CYHAL_TRIGGER_TCPWM1_TR_OUT0262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2392 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0263 (CYHAL_TRIGGER_TCPWM1_TR_OUT0263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2393 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0264 (CYHAL_TRIGGER_TCPWM1_TR_OUT0264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2394 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0265 (CYHAL_TRIGGER_TCPWM1_TR_OUT0265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2395 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0266 (CYHAL_TRIGGER_TCPWM1_TR_OUT0266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2396 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0267 (CYHAL_TRIGGER_TCPWM1_TR_OUT0267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2397 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0512 (CYHAL_TRIGGER_TCPWM1_TR_OUT0512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2398 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0513 (CYHAL_TRIGGER_TCPWM1_TR_OUT0513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2399 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0514 (CYHAL_TRIGGER_TCPWM1_TR_OUT0514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2400 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0515 (CYHAL_TRIGGER_TCPWM1_TR_OUT0515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2401 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0516 (CYHAL_TRIGGER_TCPWM1_TR_OUT0516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2402 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0517 (CYHAL_TRIGGER_TCPWM1_TR_OUT0517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2403 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0518 (CYHAL_TRIGGER_TCPWM1_TR_OUT0518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2404 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0519 (CYHAL_TRIGGER_TCPWM1_TR_OUT0519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2405 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0520 (CYHAL_TRIGGER_TCPWM1_TR_OUT0520_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2406 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0521 (CYHAL_TRIGGER_TCPWM1_TR_OUT0521_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2407 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0522 (CYHAL_TRIGGER_TCPWM1_TR_OUT0522_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2408 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0523 (CYHAL_TRIGGER_TCPWM1_TR_OUT0523_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2409 #define CYHAL_TRIGGER_TCPWM1_TR_OUT0524 (CYHAL_TRIGGER_TCPWM1_TR_OUT0524_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2410 #define CYHAL_TRIGGER_TCPWM0_TR_OUT10 (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2411 #define CYHAL_TRIGGER_TCPWM0_TR_OUT11 (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2412 #define CYHAL_TRIGGER_TCPWM0_TR_OUT12 (CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2413 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1256 (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2414 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1257 (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2415 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1258 (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2416 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1512 (CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2417 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1513 (CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2418 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1514 (CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2419 #define CYHAL_TRIGGER_TCPWM1_TR_OUT10 (CYHAL_TRIGGER_TCPWM1_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2420 #define CYHAL_TRIGGER_TCPWM1_TR_OUT11 (CYHAL_TRIGGER_TCPWM1_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2421 #define CYHAL_TRIGGER_TCPWM1_TR_OUT12 (CYHAL_TRIGGER_TCPWM1_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2422 #define CYHAL_TRIGGER_TCPWM1_TR_OUT13 (CYHAL_TRIGGER_TCPWM1_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2423 #define CYHAL_TRIGGER_TCPWM1_TR_OUT14 (CYHAL_TRIGGER_TCPWM1_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2424 #define CYHAL_TRIGGER_TCPWM1_TR_OUT15 (CYHAL_TRIGGER_TCPWM1_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2425 #define CYHAL_TRIGGER_TCPWM1_TR_OUT16 (CYHAL_TRIGGER_TCPWM1_TR_OUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2426 #define CYHAL_TRIGGER_TCPWM1_TR_OUT17 (CYHAL_TRIGGER_TCPWM1_TR_OUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2427 #define CYHAL_TRIGGER_TCPWM1_TR_OUT18 (CYHAL_TRIGGER_TCPWM1_TR_OUT18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2428 #define CYHAL_TRIGGER_TCPWM1_TR_OUT19 (CYHAL_TRIGGER_TCPWM1_TR_OUT19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2429 #define CYHAL_TRIGGER_TCPWM1_TR_OUT110 (CYHAL_TRIGGER_TCPWM1_TR_OUT110_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2430 #define CYHAL_TRIGGER_TCPWM1_TR_OUT111 (CYHAL_TRIGGER_TCPWM1_TR_OUT111_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2431 #define CYHAL_TRIGGER_TCPWM1_TR_OUT112 (CYHAL_TRIGGER_TCPWM1_TR_OUT112_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2432 #define CYHAL_TRIGGER_TCPWM1_TR_OUT113 (CYHAL_TRIGGER_TCPWM1_TR_OUT113_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2433 #define CYHAL_TRIGGER_TCPWM1_TR_OUT114 (CYHAL_TRIGGER_TCPWM1_TR_OUT114_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2434 #define CYHAL_TRIGGER_TCPWM1_TR_OUT115 (CYHAL_TRIGGER_TCPWM1_TR_OUT115_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2435 #define CYHAL_TRIGGER_TCPWM1_TR_OUT116 (CYHAL_TRIGGER_TCPWM1_TR_OUT116_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2436 #define CYHAL_TRIGGER_TCPWM1_TR_OUT117 (CYHAL_TRIGGER_TCPWM1_TR_OUT117_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2437 #define CYHAL_TRIGGER_TCPWM1_TR_OUT118 (CYHAL_TRIGGER_TCPWM1_TR_OUT118_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2438 #define CYHAL_TRIGGER_TCPWM1_TR_OUT119 (CYHAL_TRIGGER_TCPWM1_TR_OUT119_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2439 #define CYHAL_TRIGGER_TCPWM1_TR_OUT120 (CYHAL_TRIGGER_TCPWM1_TR_OUT120_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2440 #define CYHAL_TRIGGER_TCPWM1_TR_OUT121 (CYHAL_TRIGGER_TCPWM1_TR_OUT121_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2441 #define CYHAL_TRIGGER_TCPWM1_TR_OUT122 (CYHAL_TRIGGER_TCPWM1_TR_OUT122_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2442 #define CYHAL_TRIGGER_TCPWM1_TR_OUT123 (CYHAL_TRIGGER_TCPWM1_TR_OUT123_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2443 #define CYHAL_TRIGGER_TCPWM1_TR_OUT124 (CYHAL_TRIGGER_TCPWM1_TR_OUT124_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2444 #define CYHAL_TRIGGER_TCPWM1_TR_OUT125 (CYHAL_TRIGGER_TCPWM1_TR_OUT125_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2445 #define CYHAL_TRIGGER_TCPWM1_TR_OUT126 (CYHAL_TRIGGER_TCPWM1_TR_OUT126_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2446 #define CYHAL_TRIGGER_TCPWM1_TR_OUT127 (CYHAL_TRIGGER_TCPWM1_TR_OUT127_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2447 #define CYHAL_TRIGGER_TCPWM1_TR_OUT128 (CYHAL_TRIGGER_TCPWM1_TR_OUT128_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2448 #define CYHAL_TRIGGER_TCPWM1_TR_OUT129 (CYHAL_TRIGGER_TCPWM1_TR_OUT129_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2449 #define CYHAL_TRIGGER_TCPWM1_TR_OUT130 (CYHAL_TRIGGER_TCPWM1_TR_OUT130_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2450 #define CYHAL_TRIGGER_TCPWM1_TR_OUT131 (CYHAL_TRIGGER_TCPWM1_TR_OUT131_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2451 #define CYHAL_TRIGGER_TCPWM1_TR_OUT132 (CYHAL_TRIGGER_TCPWM1_TR_OUT132_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2452 #define CYHAL_TRIGGER_TCPWM1_TR_OUT133 (CYHAL_TRIGGER_TCPWM1_TR_OUT133_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2453 #define CYHAL_TRIGGER_TCPWM1_TR_OUT134 (CYHAL_TRIGGER_TCPWM1_TR_OUT134_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2454 #define CYHAL_TRIGGER_TCPWM1_TR_OUT135 (CYHAL_TRIGGER_TCPWM1_TR_OUT135_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2455 #define CYHAL_TRIGGER_TCPWM1_TR_OUT136 (CYHAL_TRIGGER_TCPWM1_TR_OUT136_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2456 #define CYHAL_TRIGGER_TCPWM1_TR_OUT137 (CYHAL_TRIGGER_TCPWM1_TR_OUT137_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2457 #define CYHAL_TRIGGER_TCPWM1_TR_OUT138 (CYHAL_TRIGGER_TCPWM1_TR_OUT138_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2458 #define CYHAL_TRIGGER_TCPWM1_TR_OUT139 (CYHAL_TRIGGER_TCPWM1_TR_OUT139_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2459 #define CYHAL_TRIGGER_TCPWM1_TR_OUT140 (CYHAL_TRIGGER_TCPWM1_TR_OUT140_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2460 #define CYHAL_TRIGGER_TCPWM1_TR_OUT141 (CYHAL_TRIGGER_TCPWM1_TR_OUT141_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2461 #define CYHAL_TRIGGER_TCPWM1_TR_OUT142 (CYHAL_TRIGGER_TCPWM1_TR_OUT142_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2462 #define CYHAL_TRIGGER_TCPWM1_TR_OUT143 (CYHAL_TRIGGER_TCPWM1_TR_OUT143_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2463 #define CYHAL_TRIGGER_TCPWM1_TR_OUT144 (CYHAL_TRIGGER_TCPWM1_TR_OUT144_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2464 #define CYHAL_TRIGGER_TCPWM1_TR_OUT145 (CYHAL_TRIGGER_TCPWM1_TR_OUT145_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2465 #define CYHAL_TRIGGER_TCPWM1_TR_OUT146 (CYHAL_TRIGGER_TCPWM1_TR_OUT146_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2466 #define CYHAL_TRIGGER_TCPWM1_TR_OUT147 (CYHAL_TRIGGER_TCPWM1_TR_OUT147_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2467 #define CYHAL_TRIGGER_TCPWM1_TR_OUT148 (CYHAL_TRIGGER_TCPWM1_TR_OUT148_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2468 #define CYHAL_TRIGGER_TCPWM1_TR_OUT149 (CYHAL_TRIGGER_TCPWM1_TR_OUT149_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2469 #define CYHAL_TRIGGER_TCPWM1_TR_OUT150 (CYHAL_TRIGGER_TCPWM1_TR_OUT150_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2470 #define CYHAL_TRIGGER_TCPWM1_TR_OUT151 (CYHAL_TRIGGER_TCPWM1_TR_OUT151_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2471 #define CYHAL_TRIGGER_TCPWM1_TR_OUT152 (CYHAL_TRIGGER_TCPWM1_TR_OUT152_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2472 #define CYHAL_TRIGGER_TCPWM1_TR_OUT153 (CYHAL_TRIGGER_TCPWM1_TR_OUT153_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2473 #define CYHAL_TRIGGER_TCPWM1_TR_OUT154 (CYHAL_TRIGGER_TCPWM1_TR_OUT154_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2474 #define CYHAL_TRIGGER_TCPWM1_TR_OUT155 (CYHAL_TRIGGER_TCPWM1_TR_OUT155_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2475 #define CYHAL_TRIGGER_TCPWM1_TR_OUT156 (CYHAL_TRIGGER_TCPWM1_TR_OUT156_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2476 #define CYHAL_TRIGGER_TCPWM1_TR_OUT157 (CYHAL_TRIGGER_TCPWM1_TR_OUT157_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2477 #define CYHAL_TRIGGER_TCPWM1_TR_OUT158 (CYHAL_TRIGGER_TCPWM1_TR_OUT158_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2478 #define CYHAL_TRIGGER_TCPWM1_TR_OUT159 (CYHAL_TRIGGER_TCPWM1_TR_OUT159_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2479 #define CYHAL_TRIGGER_TCPWM1_TR_OUT160 (CYHAL_TRIGGER_TCPWM1_TR_OUT160_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2480 #define CYHAL_TRIGGER_TCPWM1_TR_OUT161 (CYHAL_TRIGGER_TCPWM1_TR_OUT161_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2481 #define CYHAL_TRIGGER_TCPWM1_TR_OUT162 (CYHAL_TRIGGER_TCPWM1_TR_OUT162_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2482 #define CYHAL_TRIGGER_TCPWM1_TR_OUT163 (CYHAL_TRIGGER_TCPWM1_TR_OUT163_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2483 #define CYHAL_TRIGGER_TCPWM1_TR_OUT164 (CYHAL_TRIGGER_TCPWM1_TR_OUT164_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2484 #define CYHAL_TRIGGER_TCPWM1_TR_OUT165 (CYHAL_TRIGGER_TCPWM1_TR_OUT165_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2485 #define CYHAL_TRIGGER_TCPWM1_TR_OUT166 (CYHAL_TRIGGER_TCPWM1_TR_OUT166_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2486 #define CYHAL_TRIGGER_TCPWM1_TR_OUT167 (CYHAL_TRIGGER_TCPWM1_TR_OUT167_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2487 #define CYHAL_TRIGGER_TCPWM1_TR_OUT168 (CYHAL_TRIGGER_TCPWM1_TR_OUT168_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2488 #define CYHAL_TRIGGER_TCPWM1_TR_OUT169 (CYHAL_TRIGGER_TCPWM1_TR_OUT169_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2489 #define CYHAL_TRIGGER_TCPWM1_TR_OUT170 (CYHAL_TRIGGER_TCPWM1_TR_OUT170_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2490 #define CYHAL_TRIGGER_TCPWM1_TR_OUT171 (CYHAL_TRIGGER_TCPWM1_TR_OUT171_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2491 #define CYHAL_TRIGGER_TCPWM1_TR_OUT172 (CYHAL_TRIGGER_TCPWM1_TR_OUT172_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2492 #define CYHAL_TRIGGER_TCPWM1_TR_OUT173 (CYHAL_TRIGGER_TCPWM1_TR_OUT173_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2493 #define CYHAL_TRIGGER_TCPWM1_TR_OUT174 (CYHAL_TRIGGER_TCPWM1_TR_OUT174_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2494 #define CYHAL_TRIGGER_TCPWM1_TR_OUT175 (CYHAL_TRIGGER_TCPWM1_TR_OUT175_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2495 #define CYHAL_TRIGGER_TCPWM1_TR_OUT176 (CYHAL_TRIGGER_TCPWM1_TR_OUT176_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2496 #define CYHAL_TRIGGER_TCPWM1_TR_OUT177 (CYHAL_TRIGGER_TCPWM1_TR_OUT177_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2497 #define CYHAL_TRIGGER_TCPWM1_TR_OUT178 (CYHAL_TRIGGER_TCPWM1_TR_OUT178_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2498 #define CYHAL_TRIGGER_TCPWM1_TR_OUT179 (CYHAL_TRIGGER_TCPWM1_TR_OUT179_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2499 #define CYHAL_TRIGGER_TCPWM1_TR_OUT180 (CYHAL_TRIGGER_TCPWM1_TR_OUT180_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2500 #define CYHAL_TRIGGER_TCPWM1_TR_OUT181 (CYHAL_TRIGGER_TCPWM1_TR_OUT181_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2501 #define CYHAL_TRIGGER_TCPWM1_TR_OUT182 (CYHAL_TRIGGER_TCPWM1_TR_OUT182_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2502 #define CYHAL_TRIGGER_TCPWM1_TR_OUT183 (CYHAL_TRIGGER_TCPWM1_TR_OUT183_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2503 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1256 (CYHAL_TRIGGER_TCPWM1_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2504 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1257 (CYHAL_TRIGGER_TCPWM1_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2505 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1258 (CYHAL_TRIGGER_TCPWM1_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2506 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1259 (CYHAL_TRIGGER_TCPWM1_TR_OUT1259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2507 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1260 (CYHAL_TRIGGER_TCPWM1_TR_OUT1260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2508 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1261 (CYHAL_TRIGGER_TCPWM1_TR_OUT1261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2509 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1262 (CYHAL_TRIGGER_TCPWM1_TR_OUT1262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2510 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1263 (CYHAL_TRIGGER_TCPWM1_TR_OUT1263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2511 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1264 (CYHAL_TRIGGER_TCPWM1_TR_OUT1264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2512 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1265 (CYHAL_TRIGGER_TCPWM1_TR_OUT1265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2513 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1266 (CYHAL_TRIGGER_TCPWM1_TR_OUT1266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2514 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1267 (CYHAL_TRIGGER_TCPWM1_TR_OUT1267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2515 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1512 (CYHAL_TRIGGER_TCPWM1_TR_OUT1512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2516 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1513 (CYHAL_TRIGGER_TCPWM1_TR_OUT1513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2517 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1514 (CYHAL_TRIGGER_TCPWM1_TR_OUT1514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2518 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1515 (CYHAL_TRIGGER_TCPWM1_TR_OUT1515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2519 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1516 (CYHAL_TRIGGER_TCPWM1_TR_OUT1516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2520 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1517 (CYHAL_TRIGGER_TCPWM1_TR_OUT1517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2521 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1518 (CYHAL_TRIGGER_TCPWM1_TR_OUT1518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2522 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1519 (CYHAL_TRIGGER_TCPWM1_TR_OUT1519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2523 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1520 (CYHAL_TRIGGER_TCPWM1_TR_OUT1520_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2524 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1521 (CYHAL_TRIGGER_TCPWM1_TR_OUT1521_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2525 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1522 (CYHAL_TRIGGER_TCPWM1_TR_OUT1522_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2526 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1523 (CYHAL_TRIGGER_TCPWM1_TR_OUT1523_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2527 #define CYHAL_TRIGGER_TCPWM1_TR_OUT1524 (CYHAL_TRIGGER_TCPWM1_TR_OUT1524_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2528 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2529 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2530 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2531 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2532 #define CYHAL_TRIGGER_TR_GROUP10_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP10_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2533 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2534 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2535 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2536 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2537 #define CYHAL_TRIGGER_TR_GROUP11_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP11_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2538 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT0 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2539 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT1 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2540 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT2 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2541 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT3 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2542 #define CYHAL_TRIGGER_TR_GROUP12_OUTPUT4 (CYHAL_TRIGGER_TR_GROUP12_OUTPUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 2543 2544 /** @brief Name of each output trigger. */ 2545 typedef enum 2546 { 2547 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[0] 2548 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK1 = 1, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[1] 2549 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK2 = 2, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[2] 2550 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK3 = 3, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[3] 2551 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK4 = 4, //!< CAN0 DW0 triggers (from DW0 back to CAN0) - canfd[0].tr_dbg_dma_ack[4] 2552 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK0 = 5, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[0] 2553 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK1 = 6, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[1] 2554 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK2 = 7, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[2] 2555 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK3 = 8, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[3] 2556 CYHAL_TRIGGER_CANFD1_TR_DBG_DMA_ACK4 = 9, //!< CAN1 DW1 triggers (from DW1 back to CAN1) - canfd[1].tr_dbg_dma_ack[4] 2557 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 10, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0] 2558 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN1 = 11, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[1] 2559 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN2 = 12, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[2] 2560 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN3 = 13, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[3] 2561 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN4 = 14, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[4] 2562 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN0 = 15, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[0] 2563 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN1 = 16, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[1] 2564 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN2 = 17, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[2] 2565 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN3 = 18, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[3] 2566 CYHAL_TRIGGER_CANFD1_TR_EVT_SWT_IN4 = 19, //!< CAN TT Sync - canfd[1].tr_evt_swt_in[4] 2567 CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 20, //!< Debug Multiplexer - cpuss.cti_tr_in[0] 2568 CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 21, //!< Debug Multiplexer - cpuss.cti_tr_in[1] 2569 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 22, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[0] 2570 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 23, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[1] 2571 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 24, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[2] 2572 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 25, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[3] 2573 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN4 = 26, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[4] 2574 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN5 = 27, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[5] 2575 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN6 = 28, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[6] 2576 CYHAL_TRIGGER_CPUSS_DMAC_TR_IN7 = 29, //!< M-DMA trigger multiplexer - cpuss.dmac_tr_in[7] 2577 CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 30, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0] 2578 CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 31, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1] 2579 CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 32, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2] 2580 CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 33, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3] 2581 CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 34, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4] 2582 CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 35, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5] 2583 CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 36, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6] 2584 CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 37, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7] 2585 CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 38, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[8] 2586 CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 39, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[9] 2587 CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 40, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[10] 2588 CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 41, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[11] 2589 CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 42, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[12] 2590 CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 43, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[13] 2591 CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 44, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[14] 2592 CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 45, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[15] 2593 CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 46, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[16] 2594 CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 47, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[17] 2595 CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 48, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[18] 2596 CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 49, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[19] 2597 CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 50, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[20] 2598 CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 51, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[21] 2599 CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 52, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[22] 2600 CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 53, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[23] 2601 CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 54, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[24] 2602 CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 55, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[25] 2603 CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 56, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[26] 2604 CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 57, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[27] 2605 CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 58, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[28] 2606 CYHAL_TRIGGER_CPUSS_DW0_TR_IN29 = 59, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[29] 2607 CYHAL_TRIGGER_CPUSS_DW0_TR_IN30 = 60, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[30] 2608 CYHAL_TRIGGER_CPUSS_DW0_TR_IN31 = 61, //!< TCPWM to P-DMA0 trigger mux - cpuss.dw0_tr_in[31] 2609 CYHAL_TRIGGER_CPUSS_DW0_TR_IN32 = 62, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[32] 2610 CYHAL_TRIGGER_CPUSS_DW0_TR_IN33 = 63, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[33] 2611 CYHAL_TRIGGER_CPUSS_DW0_TR_IN34 = 64, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[34] 2612 CYHAL_TRIGGER_CPUSS_DW0_TR_IN35 = 65, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[35] 2613 CYHAL_TRIGGER_CPUSS_DW0_TR_IN36 = 66, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[36] 2614 CYHAL_TRIGGER_CPUSS_DW0_TR_IN37 = 67, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[37] 2615 CYHAL_TRIGGER_CPUSS_DW0_TR_IN38 = 68, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[38] 2616 CYHAL_TRIGGER_CPUSS_DW0_TR_IN39 = 69, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[39] 2617 CYHAL_TRIGGER_CPUSS_DW0_TR_IN40 = 70, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[40] 2618 CYHAL_TRIGGER_CPUSS_DW0_TR_IN41 = 71, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[41] 2619 CYHAL_TRIGGER_CPUSS_DW0_TR_IN42 = 72, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[42] 2620 CYHAL_TRIGGER_CPUSS_DW0_TR_IN43 = 73, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[43] 2621 CYHAL_TRIGGER_CPUSS_DW0_TR_IN44 = 74, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[44] 2622 CYHAL_TRIGGER_CPUSS_DW0_TR_IN45 = 75, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[45] 2623 CYHAL_TRIGGER_CPUSS_DW0_TR_IN46 = 76, //!< CAN0 DW0 Triggers - cpuss.dw0_tr_in[46] 2624 CYHAL_TRIGGER_CPUSS_DW0_TR_IN47 = 77, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[47] 2625 CYHAL_TRIGGER_CPUSS_DW0_TR_IN48 = 78, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[48] 2626 CYHAL_TRIGGER_CPUSS_DW0_TR_IN49 = 79, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[49] 2627 CYHAL_TRIGGER_CPUSS_DW0_TR_IN50 = 80, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[50] 2628 CYHAL_TRIGGER_CPUSS_DW0_TR_IN51 = 81, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[51] 2629 CYHAL_TRIGGER_CPUSS_DW0_TR_IN52 = 82, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[52] 2630 CYHAL_TRIGGER_CPUSS_DW0_TR_IN53 = 83, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[53] 2631 CYHAL_TRIGGER_CPUSS_DW0_TR_IN54 = 84, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[54] 2632 CYHAL_TRIGGER_CPUSS_DW0_TR_IN55 = 85, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[55] 2633 CYHAL_TRIGGER_CPUSS_DW0_TR_IN56 = 86, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[56] 2634 CYHAL_TRIGGER_CPUSS_DW0_TR_IN57 = 87, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[57] 2635 CYHAL_TRIGGER_CPUSS_DW0_TR_IN58 = 88, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[58] 2636 CYHAL_TRIGGER_CPUSS_DW0_TR_IN59 = 89, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[59] 2637 CYHAL_TRIGGER_CPUSS_DW0_TR_IN60 = 90, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[60] 2638 CYHAL_TRIGGER_CPUSS_DW0_TR_IN61 = 91, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[61] 2639 CYHAL_TRIGGER_CPUSS_DW0_TR_IN62 = 92, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[62] 2640 CYHAL_TRIGGER_CPUSS_DW0_TR_IN63 = 93, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[63] 2641 CYHAL_TRIGGER_CPUSS_DW0_TR_IN64 = 94, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[64] 2642 CYHAL_TRIGGER_CPUSS_DW0_TR_IN65 = 95, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[65] 2643 CYHAL_TRIGGER_CPUSS_DW0_TR_IN66 = 96, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[66] 2644 CYHAL_TRIGGER_CPUSS_DW0_TR_IN67 = 97, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[67] 2645 CYHAL_TRIGGER_CPUSS_DW0_TR_IN68 = 98, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[68] 2646 CYHAL_TRIGGER_CPUSS_DW0_TR_IN69 = 99, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[69] 2647 CYHAL_TRIGGER_CPUSS_DW0_TR_IN70 = 100, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[70] 2648 CYHAL_TRIGGER_CPUSS_DW0_TR_IN71 = 101, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[71] 2649 CYHAL_TRIGGER_CPUSS_DW0_TR_IN72 = 102, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[72] 2650 CYHAL_TRIGGER_CPUSS_DW0_TR_IN73 = 103, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[73] 2651 CYHAL_TRIGGER_CPUSS_DW0_TR_IN74 = 104, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[74] 2652 CYHAL_TRIGGER_CPUSS_DW0_TR_IN75 = 105, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[75] 2653 CYHAL_TRIGGER_CPUSS_DW0_TR_IN76 = 106, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[76] 2654 CYHAL_TRIGGER_CPUSS_DW0_TR_IN77 = 107, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[77] 2655 CYHAL_TRIGGER_CPUSS_DW0_TR_IN78 = 108, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[78] 2656 CYHAL_TRIGGER_CPUSS_DW0_TR_IN79 = 109, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[79] 2657 CYHAL_TRIGGER_CPUSS_DW0_TR_IN80 = 110, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[80] 2658 CYHAL_TRIGGER_CPUSS_DW0_TR_IN81 = 111, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[81] 2659 CYHAL_TRIGGER_CPUSS_DW0_TR_IN82 = 112, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[82] 2660 CYHAL_TRIGGER_CPUSS_DW0_TR_IN83 = 113, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[83] 2661 CYHAL_TRIGGER_CPUSS_DW0_TR_IN84 = 114, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[84] 2662 CYHAL_TRIGGER_CPUSS_DW0_TR_IN85 = 115, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[85] 2663 CYHAL_TRIGGER_CPUSS_DW0_TR_IN86 = 116, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[86] 2664 CYHAL_TRIGGER_CPUSS_DW0_TR_IN87 = 117, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[87] 2665 CYHAL_TRIGGER_CPUSS_DW0_TR_IN88 = 118, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[88] 2666 CYHAL_TRIGGER_CPUSS_DW0_TR_IN89 = 119, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[89] 2667 CYHAL_TRIGGER_CPUSS_DW0_TR_IN90 = 120, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[90] 2668 CYHAL_TRIGGER_CPUSS_DW0_TR_IN91 = 121, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[91] 2669 CYHAL_TRIGGER_CPUSS_DW0_TR_IN92 = 122, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[92] 2670 CYHAL_TRIGGER_CPUSS_DW0_TR_IN93 = 123, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[93] 2671 CYHAL_TRIGGER_CPUSS_DW0_TR_IN94 = 124, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[94] 2672 CYHAL_TRIGGER_CPUSS_DW0_TR_IN95 = 125, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[95] 2673 CYHAL_TRIGGER_CPUSS_DW0_TR_IN96 = 126, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[96] 2674 CYHAL_TRIGGER_CPUSS_DW0_TR_IN97 = 127, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[97] 2675 CYHAL_TRIGGER_CPUSS_DW0_TR_IN98 = 128, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[98] 2676 CYHAL_TRIGGER_CPUSS_DW0_TR_IN99 = 129, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[99] 2677 CYHAL_TRIGGER_CPUSS_DW0_TR_IN100 = 130, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[100] 2678 CYHAL_TRIGGER_CPUSS_DW0_TR_IN101 = 131, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[101] 2679 CYHAL_TRIGGER_CPUSS_DW0_TR_IN102 = 132, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[102] 2680 CYHAL_TRIGGER_CPUSS_DW0_TR_IN103 = 133, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[103] 2681 CYHAL_TRIGGER_CPUSS_DW0_TR_IN104 = 134, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[104] 2682 CYHAL_TRIGGER_CPUSS_DW0_TR_IN105 = 135, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[105] 2683 CYHAL_TRIGGER_CPUSS_DW0_TR_IN106 = 136, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[106] 2684 CYHAL_TRIGGER_CPUSS_DW0_TR_IN107 = 137, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[107] 2685 CYHAL_TRIGGER_CPUSS_DW0_TR_IN108 = 138, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[108] 2686 CYHAL_TRIGGER_CPUSS_DW0_TR_IN109 = 139, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[109] 2687 CYHAL_TRIGGER_CPUSS_DW0_TR_IN110 = 140, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[110] 2688 CYHAL_TRIGGER_CPUSS_DW0_TR_IN111 = 141, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[111] 2689 CYHAL_TRIGGER_CPUSS_DW0_TR_IN112 = 142, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[112] 2690 CYHAL_TRIGGER_CPUSS_DW0_TR_IN113 = 143, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[113] 2691 CYHAL_TRIGGER_CPUSS_DW0_TR_IN114 = 144, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[114] 2692 CYHAL_TRIGGER_CPUSS_DW0_TR_IN115 = 145, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[115] 2693 CYHAL_TRIGGER_CPUSS_DW0_TR_IN116 = 146, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[116] 2694 CYHAL_TRIGGER_CPUSS_DW0_TR_IN117 = 147, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[117] 2695 CYHAL_TRIGGER_CPUSS_DW0_TR_IN118 = 148, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[118] 2696 CYHAL_TRIGGER_CPUSS_DW0_TR_IN119 = 149, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[119] 2697 CYHAL_TRIGGER_CPUSS_DW0_TR_IN120 = 150, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[120] 2698 CYHAL_TRIGGER_CPUSS_DW0_TR_IN121 = 151, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[121] 2699 CYHAL_TRIGGER_CPUSS_DW0_TR_IN122 = 152, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[122] 2700 CYHAL_TRIGGER_CPUSS_DW0_TR_IN123 = 153, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[123] 2701 CYHAL_TRIGGER_CPUSS_DW0_TR_IN124 = 154, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[124] 2702 CYHAL_TRIGGER_CPUSS_DW0_TR_IN125 = 155, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[125] 2703 CYHAL_TRIGGER_CPUSS_DW0_TR_IN126 = 156, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[126] 2704 CYHAL_TRIGGER_CPUSS_DW0_TR_IN127 = 157, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[127] 2705 CYHAL_TRIGGER_CPUSS_DW0_TR_IN128 = 158, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[128] 2706 CYHAL_TRIGGER_CPUSS_DW0_TR_IN129 = 159, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[129] 2707 CYHAL_TRIGGER_CPUSS_DW0_TR_IN130 = 160, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[130] 2708 CYHAL_TRIGGER_CPUSS_DW0_TR_IN131 = 161, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[131] 2709 CYHAL_TRIGGER_CPUSS_DW0_TR_IN132 = 162, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[132] 2710 CYHAL_TRIGGER_CPUSS_DW0_TR_IN133 = 163, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[133] 2711 CYHAL_TRIGGER_CPUSS_DW0_TR_IN134 = 164, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[134] 2712 CYHAL_TRIGGER_CPUSS_DW0_TR_IN135 = 165, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[135] 2713 CYHAL_TRIGGER_CPUSS_DW0_TR_IN136 = 166, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[136] 2714 CYHAL_TRIGGER_CPUSS_DW0_TR_IN137 = 167, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[137] 2715 CYHAL_TRIGGER_CPUSS_DW0_TR_IN138 = 168, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[138] 2716 CYHAL_TRIGGER_CPUSS_DW0_TR_IN139 = 169, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[139] 2717 CYHAL_TRIGGER_CPUSS_DW0_TR_IN140 = 170, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[140] 2718 CYHAL_TRIGGER_CPUSS_DW0_TR_IN141 = 171, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[141] 2719 CYHAL_TRIGGER_CPUSS_DW0_TR_IN142 = 172, //!< PASS to DW0 direct connect - cpuss.dw0_tr_in[142] 2720 CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 173, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0] 2721 CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 174, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1] 2722 CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 175, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2] 2723 CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 176, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3] 2724 CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 177, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4] 2725 CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 178, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5] 2726 CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 179, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6] 2727 CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 180, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7] 2728 CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 181, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[8] 2729 CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 182, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[9] 2730 CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 183, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[10] 2731 CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 184, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[11] 2732 CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 185, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[12] 2733 CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 186, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[13] 2734 CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 187, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[14] 2735 CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 188, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[15] 2736 CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 189, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[16] 2737 CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 190, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[17] 2738 CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 191, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[18] 2739 CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 192, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[19] 2740 CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 193, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[20] 2741 CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 194, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[21] 2742 CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 195, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[22] 2743 CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 196, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[23] 2744 CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 197, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[24] 2745 CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 198, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[25] 2746 CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 199, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[26] 2747 CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 200, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[27] 2748 CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 201, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[28] 2749 CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 = 202, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[29] 2750 CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 = 203, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[30] 2751 CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 = 204, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[31] 2752 CYHAL_TRIGGER_CPUSS_DW1_TR_IN32 = 205, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[32] 2753 CYHAL_TRIGGER_CPUSS_DW1_TR_IN33 = 206, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[33] 2754 CYHAL_TRIGGER_CPUSS_DW1_TR_IN34 = 207, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[34] 2755 CYHAL_TRIGGER_CPUSS_DW1_TR_IN35 = 208, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[35] 2756 CYHAL_TRIGGER_CPUSS_DW1_TR_IN36 = 209, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[36] 2757 CYHAL_TRIGGER_CPUSS_DW1_TR_IN37 = 210, //!< SCB DW1 Triggers - cpuss.dw1_tr_in[37] 2758 CYHAL_TRIGGER_CPUSS_DW1_TR_IN38 = 211, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[38] 2759 CYHAL_TRIGGER_CPUSS_DW1_TR_IN39 = 212, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[39] 2760 CYHAL_TRIGGER_CPUSS_DW1_TR_IN40 = 213, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[40] 2761 CYHAL_TRIGGER_CPUSS_DW1_TR_IN41 = 214, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[41] 2762 CYHAL_TRIGGER_CPUSS_DW1_TR_IN42 = 215, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[42] 2763 CYHAL_TRIGGER_CPUSS_DW1_TR_IN43 = 216, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[43] 2764 CYHAL_TRIGGER_CPUSS_DW1_TR_IN44 = 217, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[44] 2765 CYHAL_TRIGGER_CPUSS_DW1_TR_IN45 = 218, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[45] 2766 CYHAL_TRIGGER_CPUSS_DW1_TR_IN46 = 219, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[46] 2767 CYHAL_TRIGGER_CPUSS_DW1_TR_IN47 = 220, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[47] 2768 CYHAL_TRIGGER_CPUSS_DW1_TR_IN48 = 221, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[48] 2769 CYHAL_TRIGGER_CPUSS_DW1_TR_IN49 = 222, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[49] 2770 CYHAL_TRIGGER_CPUSS_DW1_TR_IN50 = 223, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[50] 2771 CYHAL_TRIGGER_CPUSS_DW1_TR_IN51 = 224, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[51] 2772 CYHAL_TRIGGER_CPUSS_DW1_TR_IN52 = 225, //!< CAN1 DW1 Triggers - cpuss.dw1_tr_in[52] 2773 CYHAL_TRIGGER_CPUSS_DW1_TR_IN53 = 226, //!< SMIF DW1 Triggers - cpuss.dw1_tr_in[53] 2774 CYHAL_TRIGGER_CPUSS_DW1_TR_IN54 = 227, //!< SMIF DW1 Triggers - cpuss.dw1_tr_in[54] 2775 CYHAL_TRIGGER_CPUSS_DW1_TR_IN55 = 228, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[55] 2776 CYHAL_TRIGGER_CPUSS_DW1_TR_IN56 = 229, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[56] 2777 CYHAL_TRIGGER_CPUSS_DW1_TR_IN57 = 230, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[57] 2778 CYHAL_TRIGGER_CPUSS_DW1_TR_IN58 = 231, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[58] 2779 CYHAL_TRIGGER_CPUSS_DW1_TR_IN59 = 232, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[59] 2780 CYHAL_TRIGGER_CPUSS_DW1_TR_IN60 = 233, //!< I2S DW1 Triggers - cpuss.dw1_tr_in[60] 2781 CYHAL_TRIGGER_CPUSS_DW1_TR_IN61 = 234, //!< FLEXRAY DW1 Triggers - cpuss.dw1_tr_in[61] 2782 CYHAL_TRIGGER_CPUSS_DW1_TR_IN62 = 235, //!< FLEXRAY DW1 Triggers - cpuss.dw1_tr_in[62] 2783 CYHAL_TRIGGER_CPUSS_DW1_TR_IN63 = 236, //!< DW1 DW1 Triggers - cpuss.dw1_tr_in[63] 2784 CYHAL_TRIGGER_CPUSS_DW1_TR_IN64 = 237, //!< DW1 DW1 Triggers - cpuss.dw1_tr_in[64] 2785 CYHAL_TRIGGER_FLEXRAY0_TR_IBF_IN = 238, //!< DW1 FLEXRAY Triggers - flexray[0].tr_ibf_in 2786 CYHAL_TRIGGER_FLEXRAY0_TR_OBF_IN = 239, //!< DW1 FLEXRAY Triggers - flexray[0].tr_obf_in 2787 CYHAL_TRIGGER_FLEXRAY0_TR_STPWT_IN = 240, //!< CAN TT Sync - flexray[0].tr_stpwt_in 2788 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 = 241, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[0] 2789 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 = 242, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[1] 2790 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER2 = 243, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[2] 2791 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER3 = 244, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[3] 2792 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER4 = 245, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[4] 2793 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER5 = 246, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[5] 2794 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER6 = 247, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[6] 2795 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER7 = 248, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[7] 2796 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER8 = 249, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[8] 2797 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER9 = 250, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[9] 2798 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER10 = 251, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[10] 2799 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER11 = 252, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[11] 2800 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER12 = 253, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[12] 2801 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER13 = 254, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[13] 2802 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER14 = 255, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[14] 2803 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER15 = 256, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[15] 2804 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER16 = 257, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[16] 2805 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER17 = 258, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[17] 2806 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER18 = 259, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[18] 2807 CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER19 = 260, //!< TCPWM to LIN - lin[0].tr_cmd_tx_header[19] 2808 CYHAL_TRIGGER_PASS0_TR_DEBUG_FREEZE = 261, //!< Debug Multiplexer - pass[0].tr_debug_freeze 2809 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN0 = 262, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[0] 2810 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN1 = 263, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[1] 2811 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN2 = 264, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[2] 2812 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN3 = 265, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[3] 2813 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN4 = 266, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[4] 2814 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN5 = 267, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[5] 2815 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN6 = 268, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[6] 2816 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN7 = 269, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[7] 2817 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN8 = 270, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[8] 2818 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN9 = 271, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[9] 2819 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN10 = 272, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[10] 2820 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN11 = 273, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[11] 2821 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN12 = 274, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[12] 2822 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN13 = 275, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[13] 2823 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN14 = 276, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[14] 2824 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN15 = 277, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[15] 2825 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN16 = 278, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[16] 2826 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN17 = 279, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[17] 2827 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN18 = 280, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[18] 2828 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN19 = 281, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[19] 2829 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN20 = 282, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[20] 2830 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN21 = 283, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[21] 2831 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN22 = 284, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[22] 2832 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN23 = 285, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[23] 2833 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN24 = 286, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[24] 2834 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN25 = 287, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[25] 2835 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN26 = 288, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[26] 2836 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN27 = 289, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[27] 2837 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN28 = 290, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[28] 2838 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN29 = 291, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[29] 2839 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN30 = 292, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[30] 2840 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN31 = 293, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[31] 2841 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN32 = 294, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[32] 2842 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN33 = 295, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[33] 2843 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN34 = 296, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[34] 2844 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN35 = 297, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[35] 2845 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN36 = 298, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[36] 2846 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN37 = 299, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[37] 2847 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN38 = 300, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[38] 2848 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN39 = 301, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[39] 2849 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN40 = 302, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[40] 2850 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN41 = 303, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[41] 2851 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN42 = 304, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[42] 2852 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN43 = 305, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[43] 2853 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN44 = 306, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[44] 2854 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN45 = 307, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[45] 2855 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN46 = 308, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[46] 2856 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN47 = 309, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[47] 2857 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN48 = 310, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[48] 2858 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN49 = 311, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[49] 2859 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN50 = 312, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[50] 2860 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN51 = 313, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[51] 2861 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN52 = 314, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[52] 2862 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN53 = 315, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[53] 2863 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN54 = 316, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[54] 2864 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN55 = 317, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[55] 2865 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN56 = 318, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[56] 2866 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN57 = 319, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[57] 2867 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN58 = 320, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[58] 2868 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN59 = 321, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[59] 2869 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN60 = 322, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[60] 2870 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN61 = 323, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[61] 2871 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN62 = 324, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[62] 2872 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN63 = 325, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[63] 2873 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN64 = 326, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[64] 2874 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN65 = 327, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[65] 2875 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN66 = 328, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[66] 2876 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN67 = 329, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[67] 2877 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN68 = 330, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[68] 2878 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN69 = 331, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[69] 2879 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN70 = 332, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[70] 2880 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN71 = 333, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[71] 2881 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN72 = 334, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[72] 2882 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN73 = 335, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[73] 2883 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN74 = 336, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[74] 2884 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN75 = 337, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[75] 2885 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN76 = 338, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[76] 2886 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN77 = 339, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[77] 2887 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN78 = 340, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[78] 2888 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN79 = 341, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[79] 2889 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN80 = 342, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[80] 2890 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN81 = 343, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[81] 2891 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN82 = 344, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[82] 2892 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN83 = 345, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[83] 2893 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN84 = 346, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[84] 2894 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN85 = 347, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[85] 2895 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN86 = 348, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[86] 2896 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN87 = 349, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[87] 2897 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN88 = 350, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[88] 2898 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN89 = 351, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[89] 2899 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN90 = 352, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[90] 2900 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN91 = 353, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[91] 2901 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN92 = 354, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[92] 2902 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN93 = 355, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[93] 2903 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN94 = 356, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[94] 2904 CYHAL_TRIGGER_PASS0_TR_SAR_CH_IN95 = 357, //!< PWM to PASS direct connect - pass[0].tr_sar_ch_in[95] 2905 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN0 = 358, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[0] 2906 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN1 = 359, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[1] 2907 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN2 = 360, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[2] 2908 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN3 = 361, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[3] 2909 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN4 = 362, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[4] 2910 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN5 = 363, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[5] 2911 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN6 = 364, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[6] 2912 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN7 = 365, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[7] 2913 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN8 = 366, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[8] 2914 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN9 = 367, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[9] 2915 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN10 = 368, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[10] 2916 CYHAL_TRIGGER_PASS0_TR_SAR_GEN_IN11 = 369, //!< PASS trigger multiplexer - pass[0].tr_sar_gen_in[11] 2917 CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 370, //!< Debug Multiplexer - peri.tr_dbg_freeze 2918 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 371, //!< Debug Multiplexer - peri.tr_io_output[0] 2919 CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 372, //!< Debug Multiplexer - peri.tr_io_output[1] 2920 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 = 373, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[0] 2921 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 = 374, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[1] 2922 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT2 = 375, //!< Debug Multiplexer - srss.tr_debug_freeze_mcwdt[2] 2923 CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT = 376, //!< Debug Multiplexer - srss.tr_debug_freeze_wdt 2924 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 377, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[0] 2925 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 378, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[1] 2926 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 379, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[2] 2927 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 380, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[3] 2928 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 381, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[4] 2929 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 382, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[5] 2930 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 383, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[6] 2931 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 384, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[7] 2932 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 385, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[8] 2933 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 386, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[9] 2934 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 387, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[10] 2935 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 388, //!< TCPWM0 loopback mux - tcpwm[0].tr_all_cnt_in[11] 2936 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN0 = 389, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[0] 2937 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN1 = 390, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[1] 2938 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN2 = 391, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[2] 2939 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN3 = 392, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[3] 2940 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN4 = 393, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[4] 2941 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN5 = 394, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[5] 2942 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN6 = 395, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[6] 2943 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN7 = 396, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[7] 2944 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN8 = 397, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[8] 2945 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN9 = 398, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[9] 2946 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN10 = 399, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[10] 2947 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN11 = 400, //!< TCPWM1 loopback mux - tcpwm[1].tr_all_cnt_in[11] 2948 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN12 = 401, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[12] 2949 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN13 = 402, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[13] 2950 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN14 = 403, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[14] 2951 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN15 = 404, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[15] 2952 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN16 = 405, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[16] 2953 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN17 = 406, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[17] 2954 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN18 = 407, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[18] 2955 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN19 = 408, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[19] 2956 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN20 = 409, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[20] 2957 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN21 = 410, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[21] 2958 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN22 = 411, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[22] 2959 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN23 = 412, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[23] 2960 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN24 = 413, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[24] 2961 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN25 = 414, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[25] 2962 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN26 = 415, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[26] 2963 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN27 = 416, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[27] 2964 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN28 = 417, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[28] 2965 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN29 = 418, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[29] 2966 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN30 = 419, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[30] 2967 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN31 = 420, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[31] 2968 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN32 = 421, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[32] 2969 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN33 = 422, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[33] 2970 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN34 = 423, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[34] 2971 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN35 = 424, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[35] 2972 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN36 = 425, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[36] 2973 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN37 = 426, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[37] 2974 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN38 = 427, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[38] 2975 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN39 = 428, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[39] 2976 CYHAL_TRIGGER_TCPWM1_TR_ALL_CNT_IN40 = 429, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_all_cnt_in[40] 2977 CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 430, //!< Debug Multiplexer - tcpwm[0].tr_debug_freeze 2978 CYHAL_TRIGGER_TCPWM1_TR_DEBUG_FREEZE = 431, //!< Debug Multiplexer - tcpwm[1].tr_debug_freeze 2979 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN2 = 432, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[2] 2980 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN5 = 433, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[5] 2981 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN8 = 434, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[8] 2982 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN11 = 435, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[11] 2983 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN14 = 436, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[14] 2984 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN17 = 437, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[17] 2985 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN20 = 438, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[20] 2986 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN23 = 439, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[23] 2987 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN26 = 440, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[26] 2988 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN29 = 441, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[29] 2989 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN32 = 442, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[32] 2990 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN35 = 443, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[35] 2991 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN38 = 444, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[38] 2992 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN41 = 445, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[41] 2993 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN44 = 446, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[44] 2994 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN47 = 447, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[47] 2995 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN50 = 448, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[50] 2996 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN53 = 449, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[53] 2997 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN56 = 450, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[56] 2998 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN59 = 451, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[59] 2999 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN62 = 452, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[62] 3000 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN65 = 453, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[65] 3001 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN68 = 454, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[68] 3002 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN71 = 455, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[71] 3003 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN74 = 456, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[74] 3004 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN77 = 457, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[77] 3005 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN80 = 458, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[80] 3006 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN83 = 459, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[83] 3007 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN86 = 460, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[86] 3008 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN89 = 461, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[89] 3009 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN92 = 462, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[92] 3010 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN95 = 463, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[95] 3011 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN98 = 464, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[98] 3012 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN101 = 465, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[101] 3013 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN104 = 466, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[104] 3014 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN107 = 467, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[107] 3015 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN110 = 468, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[110] 3016 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN113 = 469, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[113] 3017 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN116 = 470, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[116] 3018 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN119 = 471, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[119] 3019 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN122 = 472, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[122] 3020 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN125 = 473, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[125] 3021 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN128 = 474, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[128] 3022 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN131 = 475, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[131] 3023 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN134 = 476, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[134] 3024 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN137 = 477, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[137] 3025 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN140 = 478, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[140] 3026 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN143 = 479, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[143] 3027 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN146 = 480, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[146] 3028 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN149 = 481, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[149] 3029 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN152 = 482, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[152] 3030 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN155 = 483, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[155] 3031 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN158 = 484, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[158] 3032 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN161 = 485, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[161] 3033 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN164 = 486, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[164] 3034 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN167 = 487, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[167] 3035 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN170 = 488, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[170] 3036 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN173 = 489, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[173] 3037 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN176 = 490, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[176] 3038 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN179 = 491, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[179] 3039 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN182 = 492, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[182] 3040 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN185 = 493, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[185] 3041 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN188 = 494, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[188] 3042 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN191 = 495, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[191] 3043 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN194 = 496, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[194] 3044 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN197 = 497, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[197] 3045 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN200 = 498, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[200] 3046 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN203 = 499, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[203] 3047 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN206 = 500, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[206] 3048 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN209 = 501, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[209] 3049 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN212 = 502, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[212] 3050 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN215 = 503, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[215] 3051 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN218 = 504, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[218] 3052 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN221 = 505, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[221] 3053 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN224 = 506, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[224] 3054 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN227 = 507, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[227] 3055 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN230 = 508, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[230] 3056 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN233 = 509, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[233] 3057 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN236 = 510, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[236] 3058 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN239 = 511, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[239] 3059 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN242 = 512, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[242] 3060 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN245 = 513, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[245] 3061 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN248 = 514, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[248] 3062 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN251 = 515, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[251] 3063 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN770 = 516, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[770] 3064 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN773 = 517, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[773] 3065 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN776 = 518, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[776] 3066 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN779 = 519, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[779] 3067 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN782 = 520, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[782] 3068 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN785 = 521, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[785] 3069 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN788 = 522, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[788] 3070 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN791 = 523, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[791] 3071 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN794 = 524, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[794] 3072 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN797 = 525, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[797] 3073 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN800 = 526, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[800] 3074 CYHAL_TRIGGER_TCPWM1_TR_ONE_CNT_IN803 = 527, //!< PASS to PWM direct connect - tcpwm[1].tr_one_cnt_in[803] 3075 CYHAL_TRIGGER_TR_GROUP9_INPUT1 = 528, //!< Debug Reduction #1 - tr_group[9].input[1] 3076 CYHAL_TRIGGER_TR_GROUP9_INPUT2 = 529, //!< Debug Reduction #1 - tr_group[9].input[2] 3077 CYHAL_TRIGGER_TR_GROUP9_INPUT3 = 530, //!< Debug Reduction #1 - tr_group[9].input[3] 3078 CYHAL_TRIGGER_TR_GROUP9_INPUT4 = 531, //!< Debug Reduction #1 - tr_group[9].input[4] 3079 CYHAL_TRIGGER_TR_GROUP9_INPUT5 = 532, //!< Debug Reduction #1 - tr_group[9].input[5] 3080 CYHAL_TRIGGER_TR_GROUP9_INPUT6 = 533, //!< Debug Reduction #2 - tr_group[9].input[6] 3081 CYHAL_TRIGGER_TR_GROUP9_INPUT7 = 534, //!< Debug Reduction #2 - tr_group[9].input[7] 3082 CYHAL_TRIGGER_TR_GROUP9_INPUT8 = 535, //!< Debug Reduction #2 - tr_group[9].input[8] 3083 CYHAL_TRIGGER_TR_GROUP9_INPUT9 = 536, //!< Debug Reduction #2 - tr_group[9].input[9] 3084 CYHAL_TRIGGER_TR_GROUP9_INPUT10 = 537, //!< Debug Reduction #2 - tr_group[9].input[10] 3085 CYHAL_TRIGGER_TR_GROUP9_INPUT11 = 538, //!< Debug Reduction #3 - tr_group[9].input[11] 3086 CYHAL_TRIGGER_TR_GROUP9_INPUT12 = 539, //!< Debug Reduction #3 - tr_group[9].input[12] 3087 CYHAL_TRIGGER_TR_GROUP9_INPUT13 = 540, //!< Debug Reduction #3 - tr_group[9].input[13] 3088 CYHAL_TRIGGER_TR_GROUP9_INPUT14 = 541, //!< Debug Reduction #3 - tr_group[9].input[14] 3089 CYHAL_TRIGGER_TR_GROUP9_INPUT15 = 542, //!< Debug Reduction #3 - tr_group[9].input[15] 3090 } cyhal_trigger_dest_xmc7200_t; 3091 3092 /** Typedef from device family specific trigger dest to generic trigger dest */ 3093 typedef cyhal_trigger_dest_xmc7200_t cyhal_dest_t; 3094 3095 /** \cond INTERNAL */ 3096 /** Table of number of inputs to each mux. */ 3097 extern const uint16_t cyhal_sources_per_mux[27]; 3098 3099 /** Table indicating whether mux is 1to1. */ 3100 extern const bool cyhal_is_mux_1to1[27]; 3101 3102 /** Table pointing to each mux source table. The index of each source in the table is its mux input index. */ 3103 extern const _cyhal_trigger_source_xmc7200_t* cyhal_mux_to_sources [27]; 3104 3105 /** Maps each cyhal_destination_t to a mux index. 3106 * If bit 8 of the mux index is set, this denotes that the trigger is a 3107 * one to one trigger. 3108 */ 3109 extern const uint8_t cyhal_dest_to_mux[543]; 3110 3111 /* Maps each cyhal_destination_t to a specific output in its mux */ 3112 extern const uint8_t cyhal_mux_dest_index[543]; 3113 /** \endcond */ 3114 3115 #if defined(__cplusplus) 3116 } 3117 #endif /* __cplusplus */ 3118 /** \} group_hal_impl_triggers_xmc7200 */ 3119 #endif /* _CYHAL_TRIGGERS_XMC7200_H_ */ 3120 3121 3122 /* [] END OF FILE */ 3123
