1 /***************************************************************************//**
2 * \file cyhal_hwmgr_impl_part.h
3 *
4 * \brief
5 * Provides device specific information to the hardware manager. This file must
6 * only ever be included by cyhal_hwmgr.c.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the "License");
16 * you may not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * http://www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an "AS IS" BASIS,
23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 *******************************************************************************/
27
28 /*******************************************************************************
29 * Defines
30 *******************************************************************************/
31
32 #include "cyhal_hwmgr_impl.h"
33 #include "cyhal_interconnect.h"
34 #include "cyhal_scb_common.h"
35
36 #if defined(CY_IP_MXS40PASS_SAR_INSTANCES)
37 #define CY_BLOCK_COUNT_ADC (CY_IP_MXS40PASS_SAR_INSTANCES)
38 #elif defined (CY_IP_MXS40EPASS_ESAR_INSTANCES)
39 #define CY_BLOCK_COUNT_ADC (CY_IP_MXS40EPASS_ESAR_INSTANCES)
40 #elif defined (CY_IP_M0S8PASS4A_SAR_INSTANCES)
41 #define CY_BLOCK_COUNT_ADC (CY_IP_M0S8PASS4A_SAR_INSTANCES)
42 #else
43 #define CY_BLOCK_COUNT_ADC (0)
44 #endif
45
46 #if defined(CY_IP_MXS40ADCMIC_INSTANCES)
47 #define CY_BLOCK_COUNT_ADCMIC (CY_IP_MXS40ADCMIC_INSTANCES)
48 #else
49 #define CY_BLOCK_COUNT_ADCMIC (0)
50 #endif
51
52 #if defined(CY_IP_MXBLESS_INSTANCES)
53 #define CY_BLOCK_COUNT_BLE CY_IP_MXBLESS_INSTANCES
54 #else
55 #define CY_BLOCK_COUNT_BLE (0)
56 #endif
57
58 #if defined(CY_IP_MXTTCANFD_INSTANCES)
59 #define CY_BLOCK_COUNT_CAN (CY_IP_MXTTCANFD_INSTANCES)
60 #if (CY_IP_MXTTCANFD_INSTANCES == 0)
61 #define CY_CHANNEL_COUNT_CAN (0u)
62 #elif (CY_IP_MXTTCANFD_INSTANCES == 1)
63 #define CY_CHANNEL_COUNT_CAN (CANFD_CAN_NR)
64 #elif (CY_IP_MXTTCANFD_INSTANCES == 2)
65 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR)
66 #elif (CY_IP_MXTTCANFD_INSTANCES == 3)
67 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR)
68 #elif (CY_IP_MXTTCANFD_INSTANCES == 4)
69 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR)
70 #elif (CY_IP_MXTTCANFD_INSTANCES == 5)
71 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR)
72 #elif (CY_IP_MXTTCANFD_INSTANCES == 6)
73 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR)
74 #elif (CY_IP_MXTTCANFD_INSTANCES == 7)
75 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR)
76 #elif (CY_IP_MXTTCANFD_INSTANCES == 8)
77 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR)
78 #elif (CY_IP_MXTTCANFD_INSTANCES == 9)
79 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR)
80 #elif (CY_IP_MXTTCANFD_INSTANCES == 10)
81 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR + CANFD9_CAN_NR)
82 #elif (CY_IP_MXTTCANFD_INSTANCES > 10)
83 #warning Unhandled CAN instance count
84 #endif
85 #elif defined(CY_IP_M0S8CAN_INSTANCES)
86 #define CY_BLOCK_COUNT_CAN (CY_IP_M0S8CAN_INSTANCES)
87 #define CY_CHANNEL_COUNT_CAN (1)
88 #else
89 #define CY_BLOCK_COUNT_CAN (0)
90 #define CY_CHANNEL_COUNT_CAN (0)
91 #endif
92
93 #if defined(COMPONENT_CAT1A)
94 #define PERI_DIV_NR (PERI_DIV_8_NR + PERI_DIV_16_NR + PERI_DIV_16_5_NR + PERI_DIV_24_5_NR)
95 #elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
96 #if (_CYHAL_CLOCK_PERI_GROUPS == 0)
97 #define PERI_DIV_NR (0)
98 #elif (_CYHAL_CLOCK_PERI_GROUPS == 1)
99 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0))
100 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 2
101 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1))
102 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 3
103 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2))
104 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 4
105 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3))
106 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 5
107 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4))
108 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 6
109 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5))
110 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 7
111 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6))
112 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 8
113 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7))
114 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 9
115 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8))
116 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 10
117 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9))
118 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 11
119 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10))
120 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 12
121 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11))
122 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 13
123 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12))
124 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 14
125 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13))
126 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 15
127 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13) + CY_MXSPERI_PCLK_DIV_CNT(14))
128 #else
129 #warning "PCLK table size exceeded"
130 #endif
131 #elif defined (COMPONENT_CAT1D)
132 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR == 0)
133 #define PERI0_DIV_NR (0)
134 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 1)
135 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0))
136 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 2)
137 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1))
138 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 3)
139 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2))
140 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 4)
141 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3))
142 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 5)
143 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4))
144 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 6)
145 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5))
146 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 7)
147 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6))
148 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 8)
149 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7))
150 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 9)
151 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7) + CY_MXSPERI_PCLK_DIV_CNT(0, 8))
152 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 10)
153 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7) + CY_MXSPERI_PCLK_DIV_CNT(0, 8) + CY_MXSPERI_PCLK_DIV_CNT(0, 9))
154 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR > 10)
155 #error "Unhandled PERI0_PERI_PCLK_PCLK_GROUP_NR"
156 #endif /* multiple PERI0_PERI_PCLK_PCLK_GROUP_NR values */
157
158 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR == 0)
159 #define PERI1_DIV_NR (0)
160 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 1)
161 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0))
162 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 2)
163 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1))
164 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 3)
165 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2))
166 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 4)
167 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3))
168 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 5)
169 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3) + CY_MXSPERI_PCLK_DIV_CNT(1, 4))
170 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 6)
171 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3) + CY_MXSPERI_PCLK_DIV_CNT(1, 4) + CY_MXSPERI_PCLK_DIV_CNT(1, 5))
172 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR > 6)
173 #error "Unhandled PERI1_PERI_PCLK_PCLK_GROUP_NR"
174 #endif /* multiple PERI1_PERI_PCLK_PCLK_GROUP_NR values */
175
176 #define PERI_DIV_NR (PERI0_DIV_NR + PERI1_DIV_NR)
177 #endif
178
179 #if (defined(COMPONENT_CAT1A) && !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)))
180 // 12 dedicated = IMO, EXT, ILO, FLL, LF, Pump, BAK, Timer, AltSysTick, Slow, Fast, Peri
181 // 7 optional = ECO, ALTHF, ALTLF, PILO, WCO, MFO, MF
182 #define CY_CHANNEL_COUNT_CLOCK (12 + 7 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + PERI_DIV_NR)
183 #elif (defined(COMPONENT_CAT1A) && defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
184 // 13 dedicated = IMO, EXT, ILO0, ILO1, FLL, LF, Pump, BAK, Timer, AltSysTick, Slow, Fast, Peri
185 // 6 optional = ECO, ALTHF, ALTLF, WCO, MFO, MF
186 #define CY_CHANNEL_COUNT_CLOCK (13 + 6 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + PERI_DIV_NR)
187 #elif defined(COMPONENT_CAT1B)
188 // 10 dedicated = IHO, IMO, EXT, ILO, FLL, LF, Pump, BAK, AltSysTick, Peri
189 // 7 optional = ECO, ALTHF, ALTLF, PILO, WCO, MFO, MF
190 #define CY_CHANNEL_COUNT_CLOCK (10 + 7 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + PERI_DIV_NR)
191 // TODO : to be fixed
192 #elif defined(COMPONENT_CAT1C)
193 // 15 dedicated = IMO, EXT, ILO, IL01, FLL, LF, BAK, AltSysTick, Peri, Fast0, Fast1, Slow, Mem, Timer
194 // 2 optional = ECO, WCO
195 #define CY_CHANNEL_COUNT_CLOCK (14 + 2 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + PERI_DIV_NR)
196 #elif defined(COMPONENT_CAT1D)
197 // 7 dedicated = IHO, EXT, FLL, LF, BAK, AltSysTick
198 // 6 optional = ECO, ALTHF, ALTLF, PILO, WCO, MF
199 #define CY_CHANNEL_COUNT_CLOCK (6 + 6 + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + SRSS_NUM_HFROOT + PERI_DIV_NR)
200 #elif defined(COMPONENT_CAT2)
201 // 7 dedicated = IMO, EXT, ILO, HF, LF, PUMP, SYSCLK
202 // 5 optional = ECO, WCO, PLL, PLLSEL, WDCSEL
203 #define CY_CHANNEL_COUNT_CLOCK (7 + 5 + PERI_PCLK_CLOCK_NR)
204 #endif
205
206 #if defined(CY_IP_MXCRYPTO_INSTANCES)
207 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_MXCRYPTO_INSTANCES)
208 #elif defined(CY_IP_MXCRYPTOCELL_INSTANCES)
209 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_MXCRYPTOCELL_INSTANCES)
210 #elif defined(CPUSS_CRYPTO_PRESENT)
211 #define CY_BLOCK_COUNT_CRYPTO (CPUSS_CRYPTO_PRESENT)
212 #elif defined(CY_IP_M0S8CRYPTO_INSTANCES)
213 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_M0S8CRYPTO_INSTANCES)
214 #elif defined(CY_IP_M0S8CRYPTOLITE_INSTANCES)
215 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_M0S8CRYPTOLITE_INSTANCES)
216 #else
217 #define CY_BLOCK_COUNT_CRYPTO (0)
218 #endif
219
220 #if defined(CY_IP_MXS40PASS_CTDAC_INSTANCES)
221 #define CY_BLOCK_COUNT_DAC (CY_IP_MXS40PASS_CTDAC_INSTANCES)
222 #else
223 #define CY_BLOCK_COUNT_DAC (0)
224 #endif
225
226 #if defined(CY_IP_M4CPUSS_DMAC_INSTANCES)
227 #define CY_BLOCK_COUNT_DMA (CY_IP_M4CPUSS_DMAC_INSTANCES)
228 #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR)
229 #elif defined(CY_IP_MXAHBDMAC_INSTANCES)
230 #define CY_BLOCK_COUNT_DMA (CY_IP_MXAHBDMAC_INSTANCES)
231
232 #if (CY_IP_MXAHBDMAC_INSTANCES == 0)
233 #define CY_CHANNEL_COUNT_DMA (0u)
234 #elif (CY_IP_MXAHBDMAC_INSTANCES == 1)
235 #define CY_CHANNEL_COUNT_DMA (MXAHBDMAC0_CH_NR)
236 #elif (CY_IP_MXAHBDMAC_INSTANCES == 2)
237 #define CY_CHANNEL_COUNT_DMA (MXAHBDMAC0_CH_NR + MXAHBDMAC1_CH_NR)
238 #elif (CY_IP_MXAHBDMAC_INSTANCES == 3)
239 #define CY_CHANNEL_COUNT_DMA (MXAHBDMAC0_CH_NR + MXAHBDMAC1_CH_NR + MXAHBDMAC2_CH_NR)
240 #else
241 #warning Unhandled DMA instance count
242 #endif
243 #elif defined(CY_IP_MXSAXIDMAC_INSTANCES)
244 #define CY_BLOCK_COUNT_DMA (CY_IP_MXSAXIDMAC_INSTANCES)
245 #if (APPCPUSS_AXIDMAC1_PRESENT)
246 #define CY_CHANNEL_COUNT_DMA (APPCPUSS_AXIDMAC0_CH_NR + APPCPUSS_AXIDMAC1_CH_NR)
247 #else
248 #define CY_CHANNEL_COUNT_DMA (APPCPUSS_AXIDMAC0_CH_NR)
249 #endif
250 #elif defined(CPUSS_CPUMEMSS_DMAC_PRESENT)
251 #define CY_BLOCK_COUNT_DMA (CPUSS_CPUMEMSS_DMAC_PRESENT)
252 #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR)
253 #elif defined(CPUSS_DMAC_PRESENT)
254 #define CY_BLOCK_COUNT_DMA (CPUSS_DMAC_PRESENT)
255 #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR)
256 #else
257 #define CY_BLOCK_COUNT_DMA (0)
258 #define CY_CHANNEL_COUNT_DMA (0)
259 #endif
260
261 #if defined(CY_IP_M4CPUSS_DMA_INSTANCES)
262 #define CY_BLOCK_COUNT_DW (CY_IP_M4CPUSS_DMA_INSTANCES)
263 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
264 #elif defined(CY_IP_MXDW_INSTANCES) && (CPUSS_DW0_PRESENT == 1)
265 #define CY_BLOCK_COUNT_DW (CY_IP_MXDW_INSTANCES)
266 #if(CPUSS_DW1_PRESENT == 1)
267 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
268 #else
269 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR)
270 #endif
271 #elif defined(CPUSS_DW_NR)
272 #define CY_BLOCK_COUNT_DW (CPUSS_DW_NR)
273 #if (CPUSS_DW_NR == 0)
274 #define CY_CHANNEL_COUNT_DW (0)
275 #elif (CPUSS_DW_NR == 1)
276 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR)
277 #elif (CPUSS_DW_NR == 2)
278 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
279 #else
280 #warning "Unhandled number of DataWire controllers."
281 #endif /* CPUSS_DW_NR is 0, 1, 2, or other (unhandled) */
282 #else
283 #define CY_BLOCK_COUNT_DW (0)
284 #define CY_CHANNEL_COUNT_DW (0)
285 #endif
286
287 #ifdef CY_IP_MXETH_INSTANCES
288 #define CY_BLOCK_COUNT_ETH (CY_IP_MXETH_INSTANCES)
289 #else
290 #define CY_BLOCK_COUNT_ETH (0)
291 #endif
292
293 #if defined(IOSS_GPIO_GPIO_PORT_NR)
294 #define CY_BLOCK_COUNT_GPIO (IOSS_GPIO_GPIO_PORT_NR)
295 #define CY_CHANNEL_COUNT_GPIO (8 * IOSS_GPIO_GPIO_PORT_NR)
296 #else
297 #define CY_BLOCK_COUNT_GPIO (0)
298 #define CY_CHANNEL_COUNT_GPIO (0)
299 #endif
300
301 #if defined(CY_IP_MXAUDIOSS_INSTANCES)
302 #define CY_BLOCK_COUNT_I2S (CY_IP_MXAUDIOSS_INSTANCES)
303 #else
304 #define CY_BLOCK_COUNT_I2S (0)
305 #endif
306
307 #ifdef CY_IP_MXI3C_INSTANCES
308 #define CY_BLOCK_COUNT_I3C (CY_IP_MXI3C_INSTANCES)
309 #else
310 #define CY_BLOCK_COUNT_I3C (0)
311 #endif
312
313 #if defined(CY_IP_MXKEYSCAN_INSTANCES)
314 #define CY_BLOCK_COUNT_KEYSCAN (CY_IP_MXKEYSCAN_INSTANCES)
315 #else
316 #define CY_BLOCK_COUNT_KEYSCAN (0)
317 #endif
318
319 #if defined(CY_IP_MXLCD_INSTANCES)
320 #define CY_BLOCK_COUNT_LCD (CY_IP_MXLCD_INSTANCES)
321 #elif defined(CY_IP_M0S8LCD_INSTANCES)
322 #define CY_BLOCK_COUNT_LCD (CY_IP_M0S8LCD_INSTANCES)
323 #else
324 #define CY_BLOCK_COUNT_LCD (0)
325 #endif
326
327 #if defined(CY_IP_MXLIN_INSTANCES)
328 #define CY_BLOCK_COUNT_LIN (CY_IP_MXLIN_INSTANCES)
329 #else
330 #define CY_BLOCK_COUNT_LIN (0)
331 #endif
332
333 #if defined(CY_IP_MXLPCOMP_INSTANCES)
334 #define CY_BLOCK_COUNT_LPCOMP (CY_IP_MXLPCOMP_INSTANCES)
335 #elif defined(CY_IP_M0S8LPCOMP_INSTANCES)
336 #define CY_BLOCK_COUNT_LPCOMP (CY_IP_M0S8LPCOMP_INSTANCES)
337 #else
338 #define CY_BLOCK_COUNT_LPCOMP (0)
339 #endif
340 #define CY_CHANNEL_COUNT_LPCOMP (2 * CY_BLOCK_COUNT_LPCOMP)
341
342 #if defined(PASS_NR_CTBS)
343 #define CY_BLOCK_COUNT_OPAMP (PASS_NR_CTBS)
344 #elif defined(PASS0_NR_CTBS)
345 #if defined(PASS1_NR_CTBS)
346 #define CY_BLOCK_COUNT_OPAMP ((PASS0_NR_CTBS + PASS1_NR_CTBS))
347 #else
348 #define CY_BLOCK_COUNT_OPAMP (PASS0_NR_CTBS)
349 #endif
350 #else
351 #define CY_BLOCK_COUNT_OPAMP (0)
352 #endif
353 #define CY_CHANNEL_COUNT_OPAMP (2 * CY_BLOCK_COUNT_OPAMP)
354
355 #if defined(CY_IP_MXAUDIOSS_INSTANCES)
356 #define CY_BLOCK_COUNT_PDMPCM (CY_IP_MXAUDIOSS_INSTANCES)
357 #elif defined(CY_IP_MXPDM_INSTANCES)
358 #define CY_BLOCK_COUNT_PDMPCM (CY_IP_MXPDM_INSTANCES)
359 #else
360 #define CY_BLOCK_COUNT_PDMPCM (0)
361 #endif
362
363 #if defined(CY_IP_MXSMIF_INSTANCES)
364 #define CY_BLOCK_COUNT_QSPI (CY_IP_MXSMIF_INSTANCES)
365 #else
366 #define CY_BLOCK_COUNT_QSPI (0)
367 #endif
368
369 #if (defined(CY_IP_MXS40SSRSS) || defined(CY_IP_MXS40SRSS)) && SRSS_BACKUP_PRESENT
370 #define CY_BLOCK_COUNT_RTC (1)
371 #else
372 #define CY_BLOCK_COUNT_RTC (0)
373 #endif
374
375 #if defined(CY_IP_MXSCB_INSTANCES)|| defined(CY_IP_MXS22SCB_INSTANCES) || defined(CY_IP_M0S8SCB_INSTANCES)
376 #define CY_BLOCK_COUNT_SCB (_SCB_ARRAY_SIZE)
377 #else
378 #define CY_BLOCK_COUNT_SCB (0)
379 #endif
380
381 #if defined(CY_IP_MXSDHC_INSTANCES)
382 #define CY_BLOCK_COUNT_SDHC (CY_IP_MXSDHC_INSTANCES)
383 #else
384 #define CY_BLOCK_COUNT_SDHC (0)
385 #endif
386
387 #ifdef CY_IP_MXSDIODEV_INSTANCES
388 #define CY_BLOCK_COUNT_SDIODEV (CY_IP_MXSDIODEV_INSTANCES)
389 #else
390 #define CY_BLOCK_COUNT_SDIODEV (0)
391 #endif
392
393 #if defined(CY_IP_MXTCPWM_INSTANCES)
394 #define CY_BLOCK_COUNT_TCPWM CY_IP_MXTCPWM_INSTANCES
395 #if (CY_IP_MXTCPWM_VERSION == 1)
396 #if (CY_IP_MXTCPWM_INSTANCES == 0)
397 #define CY_CHANNEL_COUNT_TCPWM (0u)
398 #elif (CY_IP_MXTCPWM_INSTANCES == 1)
399 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR)
400 #elif (CY_IP_MXTCPWM_INSTANCES == 2)
401 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR)
402 #elif (CY_IP_MXTCPWM_INSTANCES == 3)
403 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR)
404 #elif (CY_IP_MXTCPWM_INSTANCES == 4)
405 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR)
406 #elif (CY_IP_MXTCPWM_INSTANCES == 5)
407 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR)
408 #elif (CY_IP_MXTCPWM_INSTANCES == 6)
409 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR)
410 #elif (CY_IP_MXTCPWM_INSTANCES == 7)
411 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR)
412 #elif (CY_IP_MXTCPWM_INSTANCES == 8)
413 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR)
414 #elif (CY_IP_MXTCPWM_INSTANCES == 9)
415 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR)
416 #elif (CY_IP_MXTCPWM_INSTANCES == 10)
417 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR + TCPWM9_CNT_NR)
418 #elif (CY_IP_MXTCPWM_INSTANCES > 10)
419 #warning Unhandled TCPWM instance count
420 #endif
421 #elif (CY_IP_MXTCPWM_VERSION == 2)
422 #if (CY_IP_MXTCPWM_INSTANCES == 1)
423 #if (TCPWM_GRP_NR == 0)
424 #define CY_CHANNEL_COUNT_TCPWM (0u)
425 #elif (TCPWM_GRP_NR == 1)
426 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR)
427 #elif (TCPWM_GRP_NR == 2)
428 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR)
429 #elif (TCPWM_GRP_NR == 3)
430 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR + TCPWM_GRP_NR2_GRP_GRP_CNT_NR)
431 #elif (TCPWM_GRP_NR == 4)
432 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR + TCPWM_GRP_NR2_GRP_GRP_CNT_NR + TCPWM_GRP_NR3_GRP_GRP_CNT_NR)
433 #elif (TCPWM_GRP_NR > 4)
434 #warning Unhandled TCPWM instance count
435 #endif
436 #elif (CY_IP_MXTCPWM_INSTANCES == 2)
437 #if (TCPWM0_GRP_NR == 0)
438 #define CY_CHANNEL_COUNT_TCPWM0 (0u)
439 #elif (TCPWM0_GRP_NR == 1)
440 #define CY_CHANNEL_COUNT_TCPWM0 (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR)
441 #elif (TCPWM0_GRP_NR == 2)
442 #define CY_CHANNEL_COUNT_TCPWM0 (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR)
443 #elif (TCPWM0_GRP_NR == 3)
444 #define CY_CHANNEL_COUNT_TCPWM0 (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR)
445 #elif (TCPWM0_GRP_NR > 3)
446 #warning Unhandled TCPWM instance count
447 #endif
448 #if (TCPWM1_GRP_NR == 0)
449 #define CY_CHANNEL_COUNT_TCPWM1 (0u)
450 #elif (TCPWM1_GRP_NR == 1)
451 #define CY_CHANNEL_COUNT_TCPWM1 (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR)
452 #elif (TCPWM1_GRP_NR == 2)
453 #define CY_CHANNEL_COUNT_TCPWM1 (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR)
454 #elif (TCPWM1_GRP_NR == 3)
455 #define CY_CHANNEL_COUNT_TCPWM1 (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR)
456 #elif (TCPWM1_GRP_NR > 3)
457 #warning Unhandled TCPWM instance count
458 #endif
459 #define CY_CHANNEL_COUNT_TCPWM (CY_CHANNEL_COUNT_TCPWM0 + CY_CHANNEL_COUNT_TCPWM1)
460 #elif (CY_IP_MXTCPWM_INSTANCES > 2)
461 #warning Unhandled TCPWM instance count
462 #endif
463 #else
464 #warning Unrecognized TCPWM IP version
465 #endif
466 #elif defined(CY_IP_M0S8TCPWM_INSTANCES)
467 #define CY_BLOCK_COUNT_TCPWM (CY_IP_M0S8TCPWM_INSTANCES)
468 #if (CY_IP_M0S8TCPWM_INSTANCES == 0)
469 #define CY_CHANNEL_COUNT_TCPWM (0u)
470 #elif (CY_IP_M0S8TCPWM_INSTANCES == 1)
471 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_CNT_NR)
472 #else
473 #warning Unhandled TCPWM instance count
474 #endif
475 #else
476 #define CY_BLOCK_COUNT_TCPWM (0)
477 #define CY_CHANNEL_COUNT_TCPWM (0)
478 #endif
479
480 #ifdef CY_IP_MXTDM_INSTANCES
481 #define CY_BLOCK_COUNT_TDM (CY_IP_MXTDM_INSTANCES)
482 #if (CY_IP_MXTDM_INSTANCES == 0)
483 #define CY_CHANNEL_COUNT_TDM (0u)
484 #elif (CY_IP_MXTDM_INSTANCES == 1)
485 #define CY_CHANNEL_COUNT_TDM (TDM_NR)
486 #else
487 #warning Unhandled TDM instance count
488 #endif
489 #else
490 #define CY_BLOCK_COUNT_TDM (0)
491 #define CY_CHANNEL_COUNT_TDM (0u)
492 #endif
493
494 #if defined(CY_IP_MXUDB_INSTANCES)
495 #define CY_BLOCK_COUNT_UDB (CY_IP_MXUDB_INSTANCES)
496 #else
497 #define CY_BLOCK_COUNT_UDB (0)
498 #endif
499
500 #if defined(CY_IP_MXUSBFS_INSTANCES)
501 #define CY_BLOCK_COUNT_USB (CY_IP_MXUSBFS_INSTANCES)
502 #else
503 #define CY_BLOCK_COUNT_USB (0)
504 #endif
505
506 #if defined(CY_IP_MXUSBPD_INSTANCES)
507 #define CY_BLOCK_COUNT_USBPD CY_IP_MXUSBPD_INSTANCES
508 #else
509 #define CY_BLOCK_COUNT_USBPD (0)
510 #endif
511
512 #if defined(CY_IP_MXS40SRSS) || defined(CY_IP_MXS40SSRSS) || defined(CY_IP_MXS22SRSS)
513 #define CY_BLOCK_COUNT_MCWDT (SRSS_NUM_MCWDT)
514 #elif (defined(CY_IP_S8SRSSLT_INSTANCES) && defined(CY_IP_M0S8WCO))
515 #define CY_BLOCK_COUNT_MCWDT (CY_IP_M0S8WCO_INSTANCES)
516 #else
517 #define CY_BLOCK_COUNT_MCWDT (0)
518 #endif
519
520 #if (defined(CY_IP_MXTCPWM_INSTANCES) && (CY_IP_MXTCPWM_VERSION >= 2) && (CY_IP_MXTCPWM_INSTANCES == 2))
521 #if (TCPWM0_GRP_NR > 3)
522 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR + TCPWM0_GRP_NR3_GRP_GRP_CNT_NR)
523 #elif (TCPWM0_GRP_NR > 2)
524 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR)
525 #elif (TCPWM0_GRP_NR > 1)
526 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR)
527 #elif (TCPWM0_GRP_NR > 0)
528 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR)
529 #endif
530 #if (TCPWM1_GRP_NR > 3)
531 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR + TCPWM1_GRP_NR3_GRP_GRP_CNT_NR)
532 #elif (TCPWM1_GRP_NR > 2)
533 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR)
534 #elif (TCPWM1_GRP_NR > 1)
535 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR)
536 #elif (TCPWM1_GRP_NR > 0)
537 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR)
538 #endif
539 #endif
540
541 /*
542 All resources have an offset and a size, offsets are stored in an array
543 Subsequent resource offset equals the preceding offset + size
544 Offsets are bit indexes in the arrays that track used, configured etc.
545
546 Channel based resources have an extra array for block offsets
547
548 Note these are NOT offsets into the device's MMIO address space;
549 they are bit offsets into arrays that are internal to the HW mgr.
550 */
551
552
553 #define CY_OFFSET_ADC 0
554 #define CY_SIZE_ADC CY_BLOCK_COUNT_ADC
555 #define CY_OFFSET_ADCMIC (CY_OFFSET_ADC + CY_SIZE_ADC)
556 #define CY_SIZE_ADCMIC CY_BLOCK_COUNT_ADCMIC
557 #define CY_OFFSET_BLE (CY_OFFSET_ADCMIC + CY_SIZE_ADCMIC)
558 #define CY_SIZE_BLE CY_BLOCK_COUNT_BLE
559 #define CY_OFFSET_CAN (CY_OFFSET_BLE + CY_SIZE_BLE)
560 #define CY_SIZE_CAN CY_CHANNEL_COUNT_CAN
561 #define CY_OFFSET_CLOCK (CY_OFFSET_CAN + CY_SIZE_CAN)
562 #define CY_SIZE_CLOCK CY_CHANNEL_COUNT_CLOCK
563 #define CY_OFFSET_CRYPTO (CY_OFFSET_CLOCK + CY_SIZE_CLOCK)
564 #define CY_SIZE_CRYPTO CY_BLOCK_COUNT_CRYPTO
565 #define CY_OFFSET_DAC (CY_OFFSET_CRYPTO + CY_SIZE_CRYPTO)
566 #define CY_SIZE_DAC CY_BLOCK_COUNT_DAC
567 #define CY_OFFSET_DMA (CY_OFFSET_DAC + CY_SIZE_DAC)
568 #define CY_SIZE_DMA CY_CHANNEL_COUNT_DMA
569 #define CY_OFFSET_DW (CY_OFFSET_DMA + CY_SIZE_DMA)
570 #define CY_SIZE_DW CY_CHANNEL_COUNT_DW
571 #define CY_OFFSET_ETH (CY_OFFSET_DW + CY_SIZE_DW)
572 #define CY_SIZE_ETH CY_BLOCK_COUNT_ETH
573 #define CY_OFFSET_GPIO (CY_OFFSET_ETH + CY_SIZE_ETH)
574 #define CY_SIZE_GPIO CY_CHANNEL_COUNT_GPIO
575 #define CY_OFFSET_I2S (CY_OFFSET_GPIO + CY_SIZE_GPIO)
576 #define CY_SIZE_I2S CY_BLOCK_COUNT_I2S
577 #define CY_OFFSET_I3C (CY_OFFSET_I2S + CY_SIZE_I2S)
578 #define CY_SIZE_I3C CY_BLOCK_COUNT_I3C
579 #define CY_OFFSET_KEYSCAN (CY_OFFSET_I3C + CY_SIZE_I3C)
580 #define CY_SIZE_KEYSCAN CY_BLOCK_COUNT_KEYSCAN
581 #define CY_OFFSET_LCD (CY_OFFSET_KEYSCAN + CY_SIZE_KEYSCAN)
582 #define CY_SIZE_LCD CY_BLOCK_COUNT_LCD
583 #define CY_OFFSET_LIN (CY_OFFSET_LCD + CY_SIZE_LCD)
584 #define CY_SIZE_LIN CY_BLOCK_COUNT_LIN
585 #define CY_OFFSET_LPCOMP (CY_OFFSET_LIN + CY_SIZE_LIN)
586 #define CY_SIZE_LPCOMP CY_CHANNEL_COUNT_LPCOMP
587 #define CY_OFFSET_LPTIMER (CY_OFFSET_LPCOMP + CY_SIZE_LPCOMP)
588 #define CY_SIZE_LPTIMER CY_BLOCK_COUNT_MCWDT
589 #define CY_OFFSET_OPAMP (CY_OFFSET_LPTIMER + CY_SIZE_LPTIMER)
590 #define CY_SIZE_OPAMP CY_CHANNEL_COUNT_OPAMP
591 #define CY_OFFSET_PDMPCM (CY_OFFSET_OPAMP + CY_SIZE_OPAMP)
592 #define CY_SIZE_PDMPCM CY_BLOCK_COUNT_PDMPCM
593 #define CY_OFFSET_QSPI (CY_OFFSET_PDMPCM + CY_SIZE_PDMPCM)
594 #define CY_SIZE_QSPI CY_BLOCK_COUNT_QSPI
595 #define CY_OFFSET_RTC (CY_OFFSET_QSPI + CY_SIZE_QSPI)
596 #define CY_SIZE_RTC CY_BLOCK_COUNT_RTC
597 #define CY_OFFSET_SCB (CY_OFFSET_RTC + CY_SIZE_RTC)
598 #define CY_SIZE_SCB CY_BLOCK_COUNT_SCB
599 #define CY_OFFSET_SDHC (CY_OFFSET_SCB + CY_SIZE_SCB)
600 #define CY_SIZE_SDHC CY_BLOCK_COUNT_SDHC
601 #define CY_OFFSET_SDIODEV (CY_OFFSET_SDHC + CY_SIZE_SDHC)
602 #define CY_SIZE_SDIODEV CY_BLOCK_COUNT_SDIODEV
603 #define CY_OFFSET_TCPWM (CY_OFFSET_SDIODEV + CY_SIZE_SDIODEV)
604 #define CY_SIZE_TCPWM CY_CHANNEL_COUNT_TCPWM
605 #define CY_OFFSET_TDM (CY_OFFSET_TCPWM + CY_SIZE_TCPWM)
606 #define CY_SIZE_TDM CY_CHANNEL_COUNT_TDM
607 #define CY_OFFSET_UDB (CY_OFFSET_TDM + CY_SIZE_TDM)
608 #define CY_SIZE_UDB CY_BLOCK_COUNT_UDB
609 #define CY_OFFSET_USB (CY_OFFSET_UDB + CY_SIZE_UDB)
610 #define CY_SIZE_USB CY_BLOCK_COUNT_USB
611 #define CY_OFFSET_USBPD (CY_OFFSET_USB + CY_SIZE_USB)
612 #define CY_SIZE_USBPD CY_BLOCK_COUNT_USBPD
613
614 #define CY_TOTAL_ALLOCATABLE_ITEMS (CY_OFFSET_USBPD + CY_SIZE_USBPD)
615
616 /*******************************************************************************
617 * Variables
618 *******************************************************************************/
619
620 #if ((CY_CHANNEL_COUNT_GPIO) > 32)
621 /* 8 bits per port, offset = 8 * (portIdx) means port 33 has offset >= 256 */
622 typedef uint16_t _cyhal_hwmgr_offset_t;
623 #else
624 typedef uint8_t _cyhal_hwmgr_offset_t;
625 #endif
626
627 #if defined(COMPONENT_CAT1A)
628
629 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
630 #error "Too many clocks to use uint8_t as offset type"
631 #endif
632
633 #if (defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
634 #define _SRSS_NUM_PILO 0U
635 #if !defined(SRSS_NUM_PLL400M)
636 #define SRSS_NUM_PLL400M (0)
637 #endif
638 #define _SRSS_NUM_PLL (SRSS_NUM_PLL + SRSS_NUM_PLL400M)
639 #else /* (defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)) */
640 #define _SRSS_NUM_PILO 1U
641 #define _SRSS_NUM_PLL (SRSS_NUM_PLL)
642 #endif /* (defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)) */
643
644 /* The order of items here must match the order in cyhal_clock_impl.h
645 *
646 * Each entry in the array below is the prior entry plus the number of clocks that exist
647 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
648 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
649 * the subsequent value is increased by the define that specifies how many clocks are
650 * actually present. */
651 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[26] =
652 {
653 0, // 8-bit dividers
654 PERI_DIV_8_NR, // 16-bit dividers
655 PERI_DIV_8_NR + PERI_DIV_16_NR, // 16.5 bit dividers
656 PERI_DIV_8_NR + PERI_DIV_16_NR + PERI_DIV_16_5_NR, // 24.5 bit dividers
657
658 PERI_DIV_NR, // IMO
659 PERI_DIV_NR + 1, // ECO
660 PERI_DIV_NR + 2, // EXT
661 PERI_DIV_NR + 3, // ALTHF
662 PERI_DIV_NR + 4, // ALTLF
663 PERI_DIV_NR + 5, // ILO
664 #if (!(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)))
665 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + 5, // PILO
666 #endif /* (!(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))) */
667 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + 5, // WCO
668 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + 6, // MFO
669
670 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + 7, // PathMux
671
672 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 7, // FLL
673 #if (defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
674 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 8, // PLL200
675 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 8 + SRSS_NUM_PLL, // PLL400
676 #else
677 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + 8, // PLL
678 #endif
679
680 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + 8, // LF
681 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + 9, // MF
682 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + 10, // HF
683
684 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + SRSS_NUM_HFROOT + 10, // PUMP
685 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + SRSS_NUM_HFROOT + 11, // BAK
686 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + SRSS_NUM_HFROOT + 12, // TIMER
687 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + SRSS_NUM_HFROOT + 13, // AltSysTick
688
689 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + SRSS_NUM_HFROOT + 14, // Fast
690 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + SRSS_NUM_HFROOT + 15, // Peri
691 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + _SRSS_NUM_PILO + SRSS_NUM_CLKPATH + _SRSS_NUM_PLL + SRSS_NUM_HFROOT + 16, // Slow
692 };
693
694 #elif defined(COMPONENT_CAT1B)
695
696 #define CY_MXSPERI_PCLK_DIV_CNT(gr) ( \
697 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT) + \
698 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT) + \
699 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT) + \
700 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_24_5_VECT))
701
702 #define CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(gr) \
703 (PERI_DIV_OFFSET##gr), \
704 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT), \
705 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT), \
706 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT)
707
708 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
709 #define PERI_DIV_OFFSET0 (0)
710 #endif
711 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
712 #define PERI_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(0))
713 #endif
714 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 2
715 #define PERI_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1))
716 #endif
717 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 3
718 #define PERI_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2))
719 #endif
720 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 4
721 #define PERI_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3))
722 #endif
723 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 5
724 #define PERI_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4))
725 #endif
726 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 6
727 #define PERI_DIV_OFFSET6 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5))
728 #endif
729 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 7
730 #define PERI_DIV_OFFSET7 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6))
731 #endif
732 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 8
733 #define PERI_DIV_OFFSET8 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7))
734 #endif
735 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 9
736 #define PERI_DIV_OFFSET9 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8))
737 #endif
738 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 10
739 #define PERI_DIV_OFFSET10 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9))
740 #endif
741 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 11
742 #define PERI_DIV_OFFSET11 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10))
743 #endif
744 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 12
745 #define PERI_DIV_OFFSET12 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11))
746 #endif
747 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 13
748 #define PERI_DIV_OFFSET13 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12))
749 #endif
750 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 14
751 #define PERI_DIV_OFFSET14 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13))
752 #endif
753 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 15
754 #define PERI_DIV_OFFSET15 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13) + CY_MXSPERI_PCLK_DIV_CNT(14))
755 #endif
756
757
758 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
759 #error "Too many clocks to use uint8_t as offset type"
760 #endif
761
762 /* The order of items here must match the order in cyhal_clock_impl.h
763 *
764 * Each entry in the array below is the prior entry plus the number of clocks that exist
765 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
766 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
767 * the subsequent value is increased by the define that specifies how many clocks are
768 * actually present. */
769 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[PERI_PERI_PCLK_PCLK_GROUP_NR * 4 + 22] =
770 {
771 // Peripheral dividers (8-bit, 16-bit, 16.5-bit & 24.5 bit) for each group
772 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
773 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0),
774 #endif
775 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
776 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1),
777 #endif
778 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 2)
779 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(2),
780 #endif
781 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 3)
782 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(3),
783 #endif
784 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 4)
785 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(4),
786 #endif
787 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 5)
788 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(5),
789 #endif
790 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 6)
791 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(6),
792 #endif
793 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 7)
794 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(7),
795 #endif
796 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 8)
797 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(8),
798 #endif
799 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 9)
800 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(9),
801 #endif
802 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 10)
803 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(10),
804 #endif
805 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 11)
806 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(11),
807 #endif
808 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 12)
809 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(12),
810 #endif
811 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 13)
812 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(13),
813 #endif
814 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 14)
815 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(14),
816 #endif
817 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 15)
818 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(15),
819 #endif
820
821 PERI_DIV_NR, // IHO
822 PERI_DIV_NR + 1, // IMO
823 PERI_DIV_NR + 2, // ECO
824 PERI_DIV_NR + 3, // EXT
825 PERI_DIV_NR + 4, // ALTHF
826 PERI_DIV_NR + 5, // ALTLF
827 PERI_DIV_NR + 6, // ILO
828 PERI_DIV_NR + 7, // PILO
829 PERI_DIV_NR + 8, // WCO
830 PERI_DIV_NR + 9, // MFO
831
832 PERI_DIV_NR + 10, // PathMux
833
834 PERI_DIV_NR + SRSS_NUM_CLKPATH + 10, // FLL
835 PERI_DIV_NR + SRSS_NUM_CLKPATH + 11, // PLL200
836 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + 11, // PLL400
837 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 11, // ECO_PreScaler
838
839 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 12, // LF
840 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 13, // MF
841 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 14, // HF
842
843 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 14, // PUMP
844 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 15, // BAK
845 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 16, // AltSysTick
846 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 17, // Peri
847 };
848
849 #elif defined(COMPONENT_CAT1C)
850
851 #define CY_MXSPERI_PCLK_DIV_CNT(gr) ( \
852 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT) + \
853 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT) + \
854 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT) + \
855 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_24_5_VECT))
856
857 #define CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(gr) \
858 (PERI_DIV_OFFSET##gr), \
859 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT), \
860 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT), \
861 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT)
862
863 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
864 #define PERI_DIV_OFFSET0 (0)
865 #endif
866 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
867 #define PERI_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(0))
868 #endif
869 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 2
870 #define PERI_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1))
871 #endif
872 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 3
873 #define PERI_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2))
874 #endif
875 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 4
876 #define PERI_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3))
877 #endif
878 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 5
879 #define PERI_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4))
880 #endif
881 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 6
882 #define PERI_DIV_OFFSET6 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5))
883 #endif
884 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 7
885 #define PERI_DIV_OFFSET7 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6))
886 #endif
887 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 8
888 #define PERI_DIV_OFFSET8 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7))
889 #endif
890 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 9
891 #define PERI_DIV_OFFSET9 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8))
892 #endif
893 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 10
894 #define PERI_DIV_OFFSET10 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9))
895 #endif
896 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 11
897 #define PERI_DIV_OFFSET11 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10))
898 #endif
899 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 12
900 #define PERI_DIV_OFFSET12 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11))
901 #endif
902 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 13
903 #define PERI_DIV_OFFSET13 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12))
904 #endif
905 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 14
906 #define PERI_DIV_OFFSET14 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13))
907 #endif
908 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 15
909 #define PERI_DIV_OFFSET15 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13) + CY_MXSPERI_PCLK_DIV_CNT(14))
910 #endif
911
912
913 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
914 #error "Too many clocks to use uint8_t as offset type"
915 #endif
916
917 /* The order of items here must match the order in cyhal_clock_impl.h
918 *
919 * Each entry in the array below is the prior entry plus the number of clocks that exist
920 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
921 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
922 * the subsequent value is increased by the define that specifies how many clocks are
923 * actually present. */
924 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[PERI_PERI_PCLK_PCLK_GROUP_NR * 4 + 22] =
925 {
926 // Peripheral dividers (8-bit, 16-bit, 16.5-bit & 24.5 bit) for each group
927 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
928 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0),
929 #endif
930 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
931 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1),
932 #endif
933 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 2)
934 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(2),
935 #endif
936 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 3)
937 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(3),
938 #endif
939 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 4)
940 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(4),
941 #endif
942 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 5)
943 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(5),
944 #endif
945 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 6)
946 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(6),
947 #endif
948 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 7)
949 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(7),
950 #endif
951 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 8)
952 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(8),
953 #endif
954 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 9)
955 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(9),
956 #endif
957 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 10)
958 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(10),
959 #endif
960 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 11)
961 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(11),
962 #endif
963 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 12)
964 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(12),
965 #endif
966 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 13)
967 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(13),
968 #endif
969 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 14)
970 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(14),
971 #endif
972 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 15)
973 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(15),
974 #endif
975
976 PERI_DIV_NR, // IMO
977 PERI_DIV_NR + 1, // ECO
978 PERI_DIV_NR + 2, // EXT
979 PERI_DIV_NR + 3, // ILO
980 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + 3, // WCO
981 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + 4, // PathMux
982 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + 4, // FLL
983 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + 5, // PLL200
984 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + 5, // PLL400
985
986 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + 5, // LF
987 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + 6, // HF
988
989 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 6, // BAK
990 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 7, // AltSysTick
991 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 8, // Peri
992 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 9, // Fast
993 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + _CYHAL_SRSS_NUM_FAST + 9, // Slow
994 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + _CYHAL_SRSS_NUM_FAST + 10, // MEM
995 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + _CYHAL_SRSS_NUM_FAST + 11, // Timer
996 };
997
998 #elif defined(COMPONENT_CAT1D)
999
1000 #define CY_MXSPERI_PCLK_DIV_CNT(instance, gr) ( \
1001 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT) + \
1002 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT) + \
1003 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT) + \
1004 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_24_5_VECT))
1005
1006 #define CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(instance, gr) \
1007 (PERI##instance##_DIV_OFFSET##gr), \
1008 (PERI##instance##_DIV_OFFSET##gr + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT), \
1009 (PERI##instance##_DIV_OFFSET##gr + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT), \
1010 (PERI##instance##_DIV_OFFSET##gr + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT)
1011
1012 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 0)
1013 #define PERI0_DIV_OFFSET0 (0)
1014 #endif
1015 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 1)
1016 #define PERI0_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(0, 0))
1017 #endif
1018 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 2
1019 #define PERI0_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1))
1020 #endif
1021 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 3
1022 #define PERI0_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2))
1023 #endif
1024 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 4
1025 #define PERI0_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3))
1026 #endif
1027 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 5
1028 #define PERI0_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4))
1029 #endif
1030 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 6
1031 #define PERI0_DIV_OFFSET6 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5))
1032 #endif
1033 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 7
1034 #define PERI0_DIV_OFFSET7 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6))
1035 #endif
1036 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 8
1037 #define PERI0_DIV_OFFSET8 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7))
1038 #endif
1039 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 9
1040 #define PERI0_DIV_OFFSET9 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7) + CY_MXSPERI_PCLK_DIV_CNT(0, 8))
1041 #endif
1042
1043 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 0)
1044 #define PERI1_DIV_OFFSET0 (0)
1045 #endif
1046 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 1)
1047 #define PERI1_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(1, 0))
1048 #endif
1049 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 2
1050 #define PERI1_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1))
1051 #endif
1052 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 3
1053 #define PERI1_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2))
1054 #endif
1055 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 4
1056 #define PERI1_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3))
1057 #endif
1058 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 5
1059 #define PERI1_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3) + CY_MXSPERI_PCLK_DIV_CNT(1, 4))
1060 #endif
1061 #if defined(PERI2_PERI_PCLK_PCLK_GROUP_NR)
1062 #warning "PERI2 dividers instance is not handled"
1063 #endif /* defined(PERI2_PERI_PCLK_PCLK_GROUP_NR) */
1064
1065 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
1066 #error "Too many clocks to use uint8_t as offset type"
1067 #endif
1068
1069 #if !defined(PERI0_PERI_PCLK_PCLK_GROUP_NR) || !defined(PERI1_PERI_PCLK_PCLK_GROUP_NR)
1070 #error "Unexpected number of PERI blocks"
1071 #endif /* !defined(PERI0_PERI_PCLK_PCLK_GROUP_NR) || !defined(PERI1_PERI_PCLK_PCLK_GROUP_NR) */
1072
1073 /* The order of items here must match the order in cyhal_clock_impl.h
1074 *
1075 * Each entry in the array below is the prior entry plus the number of clocks that exist
1076 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
1077 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
1078 * the subsequent value is increased by the define that specifies how many clocks are
1079 * actually present. */
1080 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[(PERI0_PERI_PCLK_PCLK_GROUP_NR + PERI1_PERI_PCLK_PCLK_GROUP_NR) * 4 + 14] =
1081 {
1082 // Peripheral dividers (8-bit, 16-bit, 16.5-bit & 24.5 bit) for each group
1083 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 0)
1084 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 0),
1085 #endif
1086 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 1)
1087 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 1),
1088 #endif
1089 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 2)
1090 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 2),
1091 #endif
1092 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 3)
1093 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 3),
1094 #endif
1095 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 4)
1096 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 4),
1097 #endif
1098 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 5)
1099 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 5),
1100 #endif
1101 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 6)
1102 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 6),
1103 #endif
1104 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 7)
1105 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 7),
1106 #endif
1107 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 8)
1108 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 8),
1109 #endif
1110 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 9)
1111 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 9),
1112 #endif
1113 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 10)
1114 #warning "Unhandled number of PERI0 PCLK"
1115 #endif
1116
1117 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 0)
1118 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 0),
1119 #endif
1120 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 1)
1121 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 1),
1122 #endif
1123 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 2)
1124 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 2),
1125 #endif
1126 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 3)
1127 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 3),
1128 #endif
1129 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 4)
1130 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 4),
1131 #endif
1132 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 5)
1133 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 5),
1134 #endif
1135 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 6)
1136 #warning "Unhandled number of PERI1 PCLK"
1137 #endif
1138
1139 PERI_DIV_NR, // IHO
1140 PERI_DIV_NR + 1, // ECO
1141 PERI_DIV_NR + 2, // EXT
1142 PERI_DIV_NR + 3, // PILO
1143 PERI_DIV_NR + 4, // WCO
1144
1145 PERI_DIV_NR + 5, // PathMux
1146
1147 PERI_DIV_NR + SRSS_NUM_CLKPATH + 5, // DPLL_LP
1148 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + 5, // DPLL_HP
1149 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 5, // ECO_PreScaler
1150
1151 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 6, // LF
1152 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 7, // MF
1153 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 8, // HF
1154
1155 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + SRSS_NUM_HFROOT + 8, // BAK
1156 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + SRSS_NUM_HFROOT + 9 // Peri
1157
1158 };
1159
1160 #elif defined(COMPONENT_CAT2)
1161 /* The order of items here must match the order in cyhal_clock_impl.h
1162 *
1163 * Each entry in the array below is the prior entry plus the number of clocks that exist
1164 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
1165 * one higher than the previous value. When there are multiple clocks (e.g.: PCLK)
1166 * the subsequent value is increased by the define that specifies how many clocks are
1167 * actually present. */
1168 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[16] =
1169 {
1170 0, // 8-bit dividers
1171 PERI_PCLK_DIV_8_NR, // 16-bit dividers
1172 PERI_PCLK_DIV_8_NR + PERI_PCLK_DIV_16_NR, // 16.5 bit dividers
1173 PERI_PCLK_DIV_8_NR + PERI_PCLK_DIV_16_NR + PERI_PCLK_DIV_16_5_NR, // 24.5 bit dividers
1174
1175 PERI_PCLK_CLOCK_NR, // IMO
1176 PERI_PCLK_CLOCK_NR + 1, // ECO
1177 PERI_PCLK_CLOCK_NR + 2, // EXT
1178 PERI_PCLK_CLOCK_NR + 3, // ILO
1179 PERI_PCLK_CLOCK_NR + 4, // WCO
1180
1181 PERI_PCLK_CLOCK_NR + 5, // WDCSEL
1182 PERI_PCLK_CLOCK_NR + 6, // PLLSEL
1183 PERI_PCLK_CLOCK_NR + 7, // PLL
1184 PERI_PCLK_CLOCK_NR + 8, // LF
1185 PERI_PCLK_CLOCK_NR + 9, // HF
1186 PERI_PCLK_CLOCK_NR + 10, // PUMP
1187 PERI_PCLK_CLOCK_NR + 11, // SYS
1188 };
1189 #endif
1190
1191 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_dma[] =
1192 {
1193 0,
1194 #if defined(CY_IP_MXAHBDMAC_INSTANCES)
1195 #if (CY_IP_MXAHBDMAC_INSTANCES > 1)
1196 MXAHBDMAC0_CH_NR,
1197 #endif
1198 #if (CY_IP_MXAHBDMAC_INSTANCES > 2)
1199 MXAHBDMAC0_CH_NR + MXAHBDMAC1_CH_NR,
1200 #endif
1201 #if (CY_IP_MXAHBDMAC_INSTANCES > 3)
1202 #warning Unhandled DMA instance count
1203 #endif
1204 #endif /* defined(CY_IP_MXAHBDMAC_INSTANCES) */
1205 };
1206
1207 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1208 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_dw[] =
1209 {
1210 0,
1211 CPUSS_DW0_CH_NR,
1212 };
1213
1214 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_tdm[] =
1215 {
1216 0,
1217 #if defined(CY_IP_MXTDM_INSTANCES)
1218 #if (CY_IP_MXTDM_INSTANCES > 1)
1219 TDM_NR,
1220 #endif
1221 #endif
1222 };
1223 #endif
1224
1225 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_gpio[] =
1226 {
1227 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
1228 #if defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1229 /* Most devices don't have more than 16 ports, so save the flash in most cases */
1230 128, 136, 144, 152, 160, 168, 176, 184, 192, 200, 208, 216, 224,
1231 232, 240, 248, 256, 264, 272, 280
1232 #elif (defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
1233 /* Covers TVIIBE parts */
1234 128, 136, 144, 152, 160, 168, 176, 184
1235 #endif
1236 };
1237
1238 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_can[] =
1239 {
1240 #ifdef CY_IP_MXTTCANFD_INSTANCES
1241 #if (CY_IP_MXTTCANFD_INSTANCES > 0)
1242 0,
1243 #endif
1244 #if (CY_IP_MXTTCANFD_INSTANCES > 1)
1245 CANFD0_CAN_NR,
1246 #endif
1247 #if (CY_IP_MXTTCANFD_INSTANCES > 2)
1248 CANFD0_CAN_NR + CANFD1_CAN_NR,
1249 #endif
1250 #if (CY_IP_MXTTCANFD_INSTANCES > 3)
1251 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR,
1252 #endif
1253 #if (CY_IP_MXTTCANFD_INSTANCES > 4)
1254 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR,
1255 #endif
1256 #if (CY_IP_MXTTCANFD_INSTANCES > 5)
1257 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR,
1258 #endif
1259 #if (CY_IP_MXTTCANFD_INSTANCES > 6)
1260 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR,
1261 #endif
1262 #if (CY_IP_MXTTCANFD_INSTANCES > 7)
1263 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR,
1264 #endif
1265 #if (CY_IP_MXTTCANFD_INSTANCES > 8)
1266 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR,
1267 #endif
1268 #if (CY_IP_MXTTCANFD_INSTANCES > 9)
1269 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR,
1270 #endif
1271 #if (CY_IP_MXTTCANFD_INSTANCES > 10)
1272 #warning Unhandled CAN instance count
1273 #endif
1274 #else
1275 0
1276 #endif
1277 };
1278
1279 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_lpcomp[] =
1280 {
1281 0,
1282 #if (CY_BLOCK_COUNT_LPCOMP > 1)
1283 #error "Unhandled LPComp count"
1284 #endif
1285 };
1286
1287 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_opamp[] =
1288 {
1289 0,
1290 #if (CY_BLOCK_COUNT_OPAMP > 1)
1291 2,
1292 #elif (CY_BLOCK_COUNT_OPAMP > 2)
1293 #error "Unhandled Opamp count"
1294 #endif
1295 };
1296
1297 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_tcpwm[] =
1298 {
1299 0,
1300 #ifdef CY_IP_MXTCPWM_INSTANCES
1301 #if CY_IP_MXTCPWM_VERSION == 1
1302 #if (CY_IP_MXTCPWM_INSTANCES > 1)
1303 TCPWM0_CNT_NR,
1304 #endif
1305 #if (CY_IP_MXTCPWM_INSTANCES > 2)
1306 TCPWM0_CNT_NR + TCPWM1_CNT_NR,
1307 #endif
1308 #if (CY_IP_MXTCPWM_INSTANCES > 3)
1309 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR,
1310 #endif
1311 #if (CY_IP_MXTCPWM_INSTANCES > 4)
1312 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR,
1313 #endif
1314 #if (CY_IP_MXTCPWM_INSTANCES > 5)
1315 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR,
1316 #endif
1317 #if (CY_IP_MXTCPWM_INSTANCES > 6)
1318 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR,
1319 #endif
1320 #if (CY_IP_MXTCPWM_INSTANCES > 7)
1321 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR,
1322 #endif
1323 #if (CY_IP_MXTCPWM_INSTANCES > 8)
1324 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR,
1325 #endif
1326 #if (CY_IP_MXTCPWM_INSTANCES > 9)
1327 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR,
1328 #endif
1329 #if (CY_IP_MXTCPWM_INSTANCES > 10)
1330 #warning Unhandled TCPWM instance count
1331 #endif
1332 #else // CY_IP_MXTCPWM_VERSION >= 2
1333 #if (CY_IP_MXTCPWM_INSTANCES == 1)
1334 #if (TCPWM_GRP_NR > 1)
1335 TCPWM_GRP_NR0_GRP_GRP_CNT_NR,
1336 #endif
1337 #if (TCPWM_GRP_NR > 2)
1338 TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR,
1339 #endif
1340 #if (TCPWM_GRP_NR > 3)
1341 TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR + TCPWM_GRP_NR2_GRP_GRP_CNT_NR,
1342 #endif
1343 #elif (CY_IP_MXTCPWM_INSTANCES == 2)
1344 // The 'else's are placeholders to ensure the groups line up, even if groups are empty or absent
1345 #if (TCPWM0_GRP_NR > 1)
1346 TCPWM0_GRP_NR0_GRP_GRP_CNT_NR,
1347 #else
1348 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1349 #endif
1350 #if (TCPWM0_GRP_NR > 2)
1351 TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR,
1352 #else
1353 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1354 #endif
1355 #if (TCPWM0_GRP_NR > 3)
1356 TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR,
1357 #else
1358 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1359 #endif
1360
1361 #if (TCPWM1_GRP_NR > 0)
1362 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1363 #else
1364 _CYHAL_TCPWM0_TOTAL_CNT_NR + _CYHAL_TCPWM1_TOTAL_CNT_NR,
1365 #endif
1366 #if (TCPWM1_GRP_NR > 1)
1367 _CYHAL_TCPWM0_TOTAL_CNT_NR + TCPWM1_GRP_NR0_GRP_GRP_CNT_NR,
1368 #else
1369 _CYHAL_TCPWM0_TOTAL_CNT_NR +_CYHAL_TCPWM1_TOTAL_CNT_NR,
1370 #endif
1371 #if (TCPWM1_GRP_NR > 2)
1372 _CYHAL_TCPWM0_TOTAL_CNT_NR + TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR,
1373 #else
1374 _CYHAL_TCPWM0_TOTAL_CNT_NR +_CYHAL_TCPWM1_TOTAL_CNT_NR,
1375 #endif
1376 #if (TCPWM1_GRP_NR > 3)
1377 _CYHAL_TCPWM0_TOTAL_CNT_NR + TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR,
1378 #else
1379 _CYHAL_TCPWM0_TOTAL_CNT_NR +_CYHAL_TCPWM1_TOTAL_CNT_NR,
1380 #endif
1381 #else
1382 #warning Unhandled TCPWM instance count
1383 #endif
1384 #endif
1385 #endif
1386 };
1387
1388 static uint8_t cyhal_used[(CY_TOTAL_ALLOCATABLE_ITEMS + 7) / 8] = {0};
1389
1390 // Note: the ordering here needs to be parallel to that of cyhal_resource_t
1391 static const uint16_t cyhal_resource_offsets[] =
1392 {
1393 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1394 CY_OFFSET_ADC,
1395 CY_OFFSET_ADCMIC,
1396 CY_OFFSET_BLE,
1397 CY_OFFSET_CAN,
1398 CY_OFFSET_CLOCK, /* Placeholder for ClockPath which is deprecated */
1399 CY_OFFSET_CLOCK,
1400 CY_OFFSET_CRYPTO,
1401 CY_OFFSET_DAC,
1402 CY_OFFSET_DMA,
1403 CY_OFFSET_DW,
1404 CY_OFFSET_ETH,
1405 CY_OFFSET_GPIO,
1406 CY_OFFSET_I2S,
1407 CY_OFFSET_I3C,
1408 CY_OFFSET_KEYSCAN,
1409 CY_OFFSET_LCD,
1410 CY_OFFSET_LIN,
1411 CY_OFFSET_LPCOMP,
1412 CY_OFFSET_LPTIMER,
1413 CY_OFFSET_OPAMP,
1414 CY_OFFSET_PDMPCM,
1415 CY_OFFSET_QSPI,
1416 CY_OFFSET_RTC,
1417 CY_OFFSET_SCB,
1418 CY_OFFSET_SDHC,
1419 CY_OFFSET_SDIODEV,
1420 CY_OFFSET_TCPWM,
1421 CY_OFFSET_TDM,
1422 CY_OFFSET_UDB,
1423 CY_OFFSET_USB,
1424 #elif defined(COMPONENT_CAT2)
1425 CY_OFFSET_ADC,
1426 CY_OFFSET_CAN,
1427 CY_OFFSET_CLOCK,
1428 CY_OFFSET_CRYPTO,
1429 CY_OFFSET_DMA,
1430 CY_OFFSET_GPIO,
1431 CY_OFFSET_I2S,
1432 CY_OFFSET_LCD,
1433 CY_OFFSET_LPCOMP,
1434 CY_OFFSET_LPTIMER,
1435 CY_OFFSET_OPAMP,
1436 CY_OFFSET_SCB,
1437 CY_OFFSET_TCPWM,
1438 CY_OFFSET_USB,
1439 CY_OFFSET_USBPD,
1440 #endif
1441 };
1442
1443 #define _CYHAL_RESOURCES (sizeof(cyhal_resource_offsets)/sizeof(cyhal_resource_offsets[0]))
1444
1445 static const uint32_t cyhal_has_channels =
1446 (1 << CYHAL_RSC_CAN) |
1447 (1 << CYHAL_RSC_CLOCK) |
1448 (1 << CYHAL_RSC_DMA) |
1449 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1450 (1 << CYHAL_RSC_DW) |
1451 (1 << CYHAL_RSC_TDM) |
1452 #endif
1453 (1 << CYHAL_RSC_GPIO) |
1454 (1 << CYHAL_RSC_LPCOMP)|
1455 (1 << CYHAL_RSC_OPAMP) |
1456 (1 << CYHAL_RSC_TCPWM) ;
1457
1458 /*******************************************************************************
1459 * Utility helper functions
1460 *******************************************************************************/
1461
_cyhal_uses_channels(cyhal_resource_t type)1462 static inline uint16_t _cyhal_uses_channels(cyhal_resource_t type)
1463 {
1464 return (cyhal_has_channels & (1 << type)) > 0;
1465 }
1466
_cyhal_get_resource_offset(cyhal_resource_t type)1467 static inline uint16_t _cyhal_get_resource_offset(cyhal_resource_t type)
1468 {
1469 return cyhal_resource_offsets[type];
1470 }
1471
_cyhal_get_block_offsets(cyhal_resource_t type)1472 static inline const _cyhal_hwmgr_offset_t* _cyhal_get_block_offsets(cyhal_resource_t type)
1473 {
1474 switch (type)
1475 {
1476 case CYHAL_RSC_CAN:
1477 return cyhal_block_offsets_can;
1478 case CYHAL_RSC_CLOCK:
1479 return cyhal_block_offsets_clock;
1480 case CYHAL_RSC_DMA:
1481 return cyhal_block_offsets_dma;
1482 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1483 case CYHAL_RSC_DW:
1484 return cyhal_block_offsets_dw;
1485 case CYHAL_RSC_TDM:
1486 return cyhal_block_offsets_tdm;
1487 #endif
1488 case CYHAL_RSC_GPIO:
1489 return cyhal_block_offsets_gpio;
1490 case CYHAL_RSC_LPCOMP:
1491 return cyhal_block_offsets_lpcomp;
1492 case CYHAL_RSC_OPAMP:
1493 return cyhal_block_offsets_opamp;
1494 case CYHAL_RSC_TCPWM:
1495 return cyhal_block_offsets_tcpwm;
1496 default:
1497 CY_ASSERT(false);
1498 return NULL;
1499 }
1500 }
1501
1502 // Gets the number of block offset entries, only valid for blocks which have channels.
_cyhal_get_block_offset_length(cyhal_resource_t type)1503 static inline uint8_t _cyhal_get_block_offset_length(cyhal_resource_t type)
1504 {
1505 switch (type)
1506 {
1507 case CYHAL_RSC_CAN:
1508 return sizeof(cyhal_block_offsets_can)/sizeof(cyhal_block_offsets_can[0]);
1509 case CYHAL_RSC_CLOCK:
1510 return sizeof(cyhal_block_offsets_clock)/sizeof(cyhal_block_offsets_clock[0]);
1511 case CYHAL_RSC_DMA:
1512 return sizeof(cyhal_block_offsets_dma)/sizeof(cyhal_block_offsets_dma[0]);
1513 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1514 case CYHAL_RSC_DW:
1515 return sizeof(cyhal_block_offsets_dw)/sizeof(cyhal_block_offsets_dw[0]);
1516 case CYHAL_RSC_TDM:
1517 return sizeof(cyhal_block_offsets_tdm)/sizeof(cyhal_block_offsets_tdm[0]);
1518 #endif
1519 case CYHAL_RSC_GPIO:
1520 return sizeof(cyhal_block_offsets_gpio)/sizeof(cyhal_block_offsets_gpio[0]);
1521 case CYHAL_RSC_LPCOMP:
1522 return sizeof(cyhal_block_offsets_lpcomp)/sizeof(cyhal_block_offsets_lpcomp[0]);
1523 case CYHAL_RSC_OPAMP:
1524 return sizeof(cyhal_block_offsets_opamp)/sizeof(cyhal_block_offsets_opamp[0]);
1525 case CYHAL_RSC_TCPWM:
1526 return sizeof(cyhal_block_offsets_tcpwm)/sizeof(cyhal_block_offsets_tcpwm[0]);
1527 default:
1528 CY_ASSERT(false);
1529 return 0;
1530 }
1531 }
1532
