1 /***************************************************************************//**
2 * \file cyhal_hwmgr_impl_part.h
3 *
4 * \brief
5 * Provides device specific information to the hardware manager. This file must
6 * only ever be included by cyhal_hwmgr.c.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the "License");
16 * you may not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * http://www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an "AS IS" BASIS,
23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 *******************************************************************************/
27
28 /*******************************************************************************
29 * Defines
30 *******************************************************************************/
31
32 #include "cyhal_hwmgr_impl.h"
33 #include "cyhal_interconnect.h"
34 #include "cyhal_scb_common.h"
35
36 #if defined(CY_IP_MXS40PASS_SAR_INSTANCES)
37 #define CY_BLOCK_COUNT_ADC (CY_IP_MXS40PASS_SAR_INSTANCES)
38 #elif defined (CY_IP_MXS40EPASS_ESAR_INSTANCES)
39 #define CY_BLOCK_COUNT_ADC (CY_IP_MXS40EPASS_ESAR_INSTANCES)
40 #elif defined (CY_IP_M0S8PASS4A_SAR_INSTANCES)
41 #define CY_BLOCK_COUNT_ADC (CY_IP_M0S8PASS4A_SAR_INSTANCES)
42 #else
43 #define CY_BLOCK_COUNT_ADC (0)
44 #endif
45
46 #if defined(CY_IP_MXS40ADCMIC_INSTANCES)
47 #define CY_BLOCK_COUNT_ADCMIC (CY_IP_MXS40ADCMIC_INSTANCES)
48 #else
49 #define CY_BLOCK_COUNT_ADCMIC (0)
50 #endif
51
52 #if defined(CY_IP_MXBLESS_INSTANCES)
53 #define CY_BLOCK_COUNT_BLE CY_IP_MXBLESS_INSTANCES
54 #else
55 #define CY_BLOCK_COUNT_BLE (0)
56 #endif
57
58 #if defined(CY_IP_MXTTCANFD_INSTANCES)
59 #define CY_BLOCK_COUNT_CAN (CY_IP_MXTTCANFD_INSTANCES)
60 #if (CY_IP_MXTTCANFD_INSTANCES == 0)
61 #define CY_CHANNEL_COUNT_CAN (0u)
62 #elif (CY_IP_MXTTCANFD_INSTANCES == 1)
63 #define CY_CHANNEL_COUNT_CAN (CANFD_CAN_NR)
64 #elif (CY_IP_MXTTCANFD_INSTANCES == 2)
65 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR)
66 #elif (CY_IP_MXTTCANFD_INSTANCES == 3)
67 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR)
68 #elif (CY_IP_MXTTCANFD_INSTANCES == 4)
69 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR)
70 #elif (CY_IP_MXTTCANFD_INSTANCES == 5)
71 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR)
72 #elif (CY_IP_MXTTCANFD_INSTANCES == 6)
73 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR)
74 #elif (CY_IP_MXTTCANFD_INSTANCES == 7)
75 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR)
76 #elif (CY_IP_MXTTCANFD_INSTANCES == 8)
77 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR)
78 #elif (CY_IP_MXTTCANFD_INSTANCES == 9)
79 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR)
80 #elif (CY_IP_MXTTCANFD_INSTANCES == 10)
81 #define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR + CANFD9_CAN_NR)
82 #elif (CY_IP_MXTTCANFD_INSTANCES > 10)
83 #warning Unhandled CAN instance count
84 #endif
85 #elif defined(CY_IP_M0S8CAN_INSTANCES)
86 #define CY_BLOCK_COUNT_CAN (CY_IP_M0S8CAN_INSTANCES)
87 #define CY_CHANNEL_COUNT_CAN (1)
88 #else
89 #define CY_BLOCK_COUNT_CAN (0)
90 #define CY_CHANNEL_COUNT_CAN (0)
91 #endif
92
93 #if defined(COMPONENT_CAT1A)
94 #define PERI_DIV_NR (PERI_DIV_8_NR + PERI_DIV_16_NR + PERI_DIV_16_5_NR + PERI_DIV_24_5_NR)
95 #elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
96 #if (_CYHAL_CLOCK_PERI_GROUPS == 0)
97 #define PERI_DIV_NR (0)
98 #elif (_CYHAL_CLOCK_PERI_GROUPS == 1)
99 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0))
100 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 2
101 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1))
102 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 3
103 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2))
104 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 4
105 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3))
106 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 5
107 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4))
108 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 6
109 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5))
110 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 7
111 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6))
112 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 8
113 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7))
114 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 9
115 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8))
116 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 10
117 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9))
118 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 11
119 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10))
120 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 12
121 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11))
122 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 13
123 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12))
124 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 14
125 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13))
126 #elif (_CYHAL_CLOCK_PERI_GROUPS) == 15
127 #define PERI_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13) + CY_MXSPERI_PCLK_DIV_CNT(14))
128 #else
129 #warning "PCLK table size exceeded"
130 #endif
131 #elif defined (COMPONENT_CAT1D)
132 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR == 0)
133 #define PERI0_DIV_NR (0)
134 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 1)
135 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0))
136 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 2)
137 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1))
138 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 3)
139 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2))
140 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 4)
141 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3))
142 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 5)
143 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4))
144 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 6)
145 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5))
146 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 7)
147 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6))
148 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 8)
149 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7))
150 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 9)
151 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7) + CY_MXSPERI_PCLK_DIV_CNT(0, 8))
152 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR == 10)
153 #define PERI0_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7) + CY_MXSPERI_PCLK_DIV_CNT(0, 8) + CY_MXSPERI_PCLK_DIV_CNT(0, 9))
154 #elif (PERI0_PERI_PCLK_PCLK_GROUP_NR > 10)
155 #error "Unhandled PERI0_PERI_PCLK_PCLK_GROUP_NR"
156 #endif /* multiple PERI0_PERI_PCLK_PCLK_GROUP_NR values */
157
158 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR == 0)
159 #define PERI1_DIV_NR (0)
160 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 1)
161 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0))
162 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 2)
163 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1))
164 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 3)
165 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2))
166 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 4)
167 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3))
168 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 5)
169 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3) + CY_MXSPERI_PCLK_DIV_CNT(1, 4))
170 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR == 6)
171 #define PERI1_DIV_NR (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3) + CY_MXSPERI_PCLK_DIV_CNT(1, 4) + CY_MXSPERI_PCLK_DIV_CNT(1, 5))
172 #elif (PERI1_PERI_PCLK_PCLK_GROUP_NR > 6)
173 #error "Unhandled PERI1_PERI_PCLK_PCLK_GROUP_NR"
174 #endif /* multiple PERI1_PERI_PCLK_PCLK_GROUP_NR values */
175
176 #define PERI_DIV_NR (PERI0_DIV_NR + PERI1_DIV_NR)
177 #endif
178
179 #if defined(COMPONENT_CAT1A)
180 // 12 dedicated = IMO, EXT, ILO, FLL, LF, Pump, BAK, Timer, AltSysTick, Slow, Fast, Peri
181 // 7 optional = ECO, ALTHF, ALTLF, PILO, WCO, MFO, MF
182 #define CY_CHANNEL_COUNT_CLOCK (12 + 7 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + PERI_DIV_NR)
183 #elif defined(COMPONENT_CAT1B)
184 // 10 dedicated = IHO, IMO, EXT, ILO, FLL, LF, Pump, BAK, AltSysTick, Peri
185 // 7 optional = ECO, ALTHF, ALTLF, PILO, WCO, MFO, MF
186 #define CY_CHANNEL_COUNT_CLOCK (10 + 7 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + PERI_DIV_NR)
187 // TODO : to be fixed
188 #elif defined(COMPONENT_CAT1C)
189 // 15 dedicated = IMO, EXT, ILO, IL01, FLL, LF, BAK, AltSysTick, Peri, Fast0, Fast1, Slow, Mem, Timer
190 // 2 optional = ECO, WCO
191 #define CY_CHANNEL_COUNT_CLOCK (14 + 2 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + PERI_DIV_NR)
192 #elif defined(COMPONENT_CAT1D)
193 // 7 dedicated = IHO, EXT, FLL, LF, BAK, AltSysTick
194 // 6 optional = ECO, ALTHF, ALTLF, PILO, WCO, MF
195 #define CY_CHANNEL_COUNT_CLOCK (6 + 6 + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + SRSS_NUM_HFROOT + PERI_DIV_NR)
196 #elif defined(COMPONENT_CAT2)
197 // 7 dedicated = IMO, EXT, ILO, HF, LF, PUMP, SYSCLK
198 // 5 optional = ECO, WCO, PLL, PLLSEL, WDCSEL
199 #define CY_CHANNEL_COUNT_CLOCK (7 + 5 + PERI_PCLK_CLOCK_NR)
200 #endif
201
202 #if defined(CY_IP_MXCRYPTO_INSTANCES)
203 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_MXCRYPTO_INSTANCES)
204 #elif defined(CY_IP_MXCRYPTOCELL_INSTANCES)
205 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_MXCRYPTOCELL_INSTANCES)
206 #elif defined(CPUSS_CRYPTO_PRESENT)
207 #define CY_BLOCK_COUNT_CRYPTO (CPUSS_CRYPTO_PRESENT)
208 #elif defined(CY_IP_M0S8CRYPTO_INSTANCES)
209 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_M0S8CRYPTO_INSTANCES)
210 #elif defined(CY_IP_M0S8CRYPTOLITE_INSTANCES)
211 #define CY_BLOCK_COUNT_CRYPTO (CY_IP_M0S8CRYPTOLITE_INSTANCES)
212 #else
213 #define CY_BLOCK_COUNT_CRYPTO (0)
214 #endif
215
216 #if defined(CY_IP_MXS40PASS_CTDAC_INSTANCES)
217 #define CY_BLOCK_COUNT_DAC (CY_IP_MXS40PASS_CTDAC_INSTANCES)
218 #else
219 #define CY_BLOCK_COUNT_DAC (0)
220 #endif
221
222 #if defined(CY_IP_M4CPUSS_DMAC_INSTANCES)
223 #define CY_BLOCK_COUNT_DMA (CY_IP_M4CPUSS_DMAC_INSTANCES)
224 #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR)
225 #elif defined(CY_IP_MXAHBDMAC_INSTANCES)
226 #define CY_BLOCK_COUNT_DMA (CY_IP_MXAHBDMAC_INSTANCES)
227
228 #if (CY_IP_MXAHBDMAC_INSTANCES == 0)
229 #define CY_CHANNEL_COUNT_DMA (0u)
230 #elif (CY_IP_MXAHBDMAC_INSTANCES == 1)
231 #define CY_CHANNEL_COUNT_DMA (MXAHBDMAC0_CH_NR)
232 #elif (CY_IP_MXAHBDMAC_INSTANCES == 2)
233 #define CY_CHANNEL_COUNT_DMA (MXAHBDMAC0_CH_NR + MXAHBDMAC1_CH_NR)
234 #elif (CY_IP_MXAHBDMAC_INSTANCES == 3)
235 #define CY_CHANNEL_COUNT_DMA (MXAHBDMAC0_CH_NR + MXAHBDMAC1_CH_NR + MXAHBDMAC2_CH_NR)
236 #else
237 #warning Unhandled DMA instance count
238 #endif
239 #elif defined(CY_IP_MXSAXIDMAC_INSTANCES)
240 #define CY_BLOCK_COUNT_DMA (CY_IP_MXSAXIDMAC_INSTANCES)
241 #if (APPCPUSS_AXIDMAC1_PRESENT)
242 #define CY_CHANNEL_COUNT_DMA (APPCPUSS_AXIDMAC0_CH_NR + APPCPUSS_AXIDMAC1_CH_NR)
243 #else
244 #define CY_CHANNEL_COUNT_DMA (APPCPUSS_AXIDMAC0_CH_NR)
245 #endif
246 #elif defined(CPUSS_CPUMEMSS_DMAC_PRESENT)
247 #define CY_BLOCK_COUNT_DMA (CPUSS_CPUMEMSS_DMAC_PRESENT)
248 #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR)
249 #elif defined(CPUSS_DMAC_PRESENT)
250 #define CY_BLOCK_COUNT_DMA (CPUSS_DMAC_PRESENT)
251 #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR)
252 #else
253 #define CY_BLOCK_COUNT_DMA (0)
254 #define CY_CHANNEL_COUNT_DMA (0)
255 #endif
256
257 #if defined(CY_IP_M4CPUSS_DMA_INSTANCES)
258 #define CY_BLOCK_COUNT_DW (CY_IP_M4CPUSS_DMA_INSTANCES)
259 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
260 #elif defined(CY_IP_MXDW_INSTANCES) && (CPUSS_DW0_PRESENT == 1)
261 #define CY_BLOCK_COUNT_DW (CY_IP_MXDW_INSTANCES)
262 #if(CPUSS_DW1_PRESENT == 1)
263 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
264 #else
265 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR)
266 #endif
267 #elif defined(CPUSS_DW_NR)
268 #define CY_BLOCK_COUNT_DW (CPUSS_DW_NR)
269 #if (CPUSS_DW_NR == 0)
270 #define CY_CHANNEL_COUNT_DW (0)
271 #elif (CPUSS_DW_NR == 1)
272 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR)
273 #elif (CPUSS_DW_NR == 2)
274 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)
275 #else
276 #warning "Unhandled number of DataWire controllers."
277 #endif /* CPUSS_DW_NR is 0, 1, 2, or other (unhandled) */
278 #else
279 #define CY_BLOCK_COUNT_DW (0)
280 #define CY_CHANNEL_COUNT_DW (0)
281 #endif
282
283 #ifdef CY_IP_MXETH_INSTANCES
284 #define CY_BLOCK_COUNT_ETH (CY_IP_MXETH_INSTANCES)
285 #else
286 #define CY_BLOCK_COUNT_ETH (0)
287 #endif
288
289 #if defined(IOSS_GPIO_GPIO_PORT_NR)
290 #define CY_BLOCK_COUNT_GPIO (IOSS_GPIO_GPIO_PORT_NR)
291 #define CY_CHANNEL_COUNT_GPIO (8 * IOSS_GPIO_GPIO_PORT_NR)
292 #else
293 #define CY_BLOCK_COUNT_GPIO (0)
294 #define CY_CHANNEL_COUNT_GPIO (0)
295 #endif
296
297 #if defined(CY_IP_MXAUDIOSS_INSTANCES)
298 #define CY_BLOCK_COUNT_I2S (CY_IP_MXAUDIOSS_INSTANCES)
299 #else
300 #define CY_BLOCK_COUNT_I2S (0)
301 #endif
302
303 #ifdef CY_IP_MXI3C_INSTANCES
304 #define CY_BLOCK_COUNT_I3C (CY_IP_MXI3C_INSTANCES)
305 #else
306 #define CY_BLOCK_COUNT_I3C (0)
307 #endif
308
309 #if defined(CY_IP_MXKEYSCAN_INSTANCES)
310 #define CY_BLOCK_COUNT_KEYSCAN (CY_IP_MXKEYSCAN_INSTANCES)
311 #else
312 #define CY_BLOCK_COUNT_KEYSCAN (0)
313 #endif
314
315 #if defined(CY_IP_MXLCD_INSTANCES)
316 #define CY_BLOCK_COUNT_LCD (CY_IP_MXLCD_INSTANCES)
317 #elif defined(CY_IP_M0S8LCD_INSTANCES)
318 #define CY_BLOCK_COUNT_LCD (CY_IP_M0S8LCD_INSTANCES)
319 #else
320 #define CY_BLOCK_COUNT_LCD (0)
321 #endif
322
323 #if defined(CY_IP_MXLIN_INSTANCES)
324 #define CY_BLOCK_COUNT_LIN (CY_IP_MXLIN_INSTANCES)
325 #else
326 #define CY_BLOCK_COUNT_LIN (0)
327 #endif
328
329 #if defined(CY_IP_MXLPCOMP_INSTANCES)
330 #define CY_BLOCK_COUNT_LPCOMP (CY_IP_MXLPCOMP_INSTANCES)
331 #elif defined(CY_IP_M0S8LPCOMP_INSTANCES)
332 #define CY_BLOCK_COUNT_LPCOMP (CY_IP_M0S8LPCOMP_INSTANCES)
333 #else
334 #define CY_BLOCK_COUNT_LPCOMP (0)
335 #endif
336 #define CY_CHANNEL_COUNT_LPCOMP (2 * CY_BLOCK_COUNT_LPCOMP)
337
338 #if defined(PASS_NR_CTBS)
339 #define CY_BLOCK_COUNT_OPAMP (PASS_NR_CTBS)
340 #elif defined(PASS0_NR_CTBS)
341 #if defined(PASS1_NR_CTBS)
342 #define CY_BLOCK_COUNT_OPAMP ((PASS0_NR_CTBS + PASS1_NR_CTBS))
343 #else
344 #define CY_BLOCK_COUNT_OPAMP (PASS0_NR_CTBS)
345 #endif
346 #else
347 #define CY_BLOCK_COUNT_OPAMP (0)
348 #endif
349 #define CY_CHANNEL_COUNT_OPAMP (2 * CY_BLOCK_COUNT_OPAMP)
350
351 #if defined(CY_IP_MXAUDIOSS_INSTANCES)
352 #define CY_BLOCK_COUNT_PDMPCM (CY_IP_MXAUDIOSS_INSTANCES)
353 #elif defined(CY_IP_MXPDM_INSTANCES)
354 #define CY_BLOCK_COUNT_PDMPCM (CY_IP_MXPDM_INSTANCES)
355 #else
356 #define CY_BLOCK_COUNT_PDMPCM (0)
357 #endif
358
359 #if defined(CY_IP_MXSMIF_INSTANCES)
360 #define CY_BLOCK_COUNT_QSPI (CY_IP_MXSMIF_INSTANCES)
361 #else
362 #define CY_BLOCK_COUNT_QSPI (0)
363 #endif
364
365 #if (defined(CY_IP_MXS40SSRSS) || defined(CY_IP_MXS40SRSS)) && SRSS_BACKUP_PRESENT
366 #define CY_BLOCK_COUNT_RTC (1)
367 #else
368 #define CY_BLOCK_COUNT_RTC (0)
369 #endif
370
371 #if defined(CY_IP_MXSCB_INSTANCES)|| defined(CY_IP_MXS22SCB_INSTANCES) || defined(CY_IP_M0S8SCB_INSTANCES)
372 #define CY_BLOCK_COUNT_SCB (_SCB_ARRAY_SIZE)
373 #else
374 #define CY_BLOCK_COUNT_SCB (0)
375 #endif
376
377 #if defined(CY_IP_MXSDHC_INSTANCES)
378 #define CY_BLOCK_COUNT_SDHC (CY_IP_MXSDHC_INSTANCES)
379 #else
380 #define CY_BLOCK_COUNT_SDHC (0)
381 #endif
382
383 #ifdef CY_IP_MXSDIODEV_INSTANCES
384 #define CY_BLOCK_COUNT_SDIODEV (CY_IP_MXSDIODEV_INSTANCES)
385 #else
386 #define CY_BLOCK_COUNT_SDIODEV (0)
387 #endif
388
389 #if defined(CY_IP_MXTCPWM_INSTANCES)
390 #define CY_BLOCK_COUNT_TCPWM CY_IP_MXTCPWM_INSTANCES
391 #if (CY_IP_MXTCPWM_VERSION == 1)
392 #if (CY_IP_MXTCPWM_INSTANCES == 0)
393 #define CY_CHANNEL_COUNT_TCPWM (0u)
394 #elif (CY_IP_MXTCPWM_INSTANCES == 1)
395 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR)
396 #elif (CY_IP_MXTCPWM_INSTANCES == 2)
397 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR)
398 #elif (CY_IP_MXTCPWM_INSTANCES == 3)
399 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR)
400 #elif (CY_IP_MXTCPWM_INSTANCES == 4)
401 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR)
402 #elif (CY_IP_MXTCPWM_INSTANCES == 5)
403 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR)
404 #elif (CY_IP_MXTCPWM_INSTANCES == 6)
405 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR)
406 #elif (CY_IP_MXTCPWM_INSTANCES == 7)
407 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR)
408 #elif (CY_IP_MXTCPWM_INSTANCES == 8)
409 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR)
410 #elif (CY_IP_MXTCPWM_INSTANCES == 9)
411 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR)
412 #elif (CY_IP_MXTCPWM_INSTANCES == 10)
413 #define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR + TCPWM9_CNT_NR)
414 #elif (CY_IP_MXTCPWM_INSTANCES > 10)
415 #warning Unhandled TCPWM instance count
416 #endif
417 #elif (CY_IP_MXTCPWM_VERSION == 2)
418 #if (CY_IP_MXTCPWM_INSTANCES == 1)
419 #if (TCPWM_GRP_NR == 0)
420 #define CY_CHANNEL_COUNT_TCPWM (0u)
421 #elif (TCPWM_GRP_NR == 1)
422 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR)
423 #elif (TCPWM_GRP_NR == 2)
424 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR)
425 #elif (TCPWM_GRP_NR == 3)
426 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR + TCPWM_GRP_NR2_GRP_GRP_CNT_NR)
427 #elif (TCPWM_GRP_NR == 4)
428 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR + TCPWM_GRP_NR2_GRP_GRP_CNT_NR + TCPWM_GRP_NR3_GRP_GRP_CNT_NR)
429 #elif (TCPWM_GRP_NR > 4)
430 #warning Unhandled TCPWM instance count
431 #endif
432 #elif (CY_IP_MXTCPWM_INSTANCES == 2)
433 #if (TCPWM0_GRP_NR == 0)
434 #define CY_CHANNEL_COUNT_TCPWM0 (0u)
435 #elif (TCPWM0_GRP_NR == 1)
436 #define CY_CHANNEL_COUNT_TCPWM0 (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR)
437 #elif (TCPWM0_GRP_NR == 2)
438 #define CY_CHANNEL_COUNT_TCPWM0 (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR)
439 #elif (TCPWM0_GRP_NR == 3)
440 #define CY_CHANNEL_COUNT_TCPWM0 (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR)
441 #elif (TCPWM0_GRP_NR > 3)
442 #warning Unhandled TCPWM instance count
443 #endif
444 #if (TCPWM1_GRP_NR == 0)
445 #define CY_CHANNEL_COUNT_TCPWM1 (0u)
446 #elif (TCPWM1_GRP_NR == 1)
447 #define CY_CHANNEL_COUNT_TCPWM1 (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR)
448 #elif (TCPWM1_GRP_NR == 2)
449 #define CY_CHANNEL_COUNT_TCPWM1 (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR)
450 #elif (TCPWM1_GRP_NR == 3)
451 #define CY_CHANNEL_COUNT_TCPWM1 (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR)
452 #elif (TCPWM1_GRP_NR > 3)
453 #warning Unhandled TCPWM instance count
454 #endif
455 #define CY_CHANNEL_COUNT_TCPWM (CY_CHANNEL_COUNT_TCPWM0 + CY_CHANNEL_COUNT_TCPWM1)
456 #elif (CY_IP_MXTCPWM_INSTANCES > 2)
457 #warning Unhandled TCPWM instance count
458 #endif
459 #else
460 #warning Unrecognized TCPWM IP version
461 #endif
462 #elif defined(CY_IP_M0S8TCPWM_INSTANCES)
463 #define CY_BLOCK_COUNT_TCPWM (CY_IP_M0S8TCPWM_INSTANCES)
464 #if (CY_IP_M0S8TCPWM_INSTANCES == 0)
465 #define CY_CHANNEL_COUNT_TCPWM (0u)
466 #elif (CY_IP_M0S8TCPWM_INSTANCES == 1)
467 #define CY_CHANNEL_COUNT_TCPWM (TCPWM_CNT_NR)
468 #else
469 #warning Unhandled TCPWM instance count
470 #endif
471 #else
472 #define CY_BLOCK_COUNT_TCPWM (0)
473 #define CY_CHANNEL_COUNT_TCPWM (0)
474 #endif
475
476 #ifdef CY_IP_MXTDM_INSTANCES
477 #define CY_BLOCK_COUNT_TDM (CY_IP_MXTDM_INSTANCES)
478 #if (CY_IP_MXTDM_INSTANCES == 0)
479 #define CY_CHANNEL_COUNT_TDM (0u)
480 #elif (CY_IP_MXTDM_INSTANCES == 1)
481 #define CY_CHANNEL_COUNT_TDM (TDM_NR)
482 #else
483 #warning Unhandled TDM instance count
484 #endif
485 #else
486 #define CY_BLOCK_COUNT_TDM (0)
487 #define CY_CHANNEL_COUNT_TDM (0u)
488 #endif
489
490 #if defined(CY_IP_MXUDB_INSTANCES)
491 #define CY_BLOCK_COUNT_UDB (CY_IP_MXUDB_INSTANCES)
492 #else
493 #define CY_BLOCK_COUNT_UDB (0)
494 #endif
495
496 #if defined(CY_IP_MXUSBFS_INSTANCES)
497 #define CY_BLOCK_COUNT_USB (CY_IP_MXUSBFS_INSTANCES)
498 #else
499 #define CY_BLOCK_COUNT_USB (0)
500 #endif
501
502 #if defined(CY_IP_MXUSBPD_INSTANCES)
503 #define CY_BLOCK_COUNT_USBPD CY_IP_MXUSBPD_INSTANCES
504 #else
505 #define CY_BLOCK_COUNT_USBPD (0)
506 #endif
507
508 #if defined(CY_IP_MXS40SRSS) || defined(CY_IP_MXS40SSRSS) || defined(CY_IP_MXS22SRSS)
509 #define CY_BLOCK_COUNT_MCWDT (SRSS_NUM_MCWDT)
510 #elif (defined(CY_IP_S8SRSSLT_INSTANCES) && defined(CY_IP_M0S8WCO))
511 #define CY_BLOCK_COUNT_MCWDT (CY_IP_M0S8WCO_INSTANCES)
512 #else
513 #define CY_BLOCK_COUNT_MCWDT (0)
514 #endif
515
516 #if (defined(CY_IP_MXTCPWM_INSTANCES) && (CY_IP_MXTCPWM_VERSION >= 2) && (CY_IP_MXTCPWM_INSTANCES == 2))
517 #if (TCPWM0_GRP_NR > 3)
518 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR + TCPWM0_GRP_NR3_GRP_GRP_CNT_NR)
519 #elif (TCPWM0_GRP_NR > 2)
520 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR)
521 #elif (TCPWM0_GRP_NR > 1)
522 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR)
523 #elif (TCPWM0_GRP_NR > 0)
524 #define _CYHAL_TCPWM0_TOTAL_CNT_NR (TCPWM0_GRP_NR0_GRP_GRP_CNT_NR)
525 #endif
526 #if (TCPWM1_GRP_NR > 3)
527 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR + TCPWM1_GRP_NR3_GRP_GRP_CNT_NR)
528 #elif (TCPWM1_GRP_NR > 2)
529 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR)
530 #elif (TCPWM1_GRP_NR > 1)
531 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR)
532 #elif (TCPWM1_GRP_NR > 0)
533 #define _CYHAL_TCPWM1_TOTAL_CNT_NR (TCPWM1_GRP_NR0_GRP_GRP_CNT_NR)
534 #endif
535 #endif
536
537 /*
538 All resources have an offset and a size, offsets are stored in an array
539 Subsequent resource offset equals the preceding offset + size
540 Offsets are bit indexes in the arrays that track used, configured etc.
541
542 Channel based resources have an extra array for block offsets
543
544 Note these are NOT offsets into the device's MMIO address space;
545 they are bit offsets into arrays that are internal to the HW mgr.
546 */
547
548
549 #define CY_OFFSET_ADC 0
550 #define CY_SIZE_ADC CY_BLOCK_COUNT_ADC
551 #define CY_OFFSET_ADCMIC (CY_OFFSET_ADC + CY_SIZE_ADC)
552 #define CY_SIZE_ADCMIC CY_BLOCK_COUNT_ADCMIC
553 #define CY_OFFSET_BLE (CY_OFFSET_ADCMIC + CY_SIZE_ADCMIC)
554 #define CY_SIZE_BLE CY_BLOCK_COUNT_BLE
555 #define CY_OFFSET_CAN (CY_OFFSET_BLE + CY_SIZE_BLE)
556 #define CY_SIZE_CAN CY_CHANNEL_COUNT_CAN
557 #define CY_OFFSET_CLOCK (CY_OFFSET_CAN + CY_SIZE_CAN)
558 #define CY_SIZE_CLOCK CY_CHANNEL_COUNT_CLOCK
559 #define CY_OFFSET_CRYPTO (CY_OFFSET_CLOCK + CY_SIZE_CLOCK)
560 #define CY_SIZE_CRYPTO CY_BLOCK_COUNT_CRYPTO
561 #define CY_OFFSET_DAC (CY_OFFSET_CRYPTO + CY_SIZE_CRYPTO)
562 #define CY_SIZE_DAC CY_BLOCK_COUNT_DAC
563 #define CY_OFFSET_DMA (CY_OFFSET_DAC + CY_SIZE_DAC)
564 #define CY_SIZE_DMA CY_CHANNEL_COUNT_DMA
565 #define CY_OFFSET_DW (CY_OFFSET_DMA + CY_SIZE_DMA)
566 #define CY_SIZE_DW CY_CHANNEL_COUNT_DW
567 #define CY_OFFSET_ETH (CY_OFFSET_DW + CY_SIZE_DW)
568 #define CY_SIZE_ETH CY_BLOCK_COUNT_ETH
569 #define CY_OFFSET_GPIO (CY_OFFSET_ETH + CY_SIZE_ETH)
570 #define CY_SIZE_GPIO CY_CHANNEL_COUNT_GPIO
571 #define CY_OFFSET_I2S (CY_OFFSET_GPIO + CY_SIZE_GPIO)
572 #define CY_SIZE_I2S CY_BLOCK_COUNT_I2S
573 #define CY_OFFSET_I3C (CY_OFFSET_I2S + CY_SIZE_I2S)
574 #define CY_SIZE_I3C CY_BLOCK_COUNT_I3C
575 #define CY_OFFSET_KEYSCAN (CY_OFFSET_I3C + CY_SIZE_I3C)
576 #define CY_SIZE_KEYSCAN CY_BLOCK_COUNT_KEYSCAN
577 #define CY_OFFSET_LCD (CY_OFFSET_KEYSCAN + CY_SIZE_KEYSCAN)
578 #define CY_SIZE_LCD CY_BLOCK_COUNT_LCD
579 #define CY_OFFSET_LIN (CY_OFFSET_LCD + CY_SIZE_LCD)
580 #define CY_SIZE_LIN CY_BLOCK_COUNT_LIN
581 #define CY_OFFSET_LPCOMP (CY_OFFSET_LIN + CY_SIZE_LIN)
582 #define CY_SIZE_LPCOMP CY_CHANNEL_COUNT_LPCOMP
583 #define CY_OFFSET_LPTIMER (CY_OFFSET_LPCOMP + CY_SIZE_LPCOMP)
584 #define CY_SIZE_LPTIMER CY_BLOCK_COUNT_MCWDT
585 #define CY_OFFSET_OPAMP (CY_OFFSET_LPTIMER + CY_SIZE_LPTIMER)
586 #define CY_SIZE_OPAMP CY_CHANNEL_COUNT_OPAMP
587 #define CY_OFFSET_PDMPCM (CY_OFFSET_OPAMP + CY_SIZE_OPAMP)
588 #define CY_SIZE_PDMPCM CY_BLOCK_COUNT_PDMPCM
589 #define CY_OFFSET_QSPI (CY_OFFSET_PDMPCM + CY_SIZE_PDMPCM)
590 #define CY_SIZE_QSPI CY_BLOCK_COUNT_QSPI
591 #define CY_OFFSET_RTC (CY_OFFSET_QSPI + CY_SIZE_QSPI)
592 #define CY_SIZE_RTC CY_BLOCK_COUNT_RTC
593 #define CY_OFFSET_SCB (CY_OFFSET_RTC + CY_SIZE_RTC)
594 #define CY_SIZE_SCB CY_BLOCK_COUNT_SCB
595 #define CY_OFFSET_SDHC (CY_OFFSET_SCB + CY_SIZE_SCB)
596 #define CY_SIZE_SDHC CY_BLOCK_COUNT_SDHC
597 #define CY_OFFSET_SDIODEV (CY_OFFSET_SDHC + CY_SIZE_SDHC)
598 #define CY_SIZE_SDIODEV CY_BLOCK_COUNT_SDIODEV
599 #define CY_OFFSET_TCPWM (CY_OFFSET_SDIODEV + CY_SIZE_SDIODEV)
600 #define CY_SIZE_TCPWM CY_CHANNEL_COUNT_TCPWM
601 #define CY_OFFSET_TDM (CY_OFFSET_TCPWM + CY_SIZE_TCPWM)
602 #define CY_SIZE_TDM CY_CHANNEL_COUNT_TDM
603 #define CY_OFFSET_UDB (CY_OFFSET_TDM + CY_SIZE_TDM)
604 #define CY_SIZE_UDB CY_BLOCK_COUNT_UDB
605 #define CY_OFFSET_USB (CY_OFFSET_UDB + CY_SIZE_UDB)
606 #define CY_SIZE_USB CY_BLOCK_COUNT_USB
607 #define CY_OFFSET_USBPD (CY_OFFSET_USB + CY_SIZE_USB)
608 #define CY_SIZE_USBPD CY_BLOCK_COUNT_USBPD
609
610 #define CY_TOTAL_ALLOCATABLE_ITEMS (CY_OFFSET_USBPD + CY_SIZE_USBPD)
611
612 /*******************************************************************************
613 * Variables
614 *******************************************************************************/
615
616 #if ((CY_CHANNEL_COUNT_GPIO) > 32)
617 /* 8 bits per port, offset = 8 * (portIdx) means port 33 has offset >= 256 */
618 typedef uint16_t _cyhal_hwmgr_offset_t;
619 #else
620 typedef uint8_t _cyhal_hwmgr_offset_t;
621 #endif
622
623 #if defined(COMPONENT_CAT1A)
624
625 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
626 #error "Too many clocks to use uint8_t as offset type"
627 #endif
628 /* The order of items here must match the order in cyhal_clock_impl.h
629 *
630 * Each entry in the array below is the prior entry plus the number of clocks that exist
631 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
632 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
633 * the subsequent value is increased by the define that specifies how many clocks are
634 * actually present. */
635 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[26] =
636 {
637 0, // 8-bit dividers
638 PERI_DIV_8_NR, // 16-bit dividers
639 PERI_DIV_8_NR + PERI_DIV_16_NR, // 16.5 bit dividers
640 PERI_DIV_8_NR + PERI_DIV_16_NR + PERI_DIV_16_5_NR, // 24.5 bit dividers
641
642 PERI_DIV_NR, // IMO
643 PERI_DIV_NR + 1, // ECO
644 PERI_DIV_NR + 2, // EXT
645 PERI_DIV_NR + 3, // ALTHF
646 PERI_DIV_NR + 4, // ALTLF
647 PERI_DIV_NR + 5, // ILO
648 PERI_DIV_NR + 6, // PILO
649 PERI_DIV_NR + 7, // WCO
650 PERI_DIV_NR + 8, // MFO
651
652 PERI_DIV_NR + 9, // PathMux
653
654 PERI_DIV_NR + SRSS_NUM_CLKPATH + 9, // FLL
655 PERI_DIV_NR + SRSS_NUM_CLKPATH + 10, // PLL
656
657 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + 10, // LF
658 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + 11, // MF
659 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + 12, // HF
660
661 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 12, // PUMP
662 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 13, // BAK
663 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 14, // TIMER
664 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 15, // AltSysTick
665
666 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 16, // Fast
667 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 17, // Peri
668 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18, // Slow
669 };
670
671 #elif defined(COMPONENT_CAT1B)
672
673 #define CY_MXSPERI_PCLK_DIV_CNT(gr) ( \
674 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT) + \
675 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT) + \
676 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT) + \
677 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_24_5_VECT))
678
679 #define CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(gr) \
680 (PERI_DIV_OFFSET##gr), \
681 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT), \
682 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT), \
683 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT)
684
685 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
686 #define PERI_DIV_OFFSET0 (0)
687 #endif
688 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
689 #define PERI_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(0))
690 #endif
691 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 2
692 #define PERI_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1))
693 #endif
694 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 3
695 #define PERI_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2))
696 #endif
697 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 4
698 #define PERI_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3))
699 #endif
700 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 5
701 #define PERI_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4))
702 #endif
703 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 6
704 #define PERI_DIV_OFFSET6 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5))
705 #endif
706 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 7
707 #define PERI_DIV_OFFSET7 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6))
708 #endif
709 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 8
710 #define PERI_DIV_OFFSET8 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7))
711 #endif
712 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 9
713 #define PERI_DIV_OFFSET9 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8))
714 #endif
715 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 10
716 #define PERI_DIV_OFFSET10 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9))
717 #endif
718 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 11
719 #define PERI_DIV_OFFSET11 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10))
720 #endif
721 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 12
722 #define PERI_DIV_OFFSET12 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11))
723 #endif
724 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 13
725 #define PERI_DIV_OFFSET13 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12))
726 #endif
727 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 14
728 #define PERI_DIV_OFFSET14 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13))
729 #endif
730 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 15
731 #define PERI_DIV_OFFSET15 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13) + CY_MXSPERI_PCLK_DIV_CNT(14))
732 #endif
733
734
735 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
736 #error "Too many clocks to use uint8_t as offset type"
737 #endif
738
739 /* The order of items here must match the order in cyhal_clock_impl.h
740 *
741 * Each entry in the array below is the prior entry plus the number of clocks that exist
742 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
743 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
744 * the subsequent value is increased by the define that specifies how many clocks are
745 * actually present. */
746 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[PERI_PERI_PCLK_PCLK_GROUP_NR * 4 + 22] =
747 {
748 // Peripheral dividers (8-bit, 16-bit, 16.5-bit & 24.5 bit) for each group
749 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
750 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0),
751 #endif
752 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
753 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1),
754 #endif
755 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 2)
756 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(2),
757 #endif
758 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 3)
759 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(3),
760 #endif
761 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 4)
762 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(4),
763 #endif
764 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 5)
765 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(5),
766 #endif
767 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 6)
768 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(6),
769 #endif
770 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 7)
771 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(7),
772 #endif
773 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 8)
774 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(8),
775 #endif
776 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 9)
777 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(9),
778 #endif
779 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 10)
780 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(10),
781 #endif
782 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 11)
783 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(11),
784 #endif
785 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 12)
786 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(12),
787 #endif
788 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 13)
789 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(13),
790 #endif
791 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 14)
792 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(14),
793 #endif
794 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 15)
795 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(15),
796 #endif
797
798 PERI_DIV_NR, // IHO
799 PERI_DIV_NR + 1, // IMO
800 PERI_DIV_NR + 2, // ECO
801 PERI_DIV_NR + 3, // EXT
802 PERI_DIV_NR + 4, // ALTHF
803 PERI_DIV_NR + 5, // ALTLF
804 PERI_DIV_NR + 6, // ILO
805 PERI_DIV_NR + 7, // PILO
806 PERI_DIV_NR + 8, // WCO
807 PERI_DIV_NR + 9, // MFO
808
809 PERI_DIV_NR + 10, // PathMux
810
811 PERI_DIV_NR + SRSS_NUM_CLKPATH + 10, // FLL
812 PERI_DIV_NR + SRSS_NUM_CLKPATH + 11, // PLL200
813 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + 11, // PLL400
814 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 11, // ECO_PreScaler
815
816 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 12, // LF
817 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 13, // MF
818 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 14, // HF
819
820 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 14, // PUMP
821 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 15, // BAK
822 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 16, // AltSysTick
823 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 17, // Peri
824 };
825
826 #elif defined(COMPONENT_CAT1C)
827
828 #define CY_MXSPERI_PCLK_DIV_CNT(gr) ( \
829 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT) + \
830 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT) + \
831 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT) + \
832 (PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_24_5_VECT))
833
834 #define CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(gr) \
835 (PERI_DIV_OFFSET##gr), \
836 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT), \
837 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT), \
838 (PERI_DIV_OFFSET##gr + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT + PERI_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT)
839
840 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
841 #define PERI_DIV_OFFSET0 (0)
842 #endif
843 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
844 #define PERI_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(0))
845 #endif
846 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 2
847 #define PERI_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1))
848 #endif
849 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 3
850 #define PERI_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2))
851 #endif
852 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 4
853 #define PERI_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3))
854 #endif
855 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 5
856 #define PERI_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4))
857 #endif
858 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 6
859 #define PERI_DIV_OFFSET6 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5))
860 #endif
861 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 7
862 #define PERI_DIV_OFFSET7 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6))
863 #endif
864 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 8
865 #define PERI_DIV_OFFSET8 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7))
866 #endif
867 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 9
868 #define PERI_DIV_OFFSET9 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8))
869 #endif
870 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 10
871 #define PERI_DIV_OFFSET10 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9))
872 #endif
873 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 11
874 #define PERI_DIV_OFFSET11 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10))
875 #endif
876 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 12
877 #define PERI_DIV_OFFSET12 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11))
878 #endif
879 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 13
880 #define PERI_DIV_OFFSET13 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12))
881 #endif
882 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 14
883 #define PERI_DIV_OFFSET14 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13))
884 #endif
885 #if (PERI_PERI_PCLK_PCLK_GROUP_NR) > 15
886 #define PERI_DIV_OFFSET15 (CY_MXSPERI_PCLK_DIV_CNT(0) + CY_MXSPERI_PCLK_DIV_CNT(1) + CY_MXSPERI_PCLK_DIV_CNT(2) + CY_MXSPERI_PCLK_DIV_CNT(3) + CY_MXSPERI_PCLK_DIV_CNT(4) + CY_MXSPERI_PCLK_DIV_CNT(5) + CY_MXSPERI_PCLK_DIV_CNT(6) + CY_MXSPERI_PCLK_DIV_CNT(7) + CY_MXSPERI_PCLK_DIV_CNT(8) + CY_MXSPERI_PCLK_DIV_CNT(9) + CY_MXSPERI_PCLK_DIV_CNT(10) + CY_MXSPERI_PCLK_DIV_CNT(11) + CY_MXSPERI_PCLK_DIV_CNT(12) + CY_MXSPERI_PCLK_DIV_CNT(13) + CY_MXSPERI_PCLK_DIV_CNT(14))
887 #endif
888
889
890 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
891 #error "Too many clocks to use uint8_t as offset type"
892 #endif
893
894 /* The order of items here must match the order in cyhal_clock_impl.h
895 *
896 * Each entry in the array below is the prior entry plus the number of clocks that exist
897 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
898 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
899 * the subsequent value is increased by the define that specifies how many clocks are
900 * actually present. */
901 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[PERI_PERI_PCLK_PCLK_GROUP_NR * 4 + 22] =
902 {
903 // Peripheral dividers (8-bit, 16-bit, 16.5-bit & 24.5 bit) for each group
904 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 0)
905 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0),
906 #endif
907 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 1)
908 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1),
909 #endif
910 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 2)
911 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(2),
912 #endif
913 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 3)
914 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(3),
915 #endif
916 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 4)
917 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(4),
918 #endif
919 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 5)
920 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(5),
921 #endif
922 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 6)
923 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(6),
924 #endif
925 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 7)
926 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(7),
927 #endif
928 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 8)
929 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(8),
930 #endif
931 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 9)
932 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(9),
933 #endif
934 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 10)
935 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(10),
936 #endif
937 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 11)
938 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(11),
939 #endif
940 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 12)
941 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(12),
942 #endif
943 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 13)
944 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(13),
945 #endif
946 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 14)
947 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(14),
948 #endif
949 #if (PERI_PERI_PCLK_PCLK_GROUP_NR > 15)
950 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(15),
951 #endif
952
953 PERI_DIV_NR, // IMO
954 PERI_DIV_NR + 1, // ECO
955 PERI_DIV_NR + 2, // EXT
956 PERI_DIV_NR + 3, // ILO
957 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + 3, // WCO
958 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + 4, // PathMux
959 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + 4, // FLL
960 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + 5, // PLL200
961 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + 5, // PLL400
962
963 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + 5, // LF
964 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + 6, // HF
965
966 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 6, // BAK
967 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 7, // AltSysTick
968 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 8, // Peri
969 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 9, // Fast
970 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + _CYHAL_SRSS_NUM_FAST + 9, // Slow
971 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + _CYHAL_SRSS_NUM_FAST + 10, // MEM
972 PERI_DIV_NR + _CYHAL_SRSS_NUM_ILO + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + _CYHAL_SRSS_NUM_FAST + 11, // Timer
973 };
974
975 #elif defined(COMPONENT_CAT1D)
976
977 #define CY_MXSPERI_PCLK_DIV_CNT(instance, gr) ( \
978 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT) + \
979 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT) + \
980 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT) + \
981 (PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_24_5_VECT))
982
983 #define CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(instance, gr) \
984 (PERI##instance##_DIV_OFFSET##gr), \
985 (PERI##instance##_DIV_OFFSET##gr + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT), \
986 (PERI##instance##_DIV_OFFSET##gr + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT), \
987 (PERI##instance##_DIV_OFFSET##gr + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_8_VECT + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_VECT + PERI##instance##_PERI_PCLK_PCLK_GROUP_NR##gr##_GR_DIV_16_5_VECT)
988
989 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 0)
990 #define PERI0_DIV_OFFSET0 (0)
991 #endif
992 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 1)
993 #define PERI0_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(0, 0))
994 #endif
995 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 2
996 #define PERI0_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1))
997 #endif
998 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 3
999 #define PERI0_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2))
1000 #endif
1001 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 4
1002 #define PERI0_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3))
1003 #endif
1004 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 5
1005 #define PERI0_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4))
1006 #endif
1007 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 6
1008 #define PERI0_DIV_OFFSET6 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5))
1009 #endif
1010 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 7
1011 #define PERI0_DIV_OFFSET7 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6))
1012 #endif
1013 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 8
1014 #define PERI0_DIV_OFFSET8 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7))
1015 #endif
1016 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR) > 9
1017 #define PERI0_DIV_OFFSET9 (CY_MXSPERI_PCLK_DIV_CNT(0, 0) + CY_MXSPERI_PCLK_DIV_CNT(0, 1) + CY_MXSPERI_PCLK_DIV_CNT(0, 2) + CY_MXSPERI_PCLK_DIV_CNT(0, 3) + CY_MXSPERI_PCLK_DIV_CNT(0, 4) + CY_MXSPERI_PCLK_DIV_CNT(0, 5) + CY_MXSPERI_PCLK_DIV_CNT(0, 6) + CY_MXSPERI_PCLK_DIV_CNT(0, 7) + CY_MXSPERI_PCLK_DIV_CNT(0, 8))
1018 #endif
1019
1020 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 0)
1021 #define PERI1_DIV_OFFSET0 (0)
1022 #endif
1023 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 1)
1024 #define PERI1_DIV_OFFSET1 (CY_MXSPERI_PCLK_DIV_CNT(1, 0))
1025 #endif
1026 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 2
1027 #define PERI1_DIV_OFFSET2 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1))
1028 #endif
1029 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 3
1030 #define PERI1_DIV_OFFSET3 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2))
1031 #endif
1032 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 4
1033 #define PERI1_DIV_OFFSET4 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3))
1034 #endif
1035 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR) > 5
1036 #define PERI1_DIV_OFFSET5 (CY_MXSPERI_PCLK_DIV_CNT(1, 0) + CY_MXSPERI_PCLK_DIV_CNT(1, 1) + CY_MXSPERI_PCLK_DIV_CNT(1, 2) + CY_MXSPERI_PCLK_DIV_CNT(1, 3) + CY_MXSPERI_PCLK_DIV_CNT(1, 4))
1037 #endif
1038 #if defined(PERI2_PERI_PCLK_PCLK_GROUP_NR)
1039 #warning "PERI2 dividers instance is not handled"
1040 #endif /* defined(PERI2_PERI_PCLK_PCLK_GROUP_NR) */
1041
1042 #if ((PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL + SRSS_NUM_HFROOT + 18) >= 256)
1043 #error "Too many clocks to use uint8_t as offset type"
1044 #endif
1045
1046 #if !defined(PERI0_PERI_PCLK_PCLK_GROUP_NR) || !defined(PERI1_PERI_PCLK_PCLK_GROUP_NR)
1047 #error "Unexpected number of PERI blocks"
1048 #endif /* !defined(PERI0_PERI_PCLK_PCLK_GROUP_NR) || !defined(PERI1_PERI_PCLK_PCLK_GROUP_NR) */
1049
1050 /* The order of items here must match the order in cyhal_clock_impl.h
1051 *
1052 * Each entry in the array below is the prior entry plus the number of clocks that exist
1053 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
1054 * one higher than the previous value. When there are multiple clocks (e.g.: PathMux/PLL)
1055 * the subsequent value is increased by the define that specifies how many clocks are
1056 * actually present. */
1057 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[(PERI0_PERI_PCLK_PCLK_GROUP_NR + PERI1_PERI_PCLK_PCLK_GROUP_NR) * 4 + 14] =
1058 {
1059 // Peripheral dividers (8-bit, 16-bit, 16.5-bit & 24.5 bit) for each group
1060 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 0)
1061 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 0),
1062 #endif
1063 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 1)
1064 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 1),
1065 #endif
1066 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 2)
1067 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 2),
1068 #endif
1069 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 3)
1070 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 3),
1071 #endif
1072 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 4)
1073 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 4),
1074 #endif
1075 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 5)
1076 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 5),
1077 #endif
1078 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 6)
1079 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 6),
1080 #endif
1081 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 7)
1082 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 7),
1083 #endif
1084 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 8)
1085 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 8),
1086 #endif
1087 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 9)
1088 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(0, 9),
1089 #endif
1090 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR > 10)
1091 #warning "Unhandled number of PERI0 PCLK"
1092 #endif
1093
1094 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 0)
1095 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 0),
1096 #endif
1097 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 1)
1098 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 1),
1099 #endif
1100 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 2)
1101 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 2),
1102 #endif
1103 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 3)
1104 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 3),
1105 #endif
1106 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 4)
1107 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 4),
1108 #endif
1109 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 5)
1110 CY_MXSPERI_PCLK_DIV_CNT_OFFSETS(1, 5),
1111 #endif
1112 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR > 6)
1113 #warning "Unhandled number of PERI1 PCLK"
1114 #endif
1115
1116 PERI_DIV_NR, // IHO
1117 PERI_DIV_NR + 1, // ECO
1118 PERI_DIV_NR + 2, // EXT
1119 PERI_DIV_NR + 3, // PILO
1120 PERI_DIV_NR + 4, // WCO
1121
1122 PERI_DIV_NR + 5, // PathMux
1123
1124 PERI_DIV_NR + SRSS_NUM_CLKPATH + 5, // DPLL_LP
1125 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + 5, // DPLL_HP
1126 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 5, // ECO_PreScaler
1127
1128 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 6, // LF
1129 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 7, // MF
1130 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + 8, // HF
1131
1132 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + SRSS_NUM_HFROOT + 8, // BAK
1133 PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_DPLL_LP + SRSS_NUM_DPLL_HP + SRSS_NUM_HFROOT + 9 // Peri
1134
1135 };
1136
1137 #elif defined(COMPONENT_CAT2)
1138 /* The order of items here must match the order in cyhal_clock_impl.h
1139 *
1140 * Each entry in the array below is the prior entry plus the number of clocks that exist
1141 * of the prior type. When there is only 1 clock (e.g: IMO/ECO) the next number is simply
1142 * one higher than the previous value. When there are multiple clocks (e.g.: PCLK)
1143 * the subsequent value is increased by the define that specifies how many clocks are
1144 * actually present. */
1145 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_clock[16] =
1146 {
1147 0, // 8-bit dividers
1148 PERI_PCLK_DIV_8_NR, // 16-bit dividers
1149 PERI_PCLK_DIV_8_NR + PERI_PCLK_DIV_16_NR, // 16.5 bit dividers
1150 PERI_PCLK_DIV_8_NR + PERI_PCLK_DIV_16_NR + PERI_PCLK_DIV_16_5_NR, // 24.5 bit dividers
1151
1152 PERI_PCLK_CLOCK_NR, // IMO
1153 PERI_PCLK_CLOCK_NR + 1, // ECO
1154 PERI_PCLK_CLOCK_NR + 2, // EXT
1155 PERI_PCLK_CLOCK_NR + 3, // ILO
1156 PERI_PCLK_CLOCK_NR + 4, // WCO
1157
1158 PERI_PCLK_CLOCK_NR + 5, // WDCSEL
1159 PERI_PCLK_CLOCK_NR + 6, // PLLSEL
1160 PERI_PCLK_CLOCK_NR + 7, // PLL
1161 PERI_PCLK_CLOCK_NR + 8, // LF
1162 PERI_PCLK_CLOCK_NR + 9, // HF
1163 PERI_PCLK_CLOCK_NR + 10, // PUMP
1164 PERI_PCLK_CLOCK_NR + 11, // SYS
1165 };
1166 #endif
1167
1168 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_dma[] =
1169 {
1170 0,
1171 #if defined(CY_IP_MXAHBDMAC_INSTANCES)
1172 #if (CY_IP_MXAHBDMAC_INSTANCES > 1)
1173 MXAHBDMAC0_CH_NR,
1174 #endif
1175 #if (CY_IP_MXAHBDMAC_INSTANCES > 2)
1176 MXAHBDMAC0_CH_NR + MXAHBDMAC1_CH_NR,
1177 #endif
1178 #if (CY_IP_MXAHBDMAC_INSTANCES > 3)
1179 #warning Unhandled DMA instance count
1180 #endif
1181 #endif /* defined(CY_IP_MXAHBDMAC_INSTANCES) */
1182 };
1183
1184 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1185 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_dw[] =
1186 {
1187 0,
1188 CPUSS_DW0_CH_NR,
1189 };
1190
1191 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_tdm[] =
1192 {
1193 0,
1194 #if defined(CY_IP_MXTDM_INSTANCES)
1195 #if (CY_IP_MXTDM_INSTANCES > 1)
1196 TDM_NR,
1197 #endif
1198 #endif
1199 };
1200 #endif
1201
1202 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_gpio[] =
1203 {
1204 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
1205 #if defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1206 /* Most devices don't have more than 16 ports, so save the flash in most cases */
1207 128, 136, 144, 152, 160, 168, 176, 184, 192, 200, 208, 216, 224,
1208 232, 240, 248, 256, 264, 272, 280
1209 #endif
1210 };
1211
1212 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_can[] =
1213 {
1214 #ifdef CY_IP_MXTTCANFD_INSTANCES
1215 #if (CY_IP_MXTTCANFD_INSTANCES > 0)
1216 0,
1217 #endif
1218 #if (CY_IP_MXTTCANFD_INSTANCES > 1)
1219 CANFD0_CAN_NR,
1220 #endif
1221 #if (CY_IP_MXTTCANFD_INSTANCES > 2)
1222 CANFD0_CAN_NR + CANFD1_CAN_NR,
1223 #endif
1224 #if (CY_IP_MXTTCANFD_INSTANCES > 3)
1225 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR,
1226 #endif
1227 #if (CY_IP_MXTTCANFD_INSTANCES > 4)
1228 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR,
1229 #endif
1230 #if (CY_IP_MXTTCANFD_INSTANCES > 5)
1231 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR,
1232 #endif
1233 #if (CY_IP_MXTTCANFD_INSTANCES > 6)
1234 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR,
1235 #endif
1236 #if (CY_IP_MXTTCANFD_INSTANCES > 7)
1237 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR,
1238 #endif
1239 #if (CY_IP_MXTTCANFD_INSTANCES > 8)
1240 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR,
1241 #endif
1242 #if (CY_IP_MXTTCANFD_INSTANCES > 9)
1243 CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR,
1244 #endif
1245 #if (CY_IP_MXTTCANFD_INSTANCES > 10)
1246 #warning Unhandled CAN instance count
1247 #endif
1248 #else
1249 0
1250 #endif
1251 };
1252
1253 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_lpcomp[] =
1254 {
1255 0,
1256 #if (CY_BLOCK_COUNT_LPCOMP > 1)
1257 #error "Unhandled LPComp count"
1258 #endif
1259 };
1260
1261 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_opamp[] =
1262 {
1263 0,
1264 #if (CY_BLOCK_COUNT_OPAMP > 1)
1265 2,
1266 #elif (CY_BLOCK_COUNT_OPAMP > 2)
1267 #error "Unhandled Opamp count"
1268 #endif
1269 };
1270
1271 static const _cyhal_hwmgr_offset_t cyhal_block_offsets_tcpwm[] =
1272 {
1273 0,
1274 #ifdef CY_IP_MXTCPWM_INSTANCES
1275 #if CY_IP_MXTCPWM_VERSION == 1
1276 #if (CY_IP_MXTCPWM_INSTANCES > 1)
1277 TCPWM0_CNT_NR,
1278 #endif
1279 #if (CY_IP_MXTCPWM_INSTANCES > 2)
1280 TCPWM0_CNT_NR + TCPWM1_CNT_NR,
1281 #endif
1282 #if (CY_IP_MXTCPWM_INSTANCES > 3)
1283 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR,
1284 #endif
1285 #if (CY_IP_MXTCPWM_INSTANCES > 4)
1286 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR,
1287 #endif
1288 #if (CY_IP_MXTCPWM_INSTANCES > 5)
1289 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR,
1290 #endif
1291 #if (CY_IP_MXTCPWM_INSTANCES > 6)
1292 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR,
1293 #endif
1294 #if (CY_IP_MXTCPWM_INSTANCES > 7)
1295 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR,
1296 #endif
1297 #if (CY_IP_MXTCPWM_INSTANCES > 8)
1298 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR,
1299 #endif
1300 #if (CY_IP_MXTCPWM_INSTANCES > 9)
1301 TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR,
1302 #endif
1303 #if (CY_IP_MXTCPWM_INSTANCES > 10)
1304 #warning Unhandled TCPWM instance count
1305 #endif
1306 #else // CY_IP_MXTCPWM_VERSION >= 2
1307 #if (CY_IP_MXTCPWM_INSTANCES == 1)
1308 #if (TCPWM_GRP_NR > 1)
1309 TCPWM_GRP_NR0_GRP_GRP_CNT_NR,
1310 #endif
1311 #if (TCPWM_GRP_NR > 2)
1312 TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR,
1313 #endif
1314 #if (TCPWM_GRP_NR > 3)
1315 TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR + TCPWM_GRP_NR2_GRP_GRP_CNT_NR,
1316 #endif
1317 #elif (CY_IP_MXTCPWM_INSTANCES == 2)
1318 // The 'else's are placeholders to ensure the groups line up, even if groups are empty or absent
1319 #if (TCPWM0_GRP_NR > 1)
1320 TCPWM0_GRP_NR0_GRP_GRP_CNT_NR,
1321 #else
1322 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1323 #endif
1324 #if (TCPWM0_GRP_NR > 2)
1325 TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR,
1326 #else
1327 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1328 #endif
1329 #if (TCPWM0_GRP_NR > 3)
1330 TCPWM0_GRP_NR0_GRP_GRP_CNT_NR + TCPWM0_GRP_NR1_GRP_GRP_CNT_NR + TCPWM0_GRP_NR2_GRP_GRP_CNT_NR,
1331 #else
1332 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1333 #endif
1334
1335 #if (TCPWM1_GRP_NR > 0)
1336 _CYHAL_TCPWM0_TOTAL_CNT_NR,
1337 #else
1338 _CYHAL_TCPWM0_TOTAL_CNT_NR + _CYHAL_TCPWM1_TOTAL_CNT_NR,
1339 #endif
1340 #if (TCPWM1_GRP_NR > 1)
1341 _CYHAL_TCPWM0_TOTAL_CNT_NR + TCPWM1_GRP_NR0_GRP_GRP_CNT_NR,
1342 #else
1343 _CYHAL_TCPWM0_TOTAL_CNT_NR +_CYHAL_TCPWM1_TOTAL_CNT_NR,
1344 #endif
1345 #if (TCPWM1_GRP_NR > 2)
1346 _CYHAL_TCPWM0_TOTAL_CNT_NR + TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR,
1347 #else
1348 _CYHAL_TCPWM0_TOTAL_CNT_NR +_CYHAL_TCPWM1_TOTAL_CNT_NR,
1349 #endif
1350 #if (TCPWM1_GRP_NR > 3)
1351 _CYHAL_TCPWM0_TOTAL_CNT_NR + TCPWM1_GRP_NR0_GRP_GRP_CNT_NR + TCPWM1_GRP_NR1_GRP_GRP_CNT_NR + TCPWM1_GRP_NR2_GRP_GRP_CNT_NR,
1352 #else
1353 _CYHAL_TCPWM0_TOTAL_CNT_NR +_CYHAL_TCPWM1_TOTAL_CNT_NR,
1354 #endif
1355 #else
1356 #warning Unhandled TCPWM instance count
1357 #endif
1358 #endif
1359 #endif
1360 };
1361
1362 static uint8_t cyhal_used[(CY_TOTAL_ALLOCATABLE_ITEMS + 7) / 8] = {0};
1363
1364 // Note: the ordering here needs to be parallel to that of cyhal_resource_t
1365 static const uint16_t cyhal_resource_offsets[] =
1366 {
1367 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1368 CY_OFFSET_ADC,
1369 CY_OFFSET_ADCMIC,
1370 CY_OFFSET_BLE,
1371 CY_OFFSET_CAN,
1372 CY_OFFSET_CLOCK, /* Placeholder for ClockPath which is deprecated */
1373 CY_OFFSET_CLOCK,
1374 CY_OFFSET_CRYPTO,
1375 CY_OFFSET_DAC,
1376 CY_OFFSET_DMA,
1377 CY_OFFSET_DW,
1378 CY_OFFSET_ETH,
1379 CY_OFFSET_GPIO,
1380 CY_OFFSET_I2S,
1381 CY_OFFSET_I3C,
1382 CY_OFFSET_KEYSCAN,
1383 CY_OFFSET_LCD,
1384 CY_OFFSET_LIN,
1385 CY_OFFSET_LPCOMP,
1386 CY_OFFSET_LPTIMER,
1387 CY_OFFSET_OPAMP,
1388 CY_OFFSET_PDMPCM,
1389 CY_OFFSET_QSPI,
1390 CY_OFFSET_RTC,
1391 CY_OFFSET_SCB,
1392 CY_OFFSET_SDHC,
1393 CY_OFFSET_SDIODEV,
1394 CY_OFFSET_TCPWM,
1395 CY_OFFSET_TDM,
1396 CY_OFFSET_UDB,
1397 CY_OFFSET_USB,
1398 #elif defined(COMPONENT_CAT2)
1399 CY_OFFSET_ADC,
1400 CY_OFFSET_CAN,
1401 CY_OFFSET_CLOCK,
1402 CY_OFFSET_CRYPTO,
1403 CY_OFFSET_DMA,
1404 CY_OFFSET_GPIO,
1405 CY_OFFSET_I2S,
1406 CY_OFFSET_LCD,
1407 CY_OFFSET_LPCOMP,
1408 CY_OFFSET_LPTIMER,
1409 CY_OFFSET_OPAMP,
1410 CY_OFFSET_SCB,
1411 CY_OFFSET_TCPWM,
1412 CY_OFFSET_USB,
1413 CY_OFFSET_USBPD,
1414 #endif
1415 };
1416
1417 #define _CYHAL_RESOURCES (sizeof(cyhal_resource_offsets)/sizeof(cyhal_resource_offsets[0]))
1418
1419 static const uint32_t cyhal_has_channels =
1420 (1 << CYHAL_RSC_CAN) |
1421 (1 << CYHAL_RSC_CLOCK) |
1422 (1 << CYHAL_RSC_DMA) |
1423 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1424 (1 << CYHAL_RSC_DW) |
1425 (1 << CYHAL_RSC_TDM) |
1426 #endif
1427 (1 << CYHAL_RSC_GPIO) |
1428 (1 << CYHAL_RSC_LPCOMP)|
1429 (1 << CYHAL_RSC_OPAMP) |
1430 (1 << CYHAL_RSC_TCPWM) ;
1431
1432 /*******************************************************************************
1433 * Utility helper functions
1434 *******************************************************************************/
1435
_cyhal_uses_channels(cyhal_resource_t type)1436 static inline uint16_t _cyhal_uses_channels(cyhal_resource_t type)
1437 {
1438 return (cyhal_has_channels & (1 << type)) > 0;
1439 }
1440
_cyhal_get_resource_offset(cyhal_resource_t type)1441 static inline uint16_t _cyhal_get_resource_offset(cyhal_resource_t type)
1442 {
1443 return cyhal_resource_offsets[type];
1444 }
1445
_cyhal_get_block_offsets(cyhal_resource_t type)1446 static inline const _cyhal_hwmgr_offset_t* _cyhal_get_block_offsets(cyhal_resource_t type)
1447 {
1448 switch (type)
1449 {
1450 case CYHAL_RSC_CAN:
1451 return cyhal_block_offsets_can;
1452 case CYHAL_RSC_CLOCK:
1453 return cyhal_block_offsets_clock;
1454 case CYHAL_RSC_DMA:
1455 return cyhal_block_offsets_dma;
1456 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1457 case CYHAL_RSC_DW:
1458 return cyhal_block_offsets_dw;
1459 case CYHAL_RSC_TDM:
1460 return cyhal_block_offsets_tdm;
1461 #endif
1462 case CYHAL_RSC_GPIO:
1463 return cyhal_block_offsets_gpio;
1464 case CYHAL_RSC_LPCOMP:
1465 return cyhal_block_offsets_lpcomp;
1466 case CYHAL_RSC_OPAMP:
1467 return cyhal_block_offsets_opamp;
1468 case CYHAL_RSC_TCPWM:
1469 return cyhal_block_offsets_tcpwm;
1470 default:
1471 CY_ASSERT(false);
1472 return NULL;
1473 }
1474 }
1475
1476 // Gets the number of block offset entries, only valid for blocks which have channels.
_cyhal_get_block_offset_length(cyhal_resource_t type)1477 static inline uint8_t _cyhal_get_block_offset_length(cyhal_resource_t type)
1478 {
1479 switch (type)
1480 {
1481 case CYHAL_RSC_CAN:
1482 return sizeof(cyhal_block_offsets_can)/sizeof(cyhal_block_offsets_can[0]);
1483 case CYHAL_RSC_CLOCK:
1484 return sizeof(cyhal_block_offsets_clock)/sizeof(cyhal_block_offsets_clock[0]);
1485 case CYHAL_RSC_DMA:
1486 return sizeof(cyhal_block_offsets_dma)/sizeof(cyhal_block_offsets_dma[0]);
1487 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
1488 case CYHAL_RSC_DW:
1489 return sizeof(cyhal_block_offsets_dw)/sizeof(cyhal_block_offsets_dw[0]);
1490 case CYHAL_RSC_TDM:
1491 return sizeof(cyhal_block_offsets_tdm)/sizeof(cyhal_block_offsets_tdm[0]);
1492 #endif
1493 case CYHAL_RSC_GPIO:
1494 return sizeof(cyhal_block_offsets_gpio)/sizeof(cyhal_block_offsets_gpio[0]);
1495 case CYHAL_RSC_LPCOMP:
1496 return sizeof(cyhal_block_offsets_lpcomp)/sizeof(cyhal_block_offsets_lpcomp[0]);
1497 case CYHAL_RSC_OPAMP:
1498 return sizeof(cyhal_block_offsets_opamp)/sizeof(cyhal_block_offsets_opamp[0]);
1499 case CYHAL_RSC_TCPWM:
1500 return sizeof(cyhal_block_offsets_tcpwm)/sizeof(cyhal_block_offsets_tcpwm[0]);
1501 default:
1502 CY_ASSERT(false);
1503 return 0;
1504 }
1505 }
1506
