1 /***************************************************************************//** 2 * \file cyhal_hw_resources.h 3 * 4 * \brief 5 * Provides struct definitions for configuration resources in the PDL. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 /** 28 * \addtogroup group_hal_impl_availability HAL Driver Availability Macros 29 * \ingroup group_hal_impl 30 * \{ 31 */ 32 33 #pragma once 34 35 #include "cy_pdl.h" 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 // Documented in cyhal.h 42 #define CYHAL_API_VERSION (2) 43 44 /** \cond INTERNAL */ 45 #define _CYHAL_DRIVER_AVAILABLE_SCB (((CY_IP_MXSCB_INSTANCES) > 0) || ((CY_IP_MXS22SCB_INSTANCES) > 0)) 46 #define _CYHAL_DRIVER_AVAILABLE_TCPWM ((CY_IP_MXTCPWM_INSTANCES) > 0) 47 #define _CYHAL_DRIVER_AVAILABLE_IRQ (1) 48 49 #if defined(CY_IP_MXUDB_INSTANCES) && defined(CYHAL_UDB_SDIO) 50 #define _CYHAL_DRIVER_AVAILABLE_SDIO_UDB (1) 51 #else 52 #define _CYHAL_DRIVER_AVAILABLE_SDIO_UDB (0) 53 #endif 54 #define _CYHAL_DRIVER_AVAILABLE_DMA_DMAC (((CY_IP_M4CPUSS_DMAC_INSTANCES) > 0) || ((CY_IP_M7CPUSS_DMAC_INSTANCES) > 0) || ((CY_IP_MXAHBDMAC_INSTANCES) > 0) || ((CY_IP_MXSAXIDMAC_INSTANCES) > 0)) 55 #define _CYHAL_DRIVER_AVAILABLE_DMA_DW (((CY_IP_M4CPUSS_DMA_INSTANCES) > 0) || ((CY_IP_M7CPUSS_DMA_INSTANCES) > 0) || ((CY_IP_MXDW_INSTANCES) > 0)) 56 57 #define _CYHAL_DRIVER_AVAILABLE_NVM_FLASH (((FLASHC_BASE) > 0) || ((CPUSS_FLASHC_PRESENT) > 0)) 58 #define _CYHAL_DRIVER_AVAILABLE_NVM_OTP ((CY_IP_MXS22RRAMC_INSTANCES) > 0) 59 #define _CYHAL_DRIVER_AVAILABLE_NVM_RRAM ((CY_IP_MXS22RRAMC_INSTANCES) > 0) 60 61 #if !defined(COMPONENT_CAT1D) 62 63 #define _CYHAL_DRIVER_AVAILABLE_ADC_SAR ((CY_IP_MXS40PASS_SAR_INSTANCES) > 0) || ((CY_IP_MXS40EPASS_ESAR_INSTANCES) > 0) 64 #define _CYHAL_DRIVER_AVAILABLE_ADC_MIC ((CY_IP_MXS40ADCMIC_INSTANCES) > 0) 65 #define _CYHAL_DRIVER_AVAILABLE_COMP_LP ((CY_IP_MXLPCOMP_INSTANCES) > 0) 66 #define _CYHAL_DRIVER_AVAILABLE_COMP_CTB (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTB_INSTANCES) > 0)) 67 68 #define _CYHAL_DRIVER_AVAILABLE_PASS ((CY_IP_MXS40PASS_INSTANCES) > 0) || ((CY_IP_MXS40EPASS_INSTANCES) > 0) 69 /* MXCRYPTOLITE is not yet supported */ 70 //#define _CYHAL_DRIVER_AVAILABLE_CRYPTO (((CY_IP_MXCRYPTO_INSTANCES) > 0) || ((CY_IP_MXCRYPTOLITE_INSTANCES) > 0)) 71 #define _CYHAL_DRIVER_AVAILABLE_CRYPTO ((CY_IP_MXCRYPTO_INSTANCES) > 0) 72 73 #else 74 75 #define _CYHAL_DRIVER_AVAILABLE_ADC_SAR (0) 76 #define _CYHAL_DRIVER_AVAILABLE_ADC_MIC (0) 77 #define _CYHAL_DRIVER_AVAILABLE_COMP_LP (0) 78 #define _CYHAL_DRIVER_AVAILABLE_COMP_CTB (0) 79 #define _CYHAL_DRIVER_AVAILABLE_PASS (0) 80 #define _CYHAL_DRIVER_AVAILABLE_CRYPTO (0) 81 82 #endif /* not COMPONENT_CAT1D or COMPONENT_CAT1D */ 83 84 #if defined(PERI_PERI_PCLK_PCLK_GROUP_NR) 85 #define _CYHAL_CLOCK_PERI_GROUPS PERI_PERI_PCLK_PCLK_GROUP_NR 86 #elif (defined(PERI0_PERI_PCLK_PCLK_GROUP_NR) && defined(PERI1_PERI_PCLK_PCLK_GROUP_NR)) 87 #define _CYHAL_CLOCK_PERI_GROUPS (PERI0_PERI_PCLK_PCLK_GROUP_NR + PERI1_PERI_PCLK_PCLK_GROUP_NR) 88 #else 89 #define _CYHAL_CLOCK_PERI_GROUPS 1 90 #endif 91 92 93 #if defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0) 94 /* CAT1C devices define _CYHAL_SRSS_NUM_PLL to be the macro that documents the number of 200MHz PLL's present */ 95 #define SRSS_NUM_PLL200M SRSS_NUM_PLL 96 #elif defined(COMPONENT_CAT1D) 97 /* CAT1D devices define SRSS_NUM_DPLL_LP/SRSS_NUM_DPLL_HP to be the macro that documents the number of 200/500MHz PLL's present */ 98 #define SRSS_NUM_DPLL250M SRSS_NUM_DPLL_LP 99 #define SRSS_NUM_DPLL500M SRSS_NUM_DPLL_HP 100 #endif 101 102 #if ((defined(COMPONENT_CAT1C) && (SRSS_HT_VARIANT)) || (defined(COMPONENT_CAT1A) && SRSS_HT_VARIANT)) 103 #define _CYHAL_SRSS_NUM_ILO 2U 104 #else 105 #define _CYHAL_SRSS_NUM_ILO 1U 106 #endif 107 108 #if defined(CPUSS_CM7_1_PRESENT) 109 #define _CYHAL_SRSS_NUM_FAST (1 + CPUSS_CM7_1_PRESENT) 110 #else 111 #define _CYHAL_SRSS_NUM_FAST (1) 112 #endif 113 114 /* Alignment for DMA descriptors */ 115 #if (CY_IP_MXSAXIDMAC) 116 /* AXI DMA controller has a 64-bit AXI master interface */ 117 #define _CYHAL_DMA_ALIGN CY_ALIGN(8) 118 #elif (CY_CPU_CORTEX_M7) && defined(ENABLE_CM7_DATA_CACHE) 119 #define _CYHAL_DMA_ALIGN CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 120 #else 121 #define _CYHAL_DMA_ALIGN 122 #endif 123 124 /** \endcond */ 125 126 // Documented in cyhal.h 127 #define CYHAL_DRIVER_AVAILABLE_HWMGR (1) 128 #define CYHAL_DRIVER_AVAILABLE_GPIO (1) 129 #define CYHAL_DRIVER_AVAILABLE_INTERCONNECT (1) 130 #define CYHAL_DRIVER_AVAILABLE_CLOCK (1) 131 #define CYHAL_DRIVER_AVAILABLE_SYSTEM (1) 132 133 #define CYHAL_DRIVER_AVAILABLE_EZI2C (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_I2C 134 #define CYHAL_DRIVER_AVAILABLE_I2C (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_I2C 135 #define CYHAL_DRIVER_AVAILABLE_SPI (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_SPI 136 #define CYHAL_DRIVER_AVAILABLE_UART (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_UART 137 #define CYHAL_DRIVER_AVAILABLE_WDT (1) 138 #define CYHAL_DRIVER_AVAILABLE_TIMER (_CYHAL_DRIVER_AVAILABLE_TCPWM) 139 #define CYHAL_DRIVER_AVAILABLE_PWM (_CYHAL_DRIVER_AVAILABLE_TCPWM) 140 #define CYHAL_DRIVER_AVAILABLE_QUADDEC (_CYHAL_DRIVER_AVAILABLE_TCPWM) 141 142 #define CYHAL_DRIVER_AVAILABLE_I2S ((((CY_IP_MXAUDIOSS_INSTANCES) > 0) && (AUDIOSS_I2S || AUDIOSS0_I2S || AUDIOSS0_I2S_I2S)) || ((CY_IP_MXTDM_INSTANCES) > 0)) //AUDIOSS[x]_I2S 143 #define CYHAL_DRIVER_AVAILABLE_I2S_TX (CYHAL_DRIVER_AVAILABLE_I2S) 144 #define CYHAL_DRIVER_AVAILABLE_I2S_RX (CYHAL_DRIVER_AVAILABLE_I2S) 145 #define CYHAL_DRIVER_AVAILABLE_TDM ((((CY_IP_MXAUDIOSS_INSTANCES) > 0) && (AUDIOSS_I2S || AUDIOSS0_I2S || AUDIOSS0_I2S_I2S)) || ((CY_IP_MXTDM_INSTANCES) > 0)) //AUDIOSS[x]_I2S 146 #define CYHAL_DRIVER_AVAILABLE_TDM_TX (CYHAL_DRIVER_AVAILABLE_TDM) 147 #define CYHAL_DRIVER_AVAILABLE_TDM_RX (CYHAL_DRIVER_AVAILABLE_TDM) 148 #define CYHAL_DRIVER_AVAILABLE_DMA ((_CYHAL_DRIVER_AVAILABLE_DMA_DMAC) || (_CYHAL_DRIVER_AVAILABLE_DMA_DW)) 149 #if !defined(COMPONENT_CAT1B) && !defined(COMPONENT_CAT1D) 150 #define CYHAL_DRIVER_AVAILABLE_IPC ((CPUSS_IPC_IPC_NR > 0) || (CY_IP_MXIPC_INSTANCES > 0)) 151 #else 152 #define CYHAL_DRIVER_AVAILABLE_IPC (0) 153 #endif /* !defined(COMPONENT_CAT1B) && !defined(COMPONENT_CAT1D) or other */ 154 #define CYHAL_DRIVER_AVAILABLE_QSPI ((CY_IP_MXSMIF_INSTANCES) > 0) 155 #if (defined(COMPONENT_CM0P) && defined(COMPONENT_CAT1D))//CAT 1D CM0P cannot have LPTimer instances because no interrupts are routed to this CPU 156 #define CYHAL_DRIVER_AVAILABLE_LPTIMER (0) 157 #else 158 #define CYHAL_DRIVER_AVAILABLE_LPTIMER ((SRSS_NUM_MCWDT) > 0) 159 #endif 160 #define CYHAL_DRIVER_AVAILABLE_SDHC ((CY_IP_MXSDHC_INSTANCES) > 0) 161 #define CYHAL_DRIVER_AVAILABLE_SDIO (((CY_IP_MXSDHC_INSTANCES) > 0) || (_CYHAL_DRIVER_AVAILABLE_SDIO_UDB)) 162 #define CYHAL_DRIVER_AVAILABLE_SDIO_HOST (CYHAL_DRIVER_AVAILABLE_SDIO) 163 #define CYHAL_DRIVER_AVAILABLE_SDIO_DEV (0) 164 #define CYHAL_DRIVER_AVAILABLE_NVM (_CYHAL_DRIVER_AVAILABLE_NVM_FLASH || _CYHAL_DRIVER_AVAILABLE_NVM_RRAM || _CYHAL_DRIVER_AVAILABLE_NVM_OTP) 165 #define CYHAL_DRIVER_AVAILABLE_FLASH (_CYHAL_DRIVER_AVAILABLE_NVM_FLASH) /* Deprecated */ 166 #define CYHAL_DRIVER_AVAILABLE_SYSPM (1) 167 #define CYHAL_DRIVER_AVAILABLE_RTC (((((CY_IP_MXS40SSRSS_INSTANCES) > 0) || ((CY_IP_MXS40SRSS_INSTANCES) > 0)) && ((SRSS_BACKUP_PRESENT) > 0)) || (((SRSS_RTC_PRESENT) > 0) && ((SRSS_NUM_HIBDATA) > 0))) 168 169 #if !defined(COMPONENT_CAT1D) 170 171 #define CYHAL_DRIVER_AVAILABLE_ADC ((_CYHAL_DRIVER_AVAILABLE_ADC_SAR) || (_CYHAL_DRIVER_AVAILABLE_ADC_MIC)) 172 #define CYHAL_DRIVER_AVAILABLE_COMP ((_CYHAL_DRIVER_AVAILABLE_COMP_LP) || (_CYHAL_DRIVER_AVAILABLE_COMP_CTB)) 173 #define CYHAL_DRIVER_AVAILABLE_CRC (((CY_IP_MXCRYPTO_INSTANCES) > 0) && (CPUSS_CRYPTO_CRC)) 174 #define CYHAL_DRIVER_AVAILABLE_DAC (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTDAC_INSTANCES) > 0)) 175 #define CYHAL_DRIVER_AVAILABLE_KEYSCAN ((CY_IP_MXKEYSCAN_INSTANCES) > 0) 176 #define CYHAL_DRIVER_AVAILABLE_OPAMP (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTB_INSTANCES) > 0)) 177 #define CYHAL_DRIVER_AVAILABLE_PDMPCM ((((CY_IP_MXAUDIOSS_INSTANCES) > 0) && (AUDIOSS_PDM || AUDIOSS0_PDM || AUDIOSS0_PDM_PDM)) || ((CY_IP_MXPDM_INSTANCES) > 0)) //AUDIOSS[x]_PDM 178 #define CYHAL_DRIVER_AVAILABLE_TRNG ((((CY_IP_MXCRYPTO_INSTANCES) > 0) && ((CPUSS_CRYPTO_TR) > 0)) /*|| (((CY_IP_MXCRYPTOLITE_INSTANCES) > 0) && ((CRYPTO_TRNG_PRESENT) > 0))*/) 179 #define CYHAL_DRIVER_AVAILABLE_USB_DEV ((CY_IP_MXUSBFS_INSTANCES) > 0) 180 181 #else /* COMPONENT_CAT1D */ 182 183 #define CYHAL_DRIVER_AVAILABLE_COMP (0) 184 #define CYHAL_DRIVER_AVAILABLE_CRC (0) 185 #define CYHAL_DRIVER_AVAILABLE_DAC (0) 186 #define CYHAL_DRIVER_AVAILABLE_KEYSCAN (0) 187 #define CYHAL_DRIVER_AVAILABLE_OPAMP (0) 188 #define CYHAL_DRIVER_AVAILABLE_PDMPCM (0) 189 #define CYHAL_DRIVER_AVAILABLE_TRNG (0) 190 #define CYHAL_DRIVER_AVAILABLE_USB_DEV (0) 191 #define CYHAL_DRIVER_AVAILABLE_ADC (0) 192 193 194 #endif /* not COMPONENT_CAT1D or other */ 195 196 /** \} group_hal_impl_availability */ 197 /** 198 * \addtogroup group_hal_impl_hw_types 199 * \ingroup group_hal_impl 200 * \{ 201 */ 202 203 204 /* NOTE: Any changes made to this enum must also be made to the hardware manager resource tracking */ 205 /** Resource types that the hardware manager supports */ 206 typedef enum 207 { 208 CYHAL_RSC_ADC, /*!< Analog to digital converter */ 209 CYHAL_RSC_ADCMIC, /*!< Analog to digital converter with Analog Mic support */ 210 CYHAL_RSC_BLESS, /*!< Bluetooth communications block */ 211 CYHAL_RSC_CAN, /*!< CAN communication block */ 212 CYHAL_RSC_CLKPATH, /*!< Clock Path. DEPRECATED. */ 213 CYHAL_RSC_CLOCK, /*!< Clock */ 214 CYHAL_RSC_CRYPTO, /*!< Crypto hardware accelerator */ 215 CYHAL_RSC_DAC, /*!< Digital to analog converter */ 216 CYHAL_RSC_DMA, /*!< DMA controller */ 217 CYHAL_RSC_DW, /*!< Datawire DMA controller */ 218 CYHAL_RSC_ETH, /*!< Ethernet communications block */ 219 CYHAL_RSC_GPIO, /*!< General purpose I/O pin */ 220 CYHAL_RSC_I2S, /*!< I2S communications block */ 221 CYHAL_RSC_I3C, /*!< I3C communications block */ 222 CYHAL_RSC_KEYSCAN, /*!< KeyScan block */ 223 CYHAL_RSC_LCD, /*!< Segment LCD controller */ 224 CYHAL_RSC_LIN, /*!< LIN communications block */ 225 CYHAL_RSC_LPCOMP, /*!< Low power comparator */ 226 CYHAL_RSC_LPTIMER, /*!< Low power timer */ 227 CYHAL_RSC_OPAMP, /*!< Opamp */ 228 CYHAL_RSC_PDM, /*!< PCM/PDM communications block */ 229 CYHAL_RSC_SMIF, /*!< Quad-SPI communications block */ 230 CYHAL_RSC_RTC, /*!< Real time clock */ 231 CYHAL_RSC_SCB, /*!< Serial Communications Block */ 232 CYHAL_RSC_SDHC, /*!< SD Host Controller */ 233 CYHAL_RSC_SDIODEV, /*!< SDIO Device Block */ 234 CYHAL_RSC_TCPWM, /*!< Timer/Counter/PWM block */ 235 CYHAL_RSC_TDM, /*!< TDM block */ 236 CYHAL_RSC_UDB, /*!< UDB Array */ 237 CYHAL_RSC_USB, /*!< USB communication block */ 238 CYHAL_RSC_INVALID, /*!< Placeholder for invalid type */ 239 } cyhal_resource_t; 240 241 /** \cond INTERNAL */ 242 /* Extracts the divider from the Peri group block number */ 243 #define _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03)) 244 #define _CYHAL_PERIPHERAL_GROUP_GET_GROUP(block) ((block) >> 2) 245 246 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D) 247 248 #if !defined(COMPONENT_CAT1D) 249 /* Converts the group/div pair into a unique block number. */ 250 #define _CYHAL_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div)) 251 252 #define _CYHAL_CLOCK_BLOCK_PERI_GROUP(gr) \ 253 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_8_BIT), /*!< 8bit Peripheral Divider Group */ \ 254 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_16_BIT), /*!< 16bit Peripheral Divider Group */ \ 255 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider Group */ \ 256 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider Group */ 257 #else /* !defined(COMPONENT_CAT1D) */ 258 /* Converts the group/div pair into a unique block number. */ 259 #define _CYHAL_PERIPHERAL_GROUP_ADJUST(instance, group, div) (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div)) 260 #define _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR) 261 #define _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock) ((clock >> 2) - (_CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR)) 262 263 #define _CYHAL_CLOCK_BLOCK_PERI_GROUP(instance, gr) \ 264 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), /*!< 8bit Peripheral Divider for specified instance and group */ \ 265 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), /*!< 16bit Peripheral Divider for specified instance and group */ \ 266 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider for specified instance and group */ \ 267 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider for specified instance and group */ 268 #endif /* !defined(COMPONENT_CAT1D) or other */ 269 #endif 270 /** \endcond */ 271 272 /* NOTE: Any changes here must also be made in cyhal_hwmgr.c */ 273 /** Enum for the different types of clocks that exist on the device. */ 274 typedef enum 275 { 276 #if defined(COMPONENT_CAT1A) 277 // The first four items are here for backwards compatability with old clock APIs 278 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< 8bit Peripheral Divider */ 279 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< 16bit Peripheral Divider */ 280 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< 16.5bit Peripheral Divider */ 281 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< 24.5bit Peripheral Divider */ 282 283 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 284 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 285 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 286 CYHAL_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */ 287 CYHAL_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */ 288 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 289 #if !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0)) 290 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 291 #endif 292 293 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 294 CYHAL_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */ 295 296 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 297 298 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 299 #if defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0) 300 CYHAL_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */ 301 CYHAL_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */ 302 #else 303 CYHAL_CLOCK_BLOCK_PLL, /*!< Phase-Locked Loop Clock */ 304 #endif 305 306 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 307 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 308 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 309 310 CYHAL_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */ 311 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 312 CYHAL_CLOCK_BLOCK_TIMER, /*!< Timer Clock */ 313 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 314 315 CYHAL_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM4 */ 316 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock */ 317 CYHAL_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */ 318 319 320 #elif defined(COMPONENT_CAT1B) 321 322 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ 323 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ 324 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */ 325 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */ 326 327 // The first four items are here for backwards compatability with old clock APIs 328 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1) 329 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0), 330 #endif 331 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2) 332 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1), 333 #endif 334 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3) 335 _CYHAL_CLOCK_BLOCK_PERI_GROUP(2), 336 #endif 337 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4) 338 _CYHAL_CLOCK_BLOCK_PERI_GROUP(3), 339 #endif 340 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5) 341 _CYHAL_CLOCK_BLOCK_PERI_GROUP(4), 342 #endif 343 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6) 344 _CYHAL_CLOCK_BLOCK_PERI_GROUP(5), 345 #endif 346 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7) 347 _CYHAL_CLOCK_BLOCK_PERI_GROUP(6), 348 #endif 349 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8) 350 _CYHAL_CLOCK_BLOCK_PERI_GROUP(7), 351 #endif 352 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9) 353 _CYHAL_CLOCK_BLOCK_PERI_GROUP(8), 354 #endif 355 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10) 356 _CYHAL_CLOCK_BLOCK_PERI_GROUP(9), 357 #endif 358 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11) 359 _CYHAL_CLOCK_BLOCK_PERI_GROUP(10), 360 #endif 361 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12) 362 _CYHAL_CLOCK_BLOCK_PERI_GROUP(11), 363 #endif 364 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13) 365 _CYHAL_CLOCK_BLOCK_PERI_GROUP(12), 366 #endif 367 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14) 368 _CYHAL_CLOCK_BLOCK_PERI_GROUP(13), 369 #endif 370 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15) 371 _CYHAL_CLOCK_BLOCK_PERI_GROUP(14), 372 #endif 373 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16) 374 _CYHAL_CLOCK_BLOCK_PERI_GROUP(15), 375 #endif 376 377 CYHAL_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */ 378 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 379 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 380 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 381 CYHAL_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */ 382 CYHAL_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */ 383 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 384 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 385 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 386 CYHAL_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */ 387 388 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 389 390 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 391 CYHAL_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */ 392 CYHAL_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */ 393 CYHAL_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */ 394 395 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 396 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 397 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 398 399 CYHAL_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */ 400 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 401 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 402 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ 403 404 #elif defined(COMPONENT_CAT1C) 405 406 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ 407 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ 408 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */ 409 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */ 410 411 // The first four items are here for backwards compatability with old clock APIs 412 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1) 413 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0), 414 #endif 415 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2) 416 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1), 417 #endif 418 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3) 419 _CYHAL_CLOCK_BLOCK_PERI_GROUP(2), 420 #endif 421 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4) 422 _CYHAL_CLOCK_BLOCK_PERI_GROUP(3), 423 #endif 424 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5) 425 _CYHAL_CLOCK_BLOCK_PERI_GROUP(4), 426 #endif 427 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6) 428 _CYHAL_CLOCK_BLOCK_PERI_GROUP(5), 429 #endif 430 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7) 431 _CYHAL_CLOCK_BLOCK_PERI_GROUP(6), 432 #endif 433 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8) 434 _CYHAL_CLOCK_BLOCK_PERI_GROUP(7), 435 #endif 436 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9) 437 _CYHAL_CLOCK_BLOCK_PERI_GROUP(8), 438 #endif 439 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10) 440 _CYHAL_CLOCK_BLOCK_PERI_GROUP(9), 441 #endif 442 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11) 443 _CYHAL_CLOCK_BLOCK_PERI_GROUP(10), 444 #endif 445 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12) 446 _CYHAL_CLOCK_BLOCK_PERI_GROUP(11), 447 #endif 448 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13) 449 _CYHAL_CLOCK_BLOCK_PERI_GROUP(12), 450 #endif 451 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14) 452 _CYHAL_CLOCK_BLOCK_PERI_GROUP(13), 453 #endif 454 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15) 455 _CYHAL_CLOCK_BLOCK_PERI_GROUP(14), 456 #endif 457 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16) 458 _CYHAL_CLOCK_BLOCK_PERI_GROUP(15), 459 #endif 460 461 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 462 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 463 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 464 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 465 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 466 467 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 468 469 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 470 CYHAL_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */ 471 CYHAL_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */ 472 473 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 474 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 475 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 476 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 477 478 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ 479 CYHAL_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM7 */ 480 CYHAL_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */ 481 CYHAL_CLOCK_BLOCK_MEM, /*!< CLK MEM */ 482 CYHAL_CLOCK_BLOCK_TIMER, /*!< CLK Timer */ 483 484 #elif defined(COMPONENT_CAT1D) 485 486 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ 487 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ 488 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */ 489 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */ 490 491 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1) 492 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 0), 493 #endif 494 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2) 495 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 1), 496 #endif 497 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3) 498 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 2), 499 #endif 500 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4) 501 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 3), 502 #endif 503 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5) 504 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 4), 505 #endif 506 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6) 507 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 5), 508 #endif 509 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7) 510 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 6), 511 #endif 512 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8) 513 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 7), 514 #endif 515 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9) 516 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 8), 517 #endif 518 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10) 519 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 9), 520 #endif 521 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11) 522 #warning "Unhandled PERI0 PCLK number" 523 #endif 524 525 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1) 526 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 0), 527 #endif 528 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2) 529 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 1), 530 #endif 531 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3) 532 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 2), 533 #endif 534 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4) 535 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 3), 536 #endif 537 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5) 538 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 4), 539 #endif 540 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6) 541 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 5), 542 #endif 543 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7) 544 #warning "Unhandled PERI1 PCLK number" 545 #endif 546 547 CYHAL_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */ 548 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 549 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 550 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 551 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 552 553 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 554 555 CYHAL_CLOCK_BLOCK_DPLL250, /*!< 250MHz Digital Phase-Locked Loop Clock */ 556 CYHAL_CLOCK_BLOCK_DPLL500, /*!< 500MHz Digital Phase-Locked Loop Clock */ 557 CYHAL_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */ 558 559 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 560 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 561 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 562 563 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 564 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ 565 566 #endif 567 } cyhal_clock_block_t; 568 569 /** @brief Clock object 570 * Application code should not rely on the specific contents of this struct. 571 * They are considered an implementation detail which is subject to change 572 * between platforms and/or HAL releases. */ 573 typedef struct 574 { 575 cyhal_clock_block_t block; 576 uint8_t channel; 577 bool reserved; 578 const void* funcs; 579 } cyhal_clock_t; 580 581 /** 582 * @brief Represents a particular instance of a resource on the chip. 583 * Application code should not rely on the specific contents of this struct. 584 * They are considered an implementation detail which is subject to change 585 * between platforms and/or HAL releases. 586 */ 587 typedef struct 588 { 589 cyhal_resource_t type; //!< The resource block type 590 uint8_t block_num; //!< The resource block index 591 /** 592 * The channel number, if the resource type defines multiple channels 593 * per block instance. Otherwise, 0 */ 594 uint8_t channel_num; 595 } cyhal_resource_inst_t; 596 597 #if defined(__cplusplus) 598 } 599 #endif /* __cplusplus */ 600 601 /** \} group_hal_impl_hw_types */ 602
