1 /***************************************************************************//** 2 * \file cyhal_hw_resources.h 3 * 4 * \brief 5 * Provides struct definitions for configuration resources in the PDL. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 /** 28 * \addtogroup group_hal_impl_availability HAL Driver Availability Macros 29 * \ingroup group_hal_impl 30 * \{ 31 */ 32 33 #pragma once 34 35 #include "cy_pdl.h" 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 // Documented in cyhal.h 42 #define CYHAL_API_VERSION (2) 43 44 /** \cond INTERNAL */ 45 #define _CYHAL_DRIVER_AVAILABLE_SCB (((CY_IP_MXSCB_INSTANCES) > 0) || ((CY_IP_MXS22SCB_INSTANCES) > 0)) 46 #define _CYHAL_DRIVER_AVAILABLE_TCPWM ((CY_IP_MXTCPWM_INSTANCES) > 0) 47 #define _CYHAL_DRIVER_AVAILABLE_IRQ (1) 48 49 #if defined(CY_IP_MXUDB_INSTANCES) && defined(CYHAL_UDB_SDIO) 50 #define _CYHAL_DRIVER_AVAILABLE_SDIO_UDB (1) 51 #else 52 #define _CYHAL_DRIVER_AVAILABLE_SDIO_UDB (0) 53 #endif 54 #define _CYHAL_DRIVER_AVAILABLE_DMA_DMAC (((CY_IP_M4CPUSS_DMAC_INSTANCES) > 0) || ((CY_IP_M7CPUSS_DMAC_INSTANCES) > 0) || ((CY_IP_MXAHBDMAC_INSTANCES) > 0) || ((CY_IP_MXSAXIDMAC_INSTANCES) > 0)) 55 #define _CYHAL_DRIVER_AVAILABLE_DMA_DW (((CY_IP_M4CPUSS_DMA_INSTANCES) > 0) || ((CY_IP_M7CPUSS_DMA_INSTANCES) > 0) || ((CY_IP_MXDW_INSTANCES) > 0)) 56 57 #define _CYHAL_DRIVER_AVAILABLE_NVM_FLASH (((FLASHC_BASE) > 0) || ((CPUSS_FLASHC_PRESENT) > 0)) 58 #define _CYHAL_DRIVER_AVAILABLE_NVM_OTP ((CY_IP_MXS22RRAMC_INSTANCES) > 0) 59 #define _CYHAL_DRIVER_AVAILABLE_NVM_RRAM ((CY_IP_MXS22RRAMC_INSTANCES) > 0) 60 61 #if !defined(COMPONENT_CAT1D) 62 63 #define _CYHAL_DRIVER_AVAILABLE_ADC_SAR ((CY_IP_MXS40PASS_SAR_INSTANCES) > 0) || ((CY_IP_MXS40EPASS_ESAR_INSTANCES) > 0) 64 #define _CYHAL_DRIVER_AVAILABLE_ADC_MIC ((CY_IP_MXS40ADCMIC_INSTANCES) > 0) 65 #define _CYHAL_DRIVER_AVAILABLE_COMP_LP ((CY_IP_MXLPCOMP_INSTANCES) > 0) 66 #define _CYHAL_DRIVER_AVAILABLE_COMP_CTB (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTB_INSTANCES) > 0)) 67 68 #define _CYHAL_DRIVER_AVAILABLE_PASS ((CY_IP_MXS40PASS_INSTANCES) > 0) || ((CY_IP_MXS40EPASS_INSTANCES) > 0) 69 /* MXCRYPTOLITE is not yet supported */ 70 //#define _CYHAL_DRIVER_AVAILABLE_CRYPTO (((CY_IP_MXCRYPTO_INSTANCES) > 0) || ((CY_IP_MXCRYPTOLITE_INSTANCES) > 0)) 71 #define _CYHAL_DRIVER_AVAILABLE_CRYPTO ((CY_IP_MXCRYPTO_INSTANCES) > 0) 72 73 #else 74 75 #define _CYHAL_DRIVER_AVAILABLE_ADC_SAR (0) 76 #define _CYHAL_DRIVER_AVAILABLE_ADC_MIC (0) 77 #define _CYHAL_DRIVER_AVAILABLE_COMP_LP (0) 78 #define _CYHAL_DRIVER_AVAILABLE_COMP_CTB (0) 79 #define _CYHAL_DRIVER_AVAILABLE_PASS (0) 80 #define _CYHAL_DRIVER_AVAILABLE_CRYPTO (0) 81 82 #endif /* not COMPONENT_CAT1D or COMPONENT_CAT1D */ 83 84 #if defined(PERI_PERI_PCLK_PCLK_GROUP_NR) 85 #define _CYHAL_CLOCK_PERI_GROUPS PERI_PERI_PCLK_PCLK_GROUP_NR 86 #elif (defined(PERI0_PERI_PCLK_PCLK_GROUP_NR) && defined(PERI1_PERI_PCLK_PCLK_GROUP_NR)) 87 #define _CYHAL_CLOCK_PERI_GROUPS (PERI0_PERI_PCLK_PCLK_GROUP_NR + PERI1_PERI_PCLK_PCLK_GROUP_NR) 88 #else 89 #define _CYHAL_CLOCK_PERI_GROUPS 1 90 #endif 91 92 93 #if defined(COMPONENT_CAT1C) 94 /* CAT1C devices define _CYHAL_SRSS_NUM_PLL to be the macro that documents the number of 200MHz PLL's present */ 95 #define SRSS_NUM_PLL200M SRSS_NUM_PLL 96 #elif defined(COMPONENT_CAT1D) 97 /* CAT1D devices define SRSS_NUM_DPLL_LP/SRSS_NUM_DPLL_HP to be the macro that documents the number of 200/500MHz PLL's present */ 98 #define SRSS_NUM_DPLL250M SRSS_NUM_DPLL_LP 99 #define SRSS_NUM_DPLL500M SRSS_NUM_DPLL_HP 100 #endif 101 102 #if defined(COMPONENT_CAT1C) && (SRSS_HT_VARIANT) 103 #define _CYHAL_SRSS_NUM_ILO 2U 104 #else 105 #define _CYHAL_SRSS_NUM_ILO 1U 106 #endif 107 108 #define _CYHAL_SRSS_NUM_FAST (1 + CPUSS_CM7_1_PRESENT) 109 110 /* Alignment for DMA descriptors */ 111 #if (CY_IP_MXSAXIDMAC) 112 /* AXI DMA controller has a 64-bit AXI master interface */ 113 #define _CYHAL_DMA_ALIGN CY_ALIGN(8) 114 #elif (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) 115 #define _CYHAL_DMA_ALIGN CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 116 #else 117 #define _CYHAL_DMA_ALIGN 118 #endif 119 120 /** \endcond */ 121 122 // Documented in cyhal.h 123 #define CYHAL_DRIVER_AVAILABLE_HWMGR (1) 124 #define CYHAL_DRIVER_AVAILABLE_GPIO (1) 125 #define CYHAL_DRIVER_AVAILABLE_INTERCONNECT (1) 126 #define CYHAL_DRIVER_AVAILABLE_CLOCK (1) 127 #define CYHAL_DRIVER_AVAILABLE_SYSTEM (1) 128 129 #define CYHAL_DRIVER_AVAILABLE_EZI2C (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_I2C 130 #define CYHAL_DRIVER_AVAILABLE_I2C (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_I2C 131 #define CYHAL_DRIVER_AVAILABLE_SPI (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_SPI 132 #define CYHAL_DRIVER_AVAILABLE_UART (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_UART 133 #define CYHAL_DRIVER_AVAILABLE_WDT (1) 134 #define CYHAL_DRIVER_AVAILABLE_TIMER (_CYHAL_DRIVER_AVAILABLE_TCPWM) 135 #define CYHAL_DRIVER_AVAILABLE_PWM (_CYHAL_DRIVER_AVAILABLE_TCPWM) 136 #define CYHAL_DRIVER_AVAILABLE_QUADDEC (_CYHAL_DRIVER_AVAILABLE_TCPWM) 137 138 #define CYHAL_DRIVER_AVAILABLE_I2S ((((CY_IP_MXAUDIOSS_INSTANCES) > 0) && (AUDIOSS_I2S || AUDIOSS0_I2S || AUDIOSS0_I2S_I2S)) || ((CY_IP_MXTDM_INSTANCES) > 0)) //AUDIOSS[x]_I2S 139 #define CYHAL_DRIVER_AVAILABLE_I2S_TX (CYHAL_DRIVER_AVAILABLE_I2S) 140 #define CYHAL_DRIVER_AVAILABLE_I2S_RX (CYHAL_DRIVER_AVAILABLE_I2S) 141 #define CYHAL_DRIVER_AVAILABLE_TDM ((((CY_IP_MXAUDIOSS_INSTANCES) > 0) && (AUDIOSS_I2S || AUDIOSS0_I2S || AUDIOSS0_I2S_I2S)) || ((CY_IP_MXTDM_INSTANCES) > 0)) //AUDIOSS[x]_I2S 142 #define CYHAL_DRIVER_AVAILABLE_TDM_TX (CYHAL_DRIVER_AVAILABLE_TDM) 143 #define CYHAL_DRIVER_AVAILABLE_TDM_RX (CYHAL_DRIVER_AVAILABLE_TDM) 144 #define CYHAL_DRIVER_AVAILABLE_DMA ((_CYHAL_DRIVER_AVAILABLE_DMA_DMAC) || (_CYHAL_DRIVER_AVAILABLE_DMA_DW)) 145 #if !defined(COMPONENT_CAT1B) && !defined(COMPONENT_CAT1D) 146 #define CYHAL_DRIVER_AVAILABLE_IPC ((CPUSS_IPC_IPC_NR > 0) || (CY_IP_MXIPC_INSTANCES > 0)) 147 #else 148 #define CYHAL_DRIVER_AVAILABLE_IPC (0) 149 #endif /* !defined(COMPONENT_CAT1B) && !defined(COMPONENT_CAT1D) or other */ 150 #define CYHAL_DRIVER_AVAILABLE_QSPI ((CY_IP_MXSMIF_INSTANCES) > 0) 151 #if (defined (COMPONENT_CM0P) && defined(COMPONENT_CAT1D))//CAT 1D CM0P cannot have LPTimer instances because no interrupts are routed to this CPU 152 #define CYHAL_DRIVER_AVAILABLE_LPTIMER (0) 153 #else 154 #define CYHAL_DRIVER_AVAILABLE_LPTIMER ((SRSS_NUM_MCWDT) > 0) 155 #endif 156 #define CYHAL_DRIVER_AVAILABLE_SDHC ((CY_IP_MXSDHC_INSTANCES) > 0) 157 #define CYHAL_DRIVER_AVAILABLE_SDIO (((CY_IP_MXSDHC_INSTANCES) > 0) || (_CYHAL_DRIVER_AVAILABLE_SDIO_UDB)) 158 #define CYHAL_DRIVER_AVAILABLE_SDIO_HOST (CYHAL_DRIVER_AVAILABLE_SDIO) 159 #define CYHAL_DRIVER_AVAILABLE_SDIO_DEV (0) 160 #define CYHAL_DRIVER_AVAILABLE_NVM (_CYHAL_DRIVER_AVAILABLE_NVM_FLASH || _CYHAL_DRIVER_AVAILABLE_NVM_RRAM || _CYHAL_DRIVER_AVAILABLE_NVM_OTP) 161 #define CYHAL_DRIVER_AVAILABLE_FLASH (_CYHAL_DRIVER_AVAILABLE_NVM_FLASH) /* Deprecated */ 162 #define CYHAL_DRIVER_AVAILABLE_SYSPM (1) 163 #define CYHAL_DRIVER_AVAILABLE_RTC (((((CY_IP_MXS40SSRSS_INSTANCES) > 0) || ((CY_IP_MXS40SRSS_INSTANCES) > 0)) && ((SRSS_BACKUP_PRESENT) > 0)) || (((SRSS_RTC_PRESENT) > 0) && ((SRSS_NUM_HIBDATA) > 0))) 164 165 #if !defined(COMPONENT_CAT1D) 166 167 #define CYHAL_DRIVER_AVAILABLE_ADC ((_CYHAL_DRIVER_AVAILABLE_ADC_SAR) || (_CYHAL_DRIVER_AVAILABLE_ADC_MIC)) 168 #define CYHAL_DRIVER_AVAILABLE_COMP ((_CYHAL_DRIVER_AVAILABLE_COMP_LP) || (_CYHAL_DRIVER_AVAILABLE_COMP_CTB)) 169 #define CYHAL_DRIVER_AVAILABLE_CRC (((CY_IP_MXCRYPTO_INSTANCES) > 0) && (CPUSS_CRYPTO_CRC)) 170 #define CYHAL_DRIVER_AVAILABLE_DAC (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTDAC_INSTANCES) > 0)) 171 #define CYHAL_DRIVER_AVAILABLE_KEYSCAN ((CY_IP_MXKEYSCAN_INSTANCES) > 0) 172 #define CYHAL_DRIVER_AVAILABLE_OPAMP (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTB_INSTANCES) > 0)) 173 #define CYHAL_DRIVER_AVAILABLE_PDMPCM ((((CY_IP_MXAUDIOSS_INSTANCES) > 0) && (AUDIOSS_PDM || AUDIOSS0_PDM || AUDIOSS0_PDM_PDM)) || ((CY_IP_MXPDM_INSTANCES) > 0)) //AUDIOSS[x]_PDM 174 #define CYHAL_DRIVER_AVAILABLE_TRNG ((((CY_IP_MXCRYPTO_INSTANCES) > 0) && ((CPUSS_CRYPTO_TR) > 0)) /*|| (((CY_IP_MXCRYPTOLITE_INSTANCES) > 0) && ((CRYPTO_TRNG_PRESENT) > 0))*/) 175 #define CYHAL_DRIVER_AVAILABLE_USB_DEV ((CY_IP_MXUSBFS_INSTANCES) > 0) 176 177 #else /* COMPONENT_CAT1D */ 178 179 #define CYHAL_DRIVER_AVAILABLE_COMP (0) 180 #define CYHAL_DRIVER_AVAILABLE_CRC (0) 181 #define CYHAL_DRIVER_AVAILABLE_DAC (0) 182 #define CYHAL_DRIVER_AVAILABLE_KEYSCAN (0) 183 #define CYHAL_DRIVER_AVAILABLE_OPAMP (0) 184 #define CYHAL_DRIVER_AVAILABLE_PDMPCM (0) 185 #define CYHAL_DRIVER_AVAILABLE_TRNG (0) 186 #define CYHAL_DRIVER_AVAILABLE_USB_DEV (0) 187 #define CYHAL_DRIVER_AVAILABLE_ADC (0) 188 189 190 #endif /* not COMPONENT_CAT1D or other */ 191 192 /** \} group_hal_impl_availability */ 193 /** 194 * \addtogroup group_hal_impl_hw_types 195 * \ingroup group_hal_impl 196 * \{ 197 */ 198 199 200 /* NOTE: Any changes made to this enum must also be made to the hardware manager resource tracking */ 201 /** Resource types that the hardware manager supports */ 202 typedef enum 203 { 204 CYHAL_RSC_ADC, /*!< Analog to digital converter */ 205 CYHAL_RSC_ADCMIC, /*!< Analog to digital converter with Analog Mic support */ 206 CYHAL_RSC_BLESS, /*!< Bluetooth communications block */ 207 CYHAL_RSC_CAN, /*!< CAN communication block */ 208 CYHAL_RSC_CLKPATH, /*!< Clock Path. DEPRECATED. */ 209 CYHAL_RSC_CLOCK, /*!< Clock */ 210 CYHAL_RSC_CRYPTO, /*!< Crypto hardware accelerator */ 211 CYHAL_RSC_DAC, /*!< Digital to analog converter */ 212 CYHAL_RSC_DMA, /*!< DMA controller */ 213 CYHAL_RSC_DW, /*!< Datawire DMA controller */ 214 CYHAL_RSC_ETH, /*!< Ethernet communications block */ 215 CYHAL_RSC_GPIO, /*!< General purpose I/O pin */ 216 CYHAL_RSC_I2S, /*!< I2S communications block */ 217 CYHAL_RSC_I3C, /*!< I3C communications block */ 218 CYHAL_RSC_KEYSCAN, /*!< KeyScan block */ 219 CYHAL_RSC_LCD, /*!< Segment LCD controller */ 220 CYHAL_RSC_LIN, /*!< LIN communications block */ 221 CYHAL_RSC_LPCOMP, /*!< Low power comparator */ 222 CYHAL_RSC_LPTIMER, /*!< Low power timer */ 223 CYHAL_RSC_OPAMP, /*!< Opamp */ 224 CYHAL_RSC_PDM, /*!< PCM/PDM communications block */ 225 CYHAL_RSC_SMIF, /*!< Quad-SPI communications block */ 226 CYHAL_RSC_RTC, /*!< Real time clock */ 227 CYHAL_RSC_SCB, /*!< Serial Communications Block */ 228 CYHAL_RSC_SDHC, /*!< SD Host Controller */ 229 CYHAL_RSC_SDIODEV, /*!< SDIO Device Block */ 230 CYHAL_RSC_TCPWM, /*!< Timer/Counter/PWM block */ 231 CYHAL_RSC_TDM, /*!< TDM block */ 232 CYHAL_RSC_UDB, /*!< UDB Array */ 233 CYHAL_RSC_USB, /*!< USB communication block */ 234 CYHAL_RSC_INVALID, /*!< Placeholder for invalid type */ 235 } cyhal_resource_t; 236 237 /** \cond INTERNAL */ 238 /* Extracts the divider from the Peri group block number */ 239 #define _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03)) 240 #define _CYHAL_PERIPHERAL_GROUP_GET_GROUP(block) ((block) >> 2) 241 242 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D) 243 244 #if !defined(COMPONENT_CAT1D) 245 /* Converts the group/div pair into a unique block number. */ 246 #define _CYHAL_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div)) 247 248 #define _CYHAL_CLOCK_BLOCK_PERI_GROUP(gr) \ 249 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_8_BIT), /*!< 8bit Peripheral Divider Group */ \ 250 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_16_BIT), /*!< 16bit Peripheral Divider Group */ \ 251 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider Group */ \ 252 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider Group */ 253 #else /* !defined(COMPONENT_CAT1D) */ 254 /* Converts the group/div pair into a unique block number. */ 255 #define _CYHAL_PERIPHERAL_GROUP_ADJUST(instance, group, div) (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div)) 256 #define _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR) 257 #define _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock) ((clock >> 2) - (_CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR)) 258 259 #define _CYHAL_CLOCK_BLOCK_PERI_GROUP(instance, gr) \ 260 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), /*!< 8bit Peripheral Divider for specified instance and group */ \ 261 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), /*!< 16bit Peripheral Divider for specified instance and group */ \ 262 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider for specified instance and group */ \ 263 CYHAL_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider for specified instance and group */ 264 #endif /* !defined(COMPONENT_CAT1D) or other */ 265 #endif 266 /** \endcond */ 267 268 /* NOTE: Any changes here must also be made in cyhal_hwmgr.c */ 269 /** Enum for the different types of clocks that exist on the device. */ 270 typedef enum 271 { 272 #if defined(COMPONENT_CAT1A) 273 // The first four items are here for backwards compatability with old clock APIs 274 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< 8bit Peripheral Divider */ 275 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< 16bit Peripheral Divider */ 276 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< 16.5bit Peripheral Divider */ 277 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< 24.5bit Peripheral Divider */ 278 279 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 280 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 281 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 282 CYHAL_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */ 283 CYHAL_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */ 284 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 285 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 286 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 287 CYHAL_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */ 288 289 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 290 291 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 292 CYHAL_CLOCK_BLOCK_PLL, /*!< Phase-Locked Loop Clock */ 293 294 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 295 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 296 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 297 298 CYHAL_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */ 299 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 300 CYHAL_CLOCK_BLOCK_TIMER, /*!< Timer Clock */ 301 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 302 303 CYHAL_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM4 */ 304 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock */ 305 CYHAL_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */ 306 #elif defined(COMPONENT_CAT1B) 307 308 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ 309 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ 310 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */ 311 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */ 312 313 // The first four items are here for backwards compatability with old clock APIs 314 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1) 315 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0), 316 #endif 317 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2) 318 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1), 319 #endif 320 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3) 321 _CYHAL_CLOCK_BLOCK_PERI_GROUP(2), 322 #endif 323 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4) 324 _CYHAL_CLOCK_BLOCK_PERI_GROUP(3), 325 #endif 326 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5) 327 _CYHAL_CLOCK_BLOCK_PERI_GROUP(4), 328 #endif 329 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6) 330 _CYHAL_CLOCK_BLOCK_PERI_GROUP(5), 331 #endif 332 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7) 333 _CYHAL_CLOCK_BLOCK_PERI_GROUP(6), 334 #endif 335 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8) 336 _CYHAL_CLOCK_BLOCK_PERI_GROUP(7), 337 #endif 338 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9) 339 _CYHAL_CLOCK_BLOCK_PERI_GROUP(8), 340 #endif 341 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10) 342 _CYHAL_CLOCK_BLOCK_PERI_GROUP(9), 343 #endif 344 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11) 345 _CYHAL_CLOCK_BLOCK_PERI_GROUP(10), 346 #endif 347 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12) 348 _CYHAL_CLOCK_BLOCK_PERI_GROUP(11), 349 #endif 350 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13) 351 _CYHAL_CLOCK_BLOCK_PERI_GROUP(12), 352 #endif 353 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14) 354 _CYHAL_CLOCK_BLOCK_PERI_GROUP(13), 355 #endif 356 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15) 357 _CYHAL_CLOCK_BLOCK_PERI_GROUP(14), 358 #endif 359 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16) 360 _CYHAL_CLOCK_BLOCK_PERI_GROUP(15), 361 #endif 362 363 CYHAL_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */ 364 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 365 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 366 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 367 CYHAL_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */ 368 CYHAL_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */ 369 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 370 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 371 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 372 CYHAL_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */ 373 374 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 375 376 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 377 CYHAL_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */ 378 CYHAL_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */ 379 CYHAL_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */ 380 381 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 382 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 383 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 384 385 CYHAL_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */ 386 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 387 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 388 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ 389 390 #elif defined(COMPONENT_CAT1C) 391 392 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ 393 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ 394 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */ 395 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */ 396 397 // The first four items are here for backwards compatability with old clock APIs 398 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1) 399 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0), 400 #endif 401 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2) 402 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1), 403 #endif 404 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3) 405 _CYHAL_CLOCK_BLOCK_PERI_GROUP(2), 406 #endif 407 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4) 408 _CYHAL_CLOCK_BLOCK_PERI_GROUP(3), 409 #endif 410 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5) 411 _CYHAL_CLOCK_BLOCK_PERI_GROUP(4), 412 #endif 413 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6) 414 _CYHAL_CLOCK_BLOCK_PERI_GROUP(5), 415 #endif 416 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7) 417 _CYHAL_CLOCK_BLOCK_PERI_GROUP(6), 418 #endif 419 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8) 420 _CYHAL_CLOCK_BLOCK_PERI_GROUP(7), 421 #endif 422 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9) 423 _CYHAL_CLOCK_BLOCK_PERI_GROUP(8), 424 #endif 425 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10) 426 _CYHAL_CLOCK_BLOCK_PERI_GROUP(9), 427 #endif 428 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11) 429 _CYHAL_CLOCK_BLOCK_PERI_GROUP(10), 430 #endif 431 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12) 432 _CYHAL_CLOCK_BLOCK_PERI_GROUP(11), 433 #endif 434 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13) 435 _CYHAL_CLOCK_BLOCK_PERI_GROUP(12), 436 #endif 437 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14) 438 _CYHAL_CLOCK_BLOCK_PERI_GROUP(13), 439 #endif 440 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15) 441 _CYHAL_CLOCK_BLOCK_PERI_GROUP(14), 442 #endif 443 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16) 444 _CYHAL_CLOCK_BLOCK_PERI_GROUP(15), 445 #endif 446 447 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 448 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 449 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 450 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 451 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 452 453 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 454 455 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 456 CYHAL_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */ 457 CYHAL_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */ 458 459 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 460 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 461 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 462 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 463 464 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ 465 CYHAL_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM7 */ 466 CYHAL_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */ 467 CYHAL_CLOCK_BLOCK_MEM, /*!< CLK MEM */ 468 CYHAL_CLOCK_BLOCK_TIMER, /*!< CLK Timer */ 469 470 #elif defined(COMPONENT_CAT1D) 471 472 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ 473 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ 474 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */ 475 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */ 476 477 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1) 478 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 0), 479 #endif 480 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2) 481 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 1), 482 #endif 483 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3) 484 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 2), 485 #endif 486 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4) 487 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 3), 488 #endif 489 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5) 490 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 4), 491 #endif 492 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6) 493 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 5), 494 #endif 495 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7) 496 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 6), 497 #endif 498 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8) 499 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 7), 500 #endif 501 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9) 502 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 8), 503 #endif 504 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10) 505 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0, 9), 506 #endif 507 #if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11) 508 #warning "Unhandled PERI0 PCLK number" 509 #endif 510 511 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1) 512 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 0), 513 #endif 514 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2) 515 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 1), 516 #endif 517 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3) 518 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 2), 519 #endif 520 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4) 521 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 3), 522 #endif 523 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5) 524 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 4), 525 #endif 526 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6) 527 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1, 5), 528 #endif 529 #if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7) 530 #warning "Unhandled PERI1 PCLK number" 531 #endif 532 533 CYHAL_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */ 534 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 535 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 536 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 537 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 538 539 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 540 541 CYHAL_CLOCK_BLOCK_DPLL250, /*!< 250MHz Digital Phase-Locked Loop Clock */ 542 CYHAL_CLOCK_BLOCK_DPLL500, /*!< 500MHz Digital Phase-Locked Loop Clock */ 543 CYHAL_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */ 544 545 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 546 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 547 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 548 549 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 550 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ 551 552 #endif 553 } cyhal_clock_block_t; 554 555 /** @brief Clock object 556 * Application code should not rely on the specific contents of this struct. 557 * They are considered an implementation detail which is subject to change 558 * between platforms and/or HAL releases. */ 559 typedef struct 560 { 561 cyhal_clock_block_t block; 562 uint8_t channel; 563 bool reserved; 564 const void* funcs; 565 } cyhal_clock_t; 566 567 /** 568 * @brief Represents a particular instance of a resource on the chip. 569 * Application code should not rely on the specific contents of this struct. 570 * They are considered an implementation detail which is subject to change 571 * between platforms and/or HAL releases. 572 */ 573 typedef struct 574 { 575 cyhal_resource_t type; //!< The resource block type 576 uint8_t block_num; //!< The resource block index 577 /** 578 * The channel number, if the resource type defines multiple channels 579 * per block instance. Otherwise, 0 */ 580 uint8_t channel_num; 581 } cyhal_resource_inst_t; 582 583 #if defined(__cplusplus) 584 } 585 #endif /* __cplusplus */ 586 587 /** \} group_hal_impl_hw_types */ 588
