1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 CMU register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_CMU_H 31 #define EFR32MG21_CMU_H 32 #define CMU_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_CMU CMU 40 * @{ 41 * @brief EFR32MG21 CMU Register Declaration. 42 *****************************************************************************/ 43 44 /** CMU Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 48 __IM uint32_t STATUS; /**< Status Register */ 49 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 50 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 51 __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ 52 uint32_t RESERVED2[2U]; /**< Reserved for future use */ 53 __IOM uint32_t IF; /**< Interrupt Flag Register */ 54 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 55 uint32_t RESERVED3[10U]; /**< Reserved for future use */ 56 __IOM uint32_t CALCMD; /**< Calibration Command Register */ 57 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 58 __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ 59 uint32_t RESERVED4[5U]; /**< Reserved for future use */ 60 __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ 61 uint32_t RESERVED5[3U]; /**< Reserved for future use */ 62 __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ 63 uint32_t RESERVED6[3U]; /**< Reserved for future use */ 64 __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ 65 uint32_t RESERVED7[27U]; /**< Reserved for future use */ 66 __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ 67 uint32_t RESERVED8[7U]; /**< Reserved for future use */ 68 __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ 69 uint32_t RESERVED9[7U]; /**< Reserved for future use */ 70 __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ 71 uint32_t RESERVED10[7U]; /**< Reserved for future use */ 72 __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ 73 uint32_t RESERVED11[7U]; /**< Reserved for future use */ 74 __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ 75 uint32_t RESERVED12[31U]; /**< Reserved for future use */ 76 __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ 77 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 78 __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ 79 uint32_t RESERVED14[13U]; /**< Reserved for future use */ 80 __IOM uint32_t RTCCCLKCTRL; /**< RTCC Clock Control */ 81 uint32_t RESERVED15[1U]; /**< Reserved for future use */ 82 __IOM uint32_t PRORTCCLKCTRL; /**< Protocol RTC Clock Control */ 83 uint32_t RESERVED16[13U]; /**< Reserved for future use */ 84 __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ 85 uint32_t RESERVED17[863U]; /**< Reserved for future use */ 86 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 87 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 88 __IM uint32_t STATUS_SET; /**< Status Register */ 89 uint32_t RESERVED19[1U]; /**< Reserved for future use */ 90 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 91 __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ 92 uint32_t RESERVED20[2U]; /**< Reserved for future use */ 93 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 94 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 95 uint32_t RESERVED21[10U]; /**< Reserved for future use */ 96 __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ 97 __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ 98 __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ 99 uint32_t RESERVED22[5U]; /**< Reserved for future use */ 100 __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ 101 uint32_t RESERVED23[3U]; /**< Reserved for future use */ 102 __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ 103 uint32_t RESERVED24[3U]; /**< Reserved for future use */ 104 __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ 105 uint32_t RESERVED25[27U]; /**< Reserved for future use */ 106 __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ 107 uint32_t RESERVED26[7U]; /**< Reserved for future use */ 108 __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ 109 uint32_t RESERVED27[7U]; /**< Reserved for future use */ 110 __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ 111 uint32_t RESERVED28[7U]; /**< Reserved for future use */ 112 __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ 113 uint32_t RESERVED29[7U]; /**< Reserved for future use */ 114 __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ 115 uint32_t RESERVED30[31U]; /**< Reserved for future use */ 116 __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ 117 uint32_t RESERVED31[1U]; /**< Reserved for future use */ 118 __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ 119 uint32_t RESERVED32[13U]; /**< Reserved for future use */ 120 __IOM uint32_t RTCCCLKCTRL_SET; /**< RTCC Clock Control */ 121 uint32_t RESERVED33[1U]; /**< Reserved for future use */ 122 __IOM uint32_t PRORTCCLKCTRL_SET; /**< Protocol RTC Clock Control */ 123 uint32_t RESERVED34[13U]; /**< Reserved for future use */ 124 __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ 125 uint32_t RESERVED35[863U]; /**< Reserved for future use */ 126 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 127 uint32_t RESERVED36[1U]; /**< Reserved for future use */ 128 __IM uint32_t STATUS_CLR; /**< Status Register */ 129 uint32_t RESERVED37[1U]; /**< Reserved for future use */ 130 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 131 __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ 132 uint32_t RESERVED38[2U]; /**< Reserved for future use */ 133 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 134 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 135 uint32_t RESERVED39[10U]; /**< Reserved for future use */ 136 __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ 137 __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ 138 __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ 139 uint32_t RESERVED40[5U]; /**< Reserved for future use */ 140 __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ 141 uint32_t RESERVED41[3U]; /**< Reserved for future use */ 142 __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ 143 uint32_t RESERVED42[3U]; /**< Reserved for future use */ 144 __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ 145 uint32_t RESERVED43[27U]; /**< Reserved for future use */ 146 __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ 147 uint32_t RESERVED44[7U]; /**< Reserved for future use */ 148 __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ 149 uint32_t RESERVED45[7U]; /**< Reserved for future use */ 150 __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ 151 uint32_t RESERVED46[7U]; /**< Reserved for future use */ 152 __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ 153 uint32_t RESERVED47[7U]; /**< Reserved for future use */ 154 __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ 155 uint32_t RESERVED48[31U]; /**< Reserved for future use */ 156 __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ 157 uint32_t RESERVED49[1U]; /**< Reserved for future use */ 158 __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ 159 uint32_t RESERVED50[13U]; /**< Reserved for future use */ 160 __IOM uint32_t RTCCCLKCTRL_CLR; /**< RTCC Clock Control */ 161 uint32_t RESERVED51[1U]; /**< Reserved for future use */ 162 __IOM uint32_t PRORTCCLKCTRL_CLR; /**< Protocol RTC Clock Control */ 163 uint32_t RESERVED52[13U]; /**< Reserved for future use */ 164 __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ 165 uint32_t RESERVED53[863U]; /**< Reserved for future use */ 166 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 167 uint32_t RESERVED54[1U]; /**< Reserved for future use */ 168 __IM uint32_t STATUS_TGL; /**< Status Register */ 169 uint32_t RESERVED55[1U]; /**< Reserved for future use */ 170 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 171 __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ 172 uint32_t RESERVED56[2U]; /**< Reserved for future use */ 173 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 174 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 175 uint32_t RESERVED57[10U]; /**< Reserved for future use */ 176 __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ 177 __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ 178 __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ 179 uint32_t RESERVED58[5U]; /**< Reserved for future use */ 180 __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ 181 uint32_t RESERVED59[3U]; /**< Reserved for future use */ 182 __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ 183 uint32_t RESERVED60[3U]; /**< Reserved for future use */ 184 __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ 185 uint32_t RESERVED61[27U]; /**< Reserved for future use */ 186 __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ 187 uint32_t RESERVED62[7U]; /**< Reserved for future use */ 188 __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ 189 uint32_t RESERVED63[7U]; /**< Reserved for future use */ 190 __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ 191 uint32_t RESERVED64[7U]; /**< Reserved for future use */ 192 __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ 193 uint32_t RESERVED65[7U]; /**< Reserved for future use */ 194 __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ 195 uint32_t RESERVED66[31U]; /**< Reserved for future use */ 196 __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ 197 uint32_t RESERVED67[1U]; /**< Reserved for future use */ 198 __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ 199 uint32_t RESERVED68[13U]; /**< Reserved for future use */ 200 __IOM uint32_t RTCCCLKCTRL_TGL; /**< RTCC Clock Control */ 201 uint32_t RESERVED69[1U]; /**< Reserved for future use */ 202 __IOM uint32_t PRORTCCLKCTRL_TGL; /**< Protocol RTC Clock Control */ 203 uint32_t RESERVED70[13U]; /**< Reserved for future use */ 204 __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ 205 } CMU_TypeDef; 206 /** @} End of group EFR32MG21_CMU */ 207 208 /**************************************************************************//** 209 * @addtogroup EFR32MG21_CMU 210 * @{ 211 * @defgroup EFR32MG21_CMU_BitFields CMU Bit Fields 212 * @{ 213 *****************************************************************************/ 214 215 /* Bit fields for CMU IPVERSION */ 216 #define _CMU_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for CMU_IPVERSION */ 217 #define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ 218 #define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ 219 #define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ 220 #define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IPVERSION */ 221 #define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ 222 223 /* Bit fields for CMU STATUS */ 224 #define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ 225 #define _CMU_STATUS_MASK 0xC0030101UL /**< Mask for CMU_STATUS */ 226 #define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ 227 #define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ 228 #define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ 229 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 230 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 231 #define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ 232 #define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ 233 #define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ 234 #define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 235 #define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ 236 #define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ 237 #define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ 238 #define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ 239 #define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ 240 #define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ 241 #define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ 242 #define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ 243 #define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 244 #define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ 245 #define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ 246 #define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ 247 #define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ 248 #define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ 249 250 /* Bit fields for CMU LOCK */ 251 #define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ 252 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 253 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 254 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 255 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ 256 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ 257 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 258 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 259 260 /* Bit fields for CMU WDOGLOCK */ 261 #define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ 262 #define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ 263 #define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 264 #define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 265 #define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ 266 #define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ 267 #define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ 268 #define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ 269 270 /* Bit fields for CMU IF */ 271 #define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ 272 #define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ 273 #define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ 274 #define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ 275 #define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ 276 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 277 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 278 #define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ 279 #define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ 280 #define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ 281 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 282 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 283 284 /* Bit fields for CMU IEN */ 285 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 286 #define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ 287 #define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ 288 #define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ 289 #define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ 290 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 291 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 292 #define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ 293 #define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ 294 #define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ 295 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 296 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 297 298 /* Bit fields for CMU CALCMD */ 299 #define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ 300 #define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ 301 #define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ 302 #define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ 303 #define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ 304 #define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ 305 #define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ 306 #define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ 307 #define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ 308 #define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ 309 #define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ 310 #define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ 311 312 /* Bit fields for CMU CALCTRL */ 313 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 314 #define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ 315 #define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ 316 #define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ 317 #define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 318 #define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 319 #define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ 320 #define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ 321 #define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ 322 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 323 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 324 #define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ 325 #define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ 326 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 327 #define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ 328 #define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ 329 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ 330 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ 331 #define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ 332 #define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ 333 #define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ 334 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ 335 #define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ 336 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 337 #define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ 338 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ 339 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ 340 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ 341 #define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ 342 #define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ 343 #define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ 344 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ 345 #define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ 346 #define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ 347 #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ 348 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 349 #define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ 350 #define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ 351 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ 352 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ 353 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ 354 #define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ 355 #define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ 356 #define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ 357 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ 358 #define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ 359 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 360 #define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ 361 #define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ 362 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ 363 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ 364 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ 365 #define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ 366 #define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ 367 #define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ 368 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ 369 #define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ 370 371 /* Bit fields for CMU CALCNT */ 372 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 373 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 374 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 375 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 376 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 377 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 378 379 /* Bit fields for CMU SYSCLKCTRL */ 380 #define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ 381 #define _CMU_SYSCLKCTRL_MASK 0x00003507UL /**< Mask for CMU_SYSCLKCTRL */ 382 #define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 383 #define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ 384 #define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ 385 #define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ 386 #define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ 387 #define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ 388 #define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ 389 #define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ 390 #define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ 391 #define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ 392 #define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ 393 #define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ 394 #define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ 395 #define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ 396 #define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ 397 #define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ 398 #define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ 399 #define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ 400 #define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ 401 #define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ 402 #define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ 403 #define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ 404 #define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0x3000UL /**< Bit mask for CMU_HCLKPRESC */ 405 #define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ 406 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ 407 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ 408 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ 409 #define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ 410 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ 411 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ 412 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ 413 414 /* Bit fields for CMU TRACECLKCTRL */ 415 #define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */ 416 #define _CMU_TRACECLKCTRL_MASK 0x00000003UL /**< Mask for CMU_TRACECLKCTRL */ 417 #define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 418 #define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 419 #define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ 420 #define _CMU_TRACECLKCTRL_CLKSEL_HCLK 0x00000002UL /**< Mode HCLK for CMU_TRACECLKCTRL */ 421 #define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */ 422 #define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ 423 #define CMU_TRACECLKCTRL_CLKSEL_HCLK (_CMU_TRACECLKCTRL_CLKSEL_HCLK << 0) /**< Shifted mode HCLK for CMU_TRACECLKCTRL */ 424 #define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */ 425 426 /* Bit fields for CMU EXPORTCLKCTRL */ 427 #define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ 428 #define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ 429 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ 430 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ 431 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 432 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ 433 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ 434 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 435 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ 436 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ 437 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ 438 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ 439 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000007UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ 440 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000008UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ 441 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ 442 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 443 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ 444 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ 445 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 446 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ 447 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ 448 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ 449 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ 450 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ 451 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ 452 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ 453 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ 454 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ 455 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 456 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ 457 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ 458 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 459 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ 460 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ 461 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ 462 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ 463 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000007UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ 464 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000008UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ 465 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ 466 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 467 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ 468 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ 469 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 470 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ 471 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ 472 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ 473 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ 474 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ 475 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ 476 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ 477 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ 478 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ 479 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 480 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ 481 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ 482 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 483 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ 484 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ 485 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ 486 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ 487 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000007UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ 488 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000008UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ 489 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ 490 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 491 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ 492 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ 493 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 494 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ 495 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ 496 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ 497 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ 498 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ 499 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ 500 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ 501 #define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ 502 #define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ 503 #define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 504 #define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 505 506 /* Bit fields for CMU DPLLREFCLKCTRL */ 507 #define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ 508 #define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ 509 #define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 510 #define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 511 #define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ 512 #define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ 513 #define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ 514 #define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ 515 #define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ 516 #define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ 517 #define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ 518 #define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ 519 #define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ 520 #define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ 521 522 /* Bit fields for CMU EM01GRPACLKCTRL */ 523 #define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ 524 #define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ 525 #define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 526 #define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ 527 #define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ 528 #define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ 529 #define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ 530 #define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ 531 #define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000004UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ 532 #define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ 533 #define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ 534 #define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ 535 #define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ 536 #define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ 537 538 /* Bit fields for CMU EM23GRPACLKCTRL */ 539 #define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ 540 #define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ 541 #define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 542 #define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 543 #define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ 544 #define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ 545 #define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ 546 #define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ 547 #define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ 548 #define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ 549 #define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ 550 #define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ 551 552 /* Bit fields for CMU EM4GRPACLKCTRL */ 553 #define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ 554 #define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ 555 #define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 556 #define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 557 #define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ 558 #define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ 559 #define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ 560 #define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ 561 #define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ 562 #define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ 563 #define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ 564 #define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ 565 566 /* Bit fields for CMU IADCCLKCTRL */ 567 #define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ 568 #define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ 569 #define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 570 #define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 571 #define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ 572 #define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ 573 #define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ 574 #define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ 575 #define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ 576 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ 577 #define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ 578 #define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ 579 580 /* Bit fields for CMU WDOG0CLKCTRL */ 581 #define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ 582 #define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ 583 #define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 584 #define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ 585 #define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ 586 #define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ 587 #define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ 588 #define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ 589 #define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ 590 #define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ 591 #define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ 592 #define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ 593 #define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ 594 #define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ 595 596 /* Bit fields for CMU WDOG1CLKCTRL */ 597 #define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ 598 #define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ 599 #define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 600 #define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ 601 #define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ 602 #define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ 603 #define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ 604 #define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ 605 #define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ 606 #define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ 607 #define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ 608 #define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ 609 #define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ 610 #define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ 611 612 /* Bit fields for CMU RTCCCLKCTRL */ 613 #define _CMU_RTCCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_RTCCCLKCTRL */ 614 #define _CMU_RTCCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_RTCCCLKCTRL */ 615 #define _CMU_RTCCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 616 #define _CMU_RTCCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 617 #define _CMU_RTCCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_RTCCCLKCTRL */ 618 #define _CMU_RTCCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_RTCCCLKCTRL */ 619 #define _CMU_RTCCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_RTCCCLKCTRL */ 620 #define _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_RTCCCLKCTRL */ 621 #define CMU_RTCCCLKCTRL_CLKSEL_DEFAULT (_CMU_RTCCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RTCCCLKCTRL */ 622 #define CMU_RTCCCLKCTRL_CLKSEL_LFRCO (_CMU_RTCCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_RTCCCLKCTRL */ 623 #define CMU_RTCCCLKCTRL_CLKSEL_LFXO (_CMU_RTCCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_RTCCCLKCTRL */ 624 #define CMU_RTCCCLKCTRL_CLKSEL_ULFRCO (_CMU_RTCCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_RTCCCLKCTRL */ 625 626 /* Bit fields for CMU PRORTCCLKCTRL */ 627 #define _CMU_PRORTCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PRORTCCLKCTRL */ 628 #define _CMU_PRORTCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PRORTCCLKCTRL */ 629 #define _CMU_PRORTCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 630 #define _CMU_PRORTCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 631 #define _CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PRORTCCLKCTRL */ 632 #define _CMU_PRORTCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_PRORTCCLKCTRL */ 633 #define _CMU_PRORTCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_PRORTCCLKCTRL */ 634 #define _CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_PRORTCCLKCTRL */ 635 #define CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT (_CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PRORTCCLKCTRL */ 636 #define CMU_PRORTCCLKCTRL_CLKSEL_LFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_PRORTCCLKCTRL */ 637 #define CMU_PRORTCCLKCTRL_CLKSEL_LFXO (_CMU_PRORTCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_PRORTCCLKCTRL */ 638 #define CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_PRORTCCLKCTRL */ 639 640 /* Bit fields for CMU RADIOCLKCTRL */ 641 #define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ 642 #define _CMU_RADIOCLKCTRL_MASK 0x00000001UL /**< Mask for CMU_RADIOCLKCTRL */ 643 #define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ 644 #define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ 645 #define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ 646 #define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ 647 #define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ 648 649 /** @} End of group EFR32MG21_CMU_BitFields */ 650 /** @} End of group EFR32MG21_CMU */ 651 /** @} End of group Parts */ 652 653 #endif /* EFR32MG21_CMU_H */ 654
