1# ARM Cortex-M platform configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6# NOTE: We have the specific core implementations first and outside of the 7# if CPU_CORTEX_M block so that SoCs can select which core they are using 8# without having to select all the options related to that core. Everything 9# else is captured inside the if CPU_CORTEX_M block so they are not exposed 10# if one select a different ARM Cortex Family (Cortex-A or Cortex-R) 11 12config CPU_CORTEX_M0 13 bool 14 select CPU_CORTEX_M 15 select ARMV6_M_ARMV8_M_BASELINE 16 help 17 This option signifies the use of a Cortex-M0 CPU 18 19config CPU_CORTEX_M0PLUS 20 bool 21 select CPU_CORTEX_M 22 select ARMV6_M_ARMV8_M_BASELINE 23 help 24 This option signifies the use of a Cortex-M0+ CPU 25 26config CPU_CORTEX_M1 27 bool 28 select CPU_CORTEX_M 29 select ARMV6_M_ARMV8_M_BASELINE 30 help 31 This option signifies the use of a Cortex-M1 CPU 32 33config CPU_CORTEX_M3 34 bool 35 select CPU_CORTEX_M 36 select ARMV7_M_ARMV8_M_MAINLINE 37 help 38 This option signifies the use of a Cortex-M3 CPU 39 40config CPU_CORTEX_M4 41 bool 42 select CPU_CORTEX_M 43 select ARMV7_M_ARMV8_M_MAINLINE 44 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 45 help 46 This option signifies the use of a Cortex-M4 CPU 47 48config CPU_CORTEX_M23 49 bool 50 select CPU_CORTEX_M 51 select ARMV8_M_BASELINE 52 select ARMV8_M_SE if CPU_HAS_TEE 53 help 54 This option signifies the use of a Cortex-M23 CPU 55 56config CPU_CORTEX_M33 57 bool 58 select CPU_CORTEX_M 59 select ARMV8_M_MAINLINE 60 select ARMV8_M_SE if CPU_HAS_TEE 61 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 62 help 63 This option signifies the use of a Cortex-M33 CPU 64 65config CPU_CORTEX_M55 66 bool 67 select CPU_CORTEX_M 68 select ARMV8_1_M_MAINLINE 69 select ARMV8_M_SE if CPU_HAS_TEE 70 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 71 select CPU_HAS_DCACHE 72 select CPU_HAS_ICACHE 73 help 74 This option signifies the use of a Cortex-M55 CPU 75 76config CPU_CORTEX_M7 77 bool 78 select CPU_CORTEX_M 79 select ARMV7_M_ARMV8_M_MAINLINE 80 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 81 select CPU_HAS_DCACHE 82 select CPU_HAS_ICACHE 83 help 84 This option signifies the use of a Cortex-M7 CPU 85 86if CPU_CORTEX_M 87 88config CPU_CORTEX_M_HAS_SYSTICK 89 bool 90 help 91 This option is enabled when the CPU implements the SysTick timer. 92 93config DCACHE_LINE_SIZE 94 default 32 95 96config ICACHE_LINE_SIZE 97 default 32 98 99config CPU_CORTEX_M_HAS_DWT 100 bool 101 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS && !CPU_CORTEX_M1 102 help 103 This option signifies that the CPU implements the Data Watchpoint and 104 Trace (DWT) unit specified by the ARMv7-M and above. 105 106 While ARMv6-M does define a "DWT" unit, this is significantly different 107 from the DWT specified by the ARMv7-M and above in terms of both feature 108 set and register mappings. 109 110config CPU_CORTEX_M_HAS_BASEPRI 111 bool 112 depends on ARMV7_M_ARMV8_M_MAINLINE 113 help 114 This option signifies the CPU has the BASEPRI register. 115 116 The BASEPRI register defines the minimum priority for 117 exception processing. When BASEPRI is set to a nonzero 118 value, it prevents the activation of all exceptions with 119 the same or lower priority level as the BASEPRI value. 120 Always present in CPUs that implement the ARMv7-M or 121 ARM8-M Mainline architectures. 122 123config CPU_CORTEX_M_HAS_VTOR 124 bool 125 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M1 126 help 127 This option signifies the CPU has the VTOR register. 128 The VTOR indicates the offset of the vector table base 129 address from memory address 0x00000000. Always present 130 in CPUs implementing the ARMv7-M or ARMv8-M architectures. 131 Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline 132 architectures (except for Cortex-M0/M1, where it is never 133 implemented). 134 135config CPU_CORTEX_M_HAS_SPLIM 136 bool 137 depends on ARMV8_M_MAINLINE || (ARMV8_M_SE && !ARM_NONSECURE_FIRMWARE) 138 help 139 This option signifies the CPU has the MSPLIM, PSPLIM registers. 140 141 The stack pointer limit registers, MSPLIM, PSPLIM, limit the 142 extend to which the Main and Process Stack Pointers, respectively, 143 can descend. MSPLIM, PSPLIM are always present in ARMv8-M 144 MCUs that implement the ARMv8-M Main Extension (Mainline). 145 146 In an ARMv8-M Mainline implementation with the Security Extension 147 the MSPLIM, PSPLIM registers have additional Secure instances. 148 In an ARMv8-M Baseline implementation with the Security Extension 149 the MSPLIM, PSPLIM registers have only Secure instances. 150 151config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 152 bool 153 depends on ARMV7_M_ARMV8_M_MAINLINE 154 help 155 This option signifies the CPU may trigger system faults 156 (other than HardFault) with configurable priority, and, 157 therefore, it needs to reserve a priority level for them. 158 159config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 160 bool 161 depends on ARMV6_M_ARMV8_M_BASELINE 162 help 163 This option signifies the Cortex-M0 has some mechanisms that can map 164 the vector table to SRAM 165 166config CPU_CORTEX_M_HAS_CMSE 167 bool 168 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 169 help 170 This option signifies the Cortex-M CPU has the CMSE intrinsics. 171 172config ARMV6_M_ARMV8_M_BASELINE 173 bool 174 select ATOMIC_OPERATIONS_C if !ARMV8_M_BASELINE 175 select ISA_THUMB2 176 help 177 This option signifies the use of an ARMv6-M processor 178 implementation, or the use of an ARMv8-M processor 179 supporting the Baseline implementation. 180 181 Notes: 182 - A Processing Element (PE) without the Main Extension 183 is also referred to as a Baseline Implementation. A 184 Baseline implementation has a subset of the instructions, 185 registers, and features, of a Mainline implementation. 186 - ARMv6-M compatibility is provided by all ARMv8-M 187 implementations. 188 189config ARMV8_M_BASELINE 190 bool 191 select ARMV6_M_ARMV8_M_BASELINE 192 select CPU_CORTEX_M_HAS_CMSE 193 help 194 This option signifies the use of an ARMv8-M processor 195 implementation. 196 197 ARMv8-M Baseline includes additional features 198 not present in the ARMv6-M architecture. 199 200config ARMV7_M_ARMV8_M_MAINLINE 201 bool 202 select ATOMIC_OPERATIONS_BUILTIN 203 select ISA_THUMB2 204 select CPU_CORTEX_M_HAS_BASEPRI 205 select CPU_CORTEX_M_HAS_VTOR 206 select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 207 select CPU_CORTEX_M_HAS_SYSTICK 208 help 209 This option signifies the use of an ARMv7-M processor 210 implementation, or the use of a backwards-compatible 211 ARMv8-M processor implementation supporting the Main 212 Extension. 213 214 Notes: 215 - A Processing Element (PE) with the Main Extension is also 216 referred to as a Mainline Implementation. 217 - ARMv7-M compatibility requires the Main Extension. 218 219 From https://developer.arm.com/products/architecture/m-profile: 220 The Main Extension provides backwards compatibility 221 with ARMv7-M. 222 223config ARMV8_M_MAINLINE 224 bool 225 select ARMV7_M_ARMV8_M_MAINLINE 226 select CPU_CORTEX_M_HAS_SPLIM 227 select CPU_CORTEX_M_HAS_CMSE 228 help 229 This option signifies the use of an ARMv8-M processor 230 implementation, supporting the Main Extension. 231 232 ARMv8-M Main Extension includes additional features 233 not present in the ARMv7-M architecture. 234 235config ARMV8_1_M_MAINLINE 236 bool 237 select ARMV8_M_MAINLINE 238 help 239 This option signifies the use of an ARMv8.1-M processor 240 implementation, supporting the Main Extension. 241 242 ARMv8.1-M Main Extension includes additional features 243 not present in the ARMv8-M architecture. 244 245config ARMV8_M_SE 246 bool 247 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 248 select CPU_CORTEX_M_HAS_SPLIM if !ARM_NONSECURE_FIRMWARE 249 help 250 This option signifies the use of an ARMv8-M processor 251 implementation (Baseline or Mainline) supporting the 252 Security Extensions. 253 254config ARMV7_M_ARMV8_M_FP 255 bool 256 depends on ARMV7_M_ARMV8_M_MAINLINE && !CPU_CORTEX_M3 257 imply FPU_SHARING 258 help 259 This option signifies the use of an ARMv7-M processor 260 implementation, or the use of an ARMv8-M processor 261 implementation supporting the Floating-Point Extension. 262 263config ARMV8_M_DSP 264 bool 265 depends on ARMV8_M_MAINLINE 266 help 267 This option signifies the use of an ARMv8-M processor 268 implementation supporting the DSP Extension. 269 270config ARMV8_1_M_MVEI 271 bool 272 depends on ARMV8_1_M_MAINLINE 273 depends on ARMV8_M_DSP 274 help 275 This option signifies the use of an ARMv8.1-M processor implementation 276 supporting the M-Profile Vector Extension (MVE) integer instruction set. 277 278config ARMV8_1_M_MVEF 279 bool 280 depends on ARMV8_1_M_MVEI 281 help 282 This option signifies the use of an ARMv8.1-M processor implementation 283 supporting the M-Profile Vector Extension (MVE) floating-point 284 instruction set. 285 286menu "ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options" 287 depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE 288 289config GEN_ISR_TABLES 290 default y 291 292config ZERO_LATENCY_IRQS 293 bool "Zero-latency interrupts" 294 depends on CPU_CORTEX_M_HAS_BASEPRI 295 help 296 The kernel may reserve some of the highest interrupts priorities in 297 the system for its own use. These interrupts will not be masked 298 by interrupt locking. 299 When connecting interrupts the kernel will offset all interrupts 300 to lower priority than those reserved by the kernel. 301 Zero-latency interrupt can be used to set up an interrupt at the 302 highest interrupt priority which will not be blocked by interrupt 303 locking. 304 Since Zero-latency ISRs will run in the same priority or possibly at 305 higher priority than the rest of the kernel they cannot use any 306 kernel functionality. 307 308config ZERO_LATENCY_LEVELS 309 int "Number of interrupt priority levels reserved for zero latency" 310 depends on ZERO_LATENCY_IRQS 311 range 1 255 312 help 313 The amount of interrupt priority levels reserved for zero latency 314 interrupts. Increase this value to reserve more than one priority 315 level for zero latency interrupts. 316 317config DYNAMIC_DIRECT_INTERRUPTS 318 bool "Support for dynamic direct interrupts" 319 depends on DYNAMIC_INTERRUPTS 320 help 321 Direct interrupts are designed for performance-critical interrupt 322 handling and do not go through all of the common interrupt handling 323 code. This option enables the installation of interrupt service 324 routines for direct interrupts at runtime. 325 Note: this requires enabling support for dynamic interrupts in the 326 kernel. 327 328config SW_VECTOR_RELAY 329 bool "Software Vector Relay" 330 help 331 When building a bootloader firmware this option adds a 332 vector table relay handler and a vector relay table, to 333 relay interrupts based on a vector table pointer. 334 This is only required but not limited to Cortex-M Baseline CPUs 335 with no hardware vector table relocation mechanisms (e.g. VTOR). 336 337config SW_VECTOR_RELAY_CLIENT 338 bool "Software Vector Relay (client)" 339 default y if BOOTLOADER_MCUBOOT && !CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 340 depends on !CPU_CORTEX_M_HAS_VTOR 341 help 342 Another image has enabled SW_VECTOR_RELAY, and will be forwarding 343 exceptions and HW interrupts to this image. Enable this option to make 344 sure the vector table pointer in RAM is set properly by the image upon 345 initialization. 346 347config CORTEX_M_DWT 348 bool "Data Watchpoint and Trace (DWT)" 349 depends on CPU_CORTEX_M_HAS_DWT 350 default y if TIMING_FUNCTIONS 351 help 352 Enable and use the Data Watchpoint and Trace (DWT) unit for 353 timing functions. 354 355config CORTEX_M_DEBUG_MONITOR_HOOK 356 bool "Debug monitor interrupt for debugging" 357 depends on !ARMV6_M_ARMV8_M_BASELINE 358 help 359 Enable this option to configure debug monitor exception to low priority 360 for debugging purposes. 361 362# enabled, which may increase ESF stacking requirements for 363# threads. 364config TEST_EXTRA_STACK_SIZE 365 default 512 if TEST_ARM_CORTEX_M && FPU_SHARING 366 367config TRAP_UNALIGNED_ACCESS 368 bool "Unaligned access trap" 369 depends on !ARMV6_M_ARMV8_M_BASELINE 370 help 371 If enabled, the CPU generates a UsageFault exception when executing a 372 halfword or word access. 373 374endmenu 375 376# Implement the null pointer detection using either the Data Watchpoint and 377# Trace Unit and the Debug Monitor Exception, or the Memory Protection Unit. 378 379choice NULL_POINTER_EXCEPTION_DETECTION 380 bool "Null-pointer exception" 381 # Disable this until https://github.com/zephyrproject-rtos/zephyr/issues/32984 is fixed 382 # default NULL_POINTER_EXCEPTION_DETECTION_DWT if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && CPU_CORTEX_M_HAS_DWT 383 default NULL_POINTER_EXCEPTION_DETECTION_MPU if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && ARM_MPU && !CPU_CORTEX_M_HAS_DWT 384 default NULL_POINTER_EXCEPTION_DETECTION_NONE 385 help 386 There are 2 implementations available, one based 387 on DWT and the other based on MPU. Use this choice 388 symbol to select one of the options. By default the 389 feature is disabled. In the test suite the feature 390 is enabled and the DWT-based solution is preferred. 391 392config NULL_POINTER_EXCEPTION_DETECTION_NONE 393 bool "No null pointer exception detection" 394 help 395 Null pointer exception detection feature is not 396 enabled. 397 398config NULL_POINTER_EXCEPTION_DETECTION_DWT 399 bool "Use DWT for null pointer exception detection" 400 depends on CPU_CORTEX_M_HAS_DWT 401 depends on !TRUSTED_EXECUTION_NONSECURE 402 select CORTEX_M_DWT 403 select CORTEX_M_NULL_POINTER_EXCEPTION 404 help 405 Null pointer dereference detection implemented 406 using the DWT unit functionality. 407 Notes: 408 - Not enabled for Non-Secure FW images, where 409 null-pointer dereferencing is likely caught as 410 a SecureFault. 411 - Requires DWT functionality in the Cortex-M SoC 412 implementation (1 comparator for ARMv7-M, 2 comparators 413 for ARMv8-M). 414 - Requires the Cortex-M core be in normal mode. 415 416config NULL_POINTER_EXCEPTION_DETECTION_MPU 417 bool "Use MPU for null pointer exception detection" 418 depends on !TRUSTED_EXECUTION_NONSECURE 419 depends on ARM_MPU 420 select CORTEX_M_NULL_POINTER_EXCEPTION 421 help 422 Null pointer dereference detection implemented 423 using MPU functionality. 424 Notes: 425 - Mutually exclusive to the DWT-based solution 426 - Not enabled for Non-Secure FW images, where 427 null-pointer dereferencing is likely caught as 428 a SecureFault. 429 - Requires MPU functionality to be present and 430 enabled. The implementation consumes 1 MPU region. 431 - In ARMv8-M, explicit null-pointer dereference 432 detection with MPU requires, additionally, that 433 the area: [0x0, 434 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) 435 is not unmapped (covered by an MPU region already). 436 If it is unmapped null-pointer dereferencing may 437 still be indirectly detected (e.g. via a precise 438 Bus access fault), but this is not guaranteed. A 439 build-time message warns the user of this scenario. 440 441endchoice 442 443config CORTEX_M_NULL_POINTER_EXCEPTION 444 bool 445 help 446 Enable and use the null pointer exception option. 447 This is a debug feature in Cortex-M, allowing for 448 detecting null pointer dereferencing (raising a 449 CPU fault). Supporting the feature results in an 450 increased code footprint, determined by option 451 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE. 452 453 Note: this hidden option is selected by the choice 454 symbols corresponding to the DWT-based or to the 455 MPU-based solution. 456 457if CORTEX_M_NULL_POINTER_EXCEPTION 458 459config CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE 460 hex "Size of paged unmapped to implement null pointer detection" 461 default 0x400 462 help 463 Size of the page reserved for detecting null pointer 464 dereferencing. Must be a power of two. A large value 465 offers enhanced detection performance to the cost of 466 wasting a large flash area that code may not use. 467 468endif # CORTEX_M_NULL_POINTER_EXCEPTION 469 470rsource "tz/Kconfig" 471 472endif # CPU_CORTEX_M 473
