1 /******************************************************************************* 2 // Copyright (c) 2003-2015 Cadence Design Systems, Inc. 3 // 4 // Permission is hereby granted, free of charge, to any person obtaining 5 // a copy of this software and associated documentation files (the 6 // "Software"), to deal in the Software without restriction, including 7 // without limitation the rights to use, copy, modify, merge, publish, 8 // distribute, sublicense, and/or sell copies of the Software, and to 9 // permit persons to whom the Software is furnished to do so, subject to 10 // the following conditions: 11 // 12 // The above copyright notice and this permission notice shall be included 13 // in all copies or substantial portions of the Software. 14 // 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 -------------------------------------------------------------------------------- 23 24 RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES 25 (FreeRTOS Port) 26 27 This header is the primary glue between generic Xtensa RTOS support 28 sources and a specific RTOS port for Xtensa. It contains definitions 29 and macros for use primarily by Xtensa assembly coded source files. 30 31 Macros in this header map callouts from generic Xtensa files to specific 32 RTOS functions. It may also be included in C source files. 33 34 Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 35 architecture, using the Xtensa hardware abstraction layer (HAL) to deal 36 with configuration specifics. 37 38 Should be included by all Xtensa generic and RTOS port-specific sources. 39 40 *******************************************************************************/ 41 42 #ifndef XTENSA_RTOS_H 43 #define XTENSA_RTOS_H 44 45 #ifdef __ASSEMBLER__ 46 #include <xtensa/coreasm.h> 47 #else 48 #include <xtensa/config/core.h> 49 #endif 50 51 #include <xtensa/corebits.h> 52 #include <xtensa/config/system.h> 53 #include "sdkconfig.h" 54 55 /* 56 Include any RTOS specific definitions that are needed by this header. 57 */ 58 #include "freertos/FreeRTOSConfig.h" 59 60 /* 61 Convert FreeRTOSConfig definitions to XTENSA definitions. 62 However these can still be overridden from the command line. 63 */ 64 65 #ifndef XT_SIMULATOR 66 #if configXT_SIMULATOR 67 #define XT_SIMULATOR 1 /* Simulator mode */ 68 #endif 69 #endif 70 71 #ifndef XT_BOARD 72 #if configXT_BOARD 73 #define XT_BOARD 1 /* Board mode */ 74 #endif 75 #endif 76 77 #ifndef XT_TIMER_INDEX 78 #if defined configXT_TIMER_INDEX 79 #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ 80 #endif 81 #endif 82 83 #ifndef XT_INTEXC_HOOKS 84 #if configXT_INTEXC_HOOKS 85 #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ 86 #endif 87 #endif 88 89 #if !defined(XT_SIMULATOR) && !defined(XT_BOARD) 90 #error Either XT_SIMULATOR or XT_BOARD must be defined. 91 #endif 92 93 94 /* 95 Name of RTOS (for messages). 96 */ 97 #define XT_RTOS_NAME FreeRTOS 98 99 /* 100 Check some Xtensa configuration requirements and report error if not met. 101 Error messages can be customize to the RTOS port. 102 */ 103 104 #if !XCHAL_HAVE_XEA2 105 #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)." 106 #endif 107 108 109 /******************************************************************************* 110 111 RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. 112 113 Define callout macros used in generic Xtensa code to interact with the RTOS. 114 The macros are simply the function names for use in calls from assembler code. 115 Some of these functions may call back to generic functions in xtensa_context.h . 116 117 *******************************************************************************/ 118 119 /* 120 Inform RTOS of entry into an interrupt handler that will affect it. 121 Allows RTOS to manage switch to any system stack and count nesting level. 122 Called after minimal context has been saved, with interrupts disabled. 123 RTOS port can call0 _xt_context_save to save the rest of the context. 124 May only be called from assembly code by the 'call0' instruction. 125 */ 126 // void XT_RTOS_INT_ENTER(void) 127 #define XT_RTOS_INT_ENTER _frxt_int_enter 128 129 /* 130 Inform RTOS of completion of an interrupt handler, and give control to 131 RTOS to perform thread/task scheduling, switch back from any system stack 132 and restore the context, and return to the exit dispatcher saved in the 133 stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore 134 to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, 135 leaving only a minimal part of the context to be restored by the exit 136 dispatcher. This function does not return to the place it was called from. 137 May only be called from assembly code by the 'call0' instruction. 138 */ 139 // void XT_RTOS_INT_EXIT(void) 140 #define XT_RTOS_INT_EXIT _frxt_int_exit 141 142 /* 143 Inform RTOS of the occurrence of a tick timer interrupt. 144 If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. 145 May be coded in or called from C or assembly, per ABI conventions. 146 RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). 147 */ 148 // void XT_RTOS_TIMER_INT(void) 149 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT 150 #define XT_RTOS_TIMER_INT _frxt_timer_int 151 #endif 152 #define XT_TICK_PER_SEC configTICK_RATE_HZ 153 154 /* 155 Return in a15 the base address of the co-processor state save area for the 156 thread that triggered a co-processor exception, or 0 if no thread was running. 157 The state save area is structured as defined in xtensa_context.h and has size 158 XT_CP_SIZE. Co-processor instructions should only be used in thread code, never 159 in interrupt handlers or the RTOS kernel. May only be called from assembly code 160 and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 161 The implementation may use only a2-4, a15 (all other regs must be preserved). 162 */ 163 // void* XT_RTOS_CP_STATE(void) 164 #define XT_RTOS_CP_STATE _frxt_task_coproc_state 165 166 167 /******************************************************************************* 168 169 HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. 170 171 This Xtensa RTOS port provides hooks for dynamically installing exception 172 and interrupt handlers to facilitate automated testing where each test 173 case can install its own handler for user exceptions and each interrupt 174 priority (level). This consists of an array of function pointers indexed 175 by interrupt priority, with index 0 being the user exception handler hook. 176 Each entry in the array is initially 0, and may be replaced by a function 177 pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. 178 179 The handler for low and medium priority obeys ABI conventions so may be coded 180 in C. For the exception handler, the cause is the contents of the EXCCAUSE 181 reg, and the result is -1 if handled, else the cause (still needs handling). 182 For interrupt handlers, the cause is a mask of pending enabled interrupts at 183 that level, and the result is the same mask with the bits for the handled 184 interrupts cleared (those not cleared still need handling). This allows a test 185 case to either pre-handle or override the default handling for the exception 186 or interrupt level (see xtensa_vectors.S). 187 188 High priority handlers (including NMI) must be coded in assembly, are always 189 called by 'call0' regardless of ABI, must preserve all registers except a0, 190 and must not use or modify the interrupted stack. The hook argument 'cause' 191 is not passed and the result is ignored, so as not to burden the caller with 192 saving and restoring a2 (it assumes only one interrupt per level - see the 193 discussion in high priority interrupts in xtensa_vectors.S). The handler 194 therefore should be coded to prototype 'void h(void)' even though it plugs 195 into an array of handlers of prototype 'unsigned h(unsigned)'. 196 197 To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. 198 199 *******************************************************************************/ 200 201 #define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI) 202 203 #ifndef __ASSEMBLER__ 204 typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause); 205 extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM]; 206 #endif 207 208 209 /******************************************************************************* 210 211 CONVENIENCE INCLUSIONS. 212 213 Ensures RTOS specific files need only include this one Xtensa-generic header. 214 These headers are included last so they can use the RTOS definitions above. 215 216 *******************************************************************************/ 217 218 #include "xtensa_context.h" 219 220 #ifdef XT_RTOS_TIMER_INT 221 #include "xtensa_timer.h" 222 #endif 223 224 225 /******************************************************************************* 226 227 Xtensa Port Version. 228 229 *******************************************************************************/ 230 231 #define XTENSA_PORT_VERSION 1.4.2 232 #define XTENSA_PORT_VERSION_STRING "1.4.2" 233 234 #endif /* XTENSA_RTOS_H */ 235
