1 /******************************************************************************* 2 // Copyright (c) 2003-2015 Cadence Design Systems, Inc. 3 // 4 // Permission is hereby granted, free of charge, to any person obtaining 5 // a copy of this software and associated documentation files (the 6 // "Software"), to deal in the Software without restriction, including 7 // without limitation the rights to use, copy, modify, merge, publish, 8 // distribute, sublicense, and/or sell copies of the Software, and to 9 // permit persons to whom the Software is furnished to do so, subject to 10 // the following conditions: 11 // 12 // The above copyright notice and this permission notice shall be included 13 // in all copies or substantial portions of the Software. 14 // 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 -------------------------------------------------------------------------------- 23 24 RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES 25 (FreeRTOS Port) 26 27 This header is the primary glue between generic Xtensa RTOS support 28 sources and a specific RTOS port for Xtensa. It contains definitions 29 and macros for use primarily by Xtensa assembly coded source files. 30 31 Macros in this header map callouts from generic Xtensa files to specific 32 RTOS functions. It may also be included in C source files. 33 34 Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 35 architecture, using the Xtensa hardware abstraction layer (HAL) to deal 36 with configuration specifics. 37 38 Should be included by all Xtensa generic and RTOS port-specific sources. 39 40 *******************************************************************************/ 41 42 #ifndef XTENSA_RTOS_H 43 #define XTENSA_RTOS_H 44 45 #ifdef __ASSEMBLER__ 46 #include <xtensa/coreasm.h> 47 #else 48 #include <xtensa/config/core.h> 49 #endif 50 51 #include <xtensa/corebits.h> 52 #include <xtensa/config/system.h> 53 54 /* 55 Include any RTOS specific definitions that are needed by this header. 56 */ 57 #include "freertos/FreeRTOSConfig.h" 58 59 /* 60 Convert FreeRTOSConfig definitions to XTENSA definitions. 61 However these can still be overridden from the command line. 62 */ 63 64 #ifndef XT_SIMULATOR 65 #if configXT_SIMULATOR 66 #define XT_SIMULATOR 1 /* Simulator mode */ 67 #endif 68 #endif 69 70 #ifndef XT_BOARD 71 #if configXT_BOARD 72 #define XT_BOARD 1 /* Board mode */ 73 #endif 74 #endif 75 76 #ifndef XT_TIMER_INDEX 77 #if defined configXT_TIMER_INDEX 78 #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ 79 #endif 80 #endif 81 82 #ifndef XT_INTEXC_HOOKS 83 #if configXT_INTEXC_HOOKS 84 #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ 85 #endif 86 #endif 87 88 #if !defined(XT_SIMULATOR) && !defined(XT_BOARD) 89 #error Either XT_SIMULATOR or XT_BOARD must be defined. 90 #endif 91 92 93 /* 94 Name of RTOS (for messages). 95 */ 96 #define XT_RTOS_NAME FreeRTOS 97 98 /* 99 Check some Xtensa configuration requirements and report error if not met. 100 Error messages can be customize to the RTOS port. 101 */ 102 103 #if !XCHAL_HAVE_XEA2 104 #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)." 105 #endif 106 107 108 /******************************************************************************* 109 110 RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. 111 112 Define callout macros used in generic Xtensa code to interact with the RTOS. 113 The macros are simply the function names for use in calls from assembler code. 114 Some of these functions may call back to generic functions in xtensa_context.h . 115 116 *******************************************************************************/ 117 118 /* 119 Inform RTOS of entry into an interrupt handler that will affect it. 120 Allows RTOS to manage switch to any system stack and count nesting level. 121 Called after minimal context has been saved, with interrupts disabled. 122 RTOS port can call0 _xt_context_save to save the rest of the context. 123 May only be called from assembly code by the 'call0' instruction. 124 */ 125 // void XT_RTOS_INT_ENTER(void) 126 #define XT_RTOS_INT_ENTER _frxt_int_enter 127 128 /* 129 Inform RTOS of completion of an interrupt handler, and give control to 130 RTOS to perform thread/task scheduling, switch back from any system stack 131 and restore the context, and return to the exit dispatcher saved in the 132 stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore 133 to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, 134 leaving only a minimal part of the context to be restored by the exit 135 dispatcher. This function does not return to the place it was called from. 136 May only be called from assembly code by the 'call0' instruction. 137 */ 138 // void XT_RTOS_INT_EXIT(void) 139 #define XT_RTOS_INT_EXIT _frxt_int_exit 140 141 /* 142 Inform RTOS of the occurrence of a tick timer interrupt. 143 If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. 144 May be coded in or called from C or assembly, per ABI conventions. 145 RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). 146 */ 147 // void XT_RTOS_TIMER_INT(void) 148 #define XT_RTOS_TIMER_INT _frxt_timer_int 149 #define XT_TICK_PER_SEC configTICK_RATE_HZ 150 151 /* 152 Return in a15 the base address of the co-processor state save area for the 153 thread that triggered a co-processor exception, or 0 if no thread was running. 154 The state save area is structured as defined in xtensa_context.h and has size 155 XT_CP_SIZE. Co-processor instructions should only be used in thread code, never 156 in interrupt handlers or the RTOS kernel. May only be called from assembly code 157 and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 158 The implementation may use only a2-4, a15 (all other regs must be preserved). 159 */ 160 // void* XT_RTOS_CP_STATE(void) 161 #define XT_RTOS_CP_STATE _frxt_task_coproc_state 162 163 164 /******************************************************************************* 165 166 HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. 167 168 This Xtensa RTOS port provides hooks for dynamically installing exception 169 and interrupt handlers to facilitate automated testing where each test 170 case can install its own handler for user exceptions and each interrupt 171 priority (level). This consists of an array of function pointers indexed 172 by interrupt priority, with index 0 being the user exception handler hook. 173 Each entry in the array is initially 0, and may be replaced by a function 174 pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. 175 176 The handler for low and medium priority obeys ABI conventions so may be coded 177 in C. For the exception handler, the cause is the contents of the EXCCAUSE 178 reg, and the result is -1 if handled, else the cause (still needs handling). 179 For interrupt handlers, the cause is a mask of pending enabled interrupts at 180 that level, and the result is the same mask with the bits for the handled 181 interrupts cleared (those not cleared still need handling). This allows a test 182 case to either pre-handle or override the default handling for the exception 183 or interrupt level (see xtensa_vectors.S). 184 185 High priority handlers (including NMI) must be coded in assembly, are always 186 called by 'call0' regardless of ABI, must preserve all registers except a0, 187 and must not use or modify the interrupted stack. The hook argument 'cause' 188 is not passed and the result is ignored, so as not to burden the caller with 189 saving and restoring a2 (it assumes only one interrupt per level - see the 190 discussion in high priority interrupts in xtensa_vectors.S). The handler 191 therefore should be coded to prototype 'void h(void)' even though it plugs 192 into an array of handlers of prototype 'unsigned h(unsigned)'. 193 194 To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. 195 196 *******************************************************************************/ 197 198 #define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI) 199 200 #ifndef __ASSEMBLER__ 201 typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause); 202 extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM]; 203 #endif 204 205 206 /******************************************************************************* 207 208 CONVENIENCE INCLUSIONS. 209 210 Ensures RTOS specific files need only include this one Xtensa-generic header. 211 These headers are included last so they can use the RTOS definitions above. 212 213 *******************************************************************************/ 214 215 #include "xtensa_context.h" 216 217 #ifdef XT_RTOS_TIMER_INT 218 #include "xtensa_timer.h" 219 #endif 220 221 222 /******************************************************************************* 223 224 Xtensa Port Version. 225 226 *******************************************************************************/ 227 228 #define XTENSA_PORT_VERSION 1.4.2 229 #define XTENSA_PORT_VERSION_STRING "1.4.2" 230 231 #endif /* XTENSA_RTOS_H */ 232
